new best in class memory subsystems with controller ip & … · 2018. 11. 8. · 260-ball, 1 mm...
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January 2013
Best in Class Memory Subsystems with
Controller IP & SigmaQuad-IIIeTM/SigmaDDR-IIIeTM
SRAMs
2
Now Available: A World Class Memory Subsystem
• Silicon-validated memory controller IP • Xilinx Virtex-6 and 7 Series FPGAs
• Altera V5 FPGAs—mid-2013
• Free to GSI customers
• 72Mb SigmaQuad-IIIe/SigmaDDR-IIIe SRAMs • Qualified and in volume production
• 725 MHz clocks 1.45G transactions/second
• Solid migration path to 144Mb & 288Mb
densities
• Complete Support Package • Source code, User Guides, User Configuration
files and applications support
• Demo boards
3
GSI Memory Controller IP: Frequently Asked Questions (1/2)
• Why do I need it?
• High speed memory interface design is a chronic problem due to narrow
valid-data windows on address and data lines. These windows are further
reduced by variations of physical signal trace lengths, capacitances,
inductances, and termination impedances among the parallel signals.
• How are the I/Os aligned?
• The Memory Controller uses a write-then-read verification flow while
adjusting each I/O delay tap to identify the best alignment value for each
signal.
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•Q: What files and documents are available?
• FPGA Development Environment: source code, simulation model, user configuration file, IP user guide, software user guide
• PCB Hardware: Schematics, layout Gerber files, Bill of Materials, Component Placement diagrams, Detailed HW description
• Q: How to combine code sets (GSI with my own)?
• GSI will provide the source code and user configuration file for users to combine with their code.
Example Resource Requirements (Xilinx 7 Series FPGAs- October 2012)
SRAM Configuration: Quad B2 Quad B4 DDR B2
Data Bus Width: x18 x36 x18 x36 x18 x36
Slice Registers: 2354 3631 2024 3337 1864 3194
Slice LUTs: 4254 6722 3555 6050 3578 6442
GSI Memory Controller IP: Frequently Asked Questions (2/2)
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SigmaQuad-IIIeTM/ SigmaDDR-IIIeTM SigmaQuad-IIIe/SigmaDDR-IIIe SRAMs: Benchmark Data
SRAM
Configuration: Clock Rates Transaction Rates Bandwidth
Read-Only
Efficiency
x36 x18 x36 x18 x36 x18
SigmaQuad-IIIe
2-word burst
700 MHz 725 MHz
1.4BT/s 1.45BT/s 100Gb/s 52Gb/s 50%
SigmaQuad-IIIe
4-word burst 700MT/s 725MT/s 100Gb/s 52Gb/s 50%
SigmaDDR-IIIe
2-word burst 700MT/s 725MT/s 50Gb/s 26Gb/s 100%
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SigmaQuad-IIIe/SigmaDDR-IIIe SRAMs: Advantage #1—Reuse What Works
• BGA Package with 1 mm Pad Pitch
• No special assembly requirements
• Conventional Control Truth Table
• Familiar Read and Write protocols
• Echo Clocks and Output Valid Signals
• DLL-controlled Output Data timing
• Programmable Output Driver Impedance
• ZQ control of Output impedance
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SigmaQuad-IIIe/SigmaDDR-IIIe SRAMs: Advantage #2—Improvements on
Earlier Generations
• Better Signal Integrity
• Larger Output Data Valid Window
• New High Performance Pinout
• User-programmable ODT (On-Die Input Termination)
• Programmable value
• Selectable input pin coverage
• KD & KD# Data Input Clocks
• Lower Signaling and Core Power Consumption
• 1.3 V/1.35 V VDD
• 1.2 V JEDEC BIC thru 1.5 V JEDEC HSTL I/O
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Higher Performance Pinouts
SigmaQuad/DDR: I, II, II+ SigmaQuad/DDR: IIIe
165 BGA :
11 x 15 Array, 15 x 17 mm, 1 mm pitch
260 BGA:
13 x 20 Array, 14 x 22 mm, 1 mm pitch
1 2 3 4 5 6 7 8 9 10 11 12 13
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
1 2 3 4 5 6 7 8 9 10 11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
Key
VDD
VDDQ
VREF
VSS
A
CTRL
D
Q,CQ
CK
JTAG
MISC
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Improved Data Valid Windows
165 BGA @ 333 MHz
40ohm driver; 60ohm thevenin termination
666 MHz data rate; 1.5 V output voltage
Result: ~780ps eye @ 1500ps Tcycle
52% data valid window
Modern 260 BGA @ 500 MHz
40ohm driver; 60ohm thevenin termination
1.0 GHz data rate; 1.2 V output voltage
Result: ~760ps eye @ 1000ps Tcycle
76% data valid window
~780ps
~760ps
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SigmaQuad-IIIe/SigmaDDR-IIIe SRAMs: A Solid Migration Path (1/2)
260-ball, 1 mm pitch BGA
72Mbit
144Mbit
288Mbit Device Options 72Mb 144Mb 288Mb
SIO-B2, x18/x36, RL = 3 725 MHz 675 MHz 500+ MHz
SIO-B4, x18/x36, RL = 3 725 MHz 675 MHz 633+ MHz
CIO-B2, x18/x36, RL = 3 725 MHz 675 MHz 633+ MHz
Additional Options
On Chip ECC √ √ -
Write Data Input Clocks √ √ √
Supply Voltage Plans
VDD 1.3 V/1.35 V 1.2 V/1.25 V 1.2 V/1.25 V
1.5 V HSTL 1.5 V HSTL 1.5 V HSTL
1.35 V HSTL - -
1.2 V HSTL 1.2 V HSTL 1.2 V HSTL
VDDQ
2013 Introduction
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SigmaQuad-IIIe/SigmaDDR-IIIe SRAMs: A Solid Migration Path (2/2)
SigmaQuad B2 72Mb IIIe 144Mb IIIe 288Mb IIIe
Read Latency 2 3 3 3
Write Latency 0 0 0 0
Clock Frequency 450 MHz 725 MHz 675 MHz 500 MHz
Address Rate 900 MHz 1450 MHz 1350 MHz 1000 MHz
Data Rate 900 MHz 1450 MHz 1350 MHz 1000 MHz
SigmaQuad B4 72Mb IIIe 144Mb IIIe 288Mb IIIe
Read Latency 2 3 3 3
Write Latency 1 1 -1 1
Clock Frequency 450 MHz 725MHz 675 MHz 633 MHz
Address Rate 450 MHz 725 MHz 675 MHz 633 MHz
Data Rate 900 MHz 1450 MHz 1350 MHz 1266 MHz
SigmaDDR B2 72Mb IIIe 144Mb IIIe 288Mb IIIe
Read Latency 2 3 3 3
Write Latency 1 1 1 1
Clock Frequency 450 MHz 725MHz 675 MHz 633 MHz
Address Rate 450 MHz 725 MHz 675 MHz 633 MHz
Data Rate 900 MHz 1450 MHz 1350 MHz 1266 MHz
2013 Introduction
260-ball, 1 mm pitch BGA
72Mbit
144Mbit
288Mbit
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Design Schedules
13
More Questions?
Features, downloads, documentation:
IIIeinfo@gsitechnology.com
IP installation / tuning / debug:
apps@gsitechnology.com
Thank You.
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