new power saving design method for cmos flash adc institute of computer, communication and control,...

New Power Saving Design Method for CMOS Flash ADC

Institute of Computer, Communication and Control, Circuits and Systems, July 2004 IEEE

班級 ：積體碩一姓名 ：黃順和

學號 ： 95662009

outline

1. Introduction 2. Proposed Method 3. Simulation Results 4. Conclusions 5. References

Introduction The flash ADC has very high data conversion

speed, low-resolution and large chip area along with large power dissipation.

The 2n-1 comparators in flash ADC also cost too large area and lead much power consumption.

we got an idea from bisection method to let only half of comparators working in every clock cycle for reducing the power consumption.

A traditional flash ADC architecture

Proposed Method we use a comparator-based inverter Inv along with

an NOMS and a PMOS as switches.

Vin < Vref/2, the upper half of thermometer codes will be set all 0.

Vin > Vref/2, the lower half of thermometer codes will be set all 1.

Thermometer codes of Vin<Vref/2 and Vin>Vref/2

Proposed circuit of 6-bit flash ADC

The operation of 6-bit flash ADC at Vin<Vref/2

The operation of 6-bit flash ADC at Vin>Vref/2

The comparator in proposed ADC

Simulation Results The simulations are made in the same condition, t

hat are, input sine-wave signal operating at 20MHz along with Vp-p,=2V,Vref=2V, clock rate at 200MHz, and power supply on 3.3V.

the power consumptions are 71.72mW and 40.75mW from the traditional ADC and our proposed ADC.

Their linearity is well controlled with in ±1LSB.

Specifications of two flash ADC

The DNL of our proposed flash ADC

The INL of our proposed flash ADC

Conclusions Our proposed circuit needs only a comparator-

based inverter along with an NMOS and a PMOS as switches

The power saving of near 50% matches our prediction that shows the encourage.

The chip size is about 1.4*1.6mm2 in 0.35μm technology and the chip layout is shown in Fig.

References [1] P. C. S. Scholtens and M. Vertregt, ”A 6-b 1.6-Gsampleh fl

ash ADC in 0.18 pm CMOS using averaging termination,” IEEE Journal of Solid-state Circuits, Vol. 37, Dec. 2002, pp.1599-1609

[2] Yoo Jincheol, Lee Daegyu, Choi Kyusun and Kim Jongsoo, ”A power and resolution adaptive flash analog-to-digital converter,” International Symposium on Low Power Electronics and Design, Aug. 2002, pp. 233-236.

[3] J. Terada, Y. Matsuya, F. Morisawa and Y.Kado, “8-mW, 1-V, 100-Msps, 6-bit A/D Converter using a trans-conductance latched comparator,” Proceedings of the Second IEEE Asia Pacific Conference on ASIC, Aug. 2000, pp.53-56