number systems and arithmeticcseweb.ucsd.edu/classes/wi13/cse141-b/slides/04-mathalu.pdf ·...
Post on 08-Feb-2018
232 Views
Preview:
TRANSCRIPT
Number Systems and Arithmetic
Jason Mars
Thursday, January 24, 13
What do all those bits mean?
bits (011011011100010 ....01)
instruction
R-format I-format ...
data
number text chars ..............
integer floating point
signed unsigned single precision double precision
... ... ... ...
Thursday, January 24, 13
Questions About Numbers
• How do you represent• negative numbers?• fractions?• really large numbers?• really small numbers?
• How do you• do arithmetic?• identify errors (e.g. overflow)?
• What is an ALU and what does it look like?• ALU=arithmetic logic unit
Thursday, January 24, 13
Introduction to Binary Numbers
• Consider a 4 bit binary number
• Examples of binary arithmetic
Binary Binary Decimal 0 0000 1 0001 2 0010 3 0011
Decimal 4 0100 5 0101 6 0110 7 0111
0 0 1 1
0 0 1 0 +
1
0 0 1 1
0 0 1 1 +
1 1
3 + 2 = 5 3 + 3 = 6
Thursday, January 24, 13
Introduction to Binary Numbers
• Consider a 4 bit binary number
• Examples of binary arithmetic
Binary Binary Decimal 0 0000 1 0001 2 0010 3 0011
Decimal 4 0100 5 0101 6 0110 7 0111
0 0 1 1
0 0 1 0 +
1
0 0 1 1
0 0 1 1 +
1 1
3 + 2 = 5 3 + 3 = 6
1
Thursday, January 24, 13
Introduction to Binary Numbers
• Consider a 4 bit binary number
• Examples of binary arithmetic
Binary Binary Decimal 0 0000 1 0001 2 0010 3 0011
Decimal 4 0100 5 0101 6 0110 7 0111
0 0 1 1
0 0 1 0 +
1
0 0 1 1
0 0 1 1 +
1 1
3 + 2 = 5 3 + 3 = 6
0 1
Thursday, January 24, 13
Introduction to Binary Numbers
• Consider a 4 bit binary number
• Examples of binary arithmetic
Binary Binary Decimal 0 0000 1 0001 2 0010 3 0011
Decimal 4 0100 5 0101 6 0110 7 0111
0 0 1 1
0 0 1 0 +
1
0 0 1 1
0 0 1 1 +
1 1
3 + 2 = 5 3 + 3 = 6
0 11
Thursday, January 24, 13
Introduction to Binary Numbers
• Consider a 4 bit binary number
• Examples of binary arithmetic
Binary Binary Decimal 0 0000 1 0001 2 0010 3 0011
Decimal 4 0100 5 0101 6 0110 7 0111
0 0 1 1
0 0 1 0 +
1
0 0 1 1
0 0 1 1 +
1 1
3 + 2 = 5 3 + 3 = 6
0 011
Thursday, January 24, 13
Introduction to Binary Numbers
• Consider a 4 bit binary number
• Examples of binary arithmetic
Binary Binary Decimal 0 0000 1 0001 2 0010 3 0011
Decimal 4 0100 5 0101 6 0110 7 0111
0 0 1 1
0 0 1 0 +
1
0 0 1 1
0 0 1 1 +
1 1
3 + 2 = 5 3 + 3 = 6
0 0111
Thursday, January 24, 13
Introduction to Binary Numbers
• Consider a 4 bit binary number
• Examples of binary arithmetic
Binary Binary Decimal 0 0000 1 0001 2 0010 3 0011
Decimal 4 0100 5 0101 6 0110 7 0111
0 0 1 1
0 0 1 0 +
1
0 0 1 1
0 0 1 1 +
1 1
3 + 2 = 5 3 + 3 = 6
0 1 0111
Thursday, January 24, 13
Negative Numbers?
• We would like a number system that provides
• obvious representation of 0,1,2...
• uses adder for addition
• single value of 0
• equal coverage of positive and negative numbers
• easy detection of sign
• easy negation
Thursday, January 24, 13
Two’s Complement Representation
• 2’s complement representation of negative numbers• Take the bitwise inverse and add 1• Biggest 4-bit Binary Number: 7 Smallest 4-bit Binary Number: -8
Decimal -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7
Two�s Complement Binary 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111
Thursday, January 24, 13
Two’s Complement Arithmetic (Subtraction)2�s Complement Binary 2�s Complement Binary Decimal
0 0000 1 0001 2 0010 3 0011
1111 1110 1101
Decimal -1 -2 -3
4 0100 5 0101 6 0110 7 0111
1100 1011 1010 1001
-4 -5 -6 -7
1000 -8
Examples: 7 - 6 = 7 + (- 6) = 1 3 - 5 = 3 + (- 5) = -2
0 1 1 1
1 0 1 0 +
0 0 1 1
1 0 1 1 +
Thursday, January 24, 13
Two’s Complement Arithmetic (Subtraction)2�s Complement Binary 2�s Complement Binary Decimal
0 0000 1 0001 2 0010 3 0011
1111 1110 1101
Decimal -1 -2 -3
4 0100 5 0101 6 0110 7 0111
1100 1011 1010 1001
-4 -5 -6 -7
1000 -8
Examples: 7 - 6 = 7 + (- 6) = 1 3 - 5 = 3 + (- 5) = -2
0 1 1 1
1 0 1 0 +
0 0 1 1
1 0 1 1 +
1Thursday, January 24, 13
Two’s Complement Arithmetic (Subtraction)2�s Complement Binary 2�s Complement Binary Decimal
0 0000 1 0001 2 0010 3 0011
1111 1110 1101
Decimal -1 -2 -3
4 0100 5 0101 6 0110 7 0111
1100 1011 1010 1001
-4 -5 -6 -7
1000 -8
Examples: 7 - 6 = 7 + (- 6) = 1 3 - 5 = 3 + (- 5) = -2
0 1 1 1
1 0 1 0 +
0 0 1 1
1 0 1 1 +
0 1Thursday, January 24, 13
Two’s Complement Arithmetic (Subtraction)2�s Complement Binary 2�s Complement Binary Decimal
0 0000 1 0001 2 0010 3 0011
1111 1110 1101
Decimal -1 -2 -3
4 0100 5 0101 6 0110 7 0111
1100 1011 1010 1001
-4 -5 -6 -7
1000 -8
Examples: 7 - 6 = 7 + (- 6) = 1 3 - 5 = 3 + (- 5) = -2
0 1 1 1
1 0 1 0 +
0 0 1 1
1 0 1 1 +
0 1
1
Thursday, January 24, 13
Two’s Complement Arithmetic (Subtraction)2�s Complement Binary 2�s Complement Binary Decimal
0 0000 1 0001 2 0010 3 0011
1111 1110 1101
Decimal -1 -2 -3
4 0100 5 0101 6 0110 7 0111
1100 1011 1010 1001
-4 -5 -6 -7
1000 -8
Examples: 7 - 6 = 7 + (- 6) = 1 3 - 5 = 3 + (- 5) = -2
0 1 1 1
1 0 1 0 +
0 0 1 1
1 0 1 1 +
0 1
1
0Thursday, January 24, 13
Two’s Complement Arithmetic (Subtraction)2�s Complement Binary 2�s Complement Binary Decimal
0 0000 1 0001 2 0010 3 0011
1111 1110 1101
Decimal -1 -2 -3
4 0100 5 0101 6 0110 7 0111
1100 1011 1010 1001
-4 -5 -6 -7
1000 -8
Examples: 7 - 6 = 7 + (- 6) = 1 3 - 5 = 3 + (- 5) = -2
0 1 1 1
1 0 1 0 +
0 0 1 1
1 0 1 1 +
0 1
1
0
1
Thursday, January 24, 13
Two’s Complement Arithmetic (Subtraction)2�s Complement Binary 2�s Complement Binary Decimal
0 0000 1 0001 2 0010 3 0011
1111 1110 1101
Decimal -1 -2 -3
4 0100 5 0101 6 0110 7 0111
1100 1011 1010 1001
-4 -5 -6 -7
1000 -8
Examples: 7 - 6 = 7 + (- 6) = 1 3 - 5 = 3 + (- 5) = -2
0 1 1 1
1 0 1 0 +
0 0 1 1
1 0 1 1 +
0 1
1
0
1
0Thursday, January 24, 13
Two’s Complement Arithmetic (Subtraction)2�s Complement Binary 2�s Complement Binary Decimal
0 0000 1 0001 2 0010 3 0011
1111 1110 1101
Decimal -1 -2 -3
4 0100 5 0101 6 0110 7 0111
1100 1011 1010 1001
-4 -5 -6 -7
1000 -8
Examples: 7 - 6 = 7 + (- 6) = 1 3 - 5 = 3 + (- 5) = -2
0 1 1 1
1 0 1 0 +
0 0 1 1
1 0 1 1 +
0 01
1
0
1
0Thursday, January 24, 13
Two’s Complement Arithmetic (Subtraction)2�s Complement Binary 2�s Complement Binary Decimal
0 0000 1 0001 2 0010 3 0011
1111 1110 1101
Decimal -1 -2 -3
4 0100 5 0101 6 0110 7 0111
1100 1011 1010 1001
-4 -5 -6 -7
1000 -8
Examples: 7 - 6 = 7 + (- 6) = 1 3 - 5 = 3 + (- 5) = -2
0 1 1 1
1 0 1 0 +
0 0 1 1
1 0 1 1 +
0 01
1
0
1
0
1
Thursday, January 24, 13
Two’s Complement Arithmetic (Subtraction)2�s Complement Binary 2�s Complement Binary Decimal
0 0000 1 0001 2 0010 3 0011
1111 1110 1101
Decimal -1 -2 -3
4 0100 5 0101 6 0110 7 0111
1100 1011 1010 1001
-4 -5 -6 -7
1000 -8
Examples: 7 - 6 = 7 + (- 6) = 1 3 - 5 = 3 + (- 5) = -2
0 1 1 1
1 0 1 0 +
0 0 1 1
1 0 1 1 +
0 011
1
0
1
0
1
Thursday, January 24, 13
Two’s Complement Arithmetic (Subtraction)2�s Complement Binary 2�s Complement Binary Decimal
0 0000 1 0001 2 0010 3 0011
1111 1110 1101
Decimal -1 -2 -3
4 0100 5 0101 6 0110 7 0111
1100 1011 1010 1001
-4 -5 -6 -7
1000 -8
Examples: 7 - 6 = 7 + (- 6) = 1 3 - 5 = 3 + (- 5) = -2
0 1 1 1
1 0 1 0 +
0 0 1 1
1 0 1 1 +
0 011
1
0
1
0
11
Thursday, January 24, 13
Two’s Complement Arithmetic (Subtraction)2�s Complement Binary 2�s Complement Binary Decimal
0 0000 1 0001 2 0010 3 0011
1111 1110 1101
Decimal -1 -2 -3
4 0100 5 0101 6 0110 7 0111
1100 1011 1010 1001
-4 -5 -6 -7
1000 -8
Examples: 7 - 6 = 7 + (- 6) = 1 3 - 5 = 3 + (- 5) = -2
0 1 1 1
1 0 1 0 +
0 0 1 1
1 0 1 1 +
0 1 011
1
0
1
0
11
Thursday, January 24, 13
Two’s Complement Arithmetic (Subtraction)2�s Complement Binary 2�s Complement Binary Decimal
0 0000 1 0001 2 0010 3 0011
1111 1110 1101
Decimal -1 -2 -3
4 0100 5 0101 6 0110 7 0111
1100 1011 1010 1001
-4 -5 -6 -7
1000 -8
Examples: 7 - 6 = 7 + (- 6) = 1 3 - 5 = 3 + (- 5) = -2
0 1 1 1
1 0 1 0 +
0 0 1 1
1 0 1 1 +
0 1 011
1
0
1
0
11
1Thursday, January 24, 13
Some Things We Want To Know About Our Number System
• Negation
• Sign extension
• +3 => 0011, 00000011, 0000000000000011
• -3 => 1101, 11111101, 1111111111111101
• Overflow detection 0101 5+ 0110 6
Thursday, January 24, 13
Some Things We Want To Know About Our Number System
• Negation
• Sign extension
• +3 => 0011, 00000011, 0000000000000011
• -3 => 1101, 11111101, 1111111111111101
• Overflow detection 0101 5+ 0110 6
1
Thursday, January 24, 13
Some Things We Want To Know About Our Number System
• Negation
• Sign extension
• +3 => 0011, 00000011, 0000000000000011
• -3 => 1101, 11111101, 1111111111111101
• Overflow detection 0101 5+ 0110 6
11
Thursday, January 24, 13
Some Things We Want To Know About Our Number System
• Negation
• Sign extension
• +3 => 0011, 00000011, 0000000000000011
• -3 => 1101, 11111101, 1111111111111101
• Overflow detection 0101 5+ 0110 6
011
Thursday, January 24, 13
Some Things We Want To Know About Our Number System
• Negation
• Sign extension
• +3 => 0011, 00000011, 0000000000000011
• -3 => 1101, 11111101, 1111111111111101
• Overflow detection 0101 5+ 0110 6
0111
Thursday, January 24, 13
Some Things We Want To Know About Our Number System
• Negation
• Sign extension
• +3 => 0011, 00000011, 0000000000000011
• -3 => 1101, 11111101, 1111111111111101
• Overflow detection 0101 5+ 0110 6
0111 -5
Thursday, January 24, 13
Some Things We Want To Know About Our Number System
• Negation
• Sign extension
• +3 => 0011, 00000011, 0000000000000011
• -3 => 1101, 11111101, 1111111111111101
• Overflow detection 0101 5+ 0110 6
0111 -5
Thursday, January 24, 13
Overflow Detection
• How do we detect overflow?• XOR Carry In and Carry Out of MSB
0 1 1 1
0 0 1 1 +
1 0 1 0
1
1 1 0 0
1 0 1 1 +
0 1 1 1
1 1 0
7 3
1
-6
- 4 - 5
7
0
0 0 1 0
0 0 1 1 +
0 1 0 1
1
1 1 0 0
1 1 1 0 +
1 0 1 0
1 0 0
2
3
0
5
- 4
- 2
- 6
1 0 0
1 0
Thursday, January 24, 13
Overflow Detection
• How do we detect overflow?• XOR Carry In and Carry Out of MSB
0 1 1 1
0 0 1 1 +
1 0 1 0
1
1 1 0 0
1 0 1 1 +
0 1 1 1
1 1 0
7 3
1
-6
- 4 - 5
7
0
0 0 1 0
0 0 1 1 +
0 1 0 1
1
1 1 0 0
1 1 1 0 +
1 0 1 0
1 0 0
2
3
0
5
- 4
- 2
- 6
1 0 0
1 0
OK
Thursday, January 24, 13
Overflow Detection
• How do we detect overflow?• XOR Carry In and Carry Out of MSB
0 1 1 1
0 0 1 1 +
1 0 1 0
1
1 1 0 0
1 0 1 1 +
0 1 1 1
1 1 0
7 3
1
-6
- 4 - 5
7
0
0 0 1 0
0 0 1 1 +
0 1 0 1
1
1 1 0 0
1 1 1 0 +
1 0 1 0
1 0 0
2
3
0
5
- 4
- 2
- 6
1 0 0
1 0
OK
Not OK
Thursday, January 24, 13
Arithmetic -- The Heart of Instruction Execution
32
32
32
operation
result
a
b
ALU
Instruction Fetch
Instruction Decode
Operand Fetch
Execute
Result Store
Next Instruction
Thursday, January 24, 13
Designing an Arithmetic Logic Unit
AL
U
N
N
N
A
B
Result
Overflow
Zero
3 ALUop
CarryOut
ALU Control Lines (ALUop) Function000 And001 Or010 Add110 Subtract111 Set-on-less-than
Thursday, January 24, 13
A One Bit ALU
• This 1-bit ALU will perform AND, OR, and ADD
1 1 0 0
1 1 1 0 +
1 0 1 0
1
- 4
- 2
- 6
1 0 0
Thursday, January 24, 13
A One Bit ALU
• This 1-bit ALU will perform AND, OR, and ADD
1 1 0 0
1 1 1 0 +
1 0 1 0
1
- 4
- 2
- 6
1 0 0
Thursday, January 24, 13
A One Bit ALU
• This 1-bit ALU will perform AND, OR, and ADD
1 1 0 0
1 1 1 0 +
1 0 1 0
1
- 4
- 2
- 6
1 0 0
1
0
Thursday, January 24, 13
A One Bit ALU
• This 1-bit ALU will perform AND, OR, and ADD
1 1 0 0
1 1 1 0 +
1 0 1 0
1
- 4
- 2
- 6
1 0 0
10
Thursday, January 24, 13
A One Bit ALU
• This 1-bit ALU will perform AND, OR, and ADD
1 1 0 0
1 1 1 0 +
1 0 1 0
1
- 4
- 2
- 6
1 0 0
10
Thursday, January 24, 13
A One Bit ALU
• This 1-bit ALU will perform AND, OR, and ADD
1 1 0 0
1 1 1 0 +
1 0 1 0
1
- 4
- 2
- 6
1 0 0
Thursday, January 24, 13
A One Bit ALU
• This 1-bit ALU will perform AND, OR, and ADD
1 1 0 0
1 1 1 0 +
1 0 1 0
1
- 4
- 2
- 6
1 0 0
1
Thursday, January 24, 13
A One Bit ALU
• This 1-bit ALU will perform AND, OR, and ADD
1 1 0 0
1 1 1 0 +
1 0 1 0
1
- 4
- 2
- 6
1 0 0
1
Thursday, January 24, 13
A One Bit ALU
• This 1-bit ALU will perform AND, OR, and ADD
1 1 0 0
1 1 1 0 +
1 0 1 0
1
- 4
- 2
- 6
1 0 0
1
0
Thursday, January 24, 13
A One Bit ALU
• This 1-bit ALU will perform AND, OR, and ADD
1 1 0 0
1 1 1 0 +
1 0 1 0
1
- 4
- 2
- 6
1 0 0
1
0
Thursday, January 24, 13
32 Bit ALU
1-bit ALU 32-bit ALU
Thursday, January 24, 13
Relationship Between ISAs and ALUs
32
32
32
operation
result
a
b
ALU
Instruction Fetch
Instruction Decode
Operand Fetch
Execute
Result Store
Next Instruction
Thursday, January 24, 13
Relationship Between ISAs and ALUs
• After Decode• Implements All Arithmetic Execution• Inputs
• Source Operands, Registers• Destination
• Destination Operand
32
32
32
operation
result
a
b
ALU
Instruction Fetch
Instruction Decode
Operand Fetch
Execute
Result Store
Next Instruction
Thursday, January 24, 13
Relationship Between ISAs and ALUs
• After Decode• Implements All Arithmetic Execution• Inputs
• Source Operands, Registers• Destination
• Destination Operand
• Will all come together with single cycle cpu, I promise ;-)
32
32
32
operation
result
a
b
ALU
Instruction Fetch
Instruction Decode
Operand Fetch
Execute
Result Store
Next Instruction
Thursday, January 24, 13
The ALU’s Job - A Few Example Operations
Thursday, January 24, 13
The ALU’s Job - A Few Example Operations
• And, Or, Addition
• add
Thursday, January 24, 13
The ALU’s Job - A Few Example Operations
• And, Or, Addition
• add
• Subtraction
• sub
Thursday, January 24, 13
The ALU’s Job - A Few Example Operations
• And, Or, Addition
• add
• Subtraction
• sub
• Set-on-less-than
• slt
Thursday, January 24, 13
The ALU’s Job - A Few Example Operations
• And, Or, Addition
• add
• Subtraction
• sub
• Set-on-less-than
• slt
• Branch-if-equal
• beq
Thursday, January 24, 13
Adding Subtraction
• Keep in mind the following:• (A - B) is the same as: A + (-B)• 2’s Complement negate: Take the inverse of every bit and add 1
• Bit-wise inverse of B is !B:• A - B = A + (-B) = A + (!B + 1) = A + !B + 1
Thursday, January 24, 13
Adding Subtraction
• Keep in mind the following:• (A - B) is the same as: A + (-B)• 2’s Complement negate: Take the inverse of every bit and add 1
• Bit-wise inverse of B is !B:• A - B = A + (-B) = A + (!B + 1) = A + !B + 1
Thursday, January 24, 13
Adding Subtraction
• Keep in mind the following:• (A - B) is the same as: A + (-B)• 2’s Complement negate: Take the inverse of every bit and add 1
• Bit-wise inverse of B is !B:• A - B = A + (-B) = A + (!B + 1) = A + !B + 1
Lets throw in NOR while we’re at it!
Thursday, January 24, 13
Adding Subtraction
• Keep in mind the following:• (A - B) is the same as: A + (-B)• 2’s Complement negate: Take the inverse of every bit and add 1
• Bit-wise inverse of B is !B:• A - B = A + (-B) = A + (!B + 1) = A + !B + 1
multiplexor in Figure C.5.8 to add an input for the slt result. We call that new input Less and use it only for slt.
The top drawing of Figure C.5.10 shows the new 1-bit ALU with the expanded multiplexor. From the description of slt above, we must connect 0 to the Less input for the upper 31 bits of the ALU, since those bits are always set to 0. What remains to consider is how to compare and set the least signifi cant bit for set on less than instructions.
What happens if we subtract b from a? If the difference is negative, then a < b since
(a ! b) < 0 " ((a ! b) + b) < (0 + b) " a < b
We want the least signifi cant bit of a set on less than operation to be a 1 if a < b; that is, a 1 if a ! b is negative and a 0 if it’s positive. This desired result corresponds exactly to the sign bit values: 1 means negative and 0 means positive. Following this line of argument, we need only connect the sign bit from the adder output to the least signifi cant bit to get set on less than.
Unfortunately, the Result output from the most signifi cant ALU bit in the top of Figure C.5.10 for the slt operation is not the output of the adder; the ALU out put for the slt operation is obviously the input value Less.
Binvert
a
b
CarryIn
CarryOut
Operation
1
0
2!
Result
1
0
Ainvert
1
0
FIGURE C.5.9 A 1-bit ALU that performs AND, OR, and addition on a and b or __ a and
__ b . By
selecting _ a (Ainvert = 1) and
__ b (Binvert = 1), we get a NOR b instead of a AND b.
C-32 Appendix C The Basics of Logic Design
AppendixC-9780123747501.indd 32AppendixC-9780123747501.indd 32 26/07/11 6:28 PM26/07/11 6:28 PM
Lets throw in NOR while we’re at it!
Thursday, January 24, 13
Adding Set-on-less-than
• We are mostly there!• A < B = (A - B) < 0
• If true, set LSB to 1, all others 0• Else, set all bits to 0
Thursday, January 24, 13
Adding Set-on-less-than
• We are mostly there!• A < B = (A - B) < 0
• If true, set LSB to 1, all others 0• Else, set all bits to 0
C.5 Constructing a Basic Arithmetic Logic Unit C-33
FIGURE C.5.10 (Top) A 1-bit ALU that performs AND, OR, and addition on a and b or b __ b , and
(bottom) a 1-bit ALU for the most signifi cant bit. The top drawing includes a direct input that is connected to perform the set on less than operation (see Figure C.5.11); the bottom has a direct output from the adder for the less than comparison called Set. (See Exercise C.24 at the end of this Appendix to see how to calculate overfl ow with fewer inputs.)
Binvert
a
b
CarryIn
CarryOut
Operation
1
0
2!
Result
1
0
Ainvert
1
0
3Less
Binvert
a
b
CarryIn
Operation
1
0
2!
Result
1
0
3Less
Overflowdetection
Set
Overflow
Ainvert
1
0
AppendixC-9780123747501.indd 33AppendixC-9780123747501.indd 33 26/07/11 6:28 PM26/07/11 6:28 PM
Thursday, January 24, 13
Adding Set-on-less-than
• We are mostly there!• A < B = (A - B) < 0
• If true, set LSB to 1, all others 0• Else, set all bits to 0
C.5 Constructing a Basic Arithmetic Logic Unit C-33
FIGURE C.5.10 (Top) A 1-bit ALU that performs AND, OR, and addition on a and b or b __ b , and
(bottom) a 1-bit ALU for the most signifi cant bit. The top drawing includes a direct input that is connected to perform the set on less than operation (see Figure C.5.11); the bottom has a direct output from the adder for the less than comparison called Set. (See Exercise C.24 at the end of this Appendix to see how to calculate overfl ow with fewer inputs.)
Binvert
a
b
CarryIn
CarryOut
Operation
1
0
2!
Result
1
0
Ainvert
1
0
3Less
Binvert
a
b
CarryIn
Operation
1
0
2!
Result
1
0
3Less
Overflowdetection
Set
Overflow
Ainvert
1
0
AppendixC-9780123747501.indd 33AppendixC-9780123747501.indd 33 26/07/11 6:28 PM26/07/11 6:28 PM
C.5 Constructing a Basic Arithmetic Logic Unit C-33
FIGURE C.5.10 (Top) A 1-bit ALU that performs AND, OR, and addition on a and b or b __ b , and
(bottom) a 1-bit ALU for the most signifi cant bit. The top drawing includes a direct input that is connected to perform the set on less than operation (see Figure C.5.11); the bottom has a direct output from the adder for the less than comparison called Set. (See Exercise C.24 at the end of this Appendix to see how to calculate overfl ow with fewer inputs.)
Binvert
a
b
CarryIn
CarryOut
Operation
1
0
2!
Result
1
0
Ainvert
1
0
3Less
Binvert
a
b
CarryIn
Operation
1
0
2!
Result
1
0
3Less
Overflowdetection
Set
Overflow
Ainvert
1
0
AppendixC-9780123747501.indd 33AppendixC-9780123747501.indd 33 26/07/11 6:28 PM26/07/11 6:28 PM
MSB
Thursday, January 24, 13
Adding Set-on-less-than
• We are mostly there!• A < B = (A - B) < 0
• If true, set LSB to 1, all others 0• Else, set all bits to 0
1 1 0 0 1 0 1 1 + 0 1 1 1
1 0 1 0
What about overflow?
C.5 Constructing a Basic Arithmetic Logic Unit C-33
FIGURE C.5.10 (Top) A 1-bit ALU that performs AND, OR, and addition on a and b or b __ b , and
(bottom) a 1-bit ALU for the most signifi cant bit. The top drawing includes a direct input that is connected to perform the set on less than operation (see Figure C.5.11); the bottom has a direct output from the adder for the less than comparison called Set. (See Exercise C.24 at the end of this Appendix to see how to calculate overfl ow with fewer inputs.)
Binvert
a
b
CarryIn
CarryOut
Operation
1
0
2!
Result
1
0
Ainvert
1
0
3Less
Binvert
a
b
CarryIn
Operation
1
0
2!
Result
1
0
3Less
Overflowdetection
Set
Overflow
Ainvert
1
0
AppendixC-9780123747501.indd 33AppendixC-9780123747501.indd 33 26/07/11 6:28 PM26/07/11 6:28 PM
C.5 Constructing a Basic Arithmetic Logic Unit C-33
FIGURE C.5.10 (Top) A 1-bit ALU that performs AND, OR, and addition on a and b or b __ b , and
(bottom) a 1-bit ALU for the most signifi cant bit. The top drawing includes a direct input that is connected to perform the set on less than operation (see Figure C.5.11); the bottom has a direct output from the adder for the less than comparison called Set. (See Exercise C.24 at the end of this Appendix to see how to calculate overfl ow with fewer inputs.)
Binvert
a
b
CarryIn
CarryOut
Operation
1
0
2!
Result
1
0
Ainvert
1
0
3Less
Binvert
a
b
CarryIn
Operation
1
0
2!
Result
1
0
3Less
Overflowdetection
Set
Overflow
Ainvert
1
0
AppendixC-9780123747501.indd 33AppendixC-9780123747501.indd 33 26/07/11 6:28 PM26/07/11 6:28 PM
MSB
Thursday, January 24, 13
Overflow Detection
• When is Overflow Possible?• Positive + Negative = Overflow Impossible• Negative + Positive = Overflow Impossible• Positive + Positive = Can Overflow• Negative + Negative = Can Overflow
Decimal -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7
Two�s Complement Binary 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111
Thursday, January 24, 13
Overflow Detection
• When is Overflow Possible?• Positive + Negative = Overflow Impossible• Negative + Positive = Overflow Impossible• Positive + Positive = Can Overflow• Negative + Negative = Can Overflow
Decimal -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7
Two�s Complement Binary 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111
• A Problem for SLT ( -7 < 6 ) -->
Thursday, January 24, 13
Overflow Detection
• When is Overflow Possible?• Positive + Negative = Overflow Impossible• Negative + Positive = Overflow Impossible• Positive + Positive = Can Overflow• Negative + Negative = Can Overflow
Decimal -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7
Two�s Complement Binary 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111
• A Problem for SLT ( -7 < 6 ) -->• -7 + (-6) = 3 -->
Thursday, January 24, 13
Overflow Detection
• When is Overflow Possible?• Positive + Negative = Overflow Impossible• Negative + Positive = Overflow Impossible• Positive + Positive = Can Overflow• Negative + Negative = Can Overflow
Decimal -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7
Two�s Complement Binary 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111
• A Problem for SLT ( -7 < 6 ) -->• -7 + (-6) = 3 --> • MSB=0 -->
Thursday, January 24, 13
Overflow Detection
• When is Overflow Possible?• Positive + Negative = Overflow Impossible• Negative + Positive = Overflow Impossible• Positive + Positive = Can Overflow• Negative + Negative = Can Overflow
Decimal -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7
Two�s Complement Binary 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111
• A Problem for SLT ( -7 < 6 ) -->• -7 + (-6) = 3 --> • MSB=0 --> • -7 > 6!!
Thursday, January 24, 13
Overflow Detection
• When is Overflow Possible?• Positive + Negative = Overflow Impossible• Negative + Positive = Overflow Impossible• Positive + Positive = Can Overflow• Negative + Negative = Can Overflow
0 1 1 1
0 0 1 1 +
1 0 1 0
1
1 1 0 0
1 0 1 1 +
0 1 1 1
1 1 0
7 3
1
-6
- 4 - 5
7
0
0 0 1 0
0 0 1 1 +
0 1 0 1
1
1 1 0 0
1 1 1 0 +
1 0 1 0
1 0 0
2
3
0
5
- 4
- 2
- 6
1 0 0
1 0
Decimal -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7
Two�s Complement Binary 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111
• A Problem for SLT ( -7 < 6 ) -->• -7 + (-6) = 3 --> • MSB=0 --> • -7 > 6!!
Thursday, January 24, 13
Overflow Detection
• When is Overflow Possible?• Positive + Negative = Overflow Impossible• Negative + Positive = Overflow Impossible• Positive + Positive = Can Overflow• Negative + Negative = Can Overflow
0 1 1 1
0 0 1 1 +
1 0 1 0
1
1 1 0 0
1 0 1 1 +
0 1 1 1
1 1 0
7 3
1
-6
- 4 - 5
7
0
0 0 1 0
0 0 1 1 +
0 1 0 1
1
1 1 0 0
1 1 1 0 +
1 0 1 0
1 0 0
2
3
0
5
- 4
- 2
- 6
1 0 0
1 0
OK
Decimal -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7
Two�s Complement Binary 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111
• A Problem for SLT ( -7 < 6 ) -->• -7 + (-6) = 3 --> • MSB=0 --> • -7 > 6!!
Thursday, January 24, 13
Overflow Detection
• When is Overflow Possible?• Positive + Negative = Overflow Impossible• Negative + Positive = Overflow Impossible• Positive + Positive = Can Overflow• Negative + Negative = Can Overflow
0 1 1 1
0 0 1 1 +
1 0 1 0
1
1 1 0 0
1 0 1 1 +
0 1 1 1
1 1 0
7 3
1
-6
- 4 - 5
7
0
0 0 1 0
0 0 1 1 +
0 1 0 1
1
1 1 0 0
1 1 1 0 +
1 0 1 0
1 0 0
2
3
0
5
- 4
- 2
- 6
1 0 0
1 0
OK
Not OK
Decimal -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7
Two�s Complement Binary 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111
• A Problem for SLT ( -7 < 6 ) -->• -7 + (-6) = 3 --> • MSB=0 --> • -7 > 6!!
Thursday, January 24, 13
Overflow Detection Logic
• Carry into MSB ! = Carry out of MSB• For a N-bit ALU: Overflow = CarryIn[N - 1] XOR CarryOut[N - 1]
A0
B0 1-bit ALU
Result0
CarryIn0
CarryOut0 A1
B1 1-bit ALU
Result1
CarryIn1
CarryOut1 A2
B2 1-bit ALU
Result2
CarryIn2
A3
B3 1-bit ALU
CarryIn3
CarryOut3
Result3
CarryOut2
X Y X XOR Y
0 0 0 0 1 1 1 0 1 1 1 0
Thursday, January 24, 13
Overflow Detection Logic
• Carry into MSB ! = Carry out of MSB• For a N-bit ALU: Overflow = CarryIn[N - 1] XOR CarryOut[N - 1]
A0
B0 1-bit ALU
Result0
CarryIn0
CarryOut0 A1
B1 1-bit ALU
Result1
CarryIn1
CarryOut1 A2
B2 1-bit ALU
Result2
CarryIn2
A3
B3 1-bit ALU
CarryIn3
CarryOut3
Result3
CarryOut2
X Y X XOR Y
0 0 0 0 1 1 1 0 1 1 1 0
Overflow
Thursday, January 24, 13
Adding Branch-if-equal
Thursday, January 24, 13
Adding Branch-if-equal
• Subtract to the rescue again!
Thursday, January 24, 13
Adding Branch-if-equal
• Subtract to the rescue again!
• If (A - B = 0) --> A = B
Thursday, January 24, 13
Adding Branch-if-equal
• Subtract to the rescue again!
• If (A - B = 0) --> A = B• Zero Detection Logic is just
one BIG NOR gate (for equality test)• Any non-zero input to the
NOR gate will cause its output to be zero
Thursday, January 24, 13
Adding Branch-if-equal
• Subtract to the rescue again!
• If (A - B = 0) --> A = B• Zero Detection Logic is just
one BIG NOR gate (for equality test)• Any non-zero input to the
NOR gate will cause its output to be zero
B.5 Constructing a Basic Arithmetic Logic Unit B-35
Thus, if we add hardware to test if the result is 0, we can test for equality. Thesimplest way is to OR all the outputs together and then send that signal throughan inverter:
Figure B.5.12 shows the revised 32-bit ALU. We can think of the combinationof the 1-bit Ainvert line, the 1-bit Binvert line, and the 2-bit Operation lines as 4-bit control lines for the ALU, telling it to perform add, subtract, AND, OR, or seton less than. Figure B.5.13 shows the ALU control lines and the correspondingALU operation.
FIGURE B.5.12 The final 32-bit ALU. This adds a Zero detector to Figure B.5.11.
Zero Result31 Result30 . . . Result2 Result1 Result0+ + + + + ( ) =
...
a0
Operation
CarryInALU0Less
CarryOut
b0
a1 CarryInALU1Less
CarryOut
b1
Result0
Result1
a2 CarryInALU2Less
CarryOut
b2
a31 CarryInALU31Less
b31
Result2
Result31
......
...
Bnegate
...
Ainvert
0
0
0 Overflow
...
Set
CarryIn...
...Zero
Thursday, January 24, 13
Full ALU
what signals accomplish: Binvert CIn Oper add? sub? and? or? beq? slt?
ALU
a
ALU operation
b
CarryOut
Zero
Result
Overflow
FIGURE C.5.14 The symbol commonly used to represent an ALU, as shown in Figure C.5.12. This symbol is also used to represent an adder, so it is normally labeled either with ALU or Adder.
module MIPSALU (ALUctl, A, B, ALUOut, Zero); input [3:0] ALUctl; input [31:0] A,B; output reg [31:0] ALUOut; output Zero;
assign Zero = (ALUOut==0); //Zero is true if ALUOut is 0 always @(ALUctl, A, B) begin //reevaluate if these change case (ALUctl) 0: ALUOut <= A & B; 1: ALUOut <= A | B; 2: ALUOut <= A + B; 6: ALUOut <= A - B; 7: ALUOut <= A < B ? 1 : 0; 12: ALUOut <= ~(A | B); // result is nor default: ALUOut <= 0; endcase endendmodule
FIGURE C.5.15 A Verilog behavioral defi nition of a MIPS ALU.
C.5 Constructing a Basic Arithmetic Logic Unit C-37
AppendixC-9780123747501.indd 37AppendixC-9780123747501.indd 37 26/07/11 6:28 PM26/07/11 6:28 PM
Thursday, January 24, 13
Full ALU
what signals accomplish: Binvert CIn Oper add? sub? and? or? beq? slt?
0 0 2
ALU
a
ALU operation
b
CarryOut
Zero
Result
Overflow
FIGURE C.5.14 The symbol commonly used to represent an ALU, as shown in Figure C.5.12. This symbol is also used to represent an adder, so it is normally labeled either with ALU or Adder.
module MIPSALU (ALUctl, A, B, ALUOut, Zero); input [3:0] ALUctl; input [31:0] A,B; output reg [31:0] ALUOut; output Zero;
assign Zero = (ALUOut==0); //Zero is true if ALUOut is 0 always @(ALUctl, A, B) begin //reevaluate if these change case (ALUctl) 0: ALUOut <= A & B; 1: ALUOut <= A | B; 2: ALUOut <= A + B; 6: ALUOut <= A - B; 7: ALUOut <= A < B ? 1 : 0; 12: ALUOut <= ~(A | B); // result is nor default: ALUOut <= 0; endcase endendmodule
FIGURE C.5.15 A Verilog behavioral defi nition of a MIPS ALU.
C.5 Constructing a Basic Arithmetic Logic Unit C-37
AppendixC-9780123747501.indd 37AppendixC-9780123747501.indd 37 26/07/11 6:28 PM26/07/11 6:28 PM
Thursday, January 24, 13
Full ALU
what signals accomplish: Binvert CIn Oper add? sub? and? or? beq? slt?
0 0 21 1 2
ALU
a
ALU operation
b
CarryOut
Zero
Result
Overflow
FIGURE C.5.14 The symbol commonly used to represent an ALU, as shown in Figure C.5.12. This symbol is also used to represent an adder, so it is normally labeled either with ALU or Adder.
module MIPSALU (ALUctl, A, B, ALUOut, Zero); input [3:0] ALUctl; input [31:0] A,B; output reg [31:0] ALUOut; output Zero;
assign Zero = (ALUOut==0); //Zero is true if ALUOut is 0 always @(ALUctl, A, B) begin //reevaluate if these change case (ALUctl) 0: ALUOut <= A & B; 1: ALUOut <= A | B; 2: ALUOut <= A + B; 6: ALUOut <= A - B; 7: ALUOut <= A < B ? 1 : 0; 12: ALUOut <= ~(A | B); // result is nor default: ALUOut <= 0; endcase endendmodule
FIGURE C.5.15 A Verilog behavioral defi nition of a MIPS ALU.
C.5 Constructing a Basic Arithmetic Logic Unit C-37
AppendixC-9780123747501.indd 37AppendixC-9780123747501.indd 37 26/07/11 6:28 PM26/07/11 6:28 PM
Thursday, January 24, 13
Full ALU
what signals accomplish: Binvert CIn Oper add? sub? and? or? beq? slt?
0 0 21 1 20 0 0
ALU
a
ALU operation
b
CarryOut
Zero
Result
Overflow
FIGURE C.5.14 The symbol commonly used to represent an ALU, as shown in Figure C.5.12. This symbol is also used to represent an adder, so it is normally labeled either with ALU or Adder.
module MIPSALU (ALUctl, A, B, ALUOut, Zero); input [3:0] ALUctl; input [31:0] A,B; output reg [31:0] ALUOut; output Zero;
assign Zero = (ALUOut==0); //Zero is true if ALUOut is 0 always @(ALUctl, A, B) begin //reevaluate if these change case (ALUctl) 0: ALUOut <= A & B; 1: ALUOut <= A | B; 2: ALUOut <= A + B; 6: ALUOut <= A - B; 7: ALUOut <= A < B ? 1 : 0; 12: ALUOut <= ~(A | B); // result is nor default: ALUOut <= 0; endcase endendmodule
FIGURE C.5.15 A Verilog behavioral defi nition of a MIPS ALU.
C.5 Constructing a Basic Arithmetic Logic Unit C-37
AppendixC-9780123747501.indd 37AppendixC-9780123747501.indd 37 26/07/11 6:28 PM26/07/11 6:28 PM
Thursday, January 24, 13
Full ALU
what signals accomplish: Binvert CIn Oper add? sub? and? or? beq? slt?
0 0 21 1 20 0 00 0 1
ALU
a
ALU operation
b
CarryOut
Zero
Result
Overflow
FIGURE C.5.14 The symbol commonly used to represent an ALU, as shown in Figure C.5.12. This symbol is also used to represent an adder, so it is normally labeled either with ALU or Adder.
module MIPSALU (ALUctl, A, B, ALUOut, Zero); input [3:0] ALUctl; input [31:0] A,B; output reg [31:0] ALUOut; output Zero;
assign Zero = (ALUOut==0); //Zero is true if ALUOut is 0 always @(ALUctl, A, B) begin //reevaluate if these change case (ALUctl) 0: ALUOut <= A & B; 1: ALUOut <= A | B; 2: ALUOut <= A + B; 6: ALUOut <= A - B; 7: ALUOut <= A < B ? 1 : 0; 12: ALUOut <= ~(A | B); // result is nor default: ALUOut <= 0; endcase endendmodule
FIGURE C.5.15 A Verilog behavioral defi nition of a MIPS ALU.
C.5 Constructing a Basic Arithmetic Logic Unit C-37
AppendixC-9780123747501.indd 37AppendixC-9780123747501.indd 37 26/07/11 6:28 PM26/07/11 6:28 PM
Thursday, January 24, 13
Full ALU
what signals accomplish: Binvert CIn Oper add? sub? and? or? beq? slt?
0 0 21 1 20 0 00 0 11 1 2
ALU
a
ALU operation
b
CarryOut
Zero
Result
Overflow
FIGURE C.5.14 The symbol commonly used to represent an ALU, as shown in Figure C.5.12. This symbol is also used to represent an adder, so it is normally labeled either with ALU or Adder.
module MIPSALU (ALUctl, A, B, ALUOut, Zero); input [3:0] ALUctl; input [31:0] A,B; output reg [31:0] ALUOut; output Zero;
assign Zero = (ALUOut==0); //Zero is true if ALUOut is 0 always @(ALUctl, A, B) begin //reevaluate if these change case (ALUctl) 0: ALUOut <= A & B; 1: ALUOut <= A | B; 2: ALUOut <= A + B; 6: ALUOut <= A - B; 7: ALUOut <= A < B ? 1 : 0; 12: ALUOut <= ~(A | B); // result is nor default: ALUOut <= 0; endcase endendmodule
FIGURE C.5.15 A Verilog behavioral defi nition of a MIPS ALU.
C.5 Constructing a Basic Arithmetic Logic Unit C-37
AppendixC-9780123747501.indd 37AppendixC-9780123747501.indd 37 26/07/11 6:28 PM26/07/11 6:28 PM
Thursday, January 24, 13
Full ALU
what signals accomplish: Binvert CIn Oper add? sub? and? or? beq? slt?
0 0 21 1 20 0 00 0 11 1 21 1 3
ALU
a
ALU operation
b
CarryOut
Zero
Result
Overflow
FIGURE C.5.14 The symbol commonly used to represent an ALU, as shown in Figure C.5.12. This symbol is also used to represent an adder, so it is normally labeled either with ALU or Adder.
module MIPSALU (ALUctl, A, B, ALUOut, Zero); input [3:0] ALUctl; input [31:0] A,B; output reg [31:0] ALUOut; output Zero;
assign Zero = (ALUOut==0); //Zero is true if ALUOut is 0 always @(ALUctl, A, B) begin //reevaluate if these change case (ALUctl) 0: ALUOut <= A & B; 1: ALUOut <= A | B; 2: ALUOut <= A + B; 6: ALUOut <= A - B; 7: ALUOut <= A < B ? 1 : 0; 12: ALUOut <= ~(A | B); // result is nor default: ALUOut <= 0; endcase endendmodule
FIGURE C.5.15 A Verilog behavioral defi nition of a MIPS ALU.
C.5 Constructing a Basic Arithmetic Logic Unit C-37
AppendixC-9780123747501.indd 37AppendixC-9780123747501.indd 37 26/07/11 6:28 PM26/07/11 6:28 PM
Thursday, January 24, 13
The Disadvantage of Ripple Carry
• The adder we just built is called a “Ripple Carry Adder”
• The carry bit may have to propagate from LSB to MSB
• Worst case delay for an N-bit RC adder: 2N-gate delay
A0
B0 1-bit ALU
Result0
CarryOut0 A1
B1 1-bit ALU
Result1
CarryIn1
CarryOut1 A2
B2 1-bit ALU
Result2
CarryIn2
A3
B3 1-bit ALU
Result3
CarryIn3
CarryOut3
CarryOut2
CarryIn0
If a · b · CarryIn is true, then all of the other three terms must also be true, so we can leave out this last term corresponding to the fourth line of the table. We can thus simplify the equation to
CarryOut = (b · CarryIn) + (a · CarryIn) + (a · b)
Figure C.5.5 shows that the hardware within the adder black box for CarryOut consists of three AND gates and one OR gate. The three AND gates correspond exactly to the three parenthesized terms of the formula above for CarryOut, and the OR gate sums the three terms.
Inputs
a b CarryIn
0 1 1
1 0 1
1 1 0
1 1 1
FIGURE C.5.4 Values of the inputs when CarryOut is a 1.
FIGURE C.5.5 Adder hardware for the CarryOut signal. The rest of the adder hardware is the logic for the Sum output given in the equation on this page.
a
b
CarryIn
CarryOut
The Sum bit is set when exactly one input is 1 or when all three inputs are 1. The Sum results in a complex Boolean equation (recall that
_ a means NOT a):
Sum = (a · __
b · _______
CarryIn ) + ( _ a · b ·
_______ CarryIn ) + (
_ a ·
__ b · CarryIn) + (a · b · CarryIn)
The drawing of the logic for the Sum bit in the adder black box is left as an exercise for the reader.
C-28 Appendix C The Basics of Logic Design
AppendixC-9780123747501.indd 28AppendixC-9780123747501.indd 28 26/07/11 6:28 PM26/07/11 6:28 PM
Thursday, January 24, 13
The Disadvantage of Ripple Carry
• The adder we just built is called a “Ripple Carry Adder”
• The carry bit may have to propagate from LSB to MSB
• Worst case delay for an N-bit RC adder: 2N-gate delay
A0
B0 1-bit ALU
Result0
CarryOut0 A1
B1 1-bit ALU
Result1
CarryIn1
CarryOut1 A2
B2 1-bit ALU
Result2
CarryIn2
A3
B3 1-bit ALU
Result3
CarryIn3
CarryOut3
CarryOut2
CarryIn0
If a · b · CarryIn is true, then all of the other three terms must also be true, so we can leave out this last term corresponding to the fourth line of the table. We can thus simplify the equation to
CarryOut = (b · CarryIn) + (a · CarryIn) + (a · b)
Figure C.5.5 shows that the hardware within the adder black box for CarryOut consists of three AND gates and one OR gate. The three AND gates correspond exactly to the three parenthesized terms of the formula above for CarryOut, and the OR gate sums the three terms.
Inputs
a b CarryIn
0 1 1
1 0 1
1 1 0
1 1 1
FIGURE C.5.4 Values of the inputs when CarryOut is a 1.
FIGURE C.5.5 Adder hardware for the CarryOut signal. The rest of the adder hardware is the logic for the Sum output given in the equation on this page.
a
b
CarryIn
CarryOut
The Sum bit is set when exactly one input is 1 or when all three inputs are 1. The Sum results in a complex Boolean equation (recall that
_ a means NOT a):
Sum = (a · __
b · _______
CarryIn ) + ( _ a · b ·
_______ CarryIn ) + (
_ a ·
__ b · CarryIn) + (a · b · CarryIn)
The drawing of the logic for the Sum bit in the adder black box is left as an exercise for the reader.
C-28 Appendix C The Basics of Logic Design
AppendixC-9780123747501.indd 28AppendixC-9780123747501.indd 28 26/07/11 6:28 PM26/07/11 6:28 PM
Faster Adders Possible: See C.6Thursday, January 24, 13
Teaser!! The ALU in Perspective
Thursday, January 24, 13
Teaser!! The ALU in Perspective
Thursday, January 24, 13
Teaser!! The ALU in Perspective
Single Cycle CPU Next Time!!Thursday, January 24, 13
top related