progress report flash adc probabilistic architecture
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Progress ReportFlash ADC Probabilistic Architecture
Yuta Toriyama
yuta@ee.ucla.eduAugust 10, 2012
2
The design of a variability-agnostic Flash ADC Using small devices and low supply voltages for a low-
power low-area design Architecture / calibration techniques to deal with large
amounts of variation Basic concept: Model each comparator as having a static
voltage offset at its input
Low Power Flash ADCs
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Probabilistic Approach
0
0
0
1
0
0
0
0
0
1
X
1
0
X
X
0
X
Enc
oder
Architectural design:– Allow only certain
comparators to be active– Turn off power to unused
comparators
Requirements:– Threshold values and
indexes of chosen comparators must be monotonically increasing
– Single 1 output to decoder
Logi
c
4
Represent the entire Flash architecture as a network Each comparator (or voltage at which it switches) is a
node
Network Formulation
, ,ij OS i OS je E i j V V
0
12
3
4
Comparator Index
Thr
esho
ld V
alue
(V
) 5
0
12
3
4
Comparator Index
Thr
esho
ld V
alue
(V
) 5
5
Any path from lowest to highest comparator in this network guarantees a monotonic sequence of active comparators To find an “optimum” path, assign weights to each edge
Network Formulation
0
12
3
4
Comparator Index
Thr
esho
ld V
alue
(V
) 5
0
12
3
4
Comparator Index
Thr
esho
ld V
alue
(V
) 5
6
LP Formulation & Simplex Algorithm
maximize cTx
s.t. Ax = [1 0 0 . . .-1]T
0 ≤ xi ≤ 1, i
x = vector s.t. xi{edge chosen (1), edge not chosen (0)} LP can be solved with Simplex Algorithm
Theoretical average-case complexity = O(|V|*|E|)
123456
arcs
no
de
s
= A
1-10000
100-100
1000-10
10000-1
0001-10
00010-1
010-100
0100-10
01000-1
0010-10
00100-1
00001-1
10-1000
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Dijkstra’s Algorithm
Solves single-source shortest path problem for networks with non-negative edge weights Simple implementation complexity = O(|V|2)
Balls (vertices) connected by strings (edges) of different lengths (weights)
0
12
43
50
12
3
4
Comparator Index
Thr
esho
ld V
alue
(V
) 5
8
FPGA Implementations
Dijkstra’s Algorithm: outperforms Simplex in time-to-solution uses much fewer resources in FPGA implementation than
an implementation of the Simplex algorithm
Hardware resourceUtilization
Simplex Algorithm Dijkstra’s Algorithm
Slice Register 10,107 / 58,880 (17%) 3735 / 58,880 ( 6%)
Slice LUT 10,884 / 58,880 (18%) 4406 / 58,880 ( 7%)
DSP48E 62 / 640 ( 9%) 11 / 640 ( 1%)
BlockRAM 62 / 244 (25%) 58 / 244 (23%)
32Mb SRAM (QDR) 1 / 1 (100%) 0 / 1 ( 0%)
Edge Weight Assignment
Calculate the noise power contribution of each arc:Vj
Allows for the inclusion of non-uniform distributions Does not take into account linearity
Ck =
Vi
for all k = {1,2,Numarcs}
di = 4
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DNL2
1
0
-10 5 10 15 3025 35 4020
INL5
0
-50 5 10 15 3025 35 4020
Code
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Look-Up Table
Currently the encoder output indicates the index for which comparator was toggled
Instead, we would like the output to indicate what analog voltage trips the comparators
Threshold voltages known from DAC measurements taken for foreground calibration
The
rmom
eter
to O
ne-H
ot, B
ubbl
e C
orre
ctio
n
Vin
Enc
oder
Dout
1
1
0
0
1
0
0
0
0
0
0
0
VFS
VFS2N
1
VFS2N
2N-3
VFS2N
2N-2
VFS2N
2N-1
VFS2N
2
N’bxxxx
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Look-Up Table
Add a look-up table at the output of encoder
Values filled in after calibration
Size of memory required ~1kb for # comparators = 1024 (based on number of active comparators after calibration)
The
rmom
eter
to O
ne-H
ot, B
ubbl
e C
orre
ctio
n
Vin
Enc
oder
Dout
1
1
0
0
1
0
0
0
0
0
0
0
VFS
Look
-Up
Tab
le
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New Graph Formulation
Divide threshold voltage axis into L equally-spaced regions
Find one comparator from each region, index of comparators still must be monotonically increasing
Cost = distance from midpoint of each region
0
12
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Comparator Index
Thr
esho
ld V
alue
(V
) 5
0
12
34
Comparator Index
Thr
esho
ld V
alue
(V
) 5
13
New Graph Formulation
ENOB, linearity improved
Conclusion
Dijkstra’s Algorithm leads to great improvement in calibration method
LUT-based calibration shows vast improvement in linearity over previous network formulation method
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