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EE582 Physical Design Automation of VLSI Circuits and Systems
Prof. Dae Hyun Kim
School of Electrical Engineering and Computer Science Washington State University
Routing
2 Physical Design Automation of VLSI Circuits and Systems
Grid Routing
3 Physical Design Automation of VLSI Circuits and Systems
Grid Routing
4 Physical Design Automation of VLSI Circuits and Systems
Grid Routing
5 Physical Design Automation of VLSI Circuits and Systems
Grid Routing
6 Physical Design Automation of VLSI Circuits and Systems
Grid Routing
• Lee’s algorithm (Maze routing) – Grid routing – If a path exists between two points, it is surely found. – It is guaranteed to be the shortest available path.
Filling (wave propagation)
Retrace
Label clearance
7 Physical Design Automation of VLSI Circuits and Systems
Grid Routing
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Grid Routing
• Filling
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Grid Routing
• Filling
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Grid Routing
• Filling
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Grid Routing
• Filling
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12 Physical Design Automation of VLSI Circuits and Systems
Grid Routing
• Filling
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14 Physical Design Automation of VLSI Circuits and Systems
Grid Routing
• Filling
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15 Physical Design Automation of VLSI Circuits and Systems
Grid Routing
• Filling
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16 Physical Design Automation of VLSI Circuits and Systems
Grid Routing
• Retrace
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17 Physical Design Automation of VLSI Circuits and Systems
Grid Routing
• Complexity – O(L2)
• L: the length of the path
18 Physical Design Automation of VLSI Circuits and Systems
Grid Routing
• How to reduce memory requirement (1,2,3,1,...)
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19 Physical Design Automation of VLSI Circuits and Systems
Grid Routing
• How to reduce memory requirement (1,1,2,2,...)
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20 Physical Design Automation of VLSI Circuits and Systems
Grid Routing
• How to reduce runtime
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21 Physical Design Automation of VLSI Circuits and Systems
Grid Routing
Starting point selection
Double fan-out Framing
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22 Physical Design Automation of VLSI Circuits and Systems
Grid Routing
• Speed-up – l(P) = MD(S, T) + 2d(P)
• l: the length of a path P • MD: Manhattan distance • d(P): detour number of a path P
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MD(S,T)=7 d(P)=4 l(P)=7+2*4=15
23 Physical Design Automation of VLSI Circuits and Systems
Grid Routing
• Hadlock’s algorithm
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24 Physical Design Automation of VLSI Circuits and Systems
Grid Routing
• Hadlock’s algorithm
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25 Physical Design Automation of VLSI Circuits and Systems
Grid Routing
• Hadlock’s algorithm
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26 Physical Design Automation of VLSI Circuits and Systems
Grid Routing
• Hadlock’s algorithm
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27 Physical Design Automation of VLSI Circuits and Systems
Grid Routing
• Soukup’s algorithm
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28 Physical Design Automation of VLSI Circuits and Systems
Grid Routing
• Soukup’s algorithm
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29 Physical Design Automation of VLSI Circuits and Systems
Grid Routing
• Soukup’s algorithm
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30 Physical Design Automation of VLSI Circuits and Systems
Grid Routing
• Soukup’s algorithm
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31 Physical Design Automation of VLSI Circuits and Systems
Steiner Routing
• Routing topology generation for multi-fanout nets
Steiner point
32 Physical Design Automation of VLSI Circuits and Systems
Steiner Routing
• Routing topology generation for multi-fanout nets
33 Physical Design Automation of VLSI Circuits and Systems
Steiner Routing
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34 Physical Design Automation of VLSI Circuits and Systems
Steiner Routing
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35 Physical Design Automation of VLSI Circuits and Systems
Steiner Routing
• FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design, TCAD’08
36 Physical Design Automation of VLSI Circuits and Systems
FLUTE
𝑥𝑥1 𝑥𝑥2 𝑥𝑥3 𝑥𝑥4 𝑥𝑥
𝑦𝑦
𝑦𝑦1
𝑦𝑦2
𝑦𝑦3
𝑦𝑦4
37 Physical Design Automation of VLSI Circuits and Systems
FLUTE
𝑥𝑥1 𝑥𝑥2 𝑥𝑥3 𝑥𝑥4 𝑥𝑥
𝑦𝑦
𝑦𝑦1
𝑦𝑦2
𝑦𝑦3
𝑦𝑦4
Horizontal edge
Vertical edge
ℎ1 ℎ2 ℎ3
𝑣𝑣1
𝑣𝑣2
𝑣𝑣3
38 Physical Design Automation of VLSI Circuits and Systems
FLUTE
𝑥𝑥1 𝑥𝑥2 𝑥𝑥3 𝑥𝑥4 𝑥𝑥
𝑦𝑦
𝑦𝑦1
𝑦𝑦2
𝑦𝑦3
𝑦𝑦4
Characterization of the topology: (3142)
𝑠𝑠1 = 3
𝑠𝑠2 = 1
𝑠𝑠3 = 4
𝑠𝑠4 = 2
39 Physical Design Automation of VLSI Circuits and Systems
FLUTE
(1234) (1243) (1324) (1342)
(1423) (1432) (2413) (4123)
40 Physical Design Automation of VLSI Circuits and Systems
FLUTE
WL=ℎ1 + 2ℎ2 + ℎ3 + 𝑣𝑣1 + 𝑣𝑣2 + 2𝑣𝑣3 WL=ℎ1 + ℎ2 + ℎ3 + 𝑣𝑣1 + 2𝑣𝑣2 + 3𝑣𝑣3 WL=ℎ1 + 2ℎ2 + ℎ3 + 𝑣𝑣1 + 𝑣𝑣2 + 𝑣𝑣3
WL=𝑎𝑎1ℎ1 + 𝑎𝑎2ℎ2 + 𝑎𝑎3ℎ3 + 𝑏𝑏1𝑣𝑣1 + 𝑏𝑏2𝑣𝑣2 + 𝑏𝑏3𝑣𝑣3
41 Physical Design Automation of VLSI Circuits and Systems
FLUTE
• Example
WL=ℎ1 + 2ℎ2 + ℎ3 + 𝑣𝑣1 + 𝑣𝑣2 + 𝑣𝑣3 = (1,2,1,1,1,1)
WL=ℎ1 + ℎ2 + ℎ3 + 𝑣𝑣1 + 2𝑣𝑣2 + 𝑣𝑣3 = (1,1,1,1,2,1)
42 Physical Design Automation of VLSI Circuits and Systems
FLUTE
• POST – Potentially Optimal Steiner Tree
• POWV
– Potentially Optimal Wirelength Vector
43 Physical Design Automation of VLSI Circuits and Systems
FLUTE
• POWV comparison
(1,2,1,1,1,1) (1,2,𝟐𝟐, 1,1,1)
44 Physical Design Automation of VLSI Circuits and Systems
FLUTE
• How to obtain the minimum-length Steiner tree – Create a look-up table. – When a topology is given, get the best one.
• How can we generate all POSTs?
– For low-degree nets (# points = 1, 2, 3, ...) • Enumerate all POSTs.
– For high-degree nets
• Use compaction.
45 Physical Design Automation of VLSI Circuits and Systems
FLUTE
• Boundary compaction
Left boundary compaction Steiner tree Expansion
46 Physical Design Automation of VLSI Circuits and Systems
FLUTE
Left boundary compaction Top boundary compaction
Steiner tree
Bottom boundary compaction
Right boundary
compaction
Expansion
Expansion Expansion Expansion
47 Physical Design Automation of VLSI Circuits and Systems
FLUTE
• Left boundary compaction
vs
48 Physical Design Automation of VLSI Circuits and Systems
ILP-Based Global Routing
• Problem formulation
1 1
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Capacity of each edge: 2
49 Physical Design Automation of VLSI Circuits and Systems
ILP-Based Global Routing
• Routing topology generation
Potential routing topologies for net 1
Potential routing topologies for net 2
Potential routing topologies for net 3
50 Physical Design Automation of VLSI Circuits and Systems
ILP-Based Global Routing
• ILP formulation – For net i, prepare a few routing topologies.
• 𝑡𝑡1𝑖𝑖 , 𝑡𝑡2𝑖𝑖 , … , 𝑡𝑡𝑛𝑛𝑖𝑖
– 𝑥𝑥𝑖𝑖,𝑗𝑗 • 1 if net i is routed according to topology 𝑡𝑡𝑗𝑗𝑖𝑖. • 0 otherwise.
– ∑ 𝑥𝑥𝑖𝑖,𝑗𝑗𝑗𝑗 = 1 • Only one routing topology is used.
51 Physical Design Automation of VLSI Circuits and Systems
ILP-Based Global Routing
• ILP formulation – Capacity constraints
• ∑∑𝑎𝑎𝑖𝑖,𝑝𝑝𝑥𝑥𝑙𝑙,𝑘𝑘 ≤ 𝑐𝑐𝑖𝑖
– Objective function • Minimize ∑∑𝑔𝑔𝑖𝑖,𝑗𝑗𝑥𝑥𝑖𝑖,𝑗𝑗
52 Physical Design Automation of VLSI Circuits and Systems
ILP-Based Global Routing
• Example
net 1
𝑥𝑥1,1 𝑥𝑥1,2 𝑥𝑥1,3
net 2
𝑥𝑥2,1 𝑥𝑥2,2 𝑥𝑥2,3
𝑥𝑥3,1 net 3
𝑥𝑥3,2
Minimize 2𝑥𝑥1,1 + 3𝑥𝑥1,2 + 3𝑥𝑥1,3 + 2𝑥𝑥2,1 + 3𝑥𝑥2,2 + 3𝑥𝑥2,3 + 2𝑥𝑥3,1 + 2𝑥𝑥3,2 Subject to 𝑥𝑥1,1 + 𝑥𝑥1,2 + 𝑥𝑥1,3 = 1 𝑥𝑥2,1 + 𝑥𝑥2,2 + 𝑥𝑥2,3 = 1 𝑥𝑥3,1 + 𝑥𝑥3,2 = 1 𝑥𝑥1,2 + 𝑥𝑥1,3 + 𝑥𝑥2,1 + 𝑥𝑥2,3 + 𝑥𝑥3,1 ≤ 2 𝑥𝑥1,1 + 𝑥𝑥1,3 + 𝑥𝑥2,2 + 𝑥𝑥2,3 + 𝑥𝑥3,2 ≤ 2 𝑥𝑥1,2 + 𝑥𝑥1,3 + 𝑥𝑥2,1 + 𝑥𝑥2,2 + 𝑥𝑥3,2 ≤ 2 𝑥𝑥1,1 + 𝑥𝑥1,2 + 𝑥𝑥2,2 + 𝑥𝑥2,3 + 𝑥𝑥3,1 ≤ 2 𝑥𝑥𝑖𝑖,𝑗𝑗 = 0, 1
53 Physical Design Automation of VLSI Circuits and Systems
Congestion Minimization
• Just satisfying the routing capacity of each edge does not guarantee 100% routability.
• Can we minimize routing congestion by ILP?
54 Physical Design Automation of VLSI Circuits and Systems
Congestion Minimization
• We minimize routing congestion by spreading wires out.
Minimize C Subject to 𝑥𝑥1,1 + 𝑥𝑥1,2 + 𝑥𝑥1,3 = 1 𝑥𝑥2,1 + 𝑥𝑥2,2 + 𝑥𝑥2,3 = 1 𝑥𝑥3,1 + 𝑥𝑥3,2 = 1 𝑥𝑥1,2 + 𝑥𝑥1,3 + 𝑥𝑥2,1 + 𝑥𝑥2,3 + 𝑥𝑥3,1 ≤ 𝐶𝐶 𝑥𝑥1,1 + 𝑥𝑥1,3 + 𝑥𝑥2,2 + 𝑥𝑥2,3 + 𝑥𝑥3,2 ≤ 𝐶𝐶 𝑥𝑥1,2 + 𝑥𝑥1,3 + 𝑥𝑥2,1 + 𝑥𝑥2,2 + 𝑥𝑥3,2 ≤ 𝐶𝐶 𝑥𝑥1,1 + 𝑥𝑥1,2 + 𝑥𝑥2,2 + 𝑥𝑥2,3 + 𝑥𝑥3,1 ≤ 𝐶𝐶 𝑥𝑥𝑖𝑖,𝑗𝑗 = 0, 1
net 1
𝑥𝑥1,1 𝑥𝑥1,2 𝑥𝑥1,3
net 2
𝑥𝑥2,1 𝑥𝑥2,2 𝑥𝑥2,3
𝑥𝑥3,1 net 3
𝑥𝑥3,2
55 Physical Design Automation of VLSI Circuits and Systems
Box Router
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