schematic,mlb,kalahari...e-net connector optic module j3900 x4 pcie gen1 lanes(2.5gbitps/lane) (port...
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3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
8
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT
3
B
7
ECNREV
BRANCH
DRAWING NUMBER
REVISION
SIZE
D
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
DRAWING TITLE
THE POSESSOR AGREES TO THE FOLLOWING:
Apple Inc.
SHEET
R
DATE
D
A
C
THE INFORMATION CONTAINED HEREIN IS THE
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
C
3456
D
B
8 7 6 5 4 2 1
12
APPDCK
DESCRIPTION OF REVISION
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DRAWING
DRAWING
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SCHEMATIC,MLB,"Kalahari"
1 OF 92
0000803841B
051-8233
B.0.0
1 OF 110
PRODUCTION RELEASED 2009-10-09
07/01/2009
K60_JERRY4852
SMBus Connections
07/01/2009
K60_SIJI4751
LPC+SPI Debug Connector
07/01/2009
K60_JERRY4650
SMC Support
07/01/2009
K60_JERRY4549
SMC
07/01/2009
K60_JERRY4447
Internal USB Connections
07/01/2009
K60_JERRY4346
EXTERNAL USB CONNECTORS
07/01/2009
K60_JERRY4245
SATA Connectors
07/16/2009
K23_AARON4143
FIREWIRE CONNECTOR
07/16/2009
K23_AARON4042
FW: 1394B MISC
07/16/2009
K23_AARON3941
FireWire LLC/PHY (XIO2213B)
07/01/2009
K60_AARON3839
ETHERNET CONNECTOR
07/01/2009
K60_AARON3738
CAESAR II SUPPORT
07/01/2009
K60_AARON3637
ETHERNET (CAESAR II)
07/01/2009
K60_AARON3536
USB HUB 2
07/01/2009
K60_AARON3435
USB HUB 1
07/16/2009
K23_AARON3334
PCI-E Wireless Connector
07/01/2009
K60_SIJI3233
DDR3 SUPPORT AND BITSWAPS
07/01/2009
K60_SIJI3132
DDR3 SO-DIMM CONNECTOR B
07/01/2009
K60_SIJI3031
DDR3 SO-DIMMs 0 & 2
07/01/2009
K60_SIJI2930
MEMORY CAPS
07/01/2009
K60_SIJI2829
DDR3 VREF MARGINING
07/01/2009
K60_SIJI2728
CHIPSET SUPPORT
07/01/2009
K60_SIJI2626
CLOCK (CK505)
07/01/2009
K60_SIJI2525
EXTENDED DEBUG PORT(XDP)
07/01/2009
K60_SIJI2424
PCH DECOUPLING
07/01/2009
K60_SIJI2323
PCH GROUNDS
07/01/2009
K60_SIJI2222
PCH POWER
07/01/2009
K60_SIJI2121
PCH MISC
07/01/2009
K60_SIJI2020
PCH PCI/FLASHCACHE/USB
07/01/2009
K60_SIJI1919
PCH DMI/FDI/GRAPHICS
07/01/2009
K60_SIJI1818
PCH SATA/PCIE/CLK/LPC/SPI
07/01/2009
K60_SIJI1717
CPU/PCH GFX DECOUPLING
07/01/2009
K60_SIJI1616
CPU NON-GFX DECOUPLING
07/01/2009
K60_SIJI1515
STRAPS,PULL UPS,PULL DOWNS FOR PCH AND CPU
07/01/2009
K60_SIJI1414
CPU GROUNDS
07/01/2009
K60_SIJI1313
CPU POWER
07/01/2009
K60_SIJI1212
CPU DDR3 INTERFACES
07/01/2009
K60_SIJI1111
CPU CLOCK/MISC/JTAG
07/01/2009
K60_SIJI1010
CPU DMI/PEG/FDI/RSVD
07/01/2009
K60_SIJI99
Signal Aliases
07/01/2009
K60_SIJI88
UNUSED SIGNAL ALIAS
07/01/2009
K60_SIJI77
Holes
07/01/2009
K60_SIJI66
Power Conn / Alias
07/01/2009
K60_MIKE55
PROTO 0 DEBUG LEDS
07/01/2009
K60_AARON44
BOM Configuration
07/01/2009
K60_MIKE33
Power Block Diagram
07/01/2009
K60_SIJI22
System Block Diagram
K22/K23 ICT/FCT110
K60_DEREK
07/01/2009
91PM RESETS ENABLES PGOOD CONST
109
K60_MIKE
07/01/2009
90POWER CONSTRAINTS
107
K60_JERRY
07/01/2009
89SMC Constraints
106
K60_JERRY
07/01/2009
88GRAPHICS CONSTRAINTS
105
K60_AARON
07/01/2009
87ENET/FIREWIRE CONSTRAINTS
104
K60_AARON
07/01/2009
86IBEX PEAK CONSTRAINTS
103
K60_SIJI
07/01/2009
85PCIE/DMI/FDI/SATA CONSTRAINTS
102
K60_SIJI
07/01/2009
84Memory Constraints
101
K60_MIKE
07/01/2009
83K60/K61 RULE DEFINITIONS
100
K60_DEREK
07/01/2009
82Display: BiDiVi Support
95
K23_AARON
07/16/2009
81Display: Ext DP Connector
94
K23_AARON
07/16/2009
80BIDIVI DP MUX2
92
K23_AARON
07/16/2009
79Display: BiDiVi Mux1
91
K23_AARON
07/16/2009
78Display: Int DP Connector
90
K23_AARON
07/16/2009
77Display: Aliases
87
K61_AARON
07/01/2009
76MXM PCIE CAPS
86
K60_AARON
07/01/2009
75MXM I/O
85
K23_AARON
07/16/2009
74MXM PCIe, DP & Power
84
K23_AARON
07/16/2009
73S3+S0 FETS
80
K60_MIKE
07/01/2009
721.05 S5 SUPPLY
79
K60_JERRY
07/01/2009
711.5V / 1.8V VREGS
78
K60_JERRY
07/01/2009
705V_S3 / 3V3_S5 VREGS
77
K60_JERRY
07/01/2009
69IBEX PEAK CORE
76
K60_JERRY
07/01/2009
68CPU VTT REGULATOR
74
K61_JERRY
07/16/2009
67VREG: CPU CORE - PHASE 4
73
K61_JERRY
07/16/2009
66VREG: CPU CORE - PHASES 1-3
72
K60_JERRY
07/01/2009
65VREG: PPVCORE_S0_CPU
71
K61_JERRY
07/16/2009
64POWER SEQUENCING PGOOD
70
K60_MIKE
07/01/2009
63POWER SEQUENCING ENABLES
69
K60_MIKE
07/01/2009
62AUDIO: Mikey
68
K23_SKIP
07/16/2009
61AUDIO: Detects/Grounding
67
K23_SKIP
07/16/2009
60Audio: MLB to I/O Conn.
66
K60
06/05/2009
59AUDIO: Woofer Amp
65
K23_SKIP
07/16/2009
58AUDIO: Tweeter Amp 1
64
K23_SKIP
07/16/2009
57AUDIO: FILTER/BUFFER
63
K23_SKIP
07/16/2009
56AUDIO: CODEC/REGULATOR
62
K23_SKIP
07/16/2009
55SPI ROM
61
K60_SIJI
07/01/2009
54CPU FAN
57
K60_DEREK
07/01/2009
53HD AND OD FAN
56
K60_DEREK
07/01/2009
52Thermal Sensors
55
K60_JERRY
07/01/2009
51GRAPHICS / DIMM POWER SENSE
54
K60_JERRY
07/01/2009
50
Date
Contents(.csa)
Page Sync
LAST_MODIFIED=Fri Oct 9 15:23:09 2009
TITLE=K22
ABBREV=DRAWING
LAST_MODIFIED=Fri Oct 9 15:23:09 2009
Page(.csa) Date
SyncContents05/21/2009
K6011
Table of Contents CPU POWER SENSE53
K60_JERRY
07/01/2009
49
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
SATA-A1
MIDBUS PROBE
X4 DMI
SO-DIMMS
SO-DIMMS
XDP CONNPG 25
J2500
WM
Port80,serialPG 51
PG 56,57
EXTERNAL
XDP
& CONNECTOR
CIO
E-NETCONNECTOR
OPTIC MODULE
J3900
X4 PCIE GEN1 LANES(2.5GBITPS/LANE)
(PORT B)
(PORT D)
CIO LINK
ROUTERCIO
X1 PCIE GEN1 LANE 2.5GBITPSE-NETMAGNETICS
PG 39
T3900 U3800
INTEL
PG 18
X1 PCIE GEN1 LANE 2.5GBITPS
HW
U93XX
LPC
INTERFACE
PG 18
PG 19
DMI INTERFACE XDP CONN
PG 18
HDMI/DVI/DP
PG 19
PG 19
PG 18
PG 18
PG 18
PG 20
PG 18
PG 19
PG 19
PG 20
U1800
PG 25
U2510
PG 38 PG 39
01
23
56
78
910
11
(UP TO 14 DEVICES)
USB 2.0
(SUPPORTED UPTO 4 REQ/GNT)
DIMM’s
FDI LINK
FDI INTERFACE
MXM CONNECTORJ8400
X4 DP
X4 DP
U2600
LGA1156 - LYNNFIELD
INTEL CPU
SPIBoot ROM
DDR3 1066/1333 CHA
CPU DIE-PECI HARD DRIVEOPTICAL DRIVE LCD TEMP
PG 13
U6100
PG 32
PG 31
J3200, J3200DDR3 1066/1333 CHB
J3100, J3100
PG 93
SUPPORT
BIDIVI
PG 53 POWER SENSE
XIO2213B
PG 55
TEMP, CURRENT SENSE
TEMP SENSORS
MXM - GPU DIE CPU HEATSINK
AMBIENT INTAKE
TO BIDIVI HW
Connectors
FAN CONN AND CONTROL
PCI
X16 PCI-E GEN2
13
12
IR
PG 47
PWR
2 SO-DIMMS
PG 10
CTRL
POWER SUPPLY
Fan
PG 47PG 47
J4700
MIKEY
Bluetooth
J4300
SPI
B,0 BSB
SMCADC
4
PG 34
GPIOs
PG 43
AirPortMini PCI-E
J4720 J4780
PG 49
U4900
HDA
6 SATA 2.O PORTS
HDMI/DVI/DP
DIGITAL VIDEO OUTPUT
RGB OUT
ConnFireWire
J3400
DIGITAL VIDEO OUTPUT
(PORT C)
PG 41
U4100
HDMI/DVI/DP
SMB
AND PHYCONTROLLERGB E-NET
U1000
2 SO-DIMMS
PG 47
USB
PG 47
J47xxJ4610,4620,4630,4640
J5100
PrtSer
PG 61
J5600, J5601, J5700
CLK
LPC+SPI CONN
Misc
GPU HEATSINK
PG 84
J9002
J9400
PG 90
PORTDISPLAY
X4 DP
CONTROL LOGIC FROM SMC
INTERNAL DISP
X4 BIDIRECTIONAL DP LINK
PG ?
U? J?
PG ?
CONN
PG 94
DIGITAL VIDEO OUTPUT
(PORT A)
ANALOG VIDEO OUTPUT
SATA IBEX PEAK
USB 96MHZ/PCIE 100MHZ/SATA 100MHZ/BCLK 133MHZ.
SATA-A2
SATA-A0
SYNTH
SATA 2.0 3GHZ.
SATA 2.0 3GHZ.
SATA 2.0 3GHZ.
PG 26CK505
HDPG 45
SATA CONN
J4510
J4520
PG 45
ODDSATA CONN
PG 45
SATA CONN
J4530
SSD
PCI-E GEN2
UP TO 8 LANES3
X1 PCIE GEN1 LANE 2.5GBITPS
U6201
Audio
Audio
Conns
Codec
CAMERA
J47xx
SD CARD
PG 47
U6400, U6500
SPEAKER AMPS
HEADPHONES INTERNAL/EXTERNAL
MICROPHONES LINE INPUT
J6600,J6601,J6602,J6603
051-8233
B.0.0
2 OF 110
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
SYNC_MASTER=K60_SIJI
System Block DiagramSYNC_DATE=07/01/2009
G S
D
IN
D1
D3
D4S3S2
GATE
S1D2
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PP3V3_S5_AVREF_SMC
PAGE 50
PP12V_S5:
12V_S5
SMCPP3V42_G3H_REG
CAMERAPP5V_S3_REG
WM
IBEX PEAK
PP12V_S5
PM_SMC_G2_EN
PPVCORE_CPU
PAGE 71-72
IBEX PEAK
MXM
PP12V_S0_HDD
AC/DC POWER SUPPLY
FET (6.9A)
PAGE 42
1.0V @ 0.08A
MAIN MEMORY
PM_SLP_S3
PAGE 79REG
SMC VREF
CARD READER
PP1V8_S0_REG
MXMOPTICAL
LCD PANELIBEX PEAKAUDIO
P3V3S3_EN
PAGE 79
VCCME, PCH
P5VS0_EN
3.3V @ 2.8A
PAGE 80
PP3V3_S5_REG3.3V @ 6.2A
AUDIO
PP1V95_S3
PAGE 76
1.1V @ 30APPVTT_S0
.65-1.5V @ 90A
PP1V05_S5
IBEX PEAKPAGE 76
FANS
PP1V05_S01.05V @ 3A
FET (10.3A)
ETHERNET
FET (2.8A)
PPDDR_S3_REG
P3V3S0_EN
BIDIVI FIREWIRE
BOOT ROM
MXMPP3V3_S0
HDD
1.05V @ 0.4A
AP
PP12V_G3H
PP5V_S0
PP12V_S0:
PP12V_S0
PM_SLP_S3_OD
HARD DRIVELCD PANEL
AUDIOPP12V_G3H:
PAGE 80
CONTROL
CPU UNCORE
SMBUS
1.5V @ 4.9A
PAGE 78
SW (1A)
CPU MEM
BT
PP1V5_S0
PP12V_S312V @ 0.2A
PAGE 80
WM
P12VS0_EN
ENET
PAGE 38
1.2V @ 0.2APP1V2_S3
13A (S3 & S0)
PAGE 74
PAGE 75
PAGE 75
0.75V @ 0.6APP0V75_S0
MEM_VTT
FIREWIREAUDIO
PP3V3_S3
PAGE 80
FW
PAGE 78
CPU PLL
IR
USB
REG
PAGE 76
CPU_CORE
PPLED_PWR
DCM/FCM
TEMP SENSOR
12V S5 FET ( 7A )
3 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
=PP12V_G3H_S5_FET PP12V_S5_FET
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=POWERMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmVOLTAGE=12VMAKE_BASE=TRUE
P12V_S5_EN_G
SMC_PM_G2_EN
P12V_S5_EN_D
P12V_S5_EN_R
SYNC_DATE=07/01/2009SYNC_MASTER=K60_MIKE
Power Block Diagram
SOI-HFFDS4465_G
CRITICALQ8040
5
6
7
8
4
1
2
3
45 SOT23-HF12N7002Q8041
3
1
2
10K
5%
402
1/16WMF-LF
R80411 2
402MF-LF
10K1/16W5%
R80401
2
5%1/16W
10K
MF-LF402
R80451
2
100K
402MF-LF1/16W5%
R80421
2
X7R
10%16V
805
0.47UFC80401
2
6 6
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
BOM OPTIONSBOM NAMEBOM NUMBERTABLE_BOMGROUP_HEAD
BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
COMMON
RAW: 335S0663
CPUS
K23F PARTS
(338S0489 - BLNK)
BOM Variants
BOM GROUPS
GROUND
POWER
SIGNAL
POWER
GROUND
SIGNAL
SIGNAL
SIGNAL
BOARD STACK-UPTOP23
BOTTOM76
45
4 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
SYNC_DATE=07/01/2009
BOM ConfigurationSYNC_MASTER=K60_AARON
IC,IBEX PEAK B3,DESKTOP,FCBGA,PCH,P425337S3823 U1800 CRITICAL1
IC,SLG2AP108,CLK GEN,CK505,QFN3359S0157 1 U2600 BUF_CLKCRITICAL
U6100 CRITICAL341T0211 IC,EFI BOOTROM,K23F1
338S0765 IC,XIO2211ZAY,1394B_PCIE,PHY/LINK1 CRITICALU4100
IC,BCM5764M,68PIN QFN U37001 CRITICAL343S0485
IC,FLASH,45DB0011D,SOIC-8S1 CRITICALU37011341T0213
X14 CRITICAL825-7122 MLB LABEL,48.0X4.81
1 CRITICALU1000511S0063 SOCKET,LGA1156,CPU-LF
2P66GHZ_CPU337S3810 1 CPU CRITICALLFD,SLBLC,PRQ,2.66,95W,1333,B1,8M,LGA
337S3811 1 CPU 2P80GHZ_CPULFD,SLBJJ,PRQ,2.80,95W,1333,B1,8M,LGA CRITICAL
SCH,K23F,MLB K23F051-8233 1 SCH1
IC,SMC,K23F K23FCRITICALU49001341T0212
PCBF,K23F,MLB820-2733 K23F1 MLB1
PCBA,MLB,K23F,2.66GHZ K23F,2P66GHZ_CPU,BASIC,CPUPOC_IMAX_100_120639-0439
085-1023 DEVELOPMENT,DEV_GROUPPCBA,MLB,DEV,K23F
K23F,2P80GHZ_CPU,BASIC,CPUPOC_IMAX_100_120PCBA,MLB,K23F,2.80GHZ639-0440
COMMON,ALTERNATE,XDP,BETTER,MXM,XDP_CPU_BPM,INT_VREF,PCH_VRM,BUF_CLK,PRODUCTIONBASIC
XDP_CONN,LPCPLUS,MOJOMUX,CPU_TDIODE,MEM_RESET_HWDEV_GROUP
IN
G
D
SING
D
SIN
G
D
SIN
G
D
SIN
G
D
SIN
G
D
S
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
CAN DELETE THESE FOR PROTO1 AND BEYOND
1
SILKSCREEN:2
1
1
PM_SLP_M_L
0
0
1
0
1
1
1
1
0
0
PM_SLP_S4_LPM_SLP_S3_L
0
0
0
1
0
0
PM_S4_STATE_L
1
0
0
1
1
0
SMC_PM_G2_ENABLE
1
1
1
0
1
Manageability
N/A
Off
Off
On
N/A
On
State
Soft-Off (S5/M-Off)
Sleep (S3/M-Off)
Soft-Off (S5/M1)
Sleep (S3/M1)
Run (S0/M0)
Battery Off (G3Hot)
SILKSCREEN:4
SILKSCREEN:4
SILKSCREEN:2
SILKSCREEN:2
SILKSCREEN:4
5 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
=PP3V3_S5_PWRCTL
PM_LED_DDRREG
=PP3V3_S0_PWRCTL
PM_LED_S4
PM_LED1_DDRREG
PM_SLP_M_L
PM_SLP_S3_L
PM_SLP_S4_3_L
PM_PGOOD_PVCORE_CPU
PCHCORE_REG_PGOOD
PM_PGOOD_DDRREG_S3
PM_LED1_SM
PM_LED_SM
PM_LED1_S3
PM_LED_S3
PM_LED1_S4
PM_LED1_PVCORE
PM_LED_PVCORE
PM_LED1_PCHCORE
PM_LED_PCHCORE
=PP3V3_S5_PWRCTL
=PP3V3_S5_PWRCTL
=PP3V3_S5_PWRCTL
=PP3V3_S0_PWRCTL
SYNC_DATE=07/01/2009
PROTO 0 DEBUG LEDSSYNC_MASTER=K60_MIKE
DEVELOPMENT
2N7002DW-X-GSOT-363
Q500
6
2
1
91 19
SILK_PART=SLP_S3DEVELOPMENT
GREEN-3.6MCD2.0X1.25MM-SM
LED510
A
K
DEVELOPMENT
603
5%3.3K1/10WMF-LF
R5101
2
SOT-3632N7002DW-X-G
DEVELOPMENT
Q500
3
5
4
DEVELOPMENT
MF-LF1/10W
3.3K5%
603
R5501
2
MF-LF
5%
603
DEVELOPMENT
1/10W
3.3KR5301
2
603
5%1/10WMF-LF
NOSTUFF
3.3KR5311
2
603
5%3.3K1/10WMF-LF
DEVELOPMENT
R5001
2
91 68 63 62
DEVELOPMENT
2N7002DW-X-GSOT-363
Q540
6
2
1
SILK_PART=PCHCORE_PGOODDEVELOPMENT
GREEN-3.6MCD2.0X1.25MM-SM
LED540
A
K
91 70 62
DEVELOPMENT
SOT-3632N7002DW-X-GQ520
6
2
1
603
5%3.3K
MF-LF
DEVELOPMENT
1/10W
R5401
2
SILK_PART=DDR_PGOODDEVELOPMENT
2.0X1.25MM-SMGREEN-3.6MCD
LED530
A
K
91 62 19
GREEN-3.6MCD2.0X1.25MM-SM
DEVELOPMENT
SILK_PART=SLP_S4 LED500
A
K
DEVELOPMENT
SOT-3632N7002DW-X-GQ520
3
5
4
SILK_PART=SLP_M
DEVELOPMENT
GREEN-3.6MCD2.0X1.25MM-SM
LED520
A
K
91 64 63 26
DEVELOPMENT
SOT-3632N7002DW-X-GQ540
3
5
4
DEVELOPMENT
MF-LF1/10W
3.3K5%
603
R5201
2
SILK_PART=VCORE_PGOODDEVELOPMENT
GREEN-3.6MCD2.0X1.25MM-SM
LED550
A
K
91 63 62 46 37 33 32 19
63 62 6 5
72 63 62 6 5 63 62 6 5
63 62 6 5
63 62 6 5
72 63 62 6 5
IN G S
D
G
D
S
G
D
SIN
IN
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
"G3H" RAILSALWAYS ON WHEN UNIT HAS AC POWER AND IN G3HOT PER SMC
THIS NET IS NOT CONNECTED TO ANY VOLTAGE RAIL. INSTEAD ON PAGE 24 IT IS CONNECTED TO GND THROUGH A RESISTOR
"S3" RAILS
G3H: ALIASES
GND RAILS
ON IN RUN AND SLEEP
SILKSCREEN:4
SILKSCREEN:2
SILKSCREEN:3
518-0352
SILKSCREEN:1
EMC: C600,C626,C627,C628,C629,C630,C631
PLACE AT J600.
ONLY ON IN RUN
"S0" RAILS"S5" RAILS
ALWAYS ON WHEN UNIT HAS AC POWER AND IN S5
6 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
PP5V_S0
VOLTAGE=5V
NET_SPACING_TYPE=POWERMAX_NECK_LENGTH=3 MM
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.5 mm
MAKE_BASE=TRUE
PP3V3_S0
NET_SPACING_TYPE=POWERMAX_NECK_LENGTH=3 MM
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.4MM
MAKE_BASE=TRUE
=PP3V3_S0_SMBUS_SMC_BSA
PP5V_S0_FET
=PP5V_S0_SATA
=PP5V_S0_VRD
=PP5V_S0_P1V8_VREG
=PP3V3_S0_PCH_PM
=PP5V_S0_ISENSE
PP12V_S0
=PP3V3_S0_ENET
=PP3V3_S0_RSTBUF
PP3V3_S3
MIN_NECK_WIDTH=0.2 mm
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5 mm
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=POWER
VOLTAGE=3.3V
=PP5V_S0_MXM
VIDEO_ON_L
PP3V3_S5
MAX_NECK_LENGTH=3 MM
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2MMNET_SPACING_TYPE=POWER
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
=PP12V_S5_FW
=PP3V3_S3_ENET
=PP3V3_S3_USB_HUB
=PP3V3_S3_BRCRYPT
=PP12V_S5_PWRCTL
PP12V_S3_FET
=PP12V_G3H_S5_FET
PP1V05_S0
MIN_NECK_WIDTH=0.2 mmNET_SPACING_TYPE=POWERMAX_NECK_LENGTH=3 MM
VOLTAGE=1.05VMIN_LINE_WIDTH=0.6 mm
MAKE_BASE=TRUE
=PP1V05_S0_PCH_VCC_CORE
=PP1V05_S0_CK505
PPVTT_S0_DDR_LDO
PP1V5_S0MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.4MM
MAX_NECK_LENGTH=3 MM
VOLTAGE=1.5V
MIN_NECK_WIDTH=0.2MMNET_SPACING_TYPE=POWER
=PP3V3_S3_USB_RESET
=PP1V5_S3_MEM_B
=PP3V3_S3_PWRCTL
PP5V_S3_REG
=PP5V_S3_USB
=PP5V_S3_S0FET
=PP12V_S3_WM
=PP3V3_S0_SMBUS_SMC_B_S0
=PP3V3_S0_SMBUS_SMC_MGMT
=PP3V3_S3_SMBUS
=PP3V3_S3_WM
=PP3V3_S3_SDCARD
=PP3V3_G3H_SMC
=PP3V3_S5_RTC_D
=PP1V5_S3_MEMRESET
=PPDDR_S3_S0FET
=PP12V_S0_PCH_CORE_VREG
=PP12V_S0_PWRCTL
=PP1V5_S0_CK505=PP12V_S0_CPU_VTT_VREG
=PPV_S0_MXM_PWR
=PP3V3_S0_SMC_LS
=PP3V3_S0_TSENS
=PP3V3_S0_ODD
=PP3V3_S0_SATALED
=PP3V3_S0_PWRCTL
=PP3V3_S0_SMC
=PP3V3_S0_MXM
=PP3V3_S0_DPCONN
=PP3V3_S0_SMBUS_SMC_0_S0
=PP3V3_S0_AUDIO
PP1V8_S0
MAX_NECK_LENGTH=3 MM
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.4MMMIN_NECK_WIDTH=0.2MMNET_SPACING_TYPE=POWER
VOLTAGE=1.5V
GPU_PRESENT_R
=PP5V_S3_BRAY
PP5V_S3
MIN_LINE_WIDTH=0.6MMVOLTAGE=5V
MIN_NECK_WIDTH=0.2MM
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=POWER
MAKE_BASE=TRUE
=PP5V_S3_DDR_VREG
PP1V5_S0_FET
=PP1V5_S0_AUD_DIG
=PP1V5_FWRS0_FWXIO
MAX_NECK_LENGTH=3 MM
MIN_LINE_WIDTH=0.4MM
NET_SPACING_TYPE=POWERMIN_NECK_WIDTH=0.2MM
VOLTAGE=1.8VMAKE_BASE=TRUE
PP1V8_S0_CPU
=PP3V3R1V8_S0_PCH_VCCPNAND
PP3V3_S3
GPU_PRESENT_DRAIN
=PP5V_S3_IR
=PP5V_S3_MEMRESET
=PP5V_S3_PWRCTL
=PP5V_S3_VREFMRGN
=PP12V_S0_AUDIO_SPKRAMP
=PP12V_S0_VRD
PP12V_S5
MAX_NECK_LENGTH=3 MM
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm
NET_SPACING_TYPE=POWER
VOLTAGE=12VMAKE_BASE=TRUE
=PP12V_S0_FAN
=PP3V3_S0_PCH_VCC3_3_PCI
=PP3V3_S0_CK505
=PP3V3_S0_VIDEO
=PP3V3_FW_FWPHY
PPVAXG_S0_CPU
NET_SPACING_TYPE=POWER
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.3MM
VOLTAGE=0V
MAX_NECK_LENGTH=3 MM
MIN_LINE_WIDTH=0.6MM
PP1V8_S0_REG
=PP1V8_S0_CPU_PLL
=PP3V3_S5_CPURESET
=PP3V3_S5_PCH
PP3V3_S5_REG
=PP3V3_S5_PCH_GPIO
=PP1V05_S0_PCH_VCCIO_SATA
PP1V05_S5
MIN_LINE_WIDTH=0.5 mmVOLTAGE=1.05V
NET_SPACING_TYPE=POWER
MAKE_BASE=TRUE
MAX_NECK_LENGTH=3 MM
MIN_NECK_WIDTH=0.2 mm
=PP0V75_S0_MEM_VTT_S0FET
=PP1V05_S0_PCH
PP1V05_S0_REG
PP12V_G3H
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=POWER
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.4 mm
VOLTAGE=12VMAKE_BASE=TRUE
PP12V_S3
MIN_NECK_WIDTH=0.2 mm
MAKE_BASE=TRUEVOLTAGE=12VMIN_LINE_WIDTH=0.6 mm
NET_SPACING_TYPE=POWERMAX_NECK_LENGTH=3 MM
PP12V_S0MAKE_BASE=TRUEVOLTAGE=12V
NET_SPACING_TYPE=POWERMAX_NECK_LENGTH=3 MM
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm
PP0V75_S0MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 mmVOLTAGE=0.75V
NET_SPACING_TYPE=POWERMAX_NECK_LENGTH=3 MM
=PP3V3_S0_PCH_VCC3_3_CORE
=PP3V3_FWRS0_FWXIO
=PP3V3_S0_DP
=PP3V3R1V5_S0_PCH_VCCSUSHDA
PPVCORE_S0_CPU
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=POWER
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUEVOLTAGE=1.1V
MIN_NECK_WIDTH=0.3MM
=PP3V3_S0_PCH_STRAPS
=PP3V3_S0_VRD
PPVTT_S0_CPUMAKE_BASE=TRUEVOLTAGE=1.1V
MIN_NECK_WIDTH=0.2 mm
MAX_NECK_LENGTH=3 MM
MIN_LINE_WIDTH=0.6 mm
NET_SPACING_TYPE=POWER
PP1V5_CPU_MEM
VOLTAGE=1.5V
NET_SPACING_TYPE=POWERMAX_NECK_LENGTH=3 MM
MIN_LINE_WIDTH=0.4MMMIN_NECK_WIDTH=0.2MM
MAKE_BASE=TRUE
PPVCORE_S0_CPU_REG
=PPVCORE_S0_CPU
=PP0V75_S0_MEM_VTT_B
PPVTT_S0_DDR
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=POWERMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 mmVOLTAGE=0.75VMAKE_BASE=TRUE
PP3V42_G3H
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE
NET_SPACING_TYPE=POWERMIN_NECK_WIDTH=0.2MM
MAX_NECK_LENGTH=3 MM
VOLTAGE=3.42V
PP3V42_G3H_REG
=PP0V75_S0_MEM_VTT_A =PP1V05_S5_SM_FET
=PPVTT_S0_CPU
PPVTT_S0_CPU_REG
=PPVTT_S0_XDP
=PPVTT_S0_PCH_VCC_DMI
=PP1V05_S0_PCH_VCCIO_DMI
=PP1V05_S0_PCH_VCCADPLL
=PP12V_S0_LCD
=PP5V_S5_PCH
PP3V3_S0
PP3V3_S0
LCD_SHOULD_ON_R
ITS_PLUGGED_IN
PP3V3_S3
ITS_ALIVE
=PP3V3_SM_PWRCTL
PP3V3_S5_REG
CORE_VOLTAGES_ON_R
=PP3V3_SM_PCH_VCC_ME
PP3V3_SM_FET
PP1V05_SM_FET
=PP1V05_SM_ME
PP3V3_S0M
NET_SPACING_TYPE=POWER
VOLTAGE=3.3VMIN_LINE_WIDTH=0.5 mm
MAKE_BASE=TRUE
MAX_NECK_LENGTH=3 MM
MIN_NECK_WIDTH=0.2 mm
=SMB_ACDC_SDA
=PP1V5_CPU_MEM
PPVTT_S0
MAX_NECK_LENGTH=3 MM
MIN_NECK_WIDTH=0.2 mm
MAKE_BASE=TRUE
NET_SPACING_TYPE=POWER
VOLTAGE=1.1VMIN_LINE_WIDTH=0.6 mm
LCD_PWM LCD_BKL_ON=PP1V05_S0_SM_FET
=PP1V05_S0_PCH_VCCIO_PCIE
PP1V05_S5_REG
=PPVTT_S0_PCH_VCCP_CPU
=PP1V05_SM_PCH_VCC_ME
PP1V05_SMMAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 mm
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=POWER
MIN_LINE_WIDTH=0.6 mmVOLTAGE=1.05V
=PP1V8R1V5_S0_PCH_VCCVRM
=PP3V3_S0_PCH
=PP3V3_S0_FAN
=PP3V3_S0_PCH_VCCADAC
=PPSPD_S0_MEM_B
PPVTT_S0_DDR_FET
MXM_GOOD
ALL_SYS_PWRGD_R
CORE_VOLTAGES_ON
=SMB_ACDC_SCL
PM_ACDC_PS_ON
=PP3V3_S0_PCH_GPIO
=PP3V3_S0_PCH_VCC3_3_SATA
PP3V3_S0_FET
=PP12V_S5_S3_FET
=PP12V_S5_P5VS3_VREG
=PP12V_S5_P3V3S5_VREG
=PP12V_S5_DDR_VREG
PP12V_S5_FET
PP5V_S5_LDOPP5V_S5
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=POWER
VOLTAGE=5VMAKE_BASE=TRUE
MIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 mm
=PPSPD_S0_MEM_A
=PP3V3_S0_SMBUS
=PP3V3_S0_ME
=PP5V_S0_CPU_VTT_VREG
=PP5V_S0_PCH_CORE_VREG
=PP5V_S0_LPCPLUS
=PP5V_S0_PCH
=PP5V_S0_AUDIO
=PPVAXG_S0_CPU
=PP3V3_S0_XDP
=PP1V05_SM_PCH_VCC_LAN
=PP3V3_S5_MEMRESET
PP1V05_SM_PCH_LAN
VOLTAGE=1.05VMAKE_BASE=TRUE
=PP1V05_S0_PCH_VCCIO_USB
=PP3V3_S5_XDP
=PP3V3_S5_PCH_STRAPS
=PP3V3_S5_LPCPLUS
=PP1V5_S3_MEM_A
PP1V5_S3_REG
=PP3V3_S3_MINI
=PP3V3_S3_SMBUS_SMC_A_S3
PP1V5_S3MAKE_BASE=TRUEVOLTAGE=1.5VMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mmNET_SPACING_TYPE=POWERMAX_NECK_LENGTH=3 MM
=PP3V3_S3_MEMRESET
=PP5V_S3_CAMERA
=PP3V42_G3H_AVREF
=PP3V3_G3H_SMCUSBMUX
=PP3V3_G3H_LPCPLUS
=PP3V3_S3_PCH_STRAPS
=PP3V3_S3_BT
=PP3V3_S3_VREFMRGN
PP3V3_S3_FET
=PP3V3_S5_PCH_VCCSUS3_3_USB
=PP3V3_S5_ROM
=PP3V3_S5_SM_FET
=PP3V3_S5_P1V05S5_VREG
=PP3V3_S5_S0FET
=PP3V3_S5_S3FET
=PP3V3_S5_PWRCTL
PM_SLPS3_BUF2_L
PP12V_G3H
=PP5V_S0_SATA
MAX_NECK_LENGTH=4.1 MMMAKE_BASE=TRUE
GND
VOLTAGE=0VNET_SPACING_TYPE=GND
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MM
SYNC_DATE=07/01/2009
Power Conn / AliasSYNC_MASTER=K60_SIJI
91 63 32 25
GREEN-3.6MCD2.0X1.25MM-SM
LED602
A
K
402
1K
MF-LF
5%1/16W
R6021
2
21
2.0X1.25MM-SMGREEN-3.6MCD
MXM
LED604
A
K
402MF-LF1/16W5%1K
MXM
R6041
2
GREEN-3.6MCD2.0X1.25MM-SM
LED603
A
K
402
1K1/16WMF-LF
5%
R6031
2
2.0X1.25MM-SMGREEN-3.6MCD
DEVELOPMENT
LED605
A
K
402MF-LF
5%1K1/16W
DEVELOPMENT
R6001
2
402MF-LF
5%1K1/16W
R6011
2
GREEN-3.6MCD2.0X1.25MM-SM
LED601
A
K
SOT-3632N7002DW-X-GQ602
6
2
1
2N7002DW-X-GSOT-363
Q602
3
5
4
M-RT-TH76833-0100
CRITICAL
J600
1
10
11
12
13
14
2
3
4
5
6
7
8
9
402X7R
0.001UF50V10%
C6311
2402
50V10%
X7R
0.001UFC6301
2X5R
20%
805
10V
10UFC6231
2
X7R
0.001UF10%50V
402
C6001
22N7002SOT23-HF1
Q6103
1
2
50VX7R
10%
402
0.001UFC6261
2 16V
10UF10%
1210X5R-CERM
C6241
2
46 45
10%0.001UF
402
50VX7R
C6271
2
92 89
89 6
48
72
42 6
64
70
27
49
89 63 6
36
27
92 89 6
73
77
89
41
37
35 34
44
72 63
72
3
89
24 22
26
70
89
34
31 29 28
72 63
92 69
43
72
44
48
48
48
44
44
46 45
27
32
72
68
63
26 67
50
51 46
51
42
42 18
72 63 62 5
50 49 46
74 73 63
80
48
61 60 59 58 57 55
89
44
89
70
72 49
55
39
89 49
24 22
92 89 6
44
32
62
28
60
64
89
53 52
24 22
26
77
41 40 39
70 49
63 16 13
11
24 19 18
69 6
20
24 22 18
89
32
24
68
89 71 6
89
89 63 6
89
24 22
39
81 79 78 77
24 22
89
15
64
89 49
89 49
66 65 64
16 13
31
89
89 71
30 72
64 46 16 13 11
67 49
25
24 22
24 22
17
77
24
89 6
89 6
92 89 6
72 63
69 6
24 22
72
72
63
89
48
29 16 13 11
89
77 77 72
24 22 19 18
71
24 22
24 22
89
24
68 24 21 18
53 52
17
31
32 48
20
24 22
72
72
69
69
70
3
69 89
46 30
48
72
67
68
47
24
61 55
17 13
25
24 22
32
89
24 22
25
15
47
30 29 28
70 50 49
33
48
89
32
44
46
43
47
15
44
28
72
24 22
54 47
72
71
72
72
63 62 5
89 71 6
42 6
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
Nuts (805-9582)
DIMM CONNECTOR NUTS
For EMC
Backer Plate
Nuts (835-0269)
EMC POGO Pins (870-1698); Near DIMMsEMC Spring (870-1577); Near DIMMs
4mm Plated Holes (998-0850)
CPU Heatsink
Standoffs (860-1255)
Rear Cover
PCH HEATSINK
EMC Springs (870-1125) Removed 2009-10-05
7 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
SYNC_MASTER=K60_SIJI SYNC_DATE=07/01/2009
Holes
STDOFF-6.8OD15.0H-1.56-TH
CRITICAL
SDF0719
1
CRITICAL
STDOFF-6.8OD15.0H-1.56-THSDF0718
1
CRITICAL
STDOFF-6.8OD15.0H-1.56-THSDF0717
1
CRITICAL
STDOFF-6.8OD15.0H-1.56-THSDF0715
1
STDOFF-6.8OD15.0H-1.56-TH
CRITICAL
SDF0714
1
2.0DIA-TALL-EMI-MLB-M97-M98SM
CRITICAL
NOSTUFF
SC0706
1
SM
CRITICAL
NOSTUFF
2.0DIA-TALL-EMI-MLB-M97-M98SC0705
1
CRITICAL
NUT-4.25OD1.4H-1.40-3.25-THNUT0750
1
CRITICAL
NUT-4.25OD1.4H-1.40-3.25-THNUT0751
1
CRITICAL
NUT-4.25OD1.4H-1.40-3.25-THNUT0752
1
CRITICAL
NUT-4.25OD1.4H-1.40-3.25-THNUT0753
1
NUT-6.5OD1.4H-1.56-3.8-TH
CRITICAL
NUT0703
1
CRITICAL
NUT-6.5OD1.4H-1.56-3.8-THNUT0702
1
NUT-6.5OD1.4H-1.56-3.8-TH
CRITICAL
NUT0701
1
NUT-6.5OD1.4H-1.56-3.8-TH
CRITICAL
NUT0700
1
STDOFF-6.8OD15.0H-1.56-TH
CRITICAL
SDF0713
1
EMI-SPRINGCLIP-SM-K2
CRITICAL
SC07021
OMIT
4P75R4ZH0703
14P75R4
OMITZH0702
1
OMIT
4P75R4ZH0701
14P75R4
OMITZH0700
1
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
NC ON UNUSED SATA ALIASES
NC ON UNUSED NAND ALIASES
NC ON UNUSED MISC ALIASES
NC ON UNUSED MEM ALIASES
NC ON UNUSED PCI ALIASES
UNUSED CPU SIGNALS
NC ON UNUSED DISPLAY ALIASES
8 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
TP_DP_IG_B_AUX_P
TP_DP_IG_B_AUX_N
TP_DP_IG_B_DDC_CLK
NC_DP_IG_C_MLN<3..0>NO_TEST=TRUEMAKE_BASE=TRUE
NO_TEST=TRUEMAKE_BASE=TRUENC_DP_IG_C_MLP<3..0>
MAKE_BASE=TRUE NO_TEST=TRUENC_DP_IG_C_AUXN
TP_SATA_F_R2D_CP
TP_SATA_F_R2D_CN
TP_SATA_F_D2RP
TP_MEM_B_DQS_N<8>
TP_JTAG_XDP_TRST_L NC_JTAG_XDP_TRST_LMAKE_BASE=TRUE NO_TEST=TRUE
NO_TEST=TRUENC_PCH_PWM0MAKE_BASE=TRUE
TP_PCH_PWM0
TP_PCH_SST
TP_PCH_PWM1 NC_PCH_PWM1MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUENC_NV_WR_RE_L<1..0>
NO_TEST=TRUE
MAKE_BASE=TRUENC_NV_RB_L
NO_TEST=TRUETP_NV_RB_L
NO_TEST=TRUEMAKE_BASE=TRUENC_DMI_CLK100M_LAN
TP_PCIE_CLK100M_XDPP
NC_CPU_FC_AG40MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUENC_PCIE_CLK100M_XDPP
TP_NV_WR_RE_L<1..0>
NC_LPC_DREQ1_LMAKE_BASE=TRUE NO_TEST=TRUE
TP_PCIE_CLK100M_XDPN
TP_MEM_B_DQ_CB<7..0>
MAKE_BASE=TRUE NO_TEST=TRUENC_NV_WE_CK_L<1..0>
TP_MEM_A_DQS_N<8>
TP_LPC_DREQ1_L
TP_MEM_A_DQ_CB<7..0>
TP_NV_DQ<15..0>
MAKE_BASE=TRUE NO_TEST=TRUENC_MEM_B_CS_L<7..4>
NC_MEM_A_DQS_P<8>NO_TEST=TRUEMAKE_BASE=TRUE
NO_TEST=TRUEMAKE_BASE=TRUENC_MEM_B_DQ_CB<7..0>
TP_MEM_B_DQS_P<8>
TP_PCH_PWM2
NO_TEST=TRUEMAKE_BASE=TRUENC_MEM_A_DQ_CB<7..0>
NC_MEM_B_DQS_P<8>MAKE_BASE=TRUE NO_TEST=TRUE
TP_MEM_B_CS_L<7..4>
NC_MEM_B_DQS_N<8>MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUENC_MEM_A_DQS_N<8>
NO_TEST=TRUE
TP_MEM_A_CS_L<7..4>
NO_TEST=TRUEMAKE_BASE=TRUENC_NV_CE_L<3..0>TP_NV_CE_L<3..0>
TP_NV_DQS<1..0>
TP_NV_WE_CK_L<1..0>
NC_PCH_PWM3NO_TEST=TRUEMAKE_BASE=TRUE
TP_PCH_PWM3
TP_MEM_A_DQS_P<8>
MAKE_BASE=TRUENC_MEM_A_CS_L<7..4>
NO_TEST=TRUE
TP_LPC_DREQ0_LMAKE_BASE=TRUE NO_TEST=TRUENC_LPC_DREQ0_L
MAKE_BASE=TRUE NO_TEST=TRUENC_DMI_CLK100M_LAP
TP_DMI_CLK100M_LAN
NO_TEST=TRUEMAKE_BASE=TRUENC_PCH_SST
NC_PCH_PWM2NO_TEST=TRUEMAKE_BASE=TRUE
TP_PCI_RESET_L
TP_PCI_PAR
TP_DMI_CLK100M_LAP
NO_TEST=TRUEMAKE_BASE=TRUENC_PCIE_CLK100M_XDPN
NC_NV_DQ<15..0>MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUENC_NV_DQS<1..0>
MAKE_BASE=TRUENC_PCI_C_BE_L<3..0>
NO_TEST=TRUE
NC_PCI_AD<31..0>NO_TEST=TRUEMAKE_BASE=TRUE
TP_PCI_AD<31..0>
TP_CPU_FC_AE38
TP_CPU_RSVD<26..1>
TP_CPU_RSVD<41..29>
TP_CPU_FC_AG40
NC_PCI_RESET_LNO_TEST=TRUEMAKE_BASE=TRUE
MAKE_BASE=TRUENC_PCI_PAR
NO_TEST=TRUE
TP_PCI_C_BE_L<3..0>
MAKE_BASE=TRUE NO_TEST=TRUENC_PCI_T28_R2D_C_N<3..0>
MAKE_BASE=TRUE NO_TEST=TRUENC_PCI_T28_R2D_C_P<3..0>
NC_PCI_T28_D2R_P<3..0>NO_TEST=TRUEMAKE_BASE=TRUE
TP_PCI_T28_R2D_C_P<3..0>
NO_TEST=TRUEMAKE_BASE=TRUENC_PCI_T28_D2R_N<3..0>NO_TEST=TRUEMAKE_BASE=TRUE
NC_CPU_RSVD<26..1>
MAKE_BASE=TRUE NO_TEST=TRUENC_CPU_FC_AE38
NO_TEST=TRUENC_CPU_RSVD<41..29>MAKE_BASE=TRUE NC_SATA_D_D2RN
MAKE_BASE=TRUE NO_TEST=TRUETP_SATA_D_D2RN
NC_SATA_D_D2RPNO_TEST=TRUEMAKE_BASE=TRUE
TP_SATA_D_D2RP
NC_SATA_D_R2D_CNMAKE_BASE=TRUE NO_TEST=TRUE
TP_SATA_D_R2D_CN
NC_SATA_D_R2D_CPNO_TEST=TRUEMAKE_BASE=TRUE
TP_SATA_D_R2D_CP
NO_TEST=TRUEMAKE_BASE=TRUENC_SATA_E_D2RNTP_SATA_E_D2RN
NC_SATA_E_R2D_CNNO_TEST=TRUEMAKE_BASE=TRUE
TP_SATA_E_R2D_CN
NO_TEST=TRUEMAKE_BASE=TRUENC_SATA_E_D2RPTP_SATA_E_D2RP
MAKE_BASE=TRUE NO_TEST=TRUENC_SATA_E_R2D_CPTP_SATA_E_R2D_CP
NC_SATA_F_D2RNMAKE_BASE=TRUE NO_TEST=TRUE
TP_SATA_F_D2RN
MAKE_BASE=TRUE NO_TEST=TRUENC_SATA_F_D2RP
NO_TEST=TRUEMAKE_BASE=TRUENC_SATA_F_R2D_CN
MAKE_BASE=TRUENC_SATA_F_R2D_CP
NO_TEST=TRUE
NO_TEST=TRUEMAKE_BASE=TRUENC_CRT_IG_DDC_CLKTP_CRT_IG_DDC_CLK
NO_TEST=TRUEMAKE_BASE=TRUENC_CRT_IG_DDC_DATA
NO_TEST=TRUEMAKE_BASE=TRUENC_CRT_IG_REDTP_CRT_IG_RED
MAKE_BASE=TRUE NO_TEST=TRUENC_CRT_IG_GREENTP_CRT_IG_GREEN
TP_CRT_IG_BLUE
MAKE_BASE=TRUE NO_TEST=TRUENC_CRT_IG_HSYNCTP_CRT_IG_HSYNC
NC_CRT_IG_VSYNCMAKE_BASE=TRUE NO_TEST=TRUE
TP_CRT_IG_VSYNC
NC_DP_IG_D_MLN<3..0>MAKE_BASE=TRUE NO_TEST=TRUE
NO_TEST=TRUENC_DP_IG_D_AUXNMAKE_BASE=TRUE
MAKE_BASE=TRUENC_DP_IG_D_MLP<3..0>
NO_TEST=TRUE
NC_DP_IG_D_AUXPNO_TEST=TRUEMAKE_BASE=TRUE
NC_DP_IG_D_CTRL_CLKMAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUENC_DP_IG_D_HPD
NC_DP_IG_D_CTRL_DATAMAKE_BASE=TRUE NO_TEST=TRUE
TP_DP_IG_D_MLN<3..0>
TP_DP_IG_D_AUXN
TP_DP_IG_D_MLP<3..0>
TP_DP_IG_D_AUXP
TP_DP_IG_D_CTRL_CLK
TP_DP_IG_D_HPD
TP_DP_IG_D_CTRL_DATA
NO_TEST=TRUEMAKE_BASE=TRUENC_CRT_IG_BLUE
TP_DP_IG_C_MLN<3..0>
TP_DP_IG_C_MLP<3..0>
TP_DP_IG_C_AUX_N
MAKE_BASE=TRUE NO_TEST=TRUENC_DP_IG_C_AUXPTP_DP_IG_C_AUX_P
NO_TEST=TRUEMAKE_BASE=TRUENC_DP_IG_C_HPDTP_DP_IG_C_HPD
NO_TEST=TRUEMAKE_BASE=TRUENC_DP_IG_C_CTRL_CLKTP_DP_IG_C_CTRL_CLK
NO_TEST=TRUEMAKE_BASE=TRUENC_DP_IG_C_CTRL_DATATP_DP_IG_C_CTRL_DATA
NO_TEST=TRUEMAKE_BASE=TRUENC_DP_IG_B_MLN<3..0>
NO_TEST=TRUEMAKE_BASE=TRUENC_DP_IG_B_MLP<3..0>TP_DP_IG_B_MLP<3..0>
MAKE_BASE=TRUE NO_TEST=TRUENC_DP_IG_B_AUXN
NO_TEST=TRUEMAKE_BASE=TRUENC_DP_IG_B_HPDTP_DP_IG_B_HPD
MAKE_BASE=TRUE NO_TEST=TRUENC_DP_IG_B_AUXP
NO_TEST=TRUEMAKE_BASE=TRUENC_DP_IG_B_CTRL_CLK
NC_DP_IG_B_CTRL_DATAMAKE_BASE=TRUE NO_TEST=TRUE
TP_DP_IG_B_DDC_DATA
MAKE_BASE=TRUE NO_TEST=TRUENC_GFX_VID<0..6>TP_GFX_VID<0..6>
MAKE_BASE=TRUE NO_TEST=TRUENC_GFX_VSENSE_N
NO_TEST=TRUEMAKE_BASE=TRUENC_GFX_VSENSE_PTP_GFX_VSENSE_P
TP_GFX_VSENSE_N
TP_CRT_IG_DDC_DATA
TP_PCI_T28_D2R_N<3..0>
TP_DP_IG_B_MLN<3..0>
TP_PCI_T28_D2R_P<3..0>
TP_PCI_T28_R2D_C_N<3..0>
NO_TEST=TRUENC_HDA_SDIN1MAKE_BASE=TRUE
TP_HDA_SDIN1
MAKE_BASE=TRUENC_HDA_SDIN3
NO_TEST=TRUETP_HDA_SDIN3
MAKE_BASE=TRUENC_HDA_SDIN2
NO_TEST=TRUETP_HDA_SDIN2
NC_PCIE_CLK100M_PE5PNO_TEST=TRUEMAKE_BASE=TRUE
TP_PCIE_CLK100M_PE5P
NO_TEST=TRUEMAKE_BASE=TRUENC_PCIE_CLK100M_PE5NTP_PCIE_CLK100M_PE5N
NC_NV_RCOMPMAKE_BASE=TRUE NO_TEST=TRUE
TP_NV_RCOMP
MAKE_BASE=TRUE NO_TEST=TRUENC_PCIE_CLK100M_EXCARD_PPCIE_CLK100M_EXCARD_P
NC_PCIE_CLK100M_EXCARD_NNO_TEST=TRUEMAKE_BASE=TRUE
PCIE_CLK100M_EXCARD_N
TP_USB_1P
TP_USB_6P
TP_USB_6N
TP_USB_7P
TP_USB_7N
NO_TEST=TRUEMAKE_BASE=TRUENC_USB_1P
NO_TEST=TRUEMAKE_BASE=TRUENC_USB_1N
MAKE_BASE=TRUE NO_TEST=TRUENC_USB_6P
NC_USB_6NNO_TEST=TRUEMAKE_BASE=TRUE
TP_USB_1N
MAKE_BASE=TRUENC_USB_7P
NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUENC_USB_7N
TP_USB_9P
TP_USB_5N
TP_USB_3P
TP_USB_3N
MAKE_BASE=TRUE NO_TEST=TRUENC_USB_5P
NO_TEST=TRUEMAKE_BASE=TRUENC_USB_9P
NO_TEST=TRUEMAKE_BASE=TRUENC_USB_9N
NO_TEST=TRUENC_USB_5NMAKE_BASE=TRUE
MAKE_BASE=TRUE NO_TEST=TRUENC_USB_3N
NO_TEST=TRUEMAKE_BASE=TRUENC_USB_11N
NO_TEST=TRUEMAKE_BASE=TRUENC_USB_10P
NO_TEST=TRUEMAKE_BASE=TRUENC_USB_11P
TP_USB_10N
TP_USB_11N
TP_USB_11P
TP_USB_10P
NO_TEST=TRUEMAKE_BASE=TRUENC_USB_10N
TP_USB_9N
TP_USB_5P
MAKE_BASE=TRUENC_USB_3P
NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUENC_PCIE_EXCARD_D2R_PPCIE_EXCARD_D2R_P
NC_PCIE_EXCARD_D2R_NNO_TEST=TRUEMAKE_BASE=TRUE
PCIE_EXCARD_D2R_N
NC_PCIE_EXCARD_R2D_C_PNO_TEST=TRUEMAKE_BASE=TRUE
PCIE_EXCARD_R2D_C_P
NC_PCIE_EXCARD_R2D_C_NMAKE_BASE=TRUE NO_TEST=TRUE
PCIE_EXCARD_R2D_C_N
NC_SDVO_TVCLKINPNO_TEST=TRUEMAKE_BASE=TRUE
TP_SDVO_TVCLKINP
NC_SDVO_TVCLKINNNO_TEST=TRUEMAKE_BASE=TRUE
TP_SDVO_TVCLKINN
NC_SDVO_STALLPNO_TEST=TRUEMAKE_BASE=TRUE
TP_SDVO_STALLP
NC_SDVO_STALLNNO_TEST=TRUEMAKE_BASE=TRUE
TP_SDVO_STALLN
NC_SDVO_INTPNO_TEST=TRUEMAKE_BASE=TRUE
TP_SDVO_INTP
NC_SDVO_INTNNO_TEST=TRUEMAKE_BASE=TRUE
TP_SDVO_INTN
TP_USB_12P
TP_USB_12N
NO_TEST=TRUEMAKE_BASE=TRUENC_USB_12P
NO_TEST=TRUEMAKE_BASE=TRUENC_USB_12N
MAKE_BASE=TRUE NO_TEST=TRUENC_USB_13N
MAKE_BASE=TRUE NO_TEST=TRUENC_USB_13P
TP_USB_13N
TP_USB_13P
SYNC_MASTER=K60_SIJI SYNC_DATE=07/01/2009
UNUSED SIGNAL ALIAS
19
19
19
18
18
18
83 12
25
21
21
21
20
21
20
21
12
83 12
18
12
20
83 12
21
12
12
20
20
20
21
83 12
18
21
20
20
21
20
13
10
10
13
20
18
18
18
18
18
18
18
18
18
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
13
13
13
19
19
18
18
18
18
18
20
18
18
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
18
18
18
18
19
19
19
19
19
19
20
20
20
20
OUT
OUTIN
IN
IN
IN
OUT
OUT
IN
IN
IN OUT
OUTIN
OUT
OUT
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
THIS SIGNAL NAME IS CONNECTED TO MXM
PEG Slot Support
9 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
PEG_RESET_LMAKE_BASE=TRUE
MXM_RESET_L
CLK_100M_MXM_P
CLK_100M_MXM_N
PEG_R2D_C_N<0..15>MAKE_BASE=TRUE
MAKE_BASE=TRUEPEG_R2D_C_P<0..15>MAKE_BASE=TRUEGPU_CLK100M_PCIE_N
MAKE_BASE=TRUEGPU_CLK100M_PCIE_P
=PEG_R2D_C_P<0..15>
PEG_CLKREQ_LMAKE_BASE=TRUEMXM_CLKREQ_L
=PEG_D2R_N<0..15>
=PEG_R2D_C_N<0..15>
PEG_D2R_P<0..15>MAKE_BASE=TRUE
PEG_CLK100M_P
PEG_CLK100M_N
PEG_D2R_N<0..15>MAKE_BASE=TRUE
=PEG_D2R_P<0..15>
PM_CLK32K_SUSCLKPM_CLK32K_SUSCLK_R
SYNC_DATE=07/01/2009SYNC_MASTER=K60_SIJI
Signal Aliases
73
73
18 73
91 85 45
PLACEMENT_NOTE=PLACE CLOSE TO U18001/16W5%
MF-LF
22
402
R9291 291 85 19
18
18
10
10
84 75
84 75
10
10 84 75
84 75
91 27 73
84
84
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
PEG_TX_2*
PEG_TX_15
PEG_TX_14
PEG_TX_10
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_11
PEG_TX_13
PEG_TX_12
PEG_TX_0
PEG_RCOMPO
PEG_ICOMPO
PEG_ICOMPI
PEG_RBIAS
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_RX_14*
PEG_RX_15*
PEG_RX_13*
PEG_RX_12*
PEG_RX_10*
PEG_RX_11*
PEG_RX_9*
PEG_RX_8*
PEG_RX_7*
PEG_RX_6*
PEG_RX_5*
PEG_RX_4*
PEG_RX_3*
PEG_RX_2*
PEG_RX_1*
PEG_RX_0*
PEG_TX_0*
PEG_TX_1*
PEG_TX_3*
PEG_TX_4*
PEG_TX_7*
PEG_TX_8*
PEG_TX_9*
PEG_TX_10*
PEG_TX_11*
PEG_TX_12*
PEG_TX_13*
PEG_TX_15*
PEG_TX_6*
PEG_TX_14*
DMI_RX_1*
DMI_RX_2*
DMI_RX_3*
DMI_RX_1
DMI_RX_0
DMI_RX_2
DMI_RX_3
DMI_TX_2
DMI_TX_1
DMI_TX_0
DMI_TX_1*
DMI_TX_0*
FDI_TX_2*
FDI_TX_3*
FDI_TX_4*
FDI_TX_6*
FDI_TX_5*
FDI_TX_7*
FDI_TX_0
FDI_TX_1
FDI_TX_2
FDI_TX_4
FDI_TX_6
FDI_TX_5
FDI_FSYNC_0
FDI_TX_7
FDI_INT
FDI_FSYNC_1
FDI_LSYNC_0
FDI_LSYNC_1
PEG_TX_5*
DMI_TX_3*
DMI_TX_2*
FDI_TX_1*
FDI_TX_0*
DMI_TX_3
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
FDI_TX_3
DMI_RX_0*
FLEXIBLE DISPLAY INTERFACE
PCI EXPRESS -- GRAPHICS
DMI
(1 OF 10)
RSVD_AM28
RSVD_AM27
RSVD_AK18
RSVD_AM21
RSVD_AH40
RSVD_AE2
RSVD_AJ39
RSVD_AK12
RSVD_AK13
RSVD_AK15
RSVD_AK16
RSVD_AK25
RSVD_AK28
RSVD_AK27
RSVD_AK26
RSVD_AK14
RSVD_AD2
RSVD_AM26
RSVD_TP_AN11
RSVD_AL17
RSVD_AM13
RSVD_A12
CFG_1
RSVD_AL26
RSVD_NCTF_AY37
RSVD_NCTF_AY3
RSVD_NCTF_AW38
RSVD_NCTF_B3
RSVD_NCTF_C2
RSVD_NCTF_D1
RSVD_AM30
RSVD_AM29
RSVD_AM25
RSVD_AM20
RSVD_AM18
RSVD_AM17
RSVD_AM16
RSVD_AM15
RSVD_AM14
RSVD_L12
RSVD_M12
RSVD_AL15
RSVD_AL14
CFG_0
CFG_5
CFG_4
CFG_3
CFG_2
RSVD_AL29
RSVD_AL27
RSVD_AL18
CFG_10
CFG_8
CFG_9
CFG_7
CFG_6
CFG_15
CFG_12
CFG_13
CFG_14
CFG_11
CFG_17
CFG_16
RSVD_NCTF_A4
RSVD_NCTF_AU40
RSVD_NCTF_AV1
RSVD_NCTF_AV39
RSVD_NCTF_AW2
RSVD_AM19
RSVD_AK29
RSVD_AL12
(5 OF 10)
RESERVED
OUT
OUT
GND
CBP
CBN
GND
GND
CFP
CFN
GND
CHP
CHN
CCP
CCNCDP
CEN
GND
CGN
CGP
GND
CAP
CAN
GND
CDN
CEP
GND
IN
IN
IN
IN
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
INTEL SUGGESTS TO KEEP THESE TPS
CFG3 :PCIE LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
FOR LYNNFIELD PROCESSOR
CFG4 :NOT USED ON DESKTOP
PLACE R1010 AND R1012 CLOSE TO CPU BALLS
FOR CLARKDALE PROCESSOR
CFG [1:0] :PCIE CONFIGURATION SELECT 11 = 1 X16 PCI EXPRESS 10 = 2 X8 PCI EXPRESS
DMI MID-BUS PROBE
CLK
10 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
CPU_CFG<15>
TP_CPU_FDI_TX_P<0>
=PEG_R2D_C_N<0>
=PEG_R2D_C_N<8>
DMI_S2N_P<0>
DMI_S2N_P<1>
DMI_S2N_P<3>
DMI_N2S_N<0>
TP_CPU_FDI_TX_P<4>
=PEG_D2R_N<13>
DMI_S2N_P<2>
DMI_N2S_P<3>
TP_CPU_FDI_TX_N<0>
DMI_N2S_P<2>
DMI_N2S_P<1>
TP_CPU_FDI_TX_N<4>
TP_CPU_FDI_TX_P<7>
CPU_FDI_FSYNC<1>
CPU_FDI_FSYNC<0>
TP_CPU_FDI_TX_P<6>
TP_CPU_FDI_TX_P<5>
TP_CPU_FDI_TX_P<3>
TP_CPU_FDI_TX_P<2>
TP_CPU_FDI_TX_N<5>
=PEG_D2R_P<6>
=PEG_D2R_P<8>
=PEG_D2R_P<5>
=PEG_D2R_P<3>
CPU_FDI_INT
CPU_FDI_LSYNC<0>
=PEG_D2R_P<13>
=PEG_D2R_P<15>
=PEG_D2R_N<2>
TP_CPU_RSVD<1>
=PEG_R2D_C_N<15>
CPU_CFG<7>
TP_CPU_RSVD<10>
TP_CPU_RSVD_NCTF<8>
TP_CPU_RSVD_NCTF<9>
TP_CPU_RSVD<38>
TP_CPU_RSVD<37>
TP_CPU_RSVD<36>
TP_CPU_RSVD<35>
TP_CPU_RSVD<30>
=PEG_D2R_N<9>
=PEG_R2D_C_N<10>
=PEG_D2R_P<10>
=PEG_D2R_P<9>
=PEG_D2R_P<1>
TP_CPU_FDI_TX_P<1>
TP_CPU_FDI_TX_N<7>
TP_CPU_FDI_TX_N<6>
DMI_S2N_N<3>
=PEG_R2D_C_N<14>
=PEG_R2D_C_N<6>
=PEG_R2D_C_N<13>
=PEG_R2D_C_N<12>
=PEG_R2D_C_N<11>
=PEG_R2D_C_N<9>
=PEG_R2D_C_N<7>
=PEG_R2D_C_N<3>
=PEG_R2D_C_N<1>
=PEG_D2R_N<1>
=PEG_D2R_N<12>
=PEG_D2R_P<14>
=PEG_D2R_P<12>
=PEG_R2D_C_P<0>
=PEG_R2D_C_P<12>
=PEG_R2D_C_P<13>
=PEG_R2D_C_P<11>
=PEG_R2D_C_P<9>
=PEG_R2D_C_P<8>
=PEG_R2D_C_P<7>
=PEG_R2D_C_P<6>
=PEG_R2D_C_P<5>
=PEG_R2D_C_P<4>
=PEG_R2D_C_P<2>
=PEG_R2D_C_P<10>
=PEG_R2D_C_P<14>
=PEG_R2D_C_P<15>
=PEG_R2D_C_N<2>
TP_CPU_RSVD<17>
TP_CPU_RSVD<16>
TP_CPU_RSVD<31>
TP_CPU_RSVD_NCTF<5>
TP_CPU_RSVD_NCTF<3>
CPU_CFG<16>
CPU_CFG<11>
TP_CPU_RSVD<23>
CPU_CFG<3>
TP_CPU_RSVD<18>
TP_CPU_RSVD<19>
TP_CPU_RSVD<40>
TP_CPU_RSVD<29>
TP_CPU_RSVD<34>
TP_CPU_RSVD_NCTF<11>
TP_CPU_RSVD_NCTF<10>
TP_CPU_RSVD_NCTF<6>
TP_CPU_RSVD_NCTF<7>
TP_CPU_RSVD<20>
TP_CPU_RSVD_TP<1>
TP_CPU_RSVD<2>
TP_CPU_RSVD<8>
TP_CPU_RSVD<13>
TP_CPU_RSVD<14>
TP_CPU_RSVD<15>
TP_CPU_RSVD<12>
TP_CPU_RSVD<9>
TP_CPU_RSVD<5>
TP_CPU_RSVD<3>
TP_CPU_RSVD<4>
TP_CPU_RSVD<33>
TP_CPU_RSVD<11>
DMI_S2N_N<1>
DMI_S2N_N<0>
TP_CPU_RSVD<6>
TP_CPU_RSVD<7>
TP_CPU_RSVD_NCTF<4>
TP_CPU_RSVD_NCTF<2>
TP_CPU_RSVD_NCTF<1>
TP_CPU_RSVD<41>
TP_CPU_RSVD<39>
CPU_FDI_LSYNC<1>
DMI_S2N_N<2>
SNS_CPU_THERMD_P
TP_CPU_RSVD<26>
TP_CPU_RSVD<25>
TP_CPU_RSVD<21>
=PEG_D2R_N<14>
TP_CPU_FDI_TX_N<3>
TP_CPU_FDI_TX_N<2>
TP_CPU_FDI_TX_N<1>
DMI_N2S_P<0>
DMI_N2S_N<3>
DMI_N2S_N<2>
DMI_N2S_N<1>
=PEG_R2D_C_N<5>
=PEG_D2R_N<3>
=PEG_D2R_N<4>
=PEG_D2R_N<5>
=PEG_D2R_N<6>
=PEG_D2R_N<7>
=PEG_D2R_N<10>
=PEG_D2R_N<15>
=PEG_D2R_P<2>
=PEG_R2D_C_P<3>
=PEG_R2D_C_N<4>
=PEG_D2R_P<4>
CPU_PEG_RBIAS
=PEG_D2R_N<0>
CPU_PEG_COMP
CPU_CFG<14>
=PEG_D2R_P<0>
=PEG_R2D_C_P<1>
TP_CPU_RSVD<24>
TP_CPU_RSVD<22>
SNS_CPU_THERMD_N
TP_CPU_RSVD<32>
CPU_CFG<8>
CPU_CFG<12>
CPU_CFG<4>
CPU_CFG<0>
CPU_CFG<5>
CPU_CFG<9>
CPU_CFG<6>
CPU_CFG<10>
CPU_CFG<2>
CPU_CFG<1>
CPU_CFG<17>
CPU_CFG<13>
DMI_MIDBUS_CLK100M_N
DMI_MIDBUS_CLK100M_P
=PEG_D2R_P<11>
=PEG_D2R_P<7>
=PEG_D2R_N<11>
=PEG_D2R_N<8>
DMI_S2N_N<3..0>
DMI_S2N_P<3..0>DMI_N2S_P<3..0>
DMI_N2S_N<3..0>
CPU DMI/PEG/FDI/RSVD
84 18
84 18
FTR-103-02-S-S
NOSTUFF
M-ST-SM
J1010
1
2
3
3
3
2
1
2
1
0
84 19 10
84 19 10
0
NOSTUFF
ST-SMLAI-TMS817J1050
3
1
6
4
9
7
12
10
15
13
18
16
21
19
24
22
2
8
14
20
5
11
17
23
2526
2728
3
2
1
3
2
1
0
0
84 19 10
84 19 10
LGA1156-SKT
OMIT
LYNNFIELD
U1000
E8
G8
K10
K8
J12
L8
K9
K12
H7
L11
E10
F10
H10
H9
E9
F9
G12
H12
A12
AD2
AE2
AH40
AJ39
AK12
AK13
AK14
AK15
AK16
AK18
AK25
AK26
AK27
AK28
AK29
AL12
AL14
AL15
AL17
AL18
AL26
AL27
AL29
AM13
AM14
AM15
AM16
AM17
AM18
AM19
AM20
AM21
AM25
AM26
AM27
AM28
AM29
AM30
L12
M12
A4
AU40
AV1
AV39
AW2
AW38
AY3
AY37
B3
C2
D1
AN11
LYNNFIELD
OMIT
LGA1156-SKT
U1000
R1
T1
U3
U2
U1
V1
W3
W2
L1
M1
N3
N2
N1
P1
R2
R3
AC4
AC3
AC2
AD4
AD3
U6
U5
V4
V3
U8
U7
W8
W7
W5
W4
R8
R7
Y4
Y3
Y6
Y5
D11
C10
A11
B10
C9
D9
B8
C8
G1
H1
J3
J2
J1
K1
L2
L3
P3
P4
T3
T4
A7
A6
B6
C6
A5
B5
B4
C4
C3
D3
D2
E2
E1
F1
G3
G2
C7
D7
E7
E6
L6
L5
M4
M3
K7
L7
N6
N5
M8
N8
R5
R6
E5
F5
F3
F4
G6
G5
H4
H3
F7
G7
J6
J5
K3
K4
H8
J8
84 25
84 25
84 25
84 25 15
84 25
84 25
84 25
84 25
84 25
84 25
84 25
84 25
84 25
84 25
84 25
84 25
84 25
84 25
1/16W1%49.9
MF-LF402
R10101
2
1%
MF-LF402
1/16W
750R10121
2
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
15
15
15
15
15
84 19 10
84 19 10
84 19 10
84 19 10
84 19 10
84 19 10
84 19 10
84 19 10
84 19 10
84 19 10
84 19 10
84 19 10
84 19 10
84 19 10
84 19 10
84 19 10
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8 8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
88 51
8
8
8 84
84
8
8
88 51
8
OUT
IN
IN
OUT
OUT
BI
BI
OUT
IN
OUT
IN
IN
IN
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
RSTIN*
TAPPWRGOOD
VTTPWRGOOD
SM_DRAMPWROK
VCCPWRGOOD_0
VCCPWRGOOD_1
PM_SYNC
RESET_OBS*
THERMTRIP*
TDO
COMP3
BPM_7*
BPM_4*
BPM_6*
BPM_5*
BPM_2*
BPM_3*
BPM_0*
BPM_1*
DBR*
TDO_M
TDI_M
TDI
TRST*
TMS
PREQ*
TCK
PM_EXT_TS_1*
PM_EXT_TS_0*
PRDY*
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
SM_DRAMRST*
PEG_CLK*
PEG_CLK
BCLK_ITP*
BCLK_ITP
BCLK_1*
BCLK_1
BCLK_0*
BCLK_0
SKTOCC*
COMP0
PROCHOT*
PECI
COMP2
CATERR*
COMP1
DDR3
MISC
JTAG & MBP
(2 OF 10)
CLOCKS
THERMAL
MISC
PWR MANAGEMENT
IN
IN
IN
OUT
IN
OUT
IN
IN
IN
IN
IN
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
COMES FROM VTT VR
DIVIDER IS BASED ON 2009 WW04 MOW
(GND)
11 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
=PP3V3_S5_CPURESET
PLT_RESET_LS3V3
CPU_RESET_L CPU_RESET_L_R
CPU_PWRGD
CPUVTT_REG_PGOOD
XDP_CPUPWRGD
PLT_RESET_LS1V1_L
GFX_CLK120M_DPLLSS_P
FSB_CLK133M_ITP_P
FSB_CLK133M_ITP_N
=PPVTT_S0_CPU
PLT_RESET_LS1V1_L
PM_MEM_PWRGD
CPU_PECI
FSB_CPURSTOUT_L
CPU_TDO_M_TDI_M
XDP_TMS
XDP_TCK
XDP_PREQ_L
FSB_CLK133M_CPU_N
CPU_PROCHOT_L
XDP_BPM_L<7>
XDP_TRST_L
XDP_BPM_L<6>
XDP_BPM_L<2>
XDP_BPM_L<1>
XDP_BPM_L<0>
XDP_DBRESET_L
XDP_TDO
XDP_TDI
XDP_BPM_L<3>
XDP_BPM_L<5>
CPU_COMP1
FSB_CLK133M_CPU_P
GFX_CLK120M_DPLLSS_N
XDP_BPM_L<4>
CPU_SKTOCC_L
=PP1V5_CPU_MEM
CPU_COMP0
PCIE_CLK100M_CPU_N
CPU_SM_RCOMP0
PM_EXT_TS_L<1>
XDP_PRDY_L
PM_EXT_TS_L<0>
CPU_MEM_RESET_L
PCIE_CLK100M_CPU_P
CPU_SM_RCOMP2
CPU_SM_RCOMP1
CPU_CATERR_L
PM_THRMTRIP_L
CPU_COMP2
CPU_COMP3
=PPVTT_S0_CPU
PM_SYNC
CPU CLOCK/MISC/JTAG
91 27
402
1%
MF-LF1/16W
10KR1125
12
MF-LF1/16W
1%10K
402
R11261
2
1%
MF-LF1/16W
402
150R11271
2
SOT-363-LFMMDT3904-X-GQ11775
3
4
SOT-363-LFMMDT3904-X-GQ11772
6
1
91 46
91 46
402
51
MF-LF
5%1/16W
R11041
2
X7R-CERM
0.1UF10%16V
402
NOSTUFF
C1100 1
2
91 19
84 18
84 25
84 18
84 25
84 18
84 18
84 21
OMIT
LGA1156-SKTLYNNFIELDU1000 AA7
AA6
AA8
Y8
AK39
AK40
AL33
AL32
AK33
AK32
AM31
AL30
AK30
AK31
AG39
AF36
AF2
B11
C11
AL40
AG35
AA3
AA4
AB5
AB4
AH39
AJ38
AK37
AH34
AL39
AF34
AK38
AH37
AV8
AG1
AD1
AE1
AK34
AN37
AM37
AF37
AM38
AF38
AF35
AN40
AM39
AH35
AH36
AG37
5%1/16W
402MF-LF
1KR11031
2
MF-LF
1%
402
1/16W
3.01KR11211
2
402
1/16WMF-LF
1%1.1K
R11201
2
91 25 21
402
1/16W5%51
MF-LF
R11701
2
84 21
PLACE R1161 CLOSE TO AD1
24.91%
402MF-LF1/16W
R11611
2
PLACE R1160 CLOSE TO AE1
1%
MF-LF1/16W
402
130R11601
2
PLACE R1162 CLOSE TO AG1
1%100
MF-LF1/16W
402
R11621
2
84 25
84 25
84 25
84 25
84 25
84 25
84 25
25
91 27 25
84 25
25
25
25
25
25
25
PLACE R1111 CLOSE TO B11
1%
MF-LF1/16W
402
20R1111
1
2
PLACE R1110 CLOSE TO C11
MF-LF
1%
402
1/16W
20R11101
2
PLACE R1113 CLOSE TO AF36
402
49.9
1/16W1%
MF-LF
R11131
2
PLACE R1112 CLOSE TO AF2
1%49.9
1/16WMF-LF402
R11121
2
402MF-LF
515%1/16W
R11001
2
515%
MF-LF1/16W
402
R11011
2
91 46 21
46
21
91 25
91 25
91 67 63 62
91 19
91 32
6
91 11
64 46 16 13 11 6
91 11
84
62
29 16 13 6
84
83
83
83
84
84
64 46 16 13 11 6
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
SA_ECC_CB_7
SA_ECC_CB_6
SA_ECC_CB_5
SA_ECC_CB_3
SA_ECC_CB_4
SA_ECC_CB_2
SA_ECC_CB_1
SA_ECC_CB_0
SA_MA_15
SA_MA_14
SA_MA_13
SA_MA_12
SA_MA_11
SA_MA_9
SA_MA_10
SA_MA_7
SA_MA_6
SA_MA_8
SA_MA_4
SA_MA_5
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_0
SA_DQS_8
SA_DQS_6
SA_DQS_7
SA_DQS_5
SA_DQS_4
SA_DQS_3
SA_DQS_2
SA_DQS_1
SA_DQS_0
SA_DQS_8*
SA_DQS_7*
SA_DQS_5*
SA_DQS_6*
SA_DQS_4*
SA_DQS_3*
SA_DQS_2*
SA_DQS_1*
SA_DQS_0*
SA_CS_3*
SA_CS_2*
SA_CS_1*
SA_CS_0*
SA_CS_4*
SA_CS_7*
SA_CS_6*
SA_CS_5*
SA_CK_2*
SA_CK_1*
SA_CK_0*
SA_DIMM_VREFDQ
SA_WE*
SA_RAS*
SA_CAS*
SA_DQ_6
SA_DQ_5
SA_DQ_13
SA_DQ_18
SA_DQ_17
SA_CKE_0
SA_DQ_7
SA_DQ_62
SA_DQ_61
SA_DQ_63
SA_BS_1
SA_BS_2
SA_BS_0
SA_DQ_52
SA_DQ_54
SA_DQ_53
SA_DQ_56
SA_DQ_57
SA_DQ_55
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_51
SA_DQ_42
SA_DQ_41
SA_DQ_43
SA_DQ_46
SA_DQ_47
SA_DQ_49
SA_DQ_48
SA_DQ_50
SA_DQ_45
SA_DQ_44
SA_DQ_40
SA_DQ_34
SA_DQ_36
SA_DQ_38
SA_DQ_39
SA_DQ_33
SA_DQ_35
SA_DQ_37
SA_DQ_20
SA_DQ_21
SA_DQ_23
SA_DQ_22
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_11
SA_DQ_12
SA_DQ_16
SA_DQ_15
SA_DQ_19
SA_DQ_10
SA_DQ_14
SA_DQ_9
SA_DQ_8
SA_DQ_0
SA_DQ_1
SA_DQ_4
SA_DQ_2
SA_DQ_3
SA_CK_0
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_CK_1
SA_CKE_1
SA_CK_2
SA_CKE_2
SA_CK_3
SA_CKE_3
SA_ODT_0
SA_ODT_2
SA_ODT_1
SA_ODT_3
SA_DM_0
SA_DM_2
SA_DM_1
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_CK_3*
(3 OF 10)
DDR SYSTEM MEMORY A
SB_DQS_2*
SB_DQS_0*
SB_DQS_1*
SB_DQS_5*
SB_DQS_6*
SB_DQS_7*
SB_DQS_8*
SB_DQS_3*
SB_DQS_4*
SB_CS_0*
SB_CS_2*
SB_CS_3*
SB_CS_1*
SB_CS_7*
SB_CS_6*
SB_CS_5*
SB_CS_4*
SB_CK_2*
SB_DQ_16
SB_DQ_1
SB_DQ_0
SB_DQ_8
SB_DQ_9
SB_DQ_52
SB_DQ_51
SB_DQ_38
SB_DQ_39
SB_DQ_63
SB_DQ_62
SB_DQ_61
SB_BS_2
SB_BS_0
SB_BS_1
SB_DQ_60
SB_DQ_59
SB_DQ_58
SB_DQ_57
SB_DQ_56
SB_DQ_55
SB_DQ_54
SB_DQ_53
SB_DQ_49
SB_DQ_47
SB_DQ_48
SB_DQ_46
SB_DQ_44
SB_DQ_45
SB_DQ_42
SB_DQ_41
SB_DQ_43
SB_DQ_50
SB_DQ_40
SB_DQ_33
SB_DQ_37
SB_DQ_35
SB_DQ_34
SB_DQ_36
SB_DQ_32
SB_DQ_31
SB_DQ_27
SB_DQ_26
SB_DQ_25
SB_DQ_24
SB_DQ_23
SB_DQ_22
SB_DQ_21
SB_DQ_20
SB_DQ_19
SB_DQ_18
SB_DQ_17
SB_DQ_15
SB_DQ_14
SB_DQ_13
SB_DQ_12
SB_DQ_11
SB_DQ_7
SB_DQ_6
SB_DQ_5
SB_DQ_4
SB_DQ_2
SB_DQ_3
SB_DIMM_VREFDQ SB_MA_15
SB_MA_10
SB_MA_12
SB_MA_11
SB_MA_13
SB_MA_14
SB_MA_8
SB_MA_9
SB_MA_7
SB_MA_6
SB_MA_5
SB_MA_4
SB_MA_2
SB_MA_1
SB_MA_0
SB_MA_3
SB_DQS_8
SB_DQS_6
SB_DQS_5
SB_DQS_4
SB_DQS_3
SB_DQS_1
SB_DQS_2
SB_DQS_0
SB_ECC_CB_0
SB_ECC_CB_1
SB_ECC_CB_2
SB_ECC_CB_3
SB_ECC_CB_5
SB_ECC_CB_4
SB_ECC_CB_6
SB_ECC_CB_7
SB_DM_7
SB_DM_6
SB_DM_5
SB_DM_4
SB_DM_2
SB_DM_0
SB_ODT_3
SB_ODT_2
SB_ODT_1
SB_ODT_0
SB_CKE_3
SB_CK_3
SB_CKE_2
SB_CKE_1
SB_CK_2
SB_CK_1
SB_CKE_0
SB_CK_0
SB_DQS_7
SB_DM_3
SB_DM_1
SB_DQ_10
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_WE*
SB_CK_3*
SB_CK_1*
SB_CAS*
SB_CK_0*
SB_RAS*
(4 OF 10)
DDR SYSTEM MEMORY B
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTOUT OUT
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
12 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
MEM_A_CKE<0>
MEM_A_CLK_N<1>
MEM_A_CKE<2>
MEM_A_CLK_P<3>
MEM_A_CLK_N<3>
TP_MEM_A_CS_L<5>
TP_MEM_A_CS_L<6>
TP_MEM_A_CS_L<7>
MEM_A_ODT<0>
MEM_A_ODT<1>
MEM_A_DM<2>
MEM_A_DM<3>
MEM_A_DM<4>
MEM_A_DM<5>
MEM_A_DM<6>
MEM_A_DM<7>
MEM_A_DM<1>
MEM_A_DM<0>
MEM_A_ODT<3>
MEM_A_ODT<2>
MEM_A_CKE<3>
MEM_A_CLK_P<2>
MEM_A_CKE<1>
MEM_A_CLK_P<1>
MEM_A_DQ<32>
MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<29>
MEM_A_DQ<3>
MEM_A_DQ<2>
MEM_A_DQ<4>
MEM_A_DQ<0>
MEM_A_DQ<8>
MEM_A_DQ<9>
MEM_A_DQ<14>
MEM_A_DQ<10>
MEM_A_DQ<19>
MEM_A_DQ<15>
MEM_A_DQ<16>
MEM_A_DQ<12>
MEM_A_DQ<11>
MEM_A_DQ<28>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DQ<25>
MEM_A_DQ<24>
MEM_A_DQ<22>
MEM_A_DQ<23>
MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<37>
MEM_A_DQ<35>
MEM_A_DQ<33>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<36>
MEM_A_DQ<34>
MEM_A_DQ<40>
MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<50>
MEM_A_DQ<48>
MEM_A_DQ<49>
MEM_A_DQ<47>
MEM_A_DQ<46>
MEM_A_DQ<43>
MEM_A_DQ<41>
MEM_A_DQ<42>
MEM_A_DQ<51>
MEM_A_DQ<60>
MEM_A_DQ<59>
MEM_A_DQ<58>
MEM_A_DQ<55>
MEM_A_DQ<57>
MEM_A_DQ<56>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<52>
MEM_A_BA<0>
MEM_A_BA<2>
MEM_A_BA<1>
MEM_A_DQ<63>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<7>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<13>
MEM_A_DQ<5>
MEM_A_DQ<6>
MEM_A_CAS_L
MEM_A_RAS_L
MEM_A_WE_L
CPU_DIMM_VREF_A
MEM_A_CLK_N<2>
TP_MEM_A_CS_L<4>
MEM_A_CS_L<2>
MEM_A_CS_L<3>
MEM_A_DQS_N<0>
MEM_A_DQS_N<1>
MEM_A_DQS_N<2>
MEM_A_DQS_N<3>
MEM_A_DQS_N<4>
MEM_A_DQS_N<6>
MEM_A_DQS_N<5>
MEM_A_DQS_N<7>
TP_MEM_A_DQS_N<8>
MEM_A_DQS_P<0>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2>
MEM_A_DQS_P<3>
MEM_A_DQS_P<4>
MEM_A_DQS_P<5>
MEM_A_DQS_P<7>
MEM_A_DQS_P<6>
TP_MEM_A_DQS_P<8>
MEM_A_A<0>
MEM_A_A<3>
MEM_A_A<2>
MEM_A_A<1>
MEM_A_A<5>
MEM_A_A<4>
MEM_A_A<8>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<10>
MEM_A_A<9>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>
TP_MEM_A_DQ_CB<0>
TP_MEM_A_DQ_CB<1>
TP_MEM_A_DQ_CB<2>
TP_MEM_A_DQ_CB<4>
TP_MEM_A_DQ_CB<3>
TP_MEM_A_DQ_CB<5>
TP_MEM_A_DQ_CB<6>
TP_MEM_A_DQ_CB<7>
MEM_B_RAS_L
MEM_B_CLK_N<0>
MEM_B_CAS_L
MEM_B_CLK_N<1>
MEM_B_CLK_N<3>
MEM_B_WE_L
MEM_B_DQ<30>
MEM_B_DQ<29>
MEM_B_DQ<28>
MEM_B_DQ<10>
MEM_B_DM<1>
MEM_B_DM<3>
MEM_B_DQS_P<7>
MEM_B_CLK_P<0>
MEM_B_CKE<0>
MEM_B_CLK_P<1>
MEM_B_CLK_P<2>
MEM_B_CKE<1>
MEM_B_CKE<2>
MEM_B_CLK_P<3>
MEM_B_CKE<3>
MEM_B_ODT<0>
MEM_B_ODT<1>
MEM_B_ODT<2>
MEM_B_ODT<3>
MEM_B_DM<0>
MEM_B_DM<2>
MEM_B_DM<4>
MEM_B_DM<5>
MEM_B_DM<6>
MEM_B_DM<7>
TP_MEM_B_DQ_CB<7>
TP_MEM_B_DQ_CB<6>
TP_MEM_B_DQ_CB<4>
TP_MEM_B_DQ_CB<5>
TP_MEM_B_DQ_CB<3>
TP_MEM_B_DQ_CB<2>
TP_MEM_B_DQ_CB<1>
TP_MEM_B_DQ_CB<0>
MEM_B_DQS_P<0>
MEM_B_DQS_P<2>
MEM_B_DQS_P<1>
MEM_B_DQS_P<3>
MEM_B_DQS_P<4>
MEM_B_DQS_P<5>
MEM_B_DQS_P<6>
TP_MEM_B_DQS_P<8>
MEM_B_A<3>
MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<14>
MEM_B_A<13>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<10>
MEM_B_A<15>CPU_DIMM_VREF_B
MEM_B_DQ<3>
MEM_B_DQ<2>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_B_DQ<13>
MEM_B_DQ<14>
MEM_B_DQ<15>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<19>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<27>
MEM_B_DQ<31>
MEM_B_DQ<32>
MEM_B_DQ<36>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<37>
MEM_B_DQ<33>
MEM_B_DQ<40>
MEM_B_DQ<50>
MEM_B_DQ<43>
MEM_B_DQ<41>
MEM_B_DQ<42>
MEM_B_DQ<45>
MEM_B_DQ<44>
MEM_B_DQ<46>
MEM_B_DQ<48>
MEM_B_DQ<47>
MEM_B_DQ<49>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_BA<1>
MEM_B_BA<0>
MEM_B_BA<2>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>
MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<9>
MEM_B_DQ<8>
MEM_B_DQ<0>
MEM_B_DQ<1>
MEM_B_DQ<16>
MEM_B_CLK_N<2>
TP_MEM_B_CS_L<4>
TP_MEM_B_CS_L<5>
TP_MEM_B_CS_L<6>
TP_MEM_B_CS_L<7>
MEM_B_CS_L<1>
MEM_B_CS_L<3>
MEM_B_CS_L<2>
MEM_B_CS_L<0>
MEM_B_DQS_N<4>
MEM_B_DQS_N<3>
TP_MEM_B_DQS_N<8>
MEM_B_DQS_N<7>
MEM_B_DQS_N<6>
MEM_B_DQS_N<5>
MEM_B_DQS_N<1>
MEM_B_DQS_N<0>
MEM_B_DQS_N<2>
MEM_A_DQ<1>
MEM_A_CS_L<1>
MEM_A_CS_L<0>
CPU DDR3 INTERFACESSYNC_MASTER=K60_SIJI SYNC_DATE=07/01/2009
83 31 83 30 83 28
83 31
83 31
83 31
83 31
83 31
83 32
83 32
83 31
83 32
83 32
83 30
83 32
83 32
83 30
83 32
83 32
83 30
83 30
83 30
83 30
83 28
OMIT
LGA1156-SKTLYNNFIELDU1000
AU25
AW25
AV12
AW27
AR17
AR16
AT15
AR15
AN17
AN16
AR19
AR18
AW8
AY9
AU9
AV9
AY27
AW29
AV26
AV29
AM23
AM24
AL24
AK24
AG3
AE4
AH4
AM7
AT7
AN24
AN32
AM33
AK35
AD7
AD6
AK6
AL4
AG6
AG4
AJ7
AK7
AL6
AN5
AP6
AR5
AH8
AL5
AM4
AN7
AP5
AT6
AR7
AR9
AM8
AN8
AR6
AJ8
AL8
AT9
AN23
AP23
AR25
AR26
AT23
AP22
AP25
AT26
AC7
AT32
AP31
AR33
AM32
AT31
AR31
AR34
AT33
AR35
AT36
AC6
AN33
AP36
AP34
AT35
AN34
AP37
AL35
AM35
AJ36
AJ37
AF5
AN35
AM34
AJ35
AL36
AE6
AG5
AH7
AF4
AE5
AH6
AJ5
AN6
AM6
AR8
AP8
AT25
AR24
AP32
AR32
AR36
AR37
AL37
AM36
AR14
AR13
AR12
AT13
AN15
AP14
AM12
AN12
AN14
AP13
AU20
AU18
AY25
AW16
AW15
AW28
AY12
AV11
AV18
AU17
AY18
AV17
AW17
AU16
AT17
AY16
AU27
AU29
AV27
AU28
AW26
AU26
OMIT
LGA1156-SKTLYNNFIELDU1000
AV20
AU19
AU12
AU22
AR22
AR21
AP18
AN18
AN21
AP21
AP19
AN19
AU10
AW10
AV10
AY10
AV21
AW24AU21
AU23
AK22
AM22
AL23
AK23
AF3
AJ2
AN1
AU1
AV6
AN29
AW31
AU35
AT38
AH1
AJ4
AR3
AR2
AM3
AM2
AP1
AR4
AT4
AU2
AW3
AW4
AL2
AT3
AT1
AV2
AV4
AW5
AY5
AU8
AY8
AU5
AV5
AL1
AV7
AW7
AN27
AT28
AP28
AP30
AN26
AR27
AR29
AN30
AG2
AU30
AU31
AV33
AU34
AV30
AW30
AU33
AW33
AW35
AY35
AH2
AV37
AU37
AY34
AW34
AV36
AW37
AT39
AT40
AN38
AN39
AK1
AU38
AU39
AP39
AP40
AK2
AN3
AN2
AK3
AJ3
AP2
AP3
AU4
AU3
AY6
AW6
AR28
AT29
AV32
AW32
AW36
AV35
AR39
AR38
AL10
AM10
AP10
AN10
AR11
AP11
AK9
AL9
AK11
AM11
AW18
AY15
AT19
AU13
AW11
AU24
AT11
AR10
AV15
AU15
AW14
AY13
AV14
AW13
AU14
AW12
AV23
AV24
AW23
AY24
AT20
AT2283 31
83 31
83 31
83 31
83 31
83 31
83 31
83 31
83 31
83 31
83 31
83 31
83 31
83 31
83 31
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 31
83 31
83 31
83 31
83 31
83 32
83 32
83 31
83 32
83 32
83 31
83 31
83 31
83 31
83 31
83 31
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 30
83 30
83 30
83 30
83 30
83 32
83 32
83 30
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 30
83 30
83 30
83 30
83 30
83 30
83 30
83 30
83 30
83 30
83 30
83 30
83 30
83 30
83 30
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 30
83 30
83 30
83 30
83 30
83 30
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
83 32
8
8
8
8
83 8
83 8
8
8
8
8
8
8
8
8 8
8
8
8
8
8
8
8
83 8
8
8
8
8
83 8
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
PSI*
VID_1/MSID_1
VID_2/MSID_2
VID_3/CSC_0
VID_5/CSC_2
VID_6
ISENSE
VID_7
VID_4/CSC_1
VID_0/MSID_0
VCC_74
VCC_73
VCC_75
VCC_76
VCC_77
VCC_39
VCC_38
VCC_37
VCC_36
VTT_33
VTT_10
VTT_4
VTT_42
VTT_44
VTT_46
VTT_49
VTT_51
VTT_53
VTT_56
VTT_57
VTT_59
VTT_61
VTT_63
VTT_65
VTT_68
VTT_70
VTT_75
VTT_77
VTT_SELECT
VTT_12
VTT_13
VTT_14
VTT_16
VCC_13
VCC_12
VCC_11
VTT_5
VCC_3
VCC_2
VCC_SENSE
VSS_SENSE
VTT_3
VTT_8
VTT_6
VTT_73
VTT_74
VTT_76
VTT_66
VTT_72
VCC_80
VCC_72
VCC_89
VCC_56
VSS_SENSE_VTT
VTT_SENSE
VCC_88
VCC_87
VCC_86
VCC_85
VCC_84
VCC_4
VCC_1
VCC_9
VCC_8
VCC_7
VCC_5
VCC_10
VCC_14
VCC_18
VCC_19
VCC_17
VCC_16
VCC_15
VCC_21
VCC_22
VCC_23
VCC_24
VCC_20
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_34
VCC_33
VCC_32
VCC_31
VCC_40
VCC_45
VCC_44
VCC_43
VCC_42
VCC_41
VCC_50
VCC_49
VCC_48
VCC_47
VCC_46
VCC_55
VCC_53
VCC_52
VCC_51
VCC_60
VCC_59
VCC_58
VCC_57
VCC_64
VCC_65
VCC_62
VCC_63
VCC_61
VCC_70
VCC_69
VCC_68
VCC_67
VCC_66
VCC_71
VCC_81
VCC_82
VCC_83
VCC_90
VCC_91
VCC_92
VCC_93
VCC_94
VCC_95
VCC_96
VCC_99
VCC_97
VCC_98
VTT_2
VTT_0
VTT_1
VTT_9
VTT_11
VTT_15
VTT_17
VTT_18
VTT_23
VTT_22
VTT_24
VTT_21
VTT_25
VTT_26
VTT_29
VTT_27
VTT_34
VTT_35
VTT_50
VTT_47
VTT_48
VTT_52
VTT_54
VTT_60
VTT_58
VTT_62
VTT_64
VTT_67
VTT_69
VTT_71
VTT_43
VTT_41
VTT_39
VTT_38
VTT_37
VTT_36
VCC_0
VCC_54
VTT_55
VTT_45
VTT_40
VTT_32
VTT_31
VTT_30
VTT_28
VTT_20
VTT_19
VCC_6
VTT_7
VCC_35
VCC_78
VCC_79
POWER
1.1V RAIL POWER
SENSE LINES
CPU CORE SUPPLY
(6 OF 10)
CPU VIDS
OUT
VAXG_14
VAXG_15
VAXG_16
VAXG_17
VAXG_0
VAXG_2
VAXG_36
VAXG_34
VAXG_SENSE
VSSAXG_SENSE
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4
GFX_VID_5
GFX_VID_6
GFX_VR_EN
GFX_DPRSLPVR
GFX_IMON
VDDQ_2
VDDQ_1
VDDQ_0
VDDQ_4
VDDQ_3
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_15
VDDQ_14
VDDQ_17
VDDQ_18
VCCPLL_0
VCCPLL_1
VAXG_9
VAXG_8
VAXG_3
VAXG_4
VAXG_7
VAXG_6
VAXG_5
VAXG_18
VAXG_19
VAXG_23
VAXG_24
VAXG_22
VAXG_21
VAXG_20
VAXG_25
VAXG_28
VAXG_29
VAXG_26
VAXG_27
VAXG_33
VAXG_35
VAXG_37
VAXG_38
VAXG_39
VAXG_40
VAXG_41
VAXG_42
VAXG_43
VAXG_44
VAXG_45
VAXG_46
VAXG_47
VAXG_48
VAXG_13
VAXG_12
VAXG_11
VAXG_10
VAXG_32
VAXG_31
VAXG_30
VAXG_1
VCCPLL_2
VDDQ_16
GRAPHICS VIDS
1.8V
DDR3-1.5V RAILS
SENSE
LINES
( 7 OF 10 )
POWER
GRAPHICS
VCC_NCTF_0
VCC_NCTF_1
CGC_TP_NCTF
FC_AE38
FC_AG40
VCC_100
VCC_104
VCC_103
VCC_102
VCC_101
VCC_105
VCC_106
VCC_107
VCC_108
VCC_109
VCC_110
VCC_111
VCC_112
VCC_114
VCC_119
VCC_118
VCC_117
VCC_115
VCC_116
VCC_124
VCC_123
VCC_122
VCC_121
VCC_120
VCC_125
VCC_126
VCC_130
VCC_134
VCC_133
VCC_132
VCC_131
VCC_135
VCC_138
VCC_139
VCC_137
VCC_136
VCC_140
VCC_145
VCC_144
VCC_143
VCC_142
VCC_141
VCC_146
VCC_150
VCC_149
VCC_148
VCC_147
VCC_155
VCC_154
VCC_153
VCC_152
VCC_151
VCC_160
VCC_159
VCC_158
VCC_157
VCC_156
VCC_165
VCC_164
VCC_163
VCC_162
VCC_161
VCC_168
VCC_169
VCC_170
VCC_167
VCC_166
VCC_171
VCC_172
VCC_173
VCC_174
VCC_175
VCC_176
VCC_177
VCC_178
VCC_179
VCC_180
VCC_181
VCC_113
VCC_129
VCC_128
VCC_127
(10 OF 10)VCC
NCTF
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
CONNECTED TO THE IMON OUT FROM CPU REG
THIS SUPPLY IS NEEDED ONLY FOR SYSTEM WITH DALE IG
(Controlled by VTT_SELECT pin)
13 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
CPU_VID<7>
CPU_VID<6>
CPU_VID<5>
CPU_VID<3>
CPU_VID<2>
TP_CPU_VTTSELECT
=PPVTT_S0_CPU
=PPVCORE_S0_CPU
TP_GFX_VR_EN
=PPVAXG_S0_CPU
CPU_VTTSENSE_P
VR_CPU_IOUT
=PPVCORE_S0_CPU
TP_GFX_VID<0>
TP_GFX_VSENSE_P
TP_GFX_VSENSE_N
TP_GFX_VID<1>
TP_GFX_VID<2>
TP_GFX_VID<3>
TP_GFX_VID<4>
TP_GFX_VID<5>
TP_GFX_VID<6>
TP_GFX_DPRSLPVR
=PP1V5_CPU_MEM
=PP1V8_S0_CPU_PLL
CPU_PSI_L
CPU_VID<1>
CPU_VID<4>
CPU_VID<0>
CPU_VCC_PKG_SENSE_P
CPU_VCC_PKG_SENSE_N
CPU_VTTSENSE_N
=PPVCORE_S0_CPU
TP_CPU_CGC_NCTF
TP_CPU_FC_AE38
TP_CPU_FC_AG40
CPU POWERSYNC_DATE=07/01/2009SYNC_MASTER=K60_SIJI
OMIT
LYNNFIELDLGA1156-SKT
U1000
B39
AE38
AG40
J21
J22
J24
J25
J27
J28
J30
J31
J33
J34
J36
J37
J39
J40
K17
K18
K20
K21
K23
K24
K26
K27
K29
K30
K32
K33
K35
K36
K38
K39
L17
L19
L20
L22
L23
L25
L26
L28
L29
L31
L32
L34
L35
L37
L38
L40
M17
M19
M21
M22
M24
M25
M27
M28
M30
M33
M34
M36
M37
M39
M40
N33
N35
N36
N38
N39
P33
P34
P35
P36
P37
P38
P39
P40
R33
R34
R35
R36
R37
R38
R39
R40
A38
C40
OMIT
LGA1156-SKTLYNNFIELDU1000
J10
F6
G10
B12
E12
E11
C12
G11
J11
F12
A14
A15
C17
C18
C20
C21
D14
D15
D17
D18
D20
D21
A17
E14
E15
E17
E18
E20
F14
F15
F17
F18
F19
A18
G14
G15
G17
G18
H14
H15
H17
J14
J15
J16
B14
K14
K15
K16
L14
L15
L16
M14
M15
M16
B15
B17
B18
C14
C15
A13
AF7
AF8
AG8
AJ11
AJ13
AV22
AV25
AV28
AW9
AY11
AY14
AY17
AY23
AY26
AJ15
AT10
AT18
AT21
AU11
AV13
AV16
AV19
B13
89 64 16
OMIT
LYNNFIELDLGA1156-SKT
U1000
T40
AG38
A23
A24
B28
B29
B31
B32
B34
B35
B37
B38
C23
C24
A26
C25
C27
C28
C30
C31
C33
C34
C36
C37
C39
A27
D23
D24
D26
D27
D29
D30
D32
D33
D35
D36
A33
D38
D39
E22
E23
E25
E26
E28
E29
E31
E32
A35
E34
E35
E37
E38
E40
F21
F22
F24
F25
F27
A36
F28
F30
F31
F33
F34
F36
F37
F39
F40
G20
B23
G21
G23
G24
G26
G27
G29
G30
G32
G33
G35
B25
G36
G38
G39
H19
H20
H22
H23
H25
H26
H28
B26
H29
H31
H32
H34
H35
H37
H38
H40
J18
J19
T35
U40
U39
U38
U37
U36
U35
U34
U33
T34
AE36
AA33
AA34
AC36
AC37
AC38
AC39
AC40
AC5
AC8
AD33
AD34
AD35
AA35
AD36
AD37
AD38
AD39
AD40
AE33
AE34
AE39
AE40
AE8
AA36
AF33
AG33
AJ17
AJ19
AJ21
AJ23
AJ25
AJ27
AJ29
AJ31
AA37
AJ32
AK19
AK20
AK21
AL20
AL21
L10
M10
M11
M9
AA38
N7
P6
P7
P8
T2
T6
T7
T8
V2
V33
AB7
V34
V35
V36
V37
V38
V39
V40
V6
V7
V8
AC33
W1
W6
Y33
Y34
Y35
Y36
Y37
Y38
AC34
AC35
AF39
AE35
89 64 49
89 64
88 64
89 67
89 67 49
89 64 16
89 64 16
89 64 16
89 64 16
89 64 16
89 64 16
89 64 16
89 64 16
64 46 16 11 6
16 13 6
17 6
16 13 6
8
8
8
8
8
8
8
8
8
29 16 11 6
63 16 6
16 13 6
8
8
VSS_27
VSS_26
VSS_84
VSS_83
VSS_82
VSS_80
VSS_81
VSS_89
VSS_88
VSS_87
VSS_85
VSS_86
VSS_94
VSS_93
VSS_92
VSS_90
VSS_91
VSS_99
VSS_98
VSS_95
VSS_96
VSS_97
VSS_104
VSS_103
VSS_102
VSS_100
VSS_101
VSS_105
VSS_109
VSS_108
VSS_107
VSS_106
VSS_110
VSS_111
VSS_114
VSS_112
VSS_113
VSS_115
VSS_119
VSS_118
VSS_117
VSS_116
VSS_120
VSS_125
VSS_124
VSS_122
VSS_121
VSS_123
VSS_130
VSS_129
VSS_128
VSS_127
VSS_126
VSS_134
VSS_133
VSS_132
VSS_135
VSS_131
VSS_140
VSS_139
VSS_138
VSS_137
VSS_136
VSS_145
VSS_144
VSS_143
VSS_141
VSS_142
VSS_150
VSS_149
VSS_148
VSS_146
VSS_147
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_159
VSS_157
VSS_158
VSS_1
VSS_0
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_11
VSS_12
VSS_13
VSS_14
VSS_10
VSS_18
VSS_15
VSS_17
VSS_16
VSS_19
VSS_23
VSS_22
VSS_21
VSS_20
VSS_24
VSS_25
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_45
VSS_44
VSS_48
VSS_49
VSS_50
VSS_47
VSS_46
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_57
VSS_56
VSS_58
VSS_59
VSS_60
VSS_65
VSS_64
VSS_63
VSS_62
VSS_70
VSS_69
VSS_68
VSS_67
VSS_66
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_78
VSS_77
VSS_79
VSS_28
VSS_61
( 8 OF 10 )
VSS
VSS_277
VSS_276
VSS_275
VSS_188
VSS_164
VSS_165
VSS_176
VSS_175
VSS_174
VSS_224
VSS_223
VSS_221
VSS_220
VSS_219
VSS_218
VSS_217
VSS_216
VSS_215
VSS_214
VSS_213
VSS_212
VSS_211
VSS_210
VSS_209
VSS_208
VSS_207
VSS_206
VSS_205
VSS_204
VSS_203
VSS_202
VSS_201
VSS_200
VSS_199
VSS_198
VSS_197
VSS_196
VSS_193
VSS_191
VSS_190
VSS_189
VSS_187
VSS_186
VSS_183
VSS_182
VSS_180
VSS_179
VSS_178
VSS_170
VSS_171
VSS_172
VSS_173
VSS_168
VSS_169
VSS_160
VSS_161
VSS_163
VSS_271
VSS_270
VSS_268
VSS_269
VSS_266
VSS_265
VSS_260
VSS_262
VSS_261
VSS_259
VSS_256
VSS_258
VSS_257
VSS_255
VSS_254
VSS_250
VSS_253
VSS_251
VSS_252
VSS_249
VSS_246
VSS_248
VSS_247
VSS_245
VSS_240
VSS_243
VSS_241
VSS_242
VSS_235
VSS_238
VSS_236
VSS_237
VSS_234
VSS_229
VSS_230
VSS_233
VSS_232
VSS_231
VSS_227
VSS_228
VSS_226
VSS_225
VSS_222
VSS_162
VSS_274
VSS_273
VSS_272
VSS_239
VSS_244VSS_185
VSS_184
VSS_195
VSS_194
VSS_192
VSS_181
VSS_167
VSS_166
VSS_267
VSS_264
VSS_263
VSS_177
(9 OF 10)
VSS
SKT MNT HOLE
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
14 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
CPU GROUNDS
OMIT
LYNNFIELDLGA1156-SKT
U1000
1157
1158
1159
E24
E27
E3
E30
E33
E36
E39
E4
F11
F13
F16
F2
F20
F23
F26
F29
F32
F35
F38
F8
G13
G16
G19
G22
G25
G28
G31
G34
G37
G4
G40
G9
H11
H13
H16
H18
H2
H21
H24
H27
H30
H33
H36
H39
H5
H6
J13
J17
J20
J23
J26
J29
J32
J35
J38
J4
J7
J9
K11
K13
K19
K2
K22
K25
K28
K31
K34
K37
K40
K5
K6
L13
L18
L21
L24
L27
L30
L33
L36
L39
L4
L9
M13
M18
M2
M20
M23
M26
M29
M32
M35
M38
M5
M6
M7
N34
N37
N4
N40
P2
P5
R4
T33
T36
T37
T38
T39
T5
U4
V5
W33
W34
W35
W36
W37
W38
Y7
AF6
OMIT
LGA1156-SKTLYNNFIELDU1000A16
A25
AB36
AT14
AT16
AT2
AT24
AT27
AT30
AT34
AT37
AT5
AT8
AB37
AU32
AU36
AU6
AU7
AV3
AV31
AV34
AV38
AY33
AY36
AB38
AY4
AY7
B16
B24
B27
B30
B33
B36
B7
B9
AB39
C13
C16
C19
C22
C26
C29
C32
C35
C38
C5
AB40
D10
D12
D13
D16
D19
D22
D25
D28
D31
D34
AB6
D37
D4
D40
D5
D6
D8
E13
E16
E19
E21
AB8
AC1
AD5
AD8
A28
AE3
AE37
AE7
AF1
AF40
AG34
AG36
AG7
AH3
AH33
A34
AH38
AH5
AJ1
AJ12
AJ14
AJ16
AJ18
AJ20
AJ22
AJ24
A37
AJ26
AJ28
AJ30
AJ33
AJ34
AJ40
AJ6
AJ9
AK10
AK17
AA5
AK36
AK4
AK5
AK8
AL11
AL13
AL16
AL19
AL22
AL25
AB3
AL28
AL3
AL31
AL34
AL38
AL7
AM1
AM40
AM5
AM9
AB33
AN13
AN20
AN22
AN25
AN28
AN31
AN36
AN4
AN9
AP12
AB34
AP15
AP16
AP17
AP20
AP24
AP26
AP27
AP29
AP33
AP35AB35
AP38
AP4
AP7
AP9
AR1
AR20
AR23
AR30
AR40
AT12
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
IF LIKE TO HAVE THE PEB CLOCKS ENABLED. STUFF R1535 AND UNSTUFF R1534
15 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
ODD_PWR_EN_L
PCH_PCI_GNT3_L
PCH_PCI_GNT2_L
PCH_PCI_GNT0_L
PCH_INIT3V3_L
PCH_NV_CLE
PCH_FDI_INT
PCH_FDI_LSYNC<0>
CPU_FDI_FSYNC<0>
CPU_FDI_LSYNC<0>
CPU_FDI_INT
CPU_FDI_FSYNC<1>
CPU_CFG<3>
PEB_CLKREQ_L
EXCARD_CLKREQ_L
ENET_ENERGY_DET
PM_LAN_PWRGD
ENET_LOW_PWR
AP_PWR_EN
=PP3V3_S3_PCH_STRAPS
MINI_CLKREQ_L
PCH_GPIO8_FCIM_EN_L
PCH_FDI_LSYNC<1>
=PP3V3_S5_PCH_STRAPS
=PP3V3_S0_PCH_STRAPS
=PP3V3_S5_PCH_STRAPS
PCH_GPIO24
PCH_GPIO27_VRMEN
PCH_FDI_FSYNC<1>
PCH_FDI_FSYNC<0>
PCH_GPIO49_SATA5GP
SMC_RUNTIME_SCI_L
PCH_GPIO34_STP_PCI_L
=PP3V3_S0_PCH_STRAPS
BRCRYPT_PWR_EN
PCH_PCI_GNT1_L
WOL_EN
=PP3V3_S0_PCH_STRAPS
PM_BATLOW_L
ENET_CLKREQ_L
PCH_GPIO14_OC7_L
PCH_CLKOUTFLEX1
PCH_CLKOUTFLEX3
PCH_CLKOUTFLEX2
SPI_DESCRIPTOR_OVERRIDE_L
=PP3V3_S0_PCH_STRAPS
BRCRYPT_RESET
PCH_GPIO0_BMBUSY_L
PCH_GPIO19_SATA1GP
CPU_FDI_LSYNC<1>
T28_CLKREQ_L
PCH_GPIO15
FW_PWR_EN
PCH_GPIO6_TACH2
FW_PME_L
PCH_GPIO37_SATA3GP
PCH_GPIO21_SATA0GP
PCH_GPIO38_SLOAD
PCH_GPIO39_SDATAOUT0
FW_CLKREQ_L
=PP3V3_S0_PCH_STRAPS
PM_CLKRUN_L
PCH_NV_ALE
PCH_SPKR
SYNC_MASTER=K60_SIJI SYNC_DATE=07/01/2009
STRAPS,PULL UPS,PULL DOWNS FOR PCH AND CPU
1/16W
402MF-LF
5%10K
R15121
2
1/16W5%
10K
MF-LF402
R15911
2
MF-LF
10K5%
402
1/16W
R15901
2
MF-LF402
5%1/16W
10KR15291
2
10K5%
MF-LF402
1/16W
R15551
2
10K5%
MF-LF402
1/16W
R15111
2
1/16WMF-LF402
5%10K
R15101
2
402
5%10K
MF-LF1/16W
R15081
2 402MF-LF
10K5%
1/16W
R15071
2
10K5%
1/16W
402MF-LF
R15061
2
5%1/16WMF-LF402
10KR15751
2
10K
402MF-LF1/16W
5%
R15741
2
10K5%
402MF-LF1/16W
R15731
2
1/16W5%
402MF-LF
10KR1572
1
2
5%1/16WMF-LF402
10KR15711
2 402MF-LF1/16W
5%10K
R15701
2
402
10K5%
1/16WMF-LF
R15041
2
402MF-LF1/16W
5%1K
R15651
2
5%
402
1/16WMF-LF
1KR15661
2
5%
MF-LF402
1/16W
1KR15671
2
MF-LF402
1/16W5%1K
R15681
2
1/16W5%
MF-LF402
1KR15691
2
1K5%
1/16WMF-LF402
R15601
2
1K
MF-LF1/16W
402
5%
R15611
2
1K
1/16W
402MF-LF
5%
R15621
2
5%1/16WMF-LF
10K
402
R15031
2
1K5%
1/16W
402MF-LF
R15631
2
1K
1/16W
402MF-LF
5%
R15641
2
10K5%
MF-LF402
1/16W
NOSTUFFR15541
2
1/16W
402MF-LF
5%10K
NOSTUFFR15531
21/16W
402MF-LF
5%10K
NOSTUFFR15521
2402MF-LF1/16W
5%10K
NOSTUFFR15511
2
5%1K
MF-LF1/16W
402
NOSTUFFR15501
2
10K
MF-LF402
1/16W5%
R15431
2 402
5%1/16WMF-LF
10K
NOSTUFFR15421
2
5%
402
1/16WMF-LF
10K
NOSTUFFR15411
2
10K
402
1/16W5%
MF-LF
R15391
2
1/16W5%
10K
MF-LF402
R15381
2
402
MLB_VR
MF-LF
5%1/16W
1KR1598
1
2
1/16W5%
10K
MF-LF402
NOSTUFFR15371
2
5%1/16WMF-LF402
10KR1536
1
2
MF-LF
5%1/16W
402
1K
FCIMR15991
2
1/16W
10K
402MF-LF
5%
R15351
2
1/16W
402MF-LF
5%10K
R15341
2
MF-LF1/16W
5%10K
402
R15321
2
5%
MF-LF402
1/16W
10KR1501
1
2
402MF-LF
10K5%
1/16W
R15331
2
1/16W
402
5%
MF-LF
10KR15261
2MF-LF1/16W
5%
402
10KR15281
2MF-LF402
10K5%
1/16W
R15271
2
PCH_VRM
1/16W
402
5%10K
MF-LF
R15301
2
10K5%
1/16W
402MF-LF
R15221
2
5%1/16WMF-LF
10K
402
R15231
2MF-LF402
5%1/16W
10KR15241
2
10K
MF-LF402
5%1/16W
R15251
2
402MF-LF1/16W
10K5%
R15151
2
1/16WMF-LF402
5%
BUF_CLK
10KR1517
1
2
10K
402
5%
MF-LF1/16W
R15091
2
402
1/16W5%
1.5K
MF-LF
NOSTUFFR1500
1
2
42 21
20
20
20
21
20
19
19
10
10
10
10
84 25 10
18
18
36 18
91 19
36 21
33 21
6
33 25 18
21
19
15 6
15 6
15 6
21
21
19
19
25 21
45 21
21
15 6
44 18
20
37 21
15 6
91 45 19
36 18
25 20
18
18
18
45 18
15 6
44 18
25 21
25 18
10
18
21
21
21
40 21
25 21
25 18
21
21
40 25 18
15 6
91 47 45 19
20
18
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
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REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PSI# = Reserved (0)
CPU Gain Setting
80A
60A
40A
IMAX @ 900mV
101
Instead call out appropriate BOM GROUP defined in tables above.
100A
30
100
011
010
001
000
45
10
15
18
22.5
1x 22uF 0805, 1x 4.7uF 0603, 1x 2.2uF 0402, 2x 1uF 0402
2x 22uF 0805, 5x 1uF 0402
Equivalent Gain
110 12.857
111
120A
140A
180A
VTT (CPU Uncore) DECOUPLING
BULK CAPS ON CPU VREG PAGE 72
BULK CAPS ON CPU VREG PAGE 74
VID[6] = Reserved (0)
VID[2:0] = FUNCTION MSI[2:0] DEFAULT (110)
INTEL RECOMMENDATION 17X 22UF 0805
CPU VCORE DECOUPLING
PLACEMENT_NOTE (C1650-C1657):
PLACEMENT_NOTE (C1660-C1666):
INTEL RECOMMENDATION 9X22UF 0805 8X 22UF 0805, 7X 10UF 0805
PLL (CPU VCCSFR) DECOUPLING
Memory (CPU VCCDDR) DECOUPLING
CPU Power On Configuration (POC) StrapsIntel recommends all option straps should be provided in layout
NOTE: BOM Configurations should not call out CPUPOCnU/D BOMOPTIONs directly.
VID[7] = VRD SELECT (0)
VID[5:3] = IMON CONFIG DEFAULT (101)
MSI - MARKET SEGMENT IDENTIFICATIONPREVENTS THE PLATFORM BOOTING USING A HIGHER POWERED CPU
16 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
=PP1V5_CPU_MEM
CPU_VID<1>
CPU_VID<2>
=PPVCORE_S0_CPU
=PP1V8_S0_CPU_PLL
=PPVTT_S0_CPU
CPU_VID<5>
CPU_VID<4>
CPU_VID<3>
CPU_VID<0>
CPU_VID<6>
CPU_VID<7>
CPU_PSI_L
=PPVTT_S0_CPU
CPUPOC_IMAX_60_80 CPUPOC3D,CPUPOC4U,CPUPOC5U
CPUPOC_IMAX_80_100 CPUPOC3U,CPUPOC4D,CPUPOC5D
CPUPOC_IMAX_100_120 CPUPOC3U,CPUPOC4D,CPUPOC5U
CPUPOC_IMAX_140_180 CPUPOC3U,CPUPOC4U,CPUPOC5U
CPUPOC_IMAX_120_140 CPUPOC3U,CPUPOC4U,CPUPOC5D
CPUPOC_IMAX_40_60 CPUPOC3D,CPUPOC4U,CPUPOC5D
CPUPOC_IMAX_0_40 CPUPOC3D,CPUPOC4D,CPUPOC5U
CPUPOC_IMAX_DIS CPUPOC3D,CPUPOC4D,CPUPOC5D
CPU NON-GFX DECOUPLINGSYNC_DATE=07/01/2009SYNC_MASTER=K60_SIJI
1UF
X5R
10%
402
10V
C16941
2
1UF
402X5R
10%10V
C16831
2
402
10V
1UF10%
X5R
C16821
2
20%6.3V
22uF
CERM-X5R805
C16801
2
603
Place at edge of socket.
6.3V20%10uF
X5R
C16601
2
Place at edge of socket.
X5R6.3V
603
10uF20%
C16611
2
10uF20%
Place at edge of socket.
X5R6.3V
603
C16621
2
Place at edge of socket.
603X5R6.3V20%10uFC16631
2
Place at edge of socket.
X5R6.3V20%
603
10uFC16641
2
Place at edge of socket.
6.3V20%10uF
603X5R
C16651
2
Place at edge of socket.
X5R6.3V20%
603
10uFC16661
2
CERM-X5R
Place under socket cavity on secondary side.
805
22UF20%6.3V
C16571
2CERM-X5R
22UF
Place under socket cavity on secondary side.
805
20%6.3V
C16561
2
Place under socket cavity on secondary side.
CERM-X5R805
22UF20%6.3V
C16551
2
Place under socket cavity on secondary side.
805
20%6.3VCERM-X5R
22UFC16541
2
Place under socket cavity on secondary side.
CERM-X5R805
22UF20%6.3V
C16531
2
Place under socket cavity on secondary side.
CERM-X5R805
22UF20%6.3V
C16521
2CERM-X5R
Place under socket cavity on secondary side.
22UF20%6.3V
805
C16511
2
6.3V20%22UF
CERM-X5R805-3
C16061
26.3V20%22UF
CERM-X5R805-3
C16051
2
Place under socket cavity on secondary side.
805
6.3VCERM-X5R
20%22UFC16501
2
22UF
6.3V20%
CERM-X5R805-3
C16041
26.3V20%22UF
CERM-X5R805-3
C16031
2
805-3CERM-X5R
22UF20%6.3V
C16021
26.3VCERM-X5R
20%22UF
805-3
C16011
26.3V20%
CERM-X5R805-3
22UFC16001
2
805-3CERM-X5R
22UF
6.3V20%
C16101
2
805-3CERM-X5R
20%6.3V
22UFC16111
26.3V20%22UF
CERM-X5R805-3
C16121
2
805-3CERM-X5R
22UF20%6.3V
C16131
2
805-3CERM-X5R
22UF20%6.3V
C16141
2
805-3CERM-X5R
22UF20%6.3V
C16151
2
805-3CERM-X5R
22UF20%6.3V
C16161
2
22UF
NOSTUFF
805-3CERM-X5R
20%6.3V
C16171
2
NOSTUFF
805-3CERM-X5R
22UF20%6.3V
C16181
2 CERM-X5R
NOSTUFF
805-3
22UF20%6.3V
C16191
2
6.3V20%22UF
CERM-X5R805-3
C16071
26.3V20%22UF
CERM-X5R805-3
C16081
2 CERM-X5R6.3V20%22UF
805-3
C16091
2
89 64 13
402MF-LF1/16W5%1KR16171
2
NO STUFF
1K
402
5%1/16WMF-LF
R16071
2
89 64 13
89 64 13
89 64 13
89 64 13
89 64 13
89 64 13
89 64 13
89 64 13
NO STUFF
1K5%
1/16WMF-LF402
R16181
2
NO STUFF
MF-LF1/16W
5%
402
1KR16081
2
402MF-LF1/16W5%1K
NO STUFF
R16111
2
5%1K
MF-LF402
1/16W
R16101
2
CPUPOC3D
MF-LF1/16W5%
402
1KR1613
1
2
MF-LF402
1K
1/16W5%
NO STUFF
R16121
2
1K5%
1/16W
402MF-LF
CPUPOC4D
R16141
2
5%1/16WMF-LF
1K
CPUPOC5D
402
R16151
2
402
1/16W5%1K
MF-LF
R16161
2
CPUPOC5U
1K
402
5%1/16WMF-LF
R16051
2
1/16W
1K5%
402MF-LF
CPUPOC4U
R16041
2
MF-LF
5%
402
1K
NO STUFF
1/16W
R16061
2
1K
402
5%1/16WMF-LF
CPUPOC3U
R16031
2
1K
402
5%1/16WMF-LF
R16011
2
402
5%1/16WMF-LF
1KR16021
2
1K
402
5%1/16WMF-LF
NO STUFF
R16001
2
X5R
10%
402
10V
1UFC16861
2X5R
10%1UF
402
10V
C16841
210V
402
10%
X5R
1UFC16851
2
20%22uF
805CERM-X5R6.3V
C16811
2
805CERM-X5R
22uF
6.3V20%
C16901
2 X5R-CERM603
4.7UF10%6.3V
C16911
26.3V
402
2.2UF10%
X5R
C16921
210V
402
1UF10%
X5R
C16931
2
29 13 11 6
13 6
63 13 6
64 46 16 13 11 6
64 46 16 13 11 6
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
69 mA
Grounding the Rail because Integrated Graphics wont be used
75 MA
69 mA
75 MA150 MA
17 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
PP3V3_S0_PCH_VCCA_DACMIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=3.3V
=PP3V3_S0_PCH_VCCADAC
VOLTAGE=1.05VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MMPP1V05_S0_PCH_VCCADPLLA
MIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MM
PP1V05_S0_PCH_VCCADPLLB
VOLTAGE=1.05V
=PPVAXG_S0_CPU
=PP1V05_S0_PCH_VCCADPLL
SYNC_MASTER=K60_SIJI SYNC_DATE=07/01/2009
CPU/PCH GFX DECOUPLING
5%1/16WMF-LF402
0R17001
2
MF-LF1/16W5%
402
0R1750
1 2
5%1/16W
0
402MF-LF
R17651 2
1/16W5%
0
402MF-LF
R17601 2
89 22 6
89 22
89 22
13 6
6
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
BI
BI
BI
BI
OUT
BI
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
BI
OUT
BI
IN
IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
SPI
(1 OF 10)
SATA
JTAG
IHDA
LPC
RTC
TRST*
GPIO33
GPIO13
SRTCRST*
SPKR
SPI_MOSI
SPI_MISO
SPI_CS1*
SPI_CS0*
SPI_CLK
SERIRQ
SATALED*
SATAICOMPO
SATAICOMPI
SATA5TXP
SATA5TXN
SATA5RXP
SATA5RXN
SATA4TXP
SATA4TXN
SATA4RXP
SATA4RXN
SATA3TXP
SATA3TXN
SATA3RXP
SATA3RXN
SATA2TXP
SATA2TXN
SATA2RXP
SATA2RXN
SATA1TXP
SATA1TXN
SATA1RXP
SATA1RXN
SATA1GP/GPIO19
SATA0TXP
SATA0TXN
SATA0RXP
SATA0RXN
SATA0GP/GPIO21
RTCX2
RTCX1
RTCRST*
LDRQ1*/GPIO23
LDRQ0*
JTAG_TMS
JTAG_TDO
JTAG_TDI
JTAG_TCK
INTRUDER*
HDA_SYNC
HDA_SDO
HDA_SDIN3
HDA_SDIN2
HDA_SDIN1
HDA_SDIN0
HDA_BCLK
FWH4/LFRAME*
FWH3/LAD3
FWH2/LAD2
FWH1/LAD1
FWH0/LAD0
INTVRMEN
HDA_RST*
PCI-E*
FLEX
CLOCK
PEG
SMBUS
(2 OF 10)
FROM CLK BUFFER
SML1DATA/GPIO75
SML1CLK/GPIO58
SML1ALERT*/GPIO74
SML0DATA
SML0CLK
SML0ALERT*/GPIO60
SMBDATA
SMBCLK
SMBALERT*/GPIO11
REFCLK14IN
PETP8
PETP7
PETP6
PETP5
PETP4
PETP3
PETP2
PETP1
PETN8
PETN7
PETN6
PETN5
PETN3
PETN2
PETN1
PERP8
PERP7
PERP6
PERP5
PERP4
PERP3
PERP2
PERP1
PERN8
PERN7
PERN6
PERN5
PERN4
PERN3
PERN2
PERN1
PEG_B_CLKRQ*/GPIO56
PEG_A_CLKRQ*/GPIO47
PCIECLKRQ5*/GPIO44
PCIECLKRQ4*/GPIO26
PCIECLKRQ3*/GPIO25
PCIECLKRQ2*/GPIO20
PCIECLKRQ1*/GPIO18
PCIECLKRQ0*/GPIO73
CLKOUTFLEX3/GPIO67
CLKOUTFLEX2/GPIO66
CLKOUTFLEX1/GPIO65
CLKOUTFLEX0/GPIO64
CLKOUT_PEG_B_P
CLKOUT_PEG_B_N
CLKOUT_PEG_A_P
CLKOUT_PEG_A_N
CLKOUT_PCIE5P
CLKOUT_PCIE5N
CLKOUT_PCIE4P
CLKOUT_PCIE4N
CLKOUT_PCIE3P
CLKOUT_PCIE3N
CLKOUT_PCIE2P
CLKOUT_PCIE2N
CLKOUT_PCIE1P
CLKOUT_PCIE1N
CLKOUT_PCIE0P
CLKOUT_PCIE0N
CLKOUT_DMI_P
CLKOUT_DMI_N
CLKIN_SATA_P/CKSSCD_P
CLKIN_SATA_N/CKSSCD_N
CLKIN_PCILOOPBACK
CLKIN_DOT_96P
CLKIN_DOT_96N
CLKIN_DMI_P
CLKIN_BCLK_P
CLKIN_BCLK_N
XTAL25_OUT
XTAL25_IN
XCLK_RCOMP
CLKIN_DMI_N
CLKOUT_DP_N/CLKOUT_BCLK1_N
CLKOUT_DP_P/CLKOUT_BCLK1_P
PETN4
IN
OUT
BI
OUT
OUT
IN
IN
OUT
OUT
IN
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
(IPD)
(IPD)
(IPU)
(IPD)
(IPD)
PLACE THIS RESISTOR NEAR THE PCH PIN
(IPU)
(IPU)
(IPU)
(IPU)
(IPD)
(IPU)
(IPD)
(IPU)
(IPU)
DOES THIS NEED LENGTH MATCH???
(IPD)
PLACE THESE 33 OHM RESISTORS CLOSE TO PCH (MIN 500MIL)
(IPD)
(IPD)
(IPD)
(IPD)
(IPD)
(IPU)
TIE THEM TOGETHER VERY CLOSE TO PINS. PLACE THE RESISTOR LESS THAN 200MILS FROM THE PINS
(IPD)
(IPD)
18 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
SPI_CLK_R
JTAG_PCH_TDO
LPC_R_AD<2>
TP_LPC_DREQ0_L
LPC_AD<2>
LPC_AD<0>LPC_R_AD<0>
LPC_R_AD<1>
LPC_FRAME_R_L
=PP1V05_S0_PCH_VCCIO_SATA
=PP3V3_S0_PCH
LPC_R_AD<3>
LPC_FRAME_L
LPC_AD<3>
LPC_AD<1>
LPC_SERIRQ
PCH_SATAICOMP
SATA_ODD_D2R_P
SATA_ODD_R2D_C_N
TP_LPC_DREQ1_L
TP_SATA_F_D2RN
TP_SATA_E_R2D_CP
SATA_HDD_D2R_P
SATA_HDD_R2D_C_N
SATA_HDD_D2R_N
PCIE_CLK100M_EXCARD_N
FW_CLKREQ_L
PCIE_CLK100M_MINI_P
ENET_CLKREQ_L
TP_PCIE_T28_R2D_C_P<3>
TP_PCIE_T28_R2D_C_P<2>
PCIE_CLK100M_ENET_N
PCIE_CLK100M_MINI_N
PCIE_CLK100M_FW_N
PCIE_CLK100M_FW_P
PCIE_CLK100M_EXCARD_P
MINI_CLKREQ_L
PCIE_FW_D2R_P
PCIE_FW_D2R_N
PCIE_MINI_R2D_C_P
PCIE_FW_R2D_C_P
PCIE_CLK100M_CPU_P
JTAG_PCH_TDI
RTC_RESET_L
SMC_WAKE_SCI_L
=PP3V3_S5_PCH
PCH_CLK25M_XTALIN
PCH_CLKOUTFLEX1
TP_PCIE_T28_D2R_P<2>
TP_PCIE_CLK100M_PE5N
BRCRYPT_PWR_EN
PCH_SATALED_L
PCH_GPIO19_SATA1GP
HDA_SDIN0
TP_HDA_SDIN1
TP_HDA_SDIN3
HDA_SDOUT_R
=PP1V05_S0_PCH_VCCIO_PCIE
=PP3V3_S0_SATALED
HDA_SDOUT_R
PCH_GPIO21_SATA0GP
HDA_RST_R_L
ENET_ENERGY_DET
JTAG_PCH_TCK
HDA_BIT_CLK_R
PCH_SRTCRST_L
PCH_CLK100M_SATA_P
PCIE_CLK100M_ENET_P
SATA_HDD_R2D_C_P
PCIE_FW_R2D_C_N
TP_PCIE_T28_R2D_C_P<0>
TP_PCIE_T28_D2R_P<3>PCIE_CLK100M_PCH_P
SML_PCH_1_DATA
PCIE_MINI_R2D_C_N
PCIE_MINI_D2R_P
PCIE_ENET_R2D_C_P
SMC_WAKE_SCI_L
SMBUS_PCH_CLK
PCH_INTRUDER_L
EXCARD_CLKREQ_L
TP_SATA_E_R2D_CN
FSB_CLK133M_PCH_N
SATA_ODD_R2D_C_P
PCIE_CLK100M_PCH_N
FSB_CLK133M_PCH_P
PCH_CLK96M_DOT_N
PCH_CLK96M_DOT_P
PCH_CLK33M_PCIIN
PEG_CLK100M_N
PEG_CLK100M_P
PEG_CLKREQ_L
PCH_CLK14P3M_REFCLK
PCH_CLK100M_SATA_N
GFX_CLK120M_DPLLSS_N
GFX_CLK120M_DPLLSS_P
PCIE_EXCARD_R2D_C_P
SML_PCH_0_CLK
SML_PCH_1_CLK
SML_PCH_0_DATA
SMBUS_PCH_DATA
HDA_SYNC
HDA_BIT_CLK_R
HDA_RST_R_L HDA_RST_L
HDA_SDOUT
SML_PCH_0_ALERT_L
SML_PCH_0_ALERT_L
SML_PCH_1_ALERT_L
HDA_SYNC_R
HDA_BIT_CLK
PCIE_ENET_R2D_C_N
PCIE_ENET_D2R_P
PCIE_ENET_D2R_N
TP_PCIE_T28_R2D_C_N<1>
TP_SATA_D_R2D_CP
TP_SATA_D_D2RP
SATA_SSD_D2R_N
SATA_SSD_D2R_P
SATA_SSD_R2D_C_N
SATA_SSD_R2D_C_P
HDA_SYNC_R
TP_SATA_E_D2RP
SATA_ODD_D2R_N
TP_SATA_D_D2RN
TP_SATA_D_R2D_CNSPI_DESCRIPTOR_OVERRIDE_L
PCH_CLK32K_RTCX1
PCH_SPKR
PCIE_CLK100M_CPU_N
PCIE_MINI_D2R_N
PCH_INTVRMEN_L
RTC_RESET_L
DMI_MIDBUS_CLK100M_N
DMI_MIDBUS_CLK100M_P
TP_PCIE_T28_R2D_C_N<3>
SML_PCH_1_ALERT_L
JTAG_PCH_TMS
BRCRYPT_RESET
PCH_CLK25M_XTALOUT
PCH_XCLK_RCOMP
PCH_CLKOUTFLEX2
PCH_CLKOUTFLEX3PEB_CLKREQ_L
TP_PCIE_CLK100M_PE5P
T28_CLKREQ_L
TP_PCIE_CLK100M_T28_P
TP_PCIE_CLK100M_T28_N
PCH_CLK32K_RTCX2
PCH_SATALED_L
JTAG_PCH_TCKJTAG_PCH_TMS
TP_PCIE_T28_D2R_N<2>
TP_SATA_E_D2RN
TP_PCIE_T28_D2R_N<1>
TP_PCIE_T28_D2R_P<0>
TP_HDA_SDIN2
TP_SATA_F_R2D_CP
TP_SATA_F_R2D_CN
TP_SATA_F_D2RP
SPI_CS0_R_L
PCH_SRTCRST_L
PCH_INTVRMEN_L
PP3V3_G3_RTC
TP_SPI_CS1_L
SPI_MISO
PCH_INTRUDER_L
=PP3V3_S5_PCH
JTAG_PCH_TDI
TP_JTAG_PCH_TRST_L
SPI_CLK_1_R
SPI_MOSI_R SPI_MOSI_1_R
TP_PCIE_T28_R2D_C_N<0>
TP_PCIE_T28_R2D_C_P<1>
TP_PCIE_T28_D2R_N<3>
TP_PCIE_T28_R2D_C_N<2>
TP_PCIE_T28_D2R_P<1>
TP_PCIE_T28_D2R_N<0>
PCIE_EXCARD_R2D_C_N
PCIE_EXCARD_D2R_N
PCIE_EXCARD_D2R_P
SYNC_MASTER=K60_SIJI SYNC_DATE=07/01/2009
PCH SATA/PCIE/CLK/LPC/SPI
402
22
MF-LF1/16W5%
R1823 1 2
402MF-LF5% 1/16W
22R1822 1 2
1/16W33
402MF-LF5%R1864 1 2
MF-LF5% 1/16W 40233R1863 1 2
33402MF-LF1/16W5%
R1862 1 2
33402MF-LF1/16W5%
R1861 1 2
5% 1/16W MF-LF 40233R1860 1 2
XDP
5%
MF-LF402
1/16W
100R18841
2
XDP
5%
MF-LF402
1/16W
100R18821
2
45 15
84 42
84 42
84 42
84 42
84 10
84 10
MF-LF1/16W5%
402
10KR18551
2402
5%1/16WMF-LF
10KR18541
2
5%
402MF-LF
10K
1/16W
R18531
2
88 48
88 48
XDP
200
MF-LF
5%
402
1/16W
R18831
2
XDP
5%
MF-LF402
1/16W
200R18811
2
515%1/16WMF-LF402
R18561
2
15
MF-LF402
10K5%
1/16W
R18501
2
FCBGA
OMIT
IBEX-PEAK-DESKTOPU1800
Y32
Y31
H20
G20
AM22
AL22
AL11
Y34
Y35
H40
J41
H37
H38
V2
W1
T10
T9
M6
M7
M9
M10
P7
P6
Y8
Y9
Y6
Y7
V7
V8
AD10
AK1
AB6
AL3
AN35
AM39
AP38
AP33
AW37
AW38
AV39
AW35
D15
B17
B15
D14
C12
D8
A12
C7
C16
A16
C14
D13
B13
C9
B11
B8
D18
H16
H14
K14
H12
G11
D11
K12
D17
G16
G14
L14
G12
H11
D10
J12
AF7
AL31
AV32
AM31
BA33
AW33
AT34
AY32
AV31
AR31
AA3
Y4
Y2
OMIT
FCBGA
IBEX-PEAK-DESKTOP
U1800AT12
AK16AL16
AM16
AR14
AR16
AT16
AW14
AV14
AV13
AP18
AU13
AN16
AP16
AU15
AN24
AW31
AK33
AL36
AN34
AL34
AL12
AP14
AK24
AW30
BA30
AJ37
W41
V40
U38
V38
AH38
Y38
Y37
AB36
AB35
AD36
AD35
AB31
AB32
AC41
AC39
AB37
AB38
AF41
AE40
AD38
AE38
AF35
AF34
AD33
AD32
T39
T41
AN39
AL40
V31
V32
T32
V30
T34
AJ38
AP28
AL35
85 55
85 55
85 55
85 55
33
MF-LF
5%1/16W
402
R18131 2
1/16W5%
MF-LF402
33R1812
1 2
402MF-LF
33
1/16W5%
R18111 2
5%
33
MF-LF1/16W
402
R18101 2
90.9
1/16W1%
402MF-LF
R18901
2
15
8
8
MF-LF402
1/16W5%10KR1820
1
2
1%1/16W
37.4
402MF-LF
R18301
2
10V
402X5R
10%1UF
C1802 1
2
1UF10%
X5R10V
402
C18031
2
MF-LF402
5%20K
1/16W
R18031
2
20K
1/16W
402
5%
MF-LF
R18021
2
1M
1/16W5%
MF-LF402
R18011
2402
1/16W5%
MF-LF
330KR1800
1
2
8
8
8
8
88 48
88 48
88 48
88 48
85 27
85 27
85 27
85 27
85 26
84 26
84 26
84 26
84 26
84 26
84 26
84 26
84 26
84 11
84 11
9
9
9
84 11
84 11
40 25 15
84 39
84 39
33 25 15
84 33
84 33
84 36
36 15
84 36
84 39
84 39
84 33
84 33
86 36
86 36
84 39
84 39
84 33
84 33
86 36
86 36
84 42
84 42
84 42
84 42
84 42
84 42
84 42
84 42
47 45
85 47 45
85 47 45
85 47 45
85 47 45
85 47 45
85 54 47
25 18
25 18
25 18
85 54 47
85 47
85 54 47
25
85 55
85 27
8
24 22 6
68 24 21 6
85
8
8
8
25 18
91 18
45 18
24 19 18 6
15
8
44 15
42 18
25 15
8
8
85 18
24 22 19 6
42 6
85 18
25 15
85 18
36 15
85 18
18
45 18
18
8
85 18
85 18
18
18
18
85 18
8
8
85 18
8
8
8
15
18
91 18
18
44 15
85
15
15 15
8
42 18
25 18 25 18
8
8
8
8
8
18
18
89 27 24 22
18
24 19 18 6
IN
OUT
OUT
OUT
OUT
OUT
IN
BI
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
MANAGEMENT
(3 OF 10)
SYSTEM POWER
FDI
DMI
TP23
GPIO32
GPIO72
SYS_RESET*
SYS_PWROK
SUSCLK/GPIO62
SUS_STAT*/GPIO61
SUS_PWR_DN_ACK/GPIO30
SLP_S5*/GPIO63
SLP_S4*
SLP_S3*
SLP_M*
SLP_LAN*/GPIO29
RSMRST*
RI*
PWROK
PWRBTN*
PMSYNCH
LAN_RST*
FDI_RXP7
FDI_RXP6
FDI_RXP5
FDI_RXP4
FDI_RXP3
FDI_RXN5
FDI_RXN4
FDI_RXN3
FDI_RXN2
FDI_RXN1
FDI_RXN0
FDI_LSYNC1
FDI_LSYNC0
FDI_FSYNC1
FDI_FSYNC0
DRAMPWROK
DMI3TXP
DMI3TXN
DMI3RXP
DMI2TXP
DMI2TXN
DMI1TXP
DMI1TXN
DMI0TXP
DMI0TXN
DMI0RXN
DMI_ZCOMP
DMI_IRCOMP
ACPRESENT/GPIO31
WAKE*
FDI_RXN6
FDI_RXN7
FDI_RXP2
FDI_INT
FDI_RXP1
FDI_RXP0
DMI1RXN
DMI2RXN
DMI3RXN
DMI0RXP
DMI1RXP
DMI2RXP
MEPWROK
DIGITAL DISPLAY INTERFACE
(4 OF 10)
CRT
SDVO_TVCLKINP
SDVO_TVCLKINN
SDVO_STALLP
SDVO_STALLN
SDVO_INTP
SDVO_INTN
SDVO_CTRLDATA
SDVO_CTRLCLK
DDPD_HPD
DDPD_CTRLDATA
DDPD_CTRLCLK
DDPD_AUXP
DDPD_AUXN
DDPD_3P
DDPD_3N
DDPD_2P
DDPD_2N
DDPD_1P
DDPD_1N
DDPD_0P
DDPD_0N
DDPC_3P
DDPC_3N
DDPC_2P
DDPC_1P
DDPC_1N
DDPC_0P
DDPB_HPD
DDPB_AUXP
DDPB_AUXN
DDPB_3N
DDPB_2P
DDPB_2N
DDPB_1P
DDPB_1N
DDPB_0P
DDPB_0N
DAC_IREF
CRT_VSYNC
CRT_RED
CRT_IRTN
CRT_HSYNC
CRT_GREEN
CRT_DDC_DATA
CRT_DDC_CLK
DDPB_3P
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_2N
CRT_BLUEOUT
OUT
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
To U6900
To R5089,R4953
To Q500
To U3300
INTERNAL DP
KEEPING TP, IF NEED TO USE IT LATER
(IPU)(IPU)
(IPU)
(IPD)
(IPD)
(IPD)
(IPD)
EXTERNAL DP
PLACE CLOSE TO U1800 PIN
SHORT THESE TWO PINS VERY NEAR THE PINSPLACE THE RESISTOR VERY CLOSE TO COMMON POINT
19 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
PM_SLP_S4_3_L
PM_SLP_S4_2_L
PM_SLP_S4_1_LPM_SLP_S4_L
TP_DP_IG_D_MLN<3>
TP_DP_IG_D_MLN<2>
SMC_ADAPTER_EN
PCH_FDI_INT
TP_PCH_FDI_RX_P<7>
=PP3V3_S5_PCH
PM_SLP_M_L
TP_SLP_LAN_L
TP_PCH_FDI_RX_P<4>
PM_PCH_PWRGD
TP_CRT_IG_BLUE
PM_CLKRUN_L
=PP3V3_S5_PCH
=PP1V05_S0_PCH_VCCIO_PCIE
TP_DP_IG_B_HPD
TP_DP_IG_B_MLN<0>
PCIE_WAKE_L
PCH_FDI_LSYNC<1>
PCH_FDI_LSYNC<0>
PCH_FDI_FSYNC<1>
PCH_FDI_FSYNC<0>
PCH_DAC_IREF
PM_MEM_PWRGD
TP_DP_IG_B_MLP<2>
TP_DP_IG_B_MLP<1>
TP_DP_IG_B_MLN<1>
TP_DP_IG_B_MLP<0>
TP_CRT_IG_GREEN
TP_CRT_IG_HSYNC
PM_ME_PWRGD
DMI_S2N_P<3>
DMI_S2N_P<2>
DMI_S2N_P<1>
TP_PCH_FDI_RX_P<2>
LPC_PWRDWN_L
TP_SDVO_INTP
TP_SDVO_INTN
TP_SDVO_STALLP
TP_SDVO_STALLN
TP_SDVO_TVCLKINP
TP_SDVO_TVCLKINN
TP_DP_IG_B_DDC_DATA
TP_DP_IG_B_DDC_CLK
TP_DP_IG_B_AUX_P
TP_DP_IG_B_AUX_N
TP_PM_SLP_DSW_L
TP_DP_IG_C_MLP<3>
PM_SYNC
TP_PCH_FDI_RX_N<1>
PCIE_WAKE_L
TP_DP_IG_D_AUXN
PM_CLK32K_SUSCLK_R
TP_DP_IG_D_MLP<3>
TP_DP_IG_D_MLP<2>
TP_DP_IG_D_MLP<1>
TP_DP_IG_D_MLN<1>
TP_DP_IG_D_MLP<0>
TP_PCH_FDI_RX_P<3>
TP_PCH_FDI_RX_P<0>
PCH_ACPRESENT_GPIO31
TP_PCH_FDI_RX_P<6>
TP_PCH_FDI_RX_P<5>
DMI_S2N_N<3>
PM_PWRBTN_L
PM_BATLOW_L
PM_SLP_S5_L
TP_CRT_IG_RED
TP_CRT_IG_VSYNC
=PP3V3_S5_PCH
TP_PCH_FDI_RX_N<0>
TP_PCH_FDI_RX_P<1>
TP_PCH_FDI_RX_N<7>
TP_PCH_FDI_RX_N<6>
TP_PCH_FDI_RX_N<5>
TP_PCH_FDI_RX_N<4>
TP_PCH_FDI_RX_N<3>
TP_PCH_FDI_RX_N<2>
TP_CRT_IG_DDC_CLK
TP_CRT_IG_DDC_DATA
TP_DP_IG_D_CTRL_DATA
TP_DP_IG_C_MLN<2>
TP_DP_IG_C_HPD
TP_DP_IG_B_MLN<2>
TP_DP_IG_B_MLN<3>
TP_DP_IG_B_MLP<3>
TP_DP_IG_C_CTRL_CLK
TP_DP_IG_C_CTRL_DATA
TP_DP_IG_C_AUX_N
TP_DP_IG_C_AUX_P
TP_DP_IG_C_MLN<0>
TP_DP_IG_C_MLP<0>
TP_DP_IG_C_MLN<1>
TP_DP_IG_C_MLP<1>
TP_DP_IG_C_MLP<2>
TP_DP_IG_D_MLN<0>
TP_DP_IG_D_HPD
TP_DP_IG_D_AUXP
TP_DP_IG_D_CTRL_CLK
TP_DP_IG_C_MLN<3>PM_SLP_S3_L
PM_SLP_S4_L
PCH_ACPRESENT_GPIO31
DMI_S2N_N<2>
DMI_S2N_N<1>
DMI_N2S_N<2>
DMI_N2S_N<1>
DMI_N2S_N<3>
DMI_N2S_P<2>
DMI_N2S_P<0>
DMI_N2S_P<1>
DMI_N2S_N<0>
DMI_N2S_P<3>
DMI_S2N_N<0>
DMI_S2N_P<0>
PM_SYS_PWRGD
PM_SYSRST_L
PM_LAN_PWRGD
PCH_DMI_COMP
PM_SUS_PWR_ACK
PCH_RI_L
PM_RSMRST_PCH_L
PCH DMI/FDI/GRAPHICS
1%
402MF-LF1/16W
10KR1909
1
2
33
1/16WMF-LF402
5%
R196812
1/16W5%
402MF-LF
33R1967
12
5%
402MF-LF1/16W
33R1966
12
MF-LF
1%1/16W
402
10KR19611
2
MF-LF
NOSTUFF
5%
0
402
1/16W
R196012
1K5%1/16WMF-LF402
R19511
2
MF-LF
1K1%
1/16W
402
R19251
2
47 45
91 11
402MF-LF
1%1/16W
100KR1915
1
2 IBEX-PEAK-DESKTOP
FCBGA
OMIT
U1800
AB2
AG2
AG4
AC3
AD4
AB4
AC1
AD3
AE2
J8
K10
J11
K11
F6
H6
H4
G4
L2
M1
J1
F4
E3
G3
F2
C4
B4
D2
D3
L10
L9
AB10
AB11
J3
B6
C5
D7
D6
G8
F8
G9
F9
L4
K4
AB7
AB9
H2
AB13
AB12
N4
M3
P3
N2
L7
L6
IBEX-PEAK-DESKTOP
FCBGA
OMIT
U1800
AP40
A19
B18
J22
H22
B20
C19
G22
F22
E20
D20
H24
G24
G18
H18
L24
K24
D21
C21
AW32
E34
E36
B36
C35
D35
K30
H30
D31
F31
K31
C30
A33
C33
J30
G30
D32
G31
J31
B31
B32
B34
AJ40
AY34
AY31
AL33
C37
AK36
AM24
AT33
AL24
BA35
AT36
AV35
AP35
AU36
AT37
AK31
AH31
AT38
AL38
AH35
AR33
402MF-LF1/16W
10K1%
R19051
2
84 10
84 10
84 10
84 10
84 10
84 10
84 10
84 10
84 10
84 10
84 10
84 10
84 10
84 10
84 10
91 45 27
91 63 32
91 63
91 63
91 15
91 45 15
19
91 45 25
91 62
91 11
91 62 5
91 63 62 46 37 33 32 5
91 32 19
91 45
91 85 9
91 47 45 15
37 33 19
1%1/16W
49.9
MF-LF402
R19001
2
15
15
15
15
15
84 10
91 5
91 46 45
91 62 91 32 19
8
8
46 45
24 19 18 6
8
24 19 18 6
24 22 18 6
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
37 33 19
8
8
8
8
8
8
8
8
24 19 18 6
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
19
85
91
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
PCI
NVRAM
USB
(5 OF 10)
TRDY*
USBRBIAS*
USBRBIAS
USBP9P
USBP9N
USBP8P
USBP8N
USBP7P
USBP7N
USBP6P
USBP6N
USBP5P
USBP5N
USBP4P
USBP4N
USBP3P
USBP3N
USBP2P
USBP2N
USBP1P
USBP1N
USBP13P
USBP13N
USBP12P
USBP12N
USBP11P
USBP11N
USBP10P
USBP10N
USBP0P
USBP0N
STOP*
SERR*
REQ3*/GPIO54
REQ2*/GPIO52
REQ1*/GPIO50
REQ0*
PME*
PLTRST*
PLOCK*
PIRQH*/GPIO5
PIRQG*/GPIO4
PIRQF*/GPIO3
PIRQE*/GPIO2
PIRQD*
PIRQC*
PIRQB*
PIRQA*
PERR*
PCIRST*
PAR
OC7*/GPIO14
OC6*/GPIO10
OC5*/GPIO9
OC4*/GPIO43
OC3*/GPIO42
OC2*/GPIO41
OC1*/GPIO40
OC0*/GPIO59
NV_WR1_RE*
NV_WR0_RE*
NV_WE_CK1*
NV_WE_CK0*
NV_RCOMP
NV_RB*
NV_DQS1
NV_DQS0
NV_DQ9/NV_IO9
NV_DQ8/NV_IO8
NV_DQ7/NV_IO7
NV_DQ6/NV_IO6
NV_DQ5/NV_IO5
NV_DQ4/NV_IO4
NV_DQ3/NV_IO3
NV_DQ2/NV_IO2
NV_DQ15/NV_IO15
NV_DQ14/NV_IO14
NV_DQ13/NV_IO13
NV_DQ12/NV_IO12
NV_DQ11/NV_IO11
NV_DQ10/NV_IO10
NV_DQ1/NV_IO1
NV_DQ0/NV_IO0
NV_CE2*
NV_CE1*
NV_CE0*
NV_ALE
IRDY*
GNT3*/GPIO55
GNT2*/GPIO53
GNT1*/GPIO51
GNT0*
FRAME*
DEVSEL*
CLKOUT_PCI4
CLKOUT_PCI3
CLKOUT_PCI2
CLKOUT_PCI1
CLKOUT_PCI0
C/BE3*
C/BE2*
C/BE1*
C/BE0*
AD9
AD8
AD7
AD6
AD5
AD4
AD31
AD30
AD3
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD2
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD0
NV_CLE
NV_CE3*
AD1
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PLACE THE RESISTOR CLOSE TO COMMON POINT
Unused
NOTE: Internal pull-downs on all USB pins
Unused
USB HUB 1
Unused
(DPD)
Unused
Unused
USB HUB 2
(IPU)
(IPD)
(IPD)
EHCI2
(IPU)
(IPU)
EHCI1
TIE TRACES TOGETHER CLOSE TO PINS
(DPD)
Blu-ray transcript
WM
Unused
Unused
Unused
Unused
Unused
20 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
PCH_GPIO42_OC3_L
PCH_GPIO9_OC5_L
PCH_GPIO10_OC6_L
PCH_GPIO14_OC7_L
PCH_GPIO59_OC0_L
PCH_GPIO43_OC4_L
TP_USB_12N
TP_USB_12P
TP_USB_9P
TP_USB_11N
=PP3V3_S5_PCH_GPIO
TP_PCI_AD<12>
TP_PCI_AD<4>
TP_USB_11P
PCH_USB_RBIAS
PCH_GPIO41_OC2_L
TP_USB_10N
TP_USB_9N
TP_USB_10P
USB_HUB1_UP_N
USB_HUB1_UP_P
PCH_NV_CLETP_PCI_AD<24>
USB_HUB2_UP_P
TP_USB_7P
TP_NV_RCOMP
PCI_REQ0_L
PCH_PCI_GNT2_L
TP_PCI_AD<13>
TP_NV_DQ<14>
TP_NV_DQ<8>
TP_NV_DQ<9>
TP_NV_DQ<10>
TP_NV_DQ<11>
TP_PCI_AD<2>
TP_PCI_AD<3>
TP_NV_CE_L<1>
TP_NV_DQS<0>
TP_NV_DQ<0>
TP_PCI_AD<11>
TP_PCI_AD<9>
TP_PCI_AD<14>
TP_PCI_AD<17>
TP_NV_DQ<12>
TP_NV_DQS<1>
TP_NV_CE_L<2>
TP_NV_CE_L<0>
TP_NV_DQ<6>
PCH_NV_ALE
PCI_DEVSEL_L
TP_NV_DQ<4>
TP_NV_DQ<15>
TP_PCI_AD<15>
TP_PCI_AD<21>
PLT_RESET_L
TP_PCI_AD<26>
TP_PCI_AD<29>
TP_NV_DQ<1>
TP_PCI_AD<20>
TP_PCI_AD<19>
PCI_FRAME_L
PCI_PERR_L
PCI_IRDY_L
PCI_STOP_L
TP_PCI_AD<22>
TP_PCI_AD<23>
TP_PCI_AD<25>
TP_PCI_AD<27>
TP_PCI_AD<28>
TP_PCI_AD<5>
TP_PCI_C_BE_L<1>
TP_PCI_AD<18>
TP_PCI_AD<6>
LPC_CLK33M_SMC_R
LPC_CLK33M_LPCPLUS_R
TP_PCI_CLK33M_OUT2
TP_PCI_CLK33M_OUT3
PCH_CLK33M_PCIOUT
TP_NV_WR_RE_L<0>
TP_PCI_AD<0>
TP_PCI_PME_L
PCI_TRDY_L
TP_PCI_PAR
PCH_PCI_GNT3_L
TP_PCI_AD<31>
PCI_INTD_L
PCH_PCI_GNT1_L
PCI_INTA_L
PCI_INTC_L
PCI_INTB_L
TP_PCI_C_BE_L<2>
PCI_REQ1_L
PCI_REQ3_L
PCI_REQ2_L
=PP3V3_S0_PCH_GPIO
AUD_IP_PERIPHERAL_DET
PCI_INTE_L
PCI_INTG_L
TP_PCI_RESET_L
TP_NV_CE_L<3>
TP_NV_DQ<3>
TP_NV_DQ<13>
TP_NV_DQ<7>
AUD_I2C_INT_L
PCH_PCI_GNT0_L
TP_PCI_AD<7>
TP_PCI_AD<10>
TP_NV_WR_RE_L<1>
TP_USB_3P
USB_WM_N
TP_USB_7N
USB_HUB2_UP_N
TP_USB_13N
TP_USB_6P
TP_USB_13P
TP_PCI_AD<16>
TP_NV_RB_L
TP_NV_WE_CK_L<1>
USB_HUB_SOFT_RESET_L
TP_USB_1N
PCI_PLOCK_L
TP_NV_WE_CK_L<0>
TP_PCI_AD<1>
TP_PCI_AD<8>
TP_NV_DQ<2>
TP_NV_DQ<5>
TP_USB_6N
TP_USB_5P
TP_USB_5N
USB_WM_P
TP_USB_3N
USB_BRCRYPT_P
USB_BRCRYPT_N
TP_PCI_AD<30>
PCI_SERR_L
TP_PCI_C_BE_L<0>
TP_PCI_C_BE_L<3>
TP_USB_1P
SYNC_DATE=07/01/2009SYNC_MASTER=K60_SIJI
PCH PCI/FLASHCACHE/USB
8
8 MF-LF 402
10K5% 1/16W
R2031 1 2
4025%
10KMF-LF1/16W
R2030 1 2
8
8
8
8
10KMF-LF5% 4021/16W
R2027 1 2
10KMF-LF5% 4021/16W
R2025 1 2
MF-LF1/16W5% 402
10KR2026 1 2
4021/16W MF-LF
10K5%
R2024 1 24021/16W MF-LF5%
10KR2023 1 2
85 27
85 27
85 27
91 27
MF-LF 4025% 1/16W
10KR2022 1 2
1/16W 402MF-LF5%
10KR2021 1 21/16W MF-LF 4025%
10KR2020 1 2
5%
10K402MF-LF1/16W
R2018 1 25%
10K402MF-LF1/16W
R2017 1 21/16W MF-LF 402
10K5%
R2016 1 25%
10KMF-LF 4021/16W
R2015 1 2
1/16W
10K4025% MF-LF
R2013 1 2402
10K5% 1/16W MF-LF
R2012 1 2402
10K5% 1/16W MF-LF
R2011 1 2
10K4025% 1/16W MF-LF
R2010 1 2
IBEX-PEAK-DESKTOP
OMIT
FCBGAU1800
AT9
AP11
AW7
AR8
AU3
AP2
AU1
AN3
AM2
AM11
AM4
AY8
AU6
AL10
AT5
AL2
AT2
AL4
AV10
AL9
AN7
AK7
AN6
AY10
AH12
AN11
AP9
AV8
AR9
AV7
AW9
AR3
AV3
AY6
AP5
AW10
AF6
AD7
AF9
AD9
AD12
AT6
AL7
AK11
AK6
BA9
AM3
AP7
J34
H36
H35
P32
E41
L35
T33
H33
F37
E39
G33
D40
F33
P35
T31
P33
M35
L33
M36
M34
M30
F36
P36
F40
M32
L36
M31
F38
J36
J35
AT31
AT30
AK28
AP30
AP31
AL28
AL30
AM30
AP6
AH10
AT4
AT8
AR4
AT11
BA5
AU8
AH7
AP12
AW4
AK12
AV34
AH11
AP4
AW5
AY4
AH8
AV6
AN8
AL6
AW25
AY25
AV17
AV18
AR20
AT20
AK18
AL18
AY17
BA16
BA23
AY24
AW23
AY22
AR22
AP22
AV21
AV22
AY20
AW21
AK20
AL20
AV20
AW19
BA19
AY18
AM20
AN20
AV15
AY15
402
1/16WMF-LF
1%22.6
R20701
2
8
8
8
8
402
1/16WMF-LF
5%10K
R20601
2
5%1/16W
10K
MF-LF402
R20611
2
402MF-LF
5%10K
1/16W
R20621
2
5%
MF-LF1/16W
10K
402
R20671
2MF-LF
5%1/16W
402
10KR20641
2
10K5%
402
1/16WMF-LF
R20651
2
402
10K
1/16WMF-LF
5%
R20661
2
8
8
85 35
85 35
8
8
8
85 44
8
8
85 44
8
85 44
85 44
8
8
85 34
85 34
25
25
25
25 15
25
25
6
8
8
85
25
15 8
8
85
15
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
15
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
15
8
15
8
85
6
60
8
8
8
8
8
61
15
8
8
8
8
8
8
34 25
8
8
8
8
8
8
8
8
IN
OUT
OUT
BI
OUT
IN
CPU
NCTF
(6 OF 10)
RSVD
GPIO
MISCGPIO8
VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
A20GATE
CLKOUT_BCLK0_N/CLKOUT_PCIE8N
CLKOUT_BCLK0_P/CLKOUT_PCIE8P
CLKOUT_PCIE6N
CLKOUT_PCIE6P
CLKOUT_PCIE7N
CLKOUT_PCIE7P
GPIO15
GPIO24
GPIO27
GPIO28
GPIO35
GPIO57
INIT3_3V*
LAN_PHY_PWR_CTRL/GPIO12
NC0
NC1
NC2
NC3
NC4
PCIECLKRQ6*/GPIO45
PCIECLKRQ7*/GPIO46
PECI
PROCPWRGD
PWM0
PWM1
PWM2
RCIN*
SATA2GP/GPIO36
SATA3GP/GPIO37
SATA4GP/GPIO16
SATA5GP/GPIO49
SCLOCK/GPIO22
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
SLOAD/GPIO38
SST
STP_PCI*/GPIO34
TACH0/GPIO17
TACH1/GPIO1
THRMTRIP*
TP1
TP10
TP11
TP12
TP13
TP18
TP19
TP2
TP20
TP21
TP22_NCTF0
TP22_NCTF1
TP22_NCTF2
TP22_NCTF3
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TACH3/GPIO7
TACH2/GPIO6
BMBUSY*/GPIO0
PWM3
IN
OUT
OUT
IN
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
IPU* = Only on TACH function.
(IPU*)
(IPU*)
(IPD)
(IPU*)
THIS SIGNAL IS INTEDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.
(IPD)
(IPU)
(IPU*)
21 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
PCH_GPIO0_BMBUSY_L
FW_PME_L
CPU_PECI
TP_PCH_TP5
TP_PCH_TP11
TP_PCH_PWM1
AP_PWR_EN
PCH_GPIO49_SATA5GP
FW_PWR_EN
=PP3V3_S0_PCH
TP_PCH_TP12
TP_PCH_TP21
TP_PCH_TP2
TP_PCH_TP20
TP_PCH_TP13
TP_PCH_TP6
CPU_PWRGD
SPIROM_USE_MLB
TP_PCH_TP19
TP_PCH_PWM3
TP_PCH_PWM0
TP_PCH_TP18
TP_PCH_SST
TP_PCH_PWM2
TP_PCH_TP1
TP_PCH_TP3
TP_DMI_CLK100M_LAP
TP_PCH_TP4
TP_DMI_CLK100M_LAN
PCH_INIT3V3_L
TP_PCH_TP9
TP_PCH_TP8
PCH_RCIN_L
TP_PCH_TP10
=PP3V3_S0_PCH
TP_PCH_TP7
PM_THRMTRIP_L
FSB_CLK133M_CPU_P
FSB_CLK133M_CPU_N
TP_PCIE_CLK100M_XDPP
SMC_RUNTIME_SCI_L
ENET_LOW_PWR
LPCPLUS_GPIO
PCH_GPIO15
AUD_IPHS_SWITCH_EN
PCH_GPIO6_TACH2
WOL_EN
PCH_GPIO39_SDATAOUT0
TP_PCIE_CLK100M_XDPN
ODD_PWR_EN_L
ISOLATE_CPU_MEM_L
PCH_GPIO24
PCH_GPIO8_FCIM_EN_L PCH_A20GATE
PCH_GPIO38_SLOAD
PCH_GPIO37_SATA3GP
SDCARD_RESET
MXM_GOOD
PCH_GPIO34_STP_PCI_L
PCH_GPIO27_VRMEN
PCH MISCSYNC_DATE=07/01/2009SYNC_MASTER=K60_SIJI
47
47K5%
402
1/16WMF-LF
R21901
2
32 25
15
15
IBEX-PEAK-DESKTOPFCBGA
OMIT
U1800
AG37
AK41
L38
K38
U4
V4
T7
T6
AY36
AR34
AP37
AV40
AR41
AL32
AK30
AR39
AU34
AF15
V10
V11
Y11
Y12
AV36
AP36
D36
B38
BA12
AR12
AW12
AY13
AM40
AK39
AR38
AH39
AG40
AN41
AL39
AG38
AM38
AN31
AT40
AW11
AL14
AV11
AY11
C38
L18
AR24
V20
P10
P9
AK35
AN36
K18
AU39
AH30
A3
A41
AY1
BA41
J20
P12
P13
T13
T12
V34
AT24
A40
A5
C1
C41
E1
AW41
AY2
AY41
B2
B40
B41
BA1
BA2
MF-LF
10K5%
1/16W
402
R21501
2
10K
402
5%1/16WMF-LF
R21551
2
91 46 11
91 25 11
11
84 11
84 11
45 15
25 15
40 15
8
33 15
25 15
15
68 24 21 18 6
85 47
8
8
8
8
8
8
15
68 24 21 18 6
8
36 15
15
61 25
37 15
15
8
42 15
15
15
25 15
92 91 44 25
6
15
15
VCCIO54
VCCFDIPLL
VCCVRM0
VCCIO48
VCCIO49
VCCIO50
VCCIO51
VCCIO52
VCC3_3_2
VCC3_3_3
VCCCORE22
VCCCORE21
VCCCORE20
VCCCORE19
VCCCORE5
VCCIO23
VCCVRM1
VCCPNAND2
VCCPNAND1
VCCPNAND0
VCCME3_3_1
VCCME3_3_0
VCCIO53
VCCIO47
VCCIO46
VCCIO45
VCCIO44
VCCIO43
VCCIO42
VCCIO41
VCCIO40
VCCIO39
VCCIO36
VCCIO31
VCCIO30
VCCIO29
VCCIO28
VCCIO27
VCCIO26
VCCIO25
VCCIO24
VCCIO0
VCCDMI
VCCCORE57
VCCCORE56
VCCCORE55
VCCCORE54
VCCCORE53
VCCCORE52
VCCCORE51
VCCCORE50
VCCCORE49
VCCCORE48
VCCCORE47
VCCCORE46
VCCCORE45
VCCCORE44
VCCCORE43
VCCCORE42
VCCCORE41
VCCCORE40
VCCCORE39
VCCCORE38
VCCCORE37
VCCCORE36
VCCCORE35
VCCCORE34
VCCCORE33
VCCCORE32
VCCCORE31
VCCCORE27
VCCCORE26
VCCCORE25
VCCCORE24
VCCCORE23
VCCCORE18
VCCCORE17
VCCCORE16
VCCCORE15
VCCCORE14
VCCCORE13
VCCCORE12
VCCCORE11
VCCCORE10
VCCCORE9
VCCCORE8
VCCCORE6
VCCCORE4
VCCCORE3
VCCCORE2
VCCCORE1
VCCCORE0
VCCAPLLEXP
VCC3_3_1
VCC3_3_0
VCCCORE30
VCCCORE29
VCCCORE28
VCCADAC
VCCCORE7
VCCIO34
VCCIO32
VCCIO38
VCCIO37
VCCIO35
VCCIO33
VCCIO
VCC CORE
NAND / SPI
CRT
(7 OF 10)
FDI
DMI
HVCMOS
CPU
PCI/GPIO/LPC
USB
CLOCK AND MISCELLANEOUS
PCI/GPIO/LPC
SATA
HDA
RTC
(10 OF 10)
VCCVRM3
VCCVRM2
V5REF_SUS
V5REF
V_CPU_IO_NCTF
V_CPU_IO
DCPSUSBYP
DCPSUS
DCPSST
DCPRTC
VCCSUSHDA
VCCSUS3_3_NCTF1
VCCSUS3_3_NCTF0
VCCSUS3_3_16
VCCSUS3_3_15
VCCSUS3_3_14
VCCSUS3_3_13
VCCSUS3_3_12
VCCSUS3_3_11
VCCSUS3_3_10
VCCSUS3_3_9
VCCSUS3_3_8
VCCSUS3_3_7
VCCSUS3_3_6
VCCSUS3_3_5
VCCSUS3_3_4
VCCSUS3_3_3
VCCSUS3_3_2
VCCSUS3_3_1
VCCSUS3_3_0
VCCSATAPLL
VCCRTC_NCTF
VCCRTC
VCCME26
VCCME25
VCCME24
VCCME23
VCCME22
VCCME21
VCCME20
VCCME19
VCCME18
VCCME17
VCCME16
VCCME15
VCCME14
VCCME13
VCCME12
VCCME11
VCCME10
VCCME9
VCCME8
VCCME7
VCCME6
VCCME5
VCCME4
VCCME3
VCCME2
VCCME1
VCCME0
VCCLAN1
VCCLAN0
VCCIO22
VCCIO21
VCCIO20
VCCIO19
VCCIO18
VCCIO17
VCCIO16
VCCIO15
VCCIO14
VCCIO13
VCCIO12
VCCIO11
VCCIO10
VCCIO9
VCCIO8
VCCIO7
VCCIO6
VCCIO5
VCCIO4
VCCIO3
VCCIO2
VCCIO1
VCCADPLLB
VCCADPLLA
VCCACLK
VCC3_3_NCTF1
VCC3_3_NCTF0
VCC3_3_10
VCC3_3_9
VCC3_3_8
VCC3_3_7
VCC3_3_6
VCC3_3_5
VCC3_3_4
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PCH output, for decoupling only
PCH output, for decoupling only
31 mA (if GPIO27 is low)
(VCCIO[1-56] total)
(VCCME[1-16] total)
2.222A S0, 800 MA M-ON
PCH output, for decoupling only
372 MA S0, 78 MA M-ON
PCH output, for decoupling only
2 mA S0-S5, ~6 uA G3
3.251 A
< 1 mA
1 (IPU) 1 1.5V Float
GPIO27 HDA_SYNC VCCVRM PLL POWERS
(VCC3_3[1-14] total)
6 MA S0
(VCCIO[1-56] total)
357 mA (VCC3_3[1-14] total)
357 mA (VCC3_3[1-14] total)
1.629 A69 MA
65 MA
156 MA (1.8V)
85 mA S0, 22 mA M-on
3.251 A
3.251 A
196 MA (VCCVRM[0-3] TOTAL)
3.251 A
(VCCIO[1-56] total)
3.251 A
3.251 A
163 mA S0, 65 mA S3-S5196 MA ( TOTAL 4 PINS)
< 1 mA S0-S5
2.222 A S0, 800 MA M-ON
(VCC3_3 - 9 TOTAL PINS)
196 MA (VCCVRM[0-3] TOTAL)
< 1 mA
357 mA
75 MA
Note: 1.5V option consumes more current than 1.8V
PLLs = VccAClk, VccSATAPLL, VccAPLLEXP & VccFDIPLL
1 (IPU) 0 (IPD) 1.8V Float
(VCCME[1-16] total)
357 mA
0 0 1.8V 1.05V
0 1 1.5V 1.05V
5 mA (if GPIO27 is low)
(VCCIO[1-56] total)
75 MA
196 MA (VCCVRM[0-3] TOTAL)
40 mA (if GPIO27 is low)
(VCCIO[1-56] total)
(VCCIO[1-56] total)
(VCCSUS3_3 - 17 TOTAL)
22 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
=PP1V05_SM_PCH_VCC_ME
VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mmPPVOUT_S0_PCH_DCPSST
VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mmPPVOUT_S0_PCH_VCCRTC_NCTF
=PP3V3_S0_PCH_VCC3_3_PCI
PPVOUT_S5_PCH_DCPSUSBYPMIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
=PP1V05_SM_PCH_VCC_LAN
PP1V05_S0_PCH_VCCADPLLA
PP1V8R1V5_S0_PCH_VCCVRMMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mmPPVOUT_G3_PCH_DCPRTC
VOLTAGE=3.3V
PP3V3_G3_RTC
=PP1V05_S0_PCH_VCCIO_DMI
PP1V8R1V5_S0_PCH_VCCVRM
PP5V_S5_PCH_V5REFSUS
PP5V_S0_PCH_V5REF
=PPVTT_S0_PCH_VCCP_CPU
PPVOUT_S5_PCH_DCPSUSMIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3V
=PP3V3R1V5_S0_PCH_VCCSUSHDA
PP1V05_S0_PCH_VCCAPLL_SATA
=PP1V05_SM_PCH_VCC_ME
=PP1V05_S0_PCH_VCCIO_DMI
=PP1V05_S0_PCH_VCCIO_USBPP1V05_S0_PCH_VCCA_CLK
=PP3V3_S0_PCH_VCC3_3_SATA
=PP3V3_S0_PCH_VCC3_3_CORE
=PP3V3_SM_PCH_VCC_ME
PP1V8R1V5_S0_PCH_VCCVRM
=PPVTT_S0_PCH_VCC_DMI
=PP1V05_S0_PCH_VCCIO_SATA
PP1V8R1V5_S0_PCH_VCCVRM
PP1V05_S0_PCH_VCCAPLL_FDI
=PP3V3_S0_PCH_VCC3_3_PCI
=PP3V3_S0_PCH_VCC3_3_SATA
=PP1V05_S0_PCH_VCCIO_SATA
PP3V3_S0_PCH_VCCA_DAC =PP1V05_S0_PCH_VCC_CORE
=PP3V3R1V8_S0_PCH_VCCPNAND
PP1V05_S0_PCH_VCCAPLL_EXP
=PP1V05_S0_PCH_VCCIO_PCIE
=PP1V05_S0_PCH_VCCIO_DMI
=PP3V3_S5_PCH_VCCSUS3_3_USB
PP1V05_S0_PCH_VCCADPLLB
PCH POWER
NOSTUFF
10V
PLACE C2260 ON THE BACK SIDE NEAR AF27
0.1UF20%
402CERM
C2260 1
2
0.1UF
402
20%10VCERM
C22501
2
FCBGA
OMIT
IBEX-PEAK-DESKTOPU1800
AY38
AH33
AF30
AF27
AN1
AW16
B39
A39
U40
AH18
AJ14
AJ16
AK14
AV2
AY3
AW1
BA3
AA1
R2
T1
AA27
C25
D24
D25
F26
G26
H26
J26
K26
L26
M16
AH20
M18
M20
M22
AH22
AH23
AJ22
AT28
B24
B25
C24
Y20
Y22
AA15
AA16
AF10
AF13
AF16
AF8
AG5
AH1
AH13
AH3
AH4
AH6
AA18
AJ2
AJ4
AJ5
Y15
Y16
Y18
Y19
AB15
AB16
AD13
AD15
AD16
AE15
AE16
AY29
BA39
P41
AK26
AL26
AV27
AV29
AW26
AW39
AW40
AY27
BA26
AM26
AN26
AP26
AR26
AT26
AU26
AU27
AV25
AY40
BA40
AJ18
L39
L40
IBEX-PEAK-DESKTOP
FCBGA
OMIT
U1800
A9
AD27
AE27
AH16
AF1
A21
A26
A28
AE18
AE19
AE20
AE22
AE23
AE24
AE26
AF19
AF20
AF22
AA23
AF23
AF24
B27
B29
C26
C28
D27
D28
D29
E26
AA24
E27
E29
F28
G28
H28
J28
K28
L28
M28
N28
AB24
P26
P27
P29
T20
T22
T23
T24
T26
T27
U20
AB26
U22
U23
U26
V23
V24
V26
Y23
Y24
AD18
AD20
AD23
AD26
A23
A37
AA26
M24
M26
N16
N18
N20
N22
N24
N26
P15
P16
P18
P19
P24
P38
P39
R37
R38
R40
T15
T19
T29
T30
T36
T37
U15
U19
V15
V29
V36
Y26
Y29
Y36
N38
N40
M39
M41
P30
C2
C3
10VCERM
0.1UF
402
20%
C22301
2
0.1UF
CERM402
10V20%
C22201
2
20%
CERM402
10V
0.1UFC22101
2
0.1UF20%10V
402CERM
C22001
2
24 22 6
89
24 22 6
89
24 6
89 17
89 24 22
89
89 27 24 18
24 22 6
89 24 22
89 24
89 24
24 6
89
24 6
89 24
24 22 6
24 22 6
24 6 89 24
24 22 6
24 6
24 6
89 24 22
24 6
24 22 18 6
89 24 22
89 24
24 22 6
24 22 6
24 22 18 6
89 17 24 6
24 6
89 24
24 19 18 6
24 22 6
24 6
89 17
(9 OF 10)
VSSVSS
(8 OF 10)
VSSVSS
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
23 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
PCH GROUNDSSYNC_DATE=07/01/2009SYNC_MASTER=K60_SIJI
FCBGA
OMIT
IBEX-PEAK-DESKTOP
U1800A14
A30
AA41
AR30
AT14
AT18
AT22
AU12
AU16
AU19
AU20
AU22
AU23
AB18
AU29
AU30
AU33
AU37
AU38
AU41
AU5
AU9
AV24
AV28
AB19
AV5
AW17
AW18
AW24
AW28
AW3
B10
B22
BA14
BA21
AB20
BA28
BA37
BA7
C10
AB22
AB23
AB27
AB29
AB30
AB33
A35
AB34
AB40
AB5
AB8
AC37
AC5
AD11
AD19
AD2
AD22
A7
AD24
AD29
AD30
AD31
AD34
AD39
AD40
AD6
AD8
AE3
AA19
AE39
AE4
AF11
AF12
AF18
AF26
AF29
AF3
AF31
AF32
AA20
AF33
AF36
AF37
AF39
AF5
AH15
AH19
AH24
AH26
AH27
AA22
AH29
AH32
AH34
AH36
AH41
AH9
AJ20
AJ24
AJ26
AJ28
AA38
AK10
AK22
AK3
AK32
AK34
AK37
AK5
AK8
AK9
AL8
AA39
AM10
AM12
AM14
AM18
AM28
AM32
AN12
AN14
AN18
AN22
AA4
AN28
AN30
AN37
AN5
AP20
AP24
AR1
AR11
AR18
AR28
OMIT
IBEX-PEAK-DESKTOP
FCBGAU1800
C11
C17
C18
C23
C31
C32
C39
D22
D34
D37
D39
E12
E13
E15
E16
E19
E22
E23
E30
E33
E37
E4
E5
E6
E8
E9
F11
F12
F14
F16
F18
F20
F24
F30
F34
F5
G1
G34
G38
G39
G41
H31
H5
H7
H9
J14
J16
J18
J24
J37
J39
J5
J6
J7
K16
K2
K20
K22
K3
K32
K39
K40
L11
L12
L16
L20
L22
L3
L30
L31
L32
L34
L8
M11
M12
M14
M33
M37
M5
M8
N14
N37
N5
P1
P11
P20
P22
P23
P31
P34
P4
P8
R4
R5
T11
T16
T18
T3
T35
T5
T8
U16
U18
U2
U24
U27
U3
U39
V12
V13
V16
V18
V19
V22
V27
V3
V33
V35
V39
V6
V9
W3
W37
W39
W5
Y10
Y13
Y27
Y30
Y33
Y40
Y5
NC
NC
NC
NC
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PCH VCCLAN BYPASS
(PCH 1.05V LAN Core PWR)
PLACEMENT_NOTEs (all 3):
<1 MA
PCH V_CPU_IO BYPASS
(PCH HD Audio 3.3V/1.5V PWR)
(PCH SUSPEND USB 3.3V PWR)
(PCH USB 1.05V PWR)
PLACEMENT_NOTE:
PCH VCCIO BYPASS
(PCH SATA 1.05V PWR)
PLACEMENT_NOTEs (all 5):
(PCH CLK 1.05V PWR)
PCH VCCIO BYPASS
3.251 A S0 /
369 MA IDLE
(VCCIO TOTAL)
PLACEMENT_NOTE:
PLACEMENT_NOTE:
PLACEMENT_NOTEs:(PCH 1.1V/1.05V CPU I/O PWR)
PCH VCCSUSHDA BYPASS
Current numbers from Ibex Peak EDS Spec Update rev 0.71, doc #386904 (Table 8-3). Pre-Silicon Mobile Estimates.
PLACEMENT_NOTEs:
HDA_SYNC: 0 = 1.8V, 1 = 1.5V
PCH VCCAPLLEXP Filter
(PCH PCIe PLL PWR)
1.5V, but draws more current.
PCH VCCME3_3 BYPASS
1 mA
PLACEMENT_NOTEs:
(VCCSUS3_3 Total)
PCH USB/VCCSUS3_3 BYPASS
PLACEMENT_NOTE:
PCH VCCIO BYPASS
PLACEMENT_NOTEs:
PCH VCC3_3 BYPASS
PLACEMENT_NOTE:
PLACEMENT_NOTEs:
(PCH Misc PLL PWR)
PCH VCCACLK Filter
PCH VCCFDIPLL Filter
PCH VCCIO BYPASS
(PCH PCIE 1.05V PWR)
PLACEMENT_NOTEs:
<1 MA
196 MA
<1 MA S0-S5
65 MA
372 MA
6 MA
(PCH FDI PLL PWR)
PLACEMENT_NOTE:
88 MA S3-S5
PCH VCCIO BYPASS
(PCH DMI 1.05V PWR)
PLACEMENT_NOTE:
PLACEMENT_NOTE:
PLACEMENT_NOTEs:
PLACEMENT_NOTE:
(PCH PCI 3.3V PWR)
PLACEMENT_NOTE:
2 mA S0-S5 /
(PCH SATA PLL PWR)
PCH VCCSATAPLL Filter
(PCH 1.05V CORE PWR)
1.629 A
PCH VCCCORE BYPASS
(PCH SUSPEND USB 3.3V PWR)
(PCH ME 3.3V PWR)
(PCH SATA 3.3V PWR)
PCH VCC3_3 BYPASS
2.22 A
PCH VCCME BYPASS
(PCH MISC 3.3V PWR)
PCH CORE/VCC3_3 BYPASS
PLACEMENT_NOTE:
(PCH Reference for 5V Tolerance on PCI)
PCH V5REF Filter & Follower
PLACEMENT_NOTEs (all 3):
PCH VCCRTC BYPASS PCH VCCPNAND BYPASS
(PCH NAND 1.8V/3.3V PWR)
1 mA S0-S5 (PCH Reference for 5V Tolerance on USB)
(OR 1.5V)
PLACEMENT_NOTEs:
196 MA
GPIO27: 1 = enabled, 0 = disabled
NOTE: VccVRM input also supports
L2412 - 155S0441
357 MA S0 /
PCH V5REF_SUS Filter & Follower
PCH VCCSUS3_3 BYPASS
6 uA G3
(PCH RTC 3.3V PWR)
PLACEMENT_NOTE:
(PCH 1.05V ME Core PWR)
PLACEMENT_NOTE:
24 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
=PP1V05_SM_PCH_VCC_LAN
=PPVTT_S0_PCH_VCCP_CPU
=PP3V3R1V8_S0_PCH_VCCPNAND
=PP1V05_S0_PCH_VCCIO_PCIE
=PP1V05_S0_PCH_VCCIO_USB
=PP1V05_S0_PCH_VCCIO_SATA
=PP3V3R1V5_S0_PCH_VCCSUSHDA
=PPVTT_S0_PCH_VCC_DMI
MIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MMVOLTAGE=1.05V
PP1V05_S0_PCH_VCCAPLL_EXP
VOLTAGE=1.05V
MIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM
PP1V05_S0_PCH_VCCAPLL_FDI
PP1V05_S0_PCH_VCCAPLL_SATAMIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MMVOLTAGE=1.05V
VOLTAGE=1.05VMIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.5MMPP1V05_S0_PCH_VCCA_CLK
PP1V05_S0_PCH_VCCA_CLK_F
MIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.5MM
VOLTAGE=1.05V
=PP5V_S0_PCH
=PP3V3_S0_PCH
MIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.3MMPP5V_S0_PCH_V5REF
VOLTAGE=5V
=PP3V3_SM_PCH_VCC_ME
=PP3V3_S5_PCH_VCCSUS3_3_USB
=PP3V3_S0_PCH_VCC3_3_SATA
=PP3V3_S5_PCH_VCCSUS3_3_USB
=PP1V05_S0_PCH_VCC_CORE
=PP3V3_S0_PCH_VCC3_3_PCI
=PP3V3_S0_PCH_VCC3_3_CORE
=PP3V3_S5_PCH
=PP5V_S5_PCH
VOLTAGE=5VMIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.3MMPP5V_S5_PCH_V5REFSUS
MIN_NECK_WIDTH=0.25MMVOLTAGE=1.5V
PP1V8R1V5_S0_PCH_VCCVRMMIN_LINE_WIDTH=0.5MM
MAKE_BASE=TRUE
=PP1V8R1V5_S0_PCH_VCCVRM
=PP1V05_S0_PCH
PP3V3_G3_RTC
=PP1V05_S0_PCH_VCCIO_DMI
=PP1V05_SM_PCH_VCC_ME
PCH DECOUPLINGSYNC_MASTER=K60_SIJI SYNC_DATE=07/01/2009
1K5%
MF-LF1/16W
402
R24601
2
6.3V20%
805CERM
22UF
PLACE C2465 NEAR BALL P18
C2490 1
2
NOSTUFF
0.1UF
X5R402
10%16V
PLACE C2441 NEAR BALL P30
C24411
2
603X5R6.3V20%
4.7UF
PLACE C2488 NEAR BALL AH23
C2488 1
2
6.3V20%
805CERM
22UF
PLACE C2465 NEAR BALL Y29
C2486 1
2
PLACE C2439 NEAR BALL A9
0.1UF
402X5R
10%16V
C24391
2
0.1UF
16V10%
402X5R
NOSTUFF
PLACE C2438 NEAR BALL AH16
C24381
2X5R402
PLACE C2437 NEAR BALL AH16
0.1UF10%16V
C24371
2
PLACE C2467 NEAR BALL AH1
603X5R6.3V
10UF20%
C2467 1
2
805
6.3V
22UF
CERM
20%
PLACE C2473 NEAR BALL AE18
C24731
2603X5R6.3V20%4.7UF
PLACE C2472 NEAR BALL AE18
C24721
20603
220-OHM-1.4A
MLB_VR
L2418
1 2
0603
220-OHM-1.4A
MLB_VRL2416
1 2
0603
220-OHM-1.4A
MLB_VR
L2414
1 2
MLB_VR
220-OHM-1.4A
0603
L2412
1 2
16V10%
402X5R
0.1UF
PLACE C2446 NEAR BALL U40
C24461
2
6.3VCERM
10%
402
1UF
PLACE C2420 NEAR BALL AY29
C2420 1
2
603X5R6.3V
10UF20%
PLACE C2470 NEAR BALL AE18
C2470 1
2
402CERM6.3V10%1UF
PLACE C2471 NEAR BALL AE18
C24711
2
PLACE C2465 NEAR BALL AB15
22UF
CERM805
20%6.3V
C2465 1
26.3V10%
CERM
1UF
PLACE C2468 NEAR BALL AJ4
402
C24681
2
10%6.3V
1UF
CERM402
PLACE C2455 NEAR BALL A23
C24551
2
1UF
CERM402
10%6.3V
PLACE C2491 NEAR BALL P18
C24911
2
1UF
CERM402
10%6.3V
PLACE C2492 NEAR BALL P15
C24921
2 CERM402
6.3V10%1UF
PLACE C2493 NEAR BALL U15
C24931
2
1UF
CERM6.3V
402
10%
PLACE C2465 NEAR BALL P24
C24941
2
6.3V
1UF
CERM402
10%
PLACE C2485 NEAR BALL Y26
C24851
2
402
6.3V
1UF
CERM
10%
PLACE C2480 NEAR BALL AJ22
C24801
2
10%1UF
402
PLACE C2475 NEAR BALL D25
CERM6.3V
C24751
2
402
1UF10%6.3VCERM
PLACE C2476 NEAR BALL H26
C24761
2
10%1UF
CERM402
6.3V
PLACE C2477 NEAR BALL AH22
C24771
2
PLACE C2466 NEAR BALL AH4
805
6.3V20%
CERM
22UFC2466 1
2
PLACE C2469 NEAR BALL AF10
402CERM6.3V10%1UFC24691
2
PLACE C2450 NEAR BALL B39
6.3VX5R603
4.7UF20%
C2450 1
2
0.1UF
X5R
10%16V
402
C24511
2
10%0.1UF
16VX5R402
C24521
2
10%
CERM402
6.3V
1UF
PLACE C2445 NEAR BALL AJ18
C24451
2
16V10%
402
0.1UF
X5R
PLACE C2440 NEAR BALL P30
C24401
2
X5R402
10%16V
0.1UF
PLACE C2436 NEAR BALL AV2
C24361
2
16V10%
X5R402
0.1UF
PLACE C2435 NEAR BALL AE27
C24351
2
0.1UF10%16VX5R402
PLACE C2430 NEAR BALL N38
C24301
2
16V10%
402X5R
0.1UF
PLACE C2426 NEAR BALL AW39
C24261
216V10%0.1UF
402X5R
PLACE C2427 NEAR BALL AJ18
C24271
2
MF-LF
5%
402
1/16W
PCH_VRM
0R2410
1 2
5%
0
MLB_VR
402MF-LF1/16W
R24111 2
1/16W
402MF-LF
15%
MLB_VR
R24181
2
Place C2416 within 2.54mm of balls
10UF
X5R603
20%6.3V
MLB_VR
C2416 1
2
402
PLACE C2417 AT BALL P41
1UF
CERM
10%6.3V
C24171
2
Place C2414 within 2.54mm of ball
10UF
X5R
20%6.3V
603
MLB_VR
C2414 1
2
PLACE C2415 AT BALL A37
6.3V10%
402CERM
1UFC24151
2
Place C2412 within 2.54mm of ball
X5R603
20%6.3V
10UF
MLB_VR
C2412 1
2
PLACE C2413 AT BALL A21
6.3V
402CERM
10%1UFC24131
2
X5R402
10%16V
0.1UFC24221
2
0.1UF
402X5R16V10%
PLACE C2425 NEAR BALL AV25
C24251
2
10%
402
16VX5R
0.1UF
PLACE C2421 NEAR BALL AY29
C24211
2
SOT-363BAT54DW-X-G
D24004
3
2
402
5%
MF-LF1/16W
10R24002
1
BAT54DW-X-GSOT-363
D24001
6
5
PLACE C2400 NEAR BALL AW16
10V
0.1UF
CERM402
20%
C2400 1
2
MF-LF1/16W
100
402
5%
R24012
1
6.3V10%
402CERM
1UF
PLACE C2419 AT BALL AA1
C24191
26.3V20%
603X5R
10UF
Place C2418 within 2.54mm of balls
MLB_VR
C2418 1
2
PLACE C2401 NEAR BALL AN1
X5R
1UF10%10V
402
C2401 1
2
22 6
22 6
22 6
22 19 18 6
22 6
22 18 6
22 6
22 6
89 22
89 22
89 22
89 22
89
6
68 21 18 6
89 22
22 6
24 22 6
22 6
24 22 6
22 6
22 6
22 6
19 18 6
6
89 22
89 22
6
6
89 27 22 18
22 6
22 6
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
IN
NC
NC
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
OBSDATA_C2
OBSDATA_C3
NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.
OBSFN_D0
OBSFN_D1
OBSDATA_C1
RESET#/HOOK6
OBSDATA_B3
VCC_OBS_AB
XDP_PRESENT#
OBSDATA_A1
OBSDATA_A3
TCK0
DBR#/HOOK7
XDP_PRESENT#
OBSDATA_B0
OBSDATA_A1
OBSFN_A0
OBSFN_A1
OBSFN_C0
OBSFN_C1
OBSDATA_C0
OBSDATA_D3
TDO
VCC_OBS_CD
DBR#/HOOK7
TRSTnSCL
PWRGD/HOOK0
PCH XDP
OBSFN_B1
OBSDATA_D0
OBSDATA_A3
TCK1
TCK0
OBSDATA_B1
OBSDATA_C0
516S0450
516S0450
PROCESSOR XDP
OBSDATA_C3
PLACE IT NEAR THE XDP
OBSDATA_B0
OBSDATA_C2
HOOK3
OBSDATA_A0
OBSDATA_B2
OBSFN_B0
TDO
TRSTn
HOOK2
OBSFN_C1
OBSFN_C0
OBSDATA_C1
OBSFN_D1
OBSFN_D0
OBSFN_B1
OBSFN_A0
OBSDATA_A2
RESET#/HOOK6
OBSDATA_D3
ITPCLK#/HOOK5
ITPCLK/HOOK4
TDI
OBSDATA_B2
OBSDATA_B1
HOOK3
SDA
SCL
TDI
TMS
SDA
TCK1
VCC_OBS_CD
ITPCLK/HOOK4
OBSDATA_D1
OBSDATA_D1
TMS
OBSDATA_B3
OBSDATA_A2
OBSFN_B0
HOOK1
OBSDATA_D2
ITPCLK#/HOOK5
OBSDATA_D2
OBSFN_A1
OBSDATA_A0
HOOK2
VCC_OBS_AB
HOOK1
PWRGD/HOOK0
NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.
1K series R on PCH Support Page
OBSDATA_D0
25 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
PCH_GPIO41_OC2_L
JTAG_PCH_TCK
TP_XDPPCH_OBSFN_A<0>
USB_HUB_SOFT_RESET_L_R
PCH_GPIO41_OC2_L_R
TP_XDPPCH_OBSFN_B<1>
PCH_GPIO43_OC4_L_R
=SMBUS_XDP_SDA
XDP_CPUPWRGD
XDP_PWRGD
XDP_BPM_L<7>
XDP_BPM_L<6>
MINI_CLKREQ_L_R
=PP3V3_S0_XDP
PCH_GPIO19_SATA1GP
TP_XDPPCH_OBSFN_D<0>
TP_XDPPCH_HOOK4
TP_XDPPCH_HOOK5
XDPPCH_PLTRST_L
XDP_DBRESET_L
SDCARD_RESET_R
PCH_GPIO49_SATA5GP
TP_JTAG_XDP_TRST_L
PCH_GPIO21_SATA0GP
TP_XDPPCH_OBSFN_D<1>
PCH_GPIO37_SATA3GP
PCH_GPIO10_OC6_L
ALL_SYS_PWRGD_R
TP_XDPPCH_HOOK3
PM_PWRBTN_L
=PPVTT_S0_XDP
XDP_BPM_L<5>
PCH_GPIO9_OC5_L_R
TP_XDPPCH_OBSFN_B<0>
JTAG_PCH_TMS
PCH_GPIO14_OC7_L
TP_XDPPCH_HOOK2
XDP_OBSDATA_A<0>
PM_PWRBTN_L
TP_XDP_HOOK3
=SMBUS_XDP_SCL
XDP_TCK
CPU_CFG<6>
XDP_TRST_L
FSB_CLK133M_ITP_N
CPU_PWRGD
XDP_BPM_L<3>
CPU_CFG<15>
FSB_CPURSTOUT_L
XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
CPU_CFG<12>
CPU_CFG<13>
CPU_CFG<14>
MINI_CLKREQ_L
=PP3V3_S5_XDP
CPU_CFG<7>
XDP_CPURST_L
FSB_CLK133M_ITP_P
XDP_TDO
XDP_PRDY_L
XDP_PREQ_L
=SMBUS_XDP_SDA
FW_CLKREQ_L_R
JTAG_PCH_TDI
PCH_GPIO59_OC0_L
TP_XDPPCH_OBSFN_A<1>
PCH_GPIO42_OC3_L
USB_HUB_SOFT_RESET_L
PCH_GPIO43_OC4_L
PCH_GPIO9_OC5_L
AUD_IPHS_SWITCH_EN_R
SDCARD_RESET
=SMBUS_XDP_SCL
XDP_TMS
AUD_IPHS_SWITCH_EN
PCH_GPIO0_BMBUSY_L
ISOLATE_CPU_MEM_L_R
JTAG_PCH_TDO
FW_CLKREQ_L
ISOLATE_CPU_MEM_L
XDP_TDI
XDP_DBRESET_L
CPU_CFG<0>
XDP_BPM_L<4>
XDP_OBSDATA_A<1>
XDP_OBSDATA_A<3>
XDP_OBSDATA_A<2>
CPU_CFG<17>
CPU_CFG<16>
CPU_CFG<5>
CPU_CFG<4>
CPU_CFG<11>
CPU_CFG<10>
CPU_CFG<3>
CPU_CFG<2>
CPU_CFG<1>
CPU_CFG<8>
CPU_CFG<9>
SYNC_MASTER=K60_SIJI
EXTENDED DEBUG PORT(XDP)SYNC_DATE=07/01/2009
34 20
XDP
5%MF-LF
0402
1/16W
R25811 2
XDP
5% 1/16WMF-LF 402
0R25831 2
XDP
5% 1/16WMF-LF 402
0R25821 2
XDP
0402
1/16WMF-LF5%
R25801 2
5%0
XDP
1/16WMF-LF 402
R25791 2
XDP
4025% 1/16W
MF-LF
0R25781 2
XDP_CONN
F-ST-SMBSH-030-01-L-D-A-TR
CRITICAL
J2550
1
10
11 12
13 14
15 16
17 18
19
2
20
21 22
23 24
25 26
27 28
29
3
30
31 32
33 34
35 36
37 38
39
4
40
41 42
43 44
45 46
47 48
49
5
50
51 52
53 54
55 56
57 58
59
6
60
7 8
9
XDP_CONN
BSH-030-01-L-D-A-TR
CRITICAL
F-ST-SM
J2500
1
10
11 12
13 14
15 16
17 18
19
2
20
21 22
23 24
25 26
27 28
29
3
30
31 32
33 34
35 36
37 38
39
4
40
41 42
43 44
45 46
47 48
49
5
50
51 52
53 54
55 56
57 58
59
6
60
7 8
9
51
XDP
5%
402MF-LF1/16W
R25151
2
91 45 25 19
XDP
5% 1/16WMF-LF 402
0R25771 2
XDP
01/16W402MF-LF
5%
R25761 2
1/16W5%0
402MF-LF
XDPR25751 2
200
1/16WMF-LF
5%
402
XDPR25551
2
18
84 10
91 63 32 6
20
20 15
20
20
91 21 11
84 10
XDP
1K
402MF-LF
5%1/16W
R25101 2
11
48 25
48 25
91 11
84 11
84 11
84 11
84 11
84 15 10
84 10
84 10
84 10
84 10
84 11
84 11
84 11
84 11
PLACEMENT_NOTE=Place R2501 close to R2500 to minimize stubs.
0
XDP_CPU_CFG
SM-LF1/16W5%
RP25011
2
3
4
8
7
6
5
XDP_CPU_BPM
1/16W5%0
SM-LF
RP25001
2
3
4
8
7
6
5
84 10
84 10
84 10
11
11
XDP
10%
X5R16V
0.1uF
402
C2500 1
2
84 10
XDP
0.1uF10%
X5R16V
402
C25011
2
18
18
18
27
21 15
21 15
84 10
18 15
18 15
40 18 15
33 18 15
32 21
21 15
11
11
11
84 10
11
91 27 25 11
84 11
84 11
84 10
84 10
84 10
84 10
XDP
402MF-LF1/16W5%
1K
PLACEMENT_NOTE=Place close to CPU to minimize stub.
R25111 2
MF-LF402
1005%1/16W
XDPR25561
2
61 21
92 91 44 21
20
20
20
91 11
84 10
48 25
91
6
91 27 25 11
8
91 45 25 19
6
84
6
48 25
84
84
84
REF
CPU
CPU*
SRC_2*
SRC_2
SATA*
SATA
27MHZ
27MHZ_SS
DOT_96*
X2
X1
SCL
SDA
CKPWRGD/PD*
VDD_CORE
VDD_REF
VDD_96_IO
VDD_27
VDD_SATA_IO
VDD_SRC_IO
VDD_CPU_IO
VSS_CPU
VSS_27
VSS_96
THRM
VSS_SATA
VSS_SRC
VSS_REF
VSS_CORE
DOT_96
27MHZ_EN
PAD
BI
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PLACE IT CLOSE TO L2650
PLACE IT CLOSE TO POWER PINS
PLACE IT CLOSE TO POWER PINSPLACE IT CLOSE TO L2600
PLACE IT CLOSE TO L2610
PLACE IT CLOSE TO POWER PINS
PCH BCLK 133MHZ
PCH SATA 100MHZ
PCH DMI/PCIe 100MHz
PCH USB Clock 96MHz
26 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
CK505_CLK27M
TP_CK505_CLK27M_SS
PCH_CLK14P3M_REFCLK
=PP3V3_S0_CK505
=PP1V05_S0_CK505
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.5mmMIN_NECK_WIDTH=0.2mm
PP1V5_S0_CK505_F=PP1V5_S0_CK505
PCH_CLK14P3M_REFCLK_R
PP1V5_S0_CK505_R
FSB_CLK133M_PCH_N
FSB_CLK133M_PCH_P
PCIE_CLK100M_PCH_N
PCIE_CLK100M_PCH_P
PCH_CLK100M_SATA_N
PCH_CLK100M_SATA_P
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5mmMIN_NECK_WIDTH=0.2mm
PP3V3_S0_CK505_F
PM_PGOOD_PVCORE_CPU
=SMBUS_CK505_SDA
VOLTAGE=1.05VMIN_NECK_WIDTH=0.2mmMIN_LINE_WIDTH=0.5mmPP1V05_S0_CK505_F
PCH_CLK96M_DOT_P
CK505_27MHZ_EN
=SMBUS_CK505_SCL
CK505_XTAL_IN
CK505_XTAL_OUT_R
CK505_XTAL_OUT
PCH_CLK96M_DOT_N
SYNC_MASTER=K60_SIJI SYNC_DATE=07/01/2009
CLOCK (CK505)
84 18
84 18
402MF-LF
1/16W5%
BUF_CLK
0R2615
1 2
84 18
84 18
84 18
84 18
84 18
84 18
BUF_CLK
10K
MF-LF402
1/16W5%
R26001
2
PLACE R2699 NEAR PIN 26
4025%
BUF_CLK
331/16W MF-LF
R26991 2
NO STUFF
10M
MF-LF
5%1/16W
402
R26161
2
BUF_CLK
10K5%
402MF-LF1/16W
R26901
2
2.2
5%1/16WMF-LF402
BUF_CLK
R26501 2
85 18
0402
FERR-120-OHM-1.5A
BUF_CLK
L2650
1 2
6.3V20%
603X5R
10UF
BUF_CLK
C2650 1
2 16V10%
402X5R
0.1UF
BUF_CLK
C26511
2
0.1UF
X5R402
10%16V
BUF_CLK
C26521
2
91 64 63 5
48
48
BUF_CLK
18pF
CERM402
5%50V
C2620 1
2
14.31818
BUF_CLK5X3.2-SM
CRITICAL
Y2620
1 2
BUF_CLK
CERM
18pF
402
50V5%
C26211
2
SLG2AP108QFN
CRITICAL
OMIT
U2600
29
32
30
1
19
18
6
7
26
14
15
3
2
10
11
33
31
8 4 22
17
25
16
9
28 5
21
20
27
13
12
24
23
0402
FERR-120-OHM-1.5A
BUF_CLK
L2600
1 2
20%
X5R
10UF
6.3V
603
BUF_CLK
C2600 1
216V
402X5R
10%0.1UF
BUF_CLK
C26021
2 X5R
10%
402
0.1UF
BUF_CLK
16V
C26031
2 X5R16V10%0.1UF
402
BUF_CLK
C26041
2 X5R
0.1UF10%16V
402
BUF_CLK
C26051
2
FERR-120-OHM-1.5A
0402
BUF_CLK
L2610
1 2
6.3V20%
X5R603
10UF
BUF_CLK
C2610 1
2 X5R402
10%16V
0.1UF
BUF_CLK
C26151
2
402
10%16V
0.1UF
X5R
BUF_CLK
C26161
2
6
6 89 6 89
89
89
91
85
85
IN OUT
NCNC
OUT
OUT
OUT
OUT
IN
OUT
IN
IN
IN
OUT
NCNC
NCNC
NCNC
OUT
OUT
OUT
OUT
IN
OUTIN
OUT
OUT
OUT
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
UnbufferedPlatform Reset ConnectionsRTC Power Sources
VTT voltage divider on CPU page
MAY NEED TO MOVE LONGER TRACE ONES TO BUFFERED
PCH RTC Crystal
fault protection for RTC battery.
Buffered
RESET circuit (see R4785)
Coin-Cell Holder
511-0054
R2888 not necessary with WLAN
NOTE: R2800 and D2800 form the double-
Reset Button
PCH 25MHz Crystal
28 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
=PP3V3_S5_RTC_D
PLT_RESET_LMAKE_BASE=TRUE
PLT_RST_BUF1_L
SDCARD_PLT_RST_L
PLT_RST_BUF2_L
=PP3V3_S0_RSTBUF
CPU_RESET_L
XDP_DBRESET_L PM_SYSRST_L
PCH_CLK25M_XTALOUT_RPCH_CLK25M_XTALOUT
PCH_CLK32K_RTCX2
PCH_CLK32K_RTCX1
=PP3V3_S0_RSTBUF
XDPPCH_PLTRST_L
PEG_RESET_L
LPC_CLK33M_SMC
PCH_CLK33M_PCIOUT
LPC_CLK33M_LPCPLUS_R
LPC_CLK33M_SMC_R
PCH_CLK33M_PCIIN
LPC_CLK33M_LPCPLUS
MINI_RESET_L
SMC_LRESET_L
PCH_CLK25M_XTALIN
FW_RESET_L
MIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3V
MIN_LINE_WIDTH=0.3 mmPP3V3_G3_RTC
DEBUG_RESET_L
LAN_RESET_L
PPVBATT_G3_RTC_R
MIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3V
MIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3V
MIN_LINE_WIDTH=0.3 mmPPVBATT_G3_RTC
PCH_CLK32K_RTCX2_R
=PP3V3_S0_PCH_PM
SYNC_DATE=07/01/2009SYNC_MASTER=K60_SIJI
CHIPSET SUPPORT
91 44 33
402MF-LF1/16W5%
R28951 2
SMNTC020-CC1J-B260T
DEVELOPMENT
SILK_PART=SYS RESET
SW28001 2
3 4
MF-LF402
5%
0
1/16W
FCIMR2815
1 2
402
1/16W5%
0
MF-LF
R28101 2
1/16W5%100K
MF-LF402
R28931
2402
0.1UF
10V20%
CERM
C2890 1
2
MC74VHC1G08SOT23-5-HF
U2890
3
2
1
4
5
MC74VHC1G08SOT23-5-HF
U2880
3
2
1
4
5
5%1/16WMF-LF402
33R28911 2
10M5%
402MF-LF
FCIM
1/16W
R28161
2
5%10M
MF-LF402
1/16W
R28111
2
4.7K
MF-LF1/16W5%
402
R28971
2
BB10201-C1403-7HSM
J2800
2
1
33
402
5%
MF-LF1/16W
R28821 2 91 36
1/16W
100K5%
402MF-LF
R28801
2
0.1UF
CERM
20%10V
402
C2880 1
2
1/16WMF-LF402
5%
33R28881 2
5%
XDP
1K
402MF-LF1/16W
R28891 2 25
85 20 33PLACEMENT_NOTE=Place close to U1800
402MF-LF1/16W5%
R28271 2 85 18
85 20
91 11
85 45
85 47
1/16WMF-LF402
5%
33R2892
1 2 91 39
85 18
85 18
SM-3.2X2.5MM
CRITICAL
25.0000M
FCIMY2815
24
13
FCIM
402
12pF
5%50VCERM
C2816
1 2
402
12pF
5%50VCERM
FCIMC2815
1 2
85 20 33PLACEMENT_NOTE=Place close to U1800
1/16WMF-LF
5%
402
R28251 2
33PLACEMENT_NOTE=Place close to U1800
5%
MF-LF1/16W
402
R28261 2
91 20
85 18
85 18
91 33
91 9
91 45
91 47
33
1/16WMF-LF
5%
402
R28901 2
33
MF-LF1/16W
402
5%
R28811 2
33
5%
402
1/16WMF-LF
R28831 2
SOT-363BAT54DW-X-GD2800
1
4
6
3
5 2
XDP
MF-LF
5%
0
1/16W
402
R28961 2
SM-232.768K
CRITICAL
Y2810
24
13
50VCERM402
12pF
5%
C2811
1 2
402
50V5%
12pF
CERM
C2810
1 2
5%1/16WMF-LF
1K
402
R28002 1
91 45 19 91 25 11
6
27 6
27 6
89 24 22 18
89 89
6
OUT
OUT
IN
SCL RH
RW
VDD
SDAGND
SCL RH
RW
VDD
SDAGND
BI
IN
BI
DS
G
DS
G
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
I2C ADDR = 0X5D (READ)
353S2369
353S2370
353S1961
I2C ADDR = 0X7D (READ)
I2C ADDR = 0X7C (WRITE)
353S1961
PLACE IT CLOSE TO DIMM CONNECTOR PIN
PLACE IT CLOSE TO DIMM CONNECTOR PIN
PLACE IT CLOSE TO DIMM CONNECTOR PIN
I2C ADDR = 0X5C (WRITE)
PLACE IT CLOSE TO DIMM CONNECTOR PIN
29 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
PP0V75_S3_MEM_VREFDQ_A
=PP3V3_S3_VREFMRGN
ISOLATE_CPU_MEM_5V_L
I2C_VREFMARGIN_DIMMB_SCL
I2C_VREFMARGIN_DIMMA_SDA
=PP3V3_S3_VREFMRGN
VREFMARGIN_DIMMA_OPFB
=PP1V5_S3_MEM_B
=I2C_VREFMRGN_B_SCL
VREFMARGIN_DIMMA_P5V
I2C_VREFMARGIN_DIMMA_SCL
VREFMARGIN_DIMMA_DACOUT
VREFMARGIN_DIMMB_P5V=PP5V_S3_VREFMRGN
I2C_VREFMARGIN_DIMMB_SDA
=I2C_VREFMRGN_A_SDA
=PP5V_S3_VREFMRGN
=I2C_VREFMRGN_B_SDA
VREFMARGIN_DIMMB_DACOUT
=PP1V5_S3_MEM_B
PP0V75_S3_MEM_VREFDQ_B
VREFMARGIN_DIMMA_DQ
=PP1V5_S3_MEM_A
VREFMARGIN_DIMMB_DQ
VREFMARGIN_DIMMA_DQ
VREFMARGIN_DIMMB_DQ
VREFMARGIN_DIMMA_DQ
VREFMARGIN_DIMMB_DQ
CPU_DIMM_VREF_A CPU_DIMM_VREF_A_SW
CPU_DIMM_VREF_B
VREFMARGIN_DIMMB_OPFB
=PP1V5_S3_MEM_A
PP0V75_S3_MEM_VREFCA_A
=PP1V5_S3_MEM_A
=PP1V5_S3_MEM_A
PP0V75_S3_MEM_VREFCA_B
CPU_DIMM_VREF_B_SW
ISOLATE_CPU_MEM_5V_L
=I2C_VREFMRGN_A_SCL
DDR3 VREF MARGININGSYNC_DATE=07/01/2009SYNC_MASTER=K60_SIJI
1K1/16WMF-LF
1%
402
R29891
2
1K
402
1/16W1%
MF-LF
R29881
2
5%
0
1/16WMF-LF402
NOSTUFFR29911 2
NOSTUFF
402MF-LF1/16W
0
5%
R29931 2
INT_VREF
2N7002SOT23-HF1
Q29933
1
2
INT_VREF
SOT23-HF12N7002Q2991
3
1
2
1K1%1/16WMF-LF402
R29761
2
1K
402MF-LF
1%1/16W
R29751
2
1K
402
1%
MF-LF1/16W
R29711
2
1K
402
1/16W1%
MF-LF
R29701
2
0
5%
MF-LF402
1/16W
INT_VREFR29531 2
VREFMRGN
402MF-LF1/16W5%
0R29561 2 NOSTUFF
1/16W5%
0
402MF-LF
R29961 2
16VX5R402
0.1UF10%
NOSTUFF
C29511
2
INT_VREF
402MF-LF1/16W
0
5%
R29501 2
NOSTUFF
0.1UF10%
402X5R16V
C29911
2
1/16WMF-LF402
0
5%
VREFMRGNR29581 2
NOSTUFF
MF-LF1/16W
402
0
5%
R29951 2
16V
402
0.1UF
X5R
10%
NOSTUFF
C29501
2NOSTUFF
16V
402
0.1UF10%
X5R
C29211
2
48
48
48
MF-LF
VREFMRGN
402
0
5%1/16W
R29111 2
1/16WMF-LF
5%
402
VREFMRGN
0R29101 2
VREFMRGN
MF-LF402
1/16W5%
0R29011 2
1/16W
402MF-LF
1%12.1K
VREFMRGN
R29131
2
10%
402X5R16V
VREFMRGN
0.1UFC29101
2
SC-70VREFMRGN
ISL90727WIE627ZTKU2910
2
6
5
3
4
1
SC-70VREFMRGN
ISL90728WIE627ZTKU2900
2
6
5
3
4
1
VREFMRGN
12.1K
402MF-LF
1%1/16W
R29121 2
VREFMRGN
1/16W
402MF-LF
1%
10R29191 2
1%12.1K
VREFMRGN
402MF-LF1/16W
R29031
2
16V10%0.1UF
402X5R
VREFMRGNC29011
2
48
1/16W
0
VREFMRGN
402MF-LF
5%
R29001 2
VREFMRGN
10%
X5R16V
402
0.1UFC29001
2
1%
MF-LF1/16W
402
12.1K
VREFMRGN
R29021 2
VREFMRGN
1/16W
402MF-LF
1%
10R29091 2
1/16W5%
2.2
402MF-LF
VREFMRGN
R29041 2
1/16W
402
1001%
MF-LF
VREFMRGN
R29151
2
SOT23-5
VREFMRGN
LM321U2911
3
1
4
2
5
16V
402X5R
10%0.1UF
VREFMRGNC29111
2
SOT23-5LM321
VREFMRGN
U2901
3
1
4
2
5
VREFMRGN
2.2
5%
MF-LF402
1/16W
R29141 2
1UF
402
10%6.3VCERM
VREFMRGN
C29121
2
1001%1/16WMF-LF402
VREFMRGN
R29051
2CERM402
10%1UF6.3V
VREFMRGNC29021
2
1K
402
1%
MF-LF1/16W
R29791
2
1K
MF-LF
1%1/16W
402
R29781
2
83 28
83 28
89 30
28 6
32 28
28 6
31 29 28 6
28 6
28 6
31 29 28 6
89 31
83 28
30 29 28 6
83 28
83 28
83 28
83 12 83
83 12
30 29 28 6
89 30
30 29 28 6
30 29 28 6
89 31
83
32 28
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
CAPS TO COUPLE CPU 1V5_MEM
EXTRA DECOUPLING CAPS FOR CPU MEM RAIL
DECOUPLING CAPS FOR DIMM ON CHANNEL B - AT CONNECTOR
DECOUPLING CAPS FOR DIMM ON CHANNEL A - AT CONNECTOR
DIMM A (FURTHER FROM CPU) DIMM B (CLOSER TO CPU)
30 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
=PP1V5_CPU_MEM
=PP1V5_CPU_MEM
=PP1V5_S3_MEM_A
=PP1V5_CPU_MEM
=PP1V5_S3_MEM_B
SYNC_DATE=07/01/2009SYNC_MASTER=K60_SIJI
MEMORY CAPS
402CERM
10%1UF6.3V
C30591
2402CERM
10%1UF6.3V
C30601
2402CERM
10%1UF6.3V
C30611
2 CERM402
10%1UF6.3V
C30621
2 6.3V
402CERM
10%1UFC30631
2402CERM
10%1UF6.3V
C30641
2402CERM
10%1UF6.3V
C30651
2
402
10%
CERM6.3V
1UFC30461
2
1UF6.3VCERM
10%
402
C30441
2
1UF6.3VCERM
10%
402
C30421
2
1UF6.3VCERM
10%
402
C30411
2
402CERM
10%1UF6.3V
C30331
26.3V
1UF10%
CERM402
C30321
26.3V
1UF10%
CERM402
C30311
26.3V
1UF10%
CERM402
C30301
26.3V
1UF10%
CERM402
C30141
26.3V
1UF10%
CERM402
C30231
26.3V
1UF10%
CERM402
C30221
26.3V
1UF10%
CERM402
C30211
26.3V
1UF10%
CERM402
C30201
2402CERM
10%1UF6.3V
C30291
26.3V
1UF10%
CERM402
C30281
26.3V
1UF10%
CERM402
C30271
26.3V
1UF10%
CERM402
C30261
26.3V
1UF10%
CERM402
C30251
2402
6.3V
1UF10%
CERM
C30101
210%6.3V
1UF
CERM402
C30191
26.3V
1UF10%
CERM402
C30181
26.3V
1UF10%
CERM402
C30171
26.3V
1UF10%
CERM402
C30161
2
402CERM
10%1UF6.3V
C30861
2402CERM
10%1UF6.3V
C30871
2402CERM
10%1UF6.3V
C30881
2402CERM
10%1UF6.3V
C30891
2
6.3V
1UF10%
CERM402
C30691
26.3V
1UF10%
CERM402
C30681
26.3V
1UF10%
CERM402
C30671
2402CERM
10%1UF6.3V
C30661
2
1UF6.3VCERM402
10%
C30A51
2402CERM
1UF6.3V10%
C30A61
2402CERM
10%1UF6.3V
C30A71
2 CERM
10%1UF
402
6.3V
C30A81
2402CERM
10%1UF6.3V
C30A91
2402CERM
10%1UF6.3V
C30AA1
2402
10%1UF6.3VCERM
C30AB1
2402
10%1UF
CERM6.3V
C30AC1
2402CERM
10%1UF6.3V
C30AD1
2402CERM
1UF6.3V10%
C30AE1
2
1UF
402
10%
CERM6.3V
C30A01
2 6.3V
1UF
CERM402
10%
C30A11
2
1UF
CERM402
6.3V10%
C30A21
2
1UF
CERM402
6.3V10%
C30A31
2
1UF
CERM402
6.3V10%
C30A41
2
1UF6.3VCERM
10%
402
C30401
210%6.3V
1UF
CERM402
C30431
2402CERM
10%1UF6.3V
C30451
26.3V
1UF10%
CERM402
C30471
26.3V
1UF10%
CERM402
C30481
26.3V
1UF10%
CERM402
C30491
26.3V
1UF10%
CERM402
C30901
26.3V
1UF10%
CERM402
C30911
26.3V
1UF10%
CERM402
C30921
26.3V
1UF10%
CERM402
C30931
26.3V
1UF10%
CERM402
C30941
2
10UF
603X5R6.3V20%
C30701
2
20%
X5R6.3V
10UF
603
C30711
26.3V
1UF
CERM
10%
402
C30721
2402CERM
1UF6.3V10%
C30731
2402CERM
10%1UF6.3V
C30741
2402CERM
10%1UF6.3V
C30751
2402CERM
10%1UF6.3V
C30761
2402CERM
10%1UF6.3V
C30771
2402CERM
10%1UF6.3V
C30781
2402CERM
10%1UF6.3V
C30791
2402CERM
10%1UF6.3V
C30801
2402CERM
10%1UF6.3V
C30811
2 6.3V
1UF10%
CERM402
C30821
2 6.3V
1UF10%
CERM402
C30831
2 6.3V
1UF10%
CERM402
C30841
2 6.3V
1UF10%
CERM402
C30851
2
10UF
X5R6.3V20%
603
C30501
2
20%
X5R6.3V
10UF
603
C30511
26.3V
1UF
CERM
10%
402
C30521
2402CERM
1UF6.3V10%
C30531
2402CERM
10%1UF6.3V
C30541
2402CERM
10%1UF6.3V
C30551
2402CERM
10%1UF6.3V
C30561
2402CERM
10%1UF6.3V
C30571
2402CERM
10%1UF6.3V
C30581
2
29 16 13 11 6
29 16 13 11 6
30 28 6
29 16 13 11 6
31 28 6
S1*
A13
VDD_14
CAS*
VDD_12
BA0
A10_AP
WE*
A3
DQ54
DQ55
VSS_44
VSS_0
VSS_2
VSS_5
DQS0
DQS0*
DQ5
DQ4
DQ6
DQ7
VREFDQ
VSS_1
VSS_3
DQ0
DQ1
DM0
VSS_4
VSS_7
DQ12
DQ20
VSS_13
DQ15
DQ14
VSS_11
RESET*
VSS_9
DQ13
DM1
DQ21
VSS_15
DQ22
VSS_16
VSS_18
DQ23
DQ28
DQS3*
VSS_20
DQ29
DM2
VSS_23
DQS3
DQ30
DQ31
VSS_25
VDD_1
CKE1
A15
A14
VDD_3
VDD_9
VDD_5
VDD_7
A7
A11
A4
A6
A2
A0
CK1
NC_1
ODT1
VDD_15
ODT0
VDD_13
RAS*
VDD_11
CK1*
BA1
S0*
DQ39
DQ38
VSS_30
VSS_29
DQ37
DQ36
VSS_27
VREFCA
VDD_17
DM4
VSS_32
DQ47
DQ44
DQ46
VSS_37
DQS5
DQS5*
VSS_39
VSS_34
DQ45
DQ52
VSS_46
DQ61
DQ60
VSS_42
VSS_41
DQ53
DM6
VTT_1
DQS7*
DQS7
EVENT*
VSS_51
DQ63
DQ62
VSS_49
SDA
SCL
DQ2
DQ3
VSS_6
DQ8
DQ9
VSS_8
DQS1*
DQS1
VSS_10
DQ16
VSS_12
DQ11
DQ10
DQ17
DQ18
DQS2
VSS_17
DQS2*
VSS_14
VSS_21
DQ24
DQ25
DQ19
VSS_19
VSS_24
DQ27
DQ26
DM3
VSS_22
CKE0
A5
VDD_4
CK0
VDD_8
A1
VDD_6
VDD_10
CK0*
DQ33
VSS_26
VDD_16
TEST
DQ32
DQ34
VSS_31
DQS4
DQS4*
VSS_28
DQ35
DQ41
VSS_33
VSS_35
DQ40
DM5
VSS_38
DQ43
DQ42
VSS_36
DQ48
VSS_43
DQS6*
DQS6
VSS_40
DQ49
DQ50
VSS_45
DQ56
DQ57
VSS_47
DM7
DQ58
VSS_48
DQ59
SA0
VSS_50
A8
A9
A12/BC*
VDD_2
BA2
NC_0
VDD_0
DQ51
VTT_0
SA1
VDDSPD
MTG PIN MTG PIN
KEY
(1 OF 2)
DQ3
VSS_10
VSS_19
DQ9
VSS_8
DQS1*
DQS1
VSS_21
DQ26
CKE0
BA2
A9
A8
VDD_6
VDD_8
CK0*
A10_AP
BA0
SA0
VTT_0
SA1
VDDSPD
VSS_50
VSS_47
DM7
DQ58
DQ59
DQ57
DQ56
VSS_45
DQ51
DQ50
DQS6
VSS_43
DQS6*
VSS_40
DQ49
DQ48
VSS_38
DQ43
DQ42
VSS_36
DM5
VSS_35
DQ41
DQ40
DQ35
DQ34
VSS_31
DQS4
DQS4*
VSS_28
VSS_26
DQ32
DQ33
TEST
VDD_16
S1*
A13
CAS*
VDD_14
WE*
VDD_12
VDD_10
CK0
A1
A3
A5
VDD_4
A12/BC*
VDD_2
VDD_0
NC_0
DQ11
DQ16
VSS_12
DQ10
DQ8
DM0
VSS_4
VSS_6
DQ2
VREFDQ
DQ0
VSS_3
DQ1
VSS_1
SCL
SDA
VTT_1
VSS_51
VSS_49
DQ63
DQS7
DQS7*
EVENT*
DQ62
DM6
DQ60
VSS_46
VSS_41
DQ53
DQ55
VSS_44
DQ54
VSS_42
DQ61
DQ52
DQ44
VSS_34
DQS5*
VSS_37
DQ46
DQ47
VSS_39
DQ45
DQS5
VSS_32
DM4
VSS_27
VSS_29
DQ36
VREFCA
VDD_17
DQ37
DQ38
DQ39
VSS_30
BA1
NC_1
VDD_13
VDD_11
VDD_15
ODT0
CK1
A0
A2
A6
A4
A7
A11
VDD_9
VDD_7
VDD_5
VDD_3
A15
A14
CKE1
VDD_1
DM1
DQ15
DQ14
DQ13
VSS_11
VSS_9
RESET*
VSS_13
DQ20
DQ12
DQ7
DQ6
DQ5
DQ4
VSS_7
DQS0*
VSS_2
VSS_0
DQS0
VSS_5
DQ21
VSS_15
DM2
VSS_16
DQ22
VSS_18
DQ23
DQ28
VSS_20
DQ29
DQS3
VSS_23
DQS3*
DQ30
DQ31
VSS_25
VSS_14
DQ17
DQS2*
VSS_17
DQS2
DQ18
DQ19
DQ25
DQ24
DM3
VSS_22
DQ27
VSS_24
CK1*
RAS*
S0*
ODT1
VSS_33
VSS_48
KEY
(2 OF 2)
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
(NONE)
BOM options provided by this page:
- =PP0V75_S0_MEM_VTT_A
- =PPSPD_S0_MEM_A (2.5 - 3.3V)
Power aliases required by this page:
DIMM2 SPD ADDR=0XA2(WR)/0XA3(RD)
- ALL DQ, DQS, DM SIGNALS;TO FACILITATE BITSWAPS WITH ALIASES
- =I2C_SODIMMA_SCL
Page Notes
- =PP1V5_S0_MEM_A
- =PP1V5_S3_MEM_A
- =I2C_SODIMMA_SDA
Signal aliases required by this page:
DIMM0 SPD ADDR=0XA0(WR)/0XA1(RD)
DIMM 2
DIMM 0
31 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
=MEM_A_DQ<38>
=MEM_A_DQ<39>
=MEM_A_DQ<8>
=MEM_A_DQ<1>
=MEM_A_DQS_P<6>
=MEM_A_DQ<58>
=PPSPD_S0_MEM_A
MEM_DIMM2_SA<1>
=PP0V75_S0_MEM_VTT_A
=MEM_A_DM<1>
=MEM_A_DQ<14>
=MEM_A_DQ<21>
=MEM_A_DQ<20>
=MEM_A_DQ<13>
=MEM_A_DQ<61>
=MEM_A_DQS_P<7>
=MEM_A_DQ<63>
MEM_EVENT_L
=I2C_SODIMMA_SDA
=I2C_SODIMMA_SCL
=MEM_A_DQ<42>
=PP1V5_S3_MEM_A
=MEM_A_DQ<29>
MEM_A_A<4>
=PPSPD_S0_MEM_A
MEM_A_A<0>
=MEM_A_CLK_P<3>
=MEM_A_DM<6>
=MEM_A_DQ<36>
=MEM_A_DQS_N<6>
=MEM_A_DQ<49>
=MEM_A_DQ<48>
=MEM_A_DQ<43>
=MEM_A_DQ<17>
=MEM_A_DQS_N<2>
MEM_A_CKE<1>
=PP1V5_S3_MEM_A
MEM_A_A<15>
=MEM_A_DQ<0>
=MEM_A_DM<0>
=MEM_A_DQ<2>
=MEM_A_DQ<3>
=MEM_A_DQ<9>
=MEM_A_DM<2>
=MEM_A_DQ<12>
=MEM_A_DQ<5>
=PP1V5_S3_MEM_A
MEM_A_A<6>
MEM_A_A<4>
MEM_A_A<14>
=MEM_A_DQS_P<3>
MEM_A_A<5>
=MEM_A_DQS_P<2>
=MEM_A_DQ<19>
=MEM_A_DQ<18>
=MEM_A_DQS_N<0>
=MEM_A_DQ<4>
PP0V75_S3_MEM_VREFDQ_A
=MEM_A_CLK_P<0>
MEM_A_A<10>
MEM_A_BA<0>
=MEM_A_CLK_N<0>
MEM_A_CKE<0>
=MEM_A_DQ<27>
=MEM_A_DQ<25>
=MEM_A_DQ<16>
=MEM_A_DQS_P<1>
MEM_DIMM0_SA<0>
=PPSPD_S0_MEM_A
=PP0V75_S0_MEM_VTT_A
PP0V75_S3_MEM_VREFDQ_A
PP0V75_S3_MEM_VREFCA_A
MEM_DIMM0_SA<1>
MEM_DIMM2_SA<0>
MEM_DIMM2_SA<1>
=PPSPD_S0_MEM_A
MEM_DIMM0_SA<1>
=PP0V75_S0_MEM_VTT_A
=MEM_A_DQ<51>
MEM_A_BA<2>
MEM_A_A<12>
MEM_DIMM0_SA<0>
=MEM_A_DQ<59>
=MEM_A_DQ<58>
=MEM_A_DM<7>
=MEM_A_DQ<57>
=MEM_A_DQ<56>
=MEM_A_DQ<50>
=MEM_A_DQ<49>
=MEM_A_DQS_P<6>
=MEM_A_DQ<48>
=MEM_A_DQ<43>
=MEM_A_DM<5>
=MEM_A_DQ<40>
=MEM_A_DQ<41>
=MEM_A_DQ<35>
=MEM_A_DQS_N<4>
=MEM_A_DQS_P<4>
=MEM_A_DQ<34>
=MEM_A_DQ<32>
=MEM_A_DQ<33>
=MEM_A_DM<3>
=MEM_A_DQ<26>
=MEM_A_DQ<24>
=MEM_A_DQ<10>
=MEM_A_DQ<11>
=MEM_A_DQS_N<1>
=MEM_A_DQ<62>
=MEM_A_DQS_N<7>
=PP0V75_S0_MEM_VTT_A
=MEM_A_DM<6>
=MEM_A_DQ<53>
=MEM_A_DQ<60>
=MEM_A_DQ<52>
=MEM_A_DQ<45>
=MEM_A_DQS_N<5>
=MEM_A_DQS_P<5>
=MEM_A_DQ<46>
=MEM_A_DQ<44>
=MEM_A_DQ<47>
=MEM_A_DM<4>
PP0V75_S3_MEM_VREFCA_A
=MEM_A_DQ<36>
=MEM_A_DQ<37>
=MEM_A_DQ<38>
=MEM_A_DQ<39>
MEM_A_CS_L<0>
MEM_A_BA<1>
=MEM_A_CLK_N<1>
MEM_A_RAS_L
MEM_A_ODT<0>
MEM_A_ODT<1>
=MEM_A_CLK_P<1>
=MEM_A_DQ<31>
=MEM_A_DQ<30>
=MEM_A_DQS_P<3>
=MEM_A_DQ<29>
=MEM_A_DQS_N<3>
=MEM_A_DQ<28>
=MEM_A_DQ<23>
=MEM_A_DQ<22>
MEM_RESET_L
=MEM_A_DQ<15>
=MEM_A_DQ<7>
=MEM_A_DQ<6>
=MEM_A_DQS_P<0>
=MEM_A_DQ<55>
=MEM_A_DQ<54>
MEM_A_WE_L
MEM_A_CAS_L
MEM_A_A<13>
MEM_A_CS_L<1>
MEM_A_ODT<3>
MEM_A_CS_L<2>
MEM_A_RAS_L
=MEM_A_CLK_N<3>
=MEM_A_DQ<27>
=MEM_A_DM<3>
=MEM_A_DQ<24>
=MEM_A_DQ<25>
=MEM_A_DQ<19>
=MEM_A_DQ<18>
=MEM_A_DQS_P<2>
=MEM_A_DQS_N<2>
=MEM_A_DQ<17>
=MEM_A_DQ<31>
=MEM_A_DQ<30>
=MEM_A_DQS_N<3>
=MEM_A_DQ<28>
=MEM_A_DQ<23>
=MEM_A_DQ<22>
=MEM_A_DM<2>
=MEM_A_DQ<21>
=MEM_A_DQS_P<0>
=MEM_A_DQS_N<0>
=MEM_A_DQ<4>
=MEM_A_DQ<5>
=MEM_A_DQ<6>
=MEM_A_DQ<7>
=MEM_A_DQ<12>
=MEM_A_DQ<20>
MEM_RESET_L
=MEM_A_DQ<13>
=MEM_A_DQ<14>
=MEM_A_DQ<15>
=MEM_A_DM<1>
MEM_A_CKE<3>
MEM_A_A<14>
MEM_A_A<15>
MEM_A_A<11>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<2>
MEM_A_ODT<2>
MEM_A_BA<1>
=MEM_A_DQ<37>
PP0V75_S3_MEM_VREFCA_A
=MEM_A_DM<4>
=MEM_A_DQS_P<5>
=MEM_A_DQ<45>
=MEM_A_DQ<47>
=MEM_A_DQ<46>
=MEM_A_DQS_N<5>
=MEM_A_DQ<44>
=MEM_A_DQ<52>
=MEM_A_DQ<61>
=MEM_A_DQ<54>
=MEM_A_DQ<55>
=MEM_A_DQ<53>
=MEM_A_DQ<60>
=MEM_A_DQ<62>
MEM_EVENT_L
=MEM_A_DQS_N<7>
=MEM_A_DQS_P<7>
=MEM_A_DQ<63>
=PP0V75_S0_MEM_VTT_A
=I2C_SODIMMA_SDA
=I2C_SODIMMA_SCL
=MEM_A_DQ<1>
=MEM_A_DQ<0>
PP0V75_S3_MEM_VREFDQ_A
=MEM_A_DQ<2>
=MEM_A_DM<0>
=MEM_A_DQ<8>
=MEM_A_DQ<10>
=MEM_A_DQ<16>
=MEM_A_DQ<11>
MEM_A_A<12>
MEM_A_A<5>
MEM_A_A<3>
MEM_A_A<1>
=MEM_A_CLK_P<2>
MEM_A_WE_L
MEM_A_CAS_L
MEM_A_A<13>
MEM_A_CS_L<3>
=MEM_A_DQ<33>
=MEM_A_DQ<32>
=MEM_A_DQS_N<4>
=MEM_A_DQS_P<4>
=MEM_A_DQ<34>
=MEM_A_DQ<35>
=MEM_A_DQ<40>
=MEM_A_DQ<41>
=MEM_A_DM<5>
=MEM_A_DQ<42>
=MEM_A_DQS_N<6>
=MEM_A_DQ<50>
=MEM_A_DQ<51>
=MEM_A_DQ<56>
=MEM_A_DQ<57>
=MEM_A_DQ<59>
=MEM_A_DM<7>
MEM_DIMM2_SA<0>
MEM_A_BA<0>
MEM_A_A<10>
=MEM_A_CLK_N<2>
=PP1V5_S3_MEM_A
MEM_A_A<8>
MEM_A_A<9>
MEM_A_BA<2>
MEM_A_CKE<2>
=MEM_A_DQ<26>
=MEM_A_DQS_P<1>
=MEM_A_DQS_N<1>
=MEM_A_DQ<9>
=MEM_A_DQ<3>
MEM_A_A<11>
MEM_A_A<7>
MEM_A_A<2>
MEM_A_A<0>MEM_A_A<1>
MEM_A_A<3>
MEM_A_A<8>
MEM_A_A<9>
DDR3 SO-DIMMs 0 & 2SYNC_DATE=07/01/2009SYNC_MASTER=K60_SIJI
F-RT-TH
DDR3-SODIMM-DUALCRITICAL
J3100
98B
107B
84B83B
119B
80B
78B
97B
96B95B
92B91B
90B
86B
89B
85B
109B
108B
79B
115B
101B
103B
102B
104B
73B 74B
11B
28B
46B
63B
136B
153B
170B
187B
5B
33B
35B
22B
24B
34B
36B
39B
41B
51B
53B
7B
40B
42B
50B
52B
57B
59B
67B
69B
56B
58B
15B
68B
70B
129B
131B
141B
143B
130B
132B
140B
142B
17B
147B
149B
157B
159B
146B
148B
158B
160B
163B
165B
4B
175B
177B
164B
166B
174B
176B
181B
183B
191B
193B
6B
180B
182B
192B
194B
16B
18B
21B
23B
12B
10B
29B
27B
47B
45B
64B
62B
137B
135B
154B
152B
171B
169B
188B
186B
198B
77B
122B
116B
120B
110B
30B
114B
121B
197B
201B 202B
200B
125B
75B
105B 106B
111B 112B
117B 118B
123B 124B
76B
81B 82B
87B 88B
93B 94B
99B 100B
199B
126B
1B 2B
31B 32B
37B 38B
43B 44B
48B
49B
54B
55B
3B
60B
61B
65B 66B
71B 72B
127B 128B
133B 134B
8B
138B
139B
144B
145B
150B
151B
155B 156B
161B 162B
9B
167B 168B
172B
173B
178B
179B
184B
185B
189B 190B
13B
195B 196B
14B
19B 20B
25B 26B
203B 204B
113B
F-RT-TH
DDR3-SODIMM-DUAL
CRITICALJ3100
98A
107A
84A83A
119A
80A
78A
97A
96A95A
92A91A
90A
86A
89A
85A
109A
108A
79A
115A
101A
103A
102A
104A
73A 74A
11A
28A
46A
63A
136A
153A
170A
187A
5A
33A
35A
22A
24A
34A
36A
39A
41A
51A
53A
7A
40A
42A
50A
52A
57A
59A
67A
69A
56A
58A
15A
68A
70A
129A
131A
141A
143A
130A
132A
140A
142A
17A
147A
149A
157A
159A
146A
148A
158A
160A
163A
165A
4A
175A
177A
164A
166A
174A
176A
181A
183A
191A
193A
6A
180A
182A
192A
194A
16A
18A
21A
23A
12A
10A
29A
27A
47A
45A
64A
62A
137A
135A
154A
152A
171A
169A
188A
186A
198A
409 410
77A
122A
116A
120A
110A
30A
114A
121A
197A
201A 202A
200A
125A
75A
105A 106A
111A 112A
117A 118A
123A 124A
76A
81A 82A
87A 88A
93A 94A
99A 100A
199A
126A
1A 2A
31A 32A
37A 38A
43A 44A
48A
49A
54A
55A
3A
60A
61A
65A 66A
71A 72A
127A 128A
133A 134A
8A
138A
139A
144A
145A
150A
151A
155A 156A
161A 162A
9A
167A 168A
172A
173A
178A
179A
184A
185A
189A 190A
13A
195A 196A
14A
19A 20A
25A 26A
203A 204A
113A
10K
402
5%1/16WMF-LF
R31431
2
10K5%
402
1/16WMF-LF
R31421
2
402-LF
6.3VCERM
20%2.2UFC31401
2
5%10K
1/16W
402MF-LF
R31401
2
MF-LF
5%
402
10K
1/16W
R31411
2
6.3V
2.2UF20%
402-LFCERM
C31501
2 CERM402-LF
6.3V
2.2UF20%
C31511
2
402-LF
20%
CERM6.3V
2.2UFC31351
210V20%0.1UF
402CERM
C31361
2
CERM
2.2UF20%6.3V
402-LF
C31301
2
402
10V
0.1UF20%
CERM
C31311
2
32 30
32 30
32 30
32 30
32 30
32 30
46 30 6
30
30 6
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
46 31 30
48 30
48 30
32 30
30 29 28 6
32 30
83 30 12
46 30 6
83 30 12
32
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
83 12
30 29 28 6
83 30 12
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
30 29 28 6
83 30 12
83 30 12
83 30 12
32 30
83 30 12
32 30
32 30
32 30
32 30
32 30
89 30 28
32
83 30 12
83 30 12
32
83 12
32 30
32 30
32 30
32 30
30
46 30 6
30 6
89 30 28
89 30 28
30
30
30
46 30 6
30
30 6
32 30
83 30 12
83 30 12
30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
30 6
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
89 30 28
32 30
32 30
32 30
32 30
83 12
83 30 12
32
83 30 12
83 12
83 12
32
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
91 32 31 30
32 30
32 30
32 30
32 30
32 30
32 30
83 30 12
83 30 12
83 30 12
83 12
83 12
83 12
83 30 12
32
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
91 32 31 30
32 30
32 30
32 30
32 30
83 12
83 30 12
83 30 12
83 30 12
83 30 12
83 30 12
83 30 12
83 12
83 30 12
32 30
89 30 28
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
46 31 30
32 30
32 30
32 30
30 6
48 30
48 30
32 30
32 30
89 30 28
32 30
32 30
32 30
32 30
32 30
32 30
83 30 12
83 30 12
83 30 12
83 30 12
32
83 30 12
83 30 12
83 30 12
83 12
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
32 30
30
83 30 12
83 30 12
32
30 29 28 6
83 30 12
83 30 12
83 30 12
83 12
32 30
32 30
32 30
32 30
32 30
83 30 12
83 30 12
83 30 12
83 30 12 83 30 12
83 30 12
83 30 12
83 30 12
S1*
A13
VDD_14
CAS*
VDD_12
BA0
A10_AP
WE*
A3
DQ54
DQ55
VSS_44
VSS_0
VSS_2
VSS_5
DQS0
DQS0*
DQ5
DQ4
DQ6
DQ7
VREFDQ
VSS_1
VSS_3
DQ0
DQ1
DM0
VSS_4
VSS_7
DQ12
DQ20
VSS_13
DQ15
DQ14
VSS_11
RESET*
VSS_9
DQ13
DM1
DQ21
VSS_15
DQ22
VSS_16
VSS_18
DQ23
DQ28
DQS3*
VSS_20
DQ29
DM2
VSS_23
DQS3
DQ30
DQ31
VSS_25
VDD_1
CKE1
A15
A14
VDD_3
VDD_9
VDD_5
VDD_7
A7
A11
A4
A6
A2
A0
CK1
NC_1
ODT1
VDD_15
ODT0
VDD_13
RAS*
VDD_11
CK1*
BA1
S0*
DQ39
DQ38
VSS_30
VSS_29
DQ37
DQ36
VSS_27
VREFCA
VDD_17
DM4
VSS_32
DQ47
DQ44
DQ46
VSS_37
DQS5
DQS5*
VSS_39
VSS_34
DQ45
DQ52
VSS_46
DQ61
DQ60
VSS_42
VSS_41
DQ53
DM6
VTT_1
DQS7*
DQS7
EVENT*
VSS_51
DQ63
DQ62
VSS_49
SDA
SCL
DQ2
DQ3
VSS_6
DQ8
DQ9
VSS_8
DQS1*
DQS1
VSS_10
DQ16
VSS_12
DQ11
DQ10
DQ17
DQ18
DQS2
VSS_17
DQS2*
VSS_14
VSS_21
DQ24
DQ25
DQ19
VSS_19
VSS_24
DQ27
DQ26
DM3
VSS_22
CKE0
A5
VDD_4
CK0
VDD_8
A1
VDD_6
VDD_10
CK0*
DQ33
VSS_26
VDD_16
TEST
DQ32
DQ34
VSS_31
DQS4
DQS4*
VSS_28
DQ35
DQ41
VSS_33
VSS_35
DQ40
DM5
VSS_38
DQ43
DQ42
VSS_36
DQ48
VSS_43
DQS6*
DQS6
VSS_40
DQ49
DQ50
VSS_45
DQ56
DQ57
VSS_47
DM7
DQ58
VSS_48
DQ59
SA0
VSS_50
A8
A9
A12/BC*
VDD_2
BA2
NC_0
VDD_0
DQ51
VTT_0
SA1
VDDSPD
MTG PIN MTG PIN
KEY
(1 OF 2)
DQ3
VSS_10
VSS_19
DQ9
VSS_8
DQS1*
DQS1
VSS_21
DQ26
CKE0
BA2
A9
A8
VDD_6
VDD_8
CK0*
A10_AP
BA0
SA0
VTT_0
SA1
VDDSPD
VSS_50
VSS_47
DM7
DQ58
DQ59
DQ57
DQ56
VSS_45
DQ51
DQ50
DQS6
VSS_43
DQS6*
VSS_40
DQ49
DQ48
VSS_38
DQ43
DQ42
VSS_36
DM5
VSS_35
DQ41
DQ40
DQ35
DQ34
VSS_31
DQS4
DQS4*
VSS_28
VSS_26
DQ32
DQ33
TEST
VDD_16
S1*
A13
CAS*
VDD_14
WE*
VDD_12
VDD_10
CK0
A1
A3
A5
VDD_4
A12/BC*
VDD_2
VDD_0
NC_0
DQ11
DQ16
VSS_12
DQ10
DQ8
DM0
VSS_4
VSS_6
DQ2
VREFDQ
DQ0
VSS_3
DQ1
VSS_1
SCL
SDA
VTT_1
VSS_51
VSS_49
DQ63
DQS7
DQS7*
EVENT*
DQ62
DM6
DQ60
VSS_46
VSS_41
DQ53
DQ55
VSS_44
DQ54
VSS_42
DQ61
DQ52
DQ44
VSS_34
DQS5*
VSS_37
DQ46
DQ47
VSS_39
DQ45
DQS5
VSS_32
DM4
VSS_27
VSS_29
DQ36
VREFCA
VDD_17
DQ37
DQ38
DQ39
VSS_30
BA1
NC_1
VDD_13
VDD_11
VDD_15
ODT0
CK1
A0
A2
A6
A4
A7
A11
VDD_9
VDD_7
VDD_5
VDD_3
A15
A14
CKE1
VDD_1
DM1
DQ15
DQ14
DQ13
VSS_11
VSS_9
RESET*
VSS_13
DQ20
DQ12
DQ7
DQ6
DQ5
DQ4
VSS_7
DQS0*
VSS_2
VSS_0
DQS0
VSS_5
DQ21
VSS_15
DM2
VSS_16
DQ22
VSS_18
DQ23
DQ28
VSS_20
DQ29
DQS3
VSS_23
DQS3*
DQ30
DQ31
VSS_25
VSS_14
DQ17
DQS2*
VSS_17
DQS2
DQ18
DQ19
DQ25
DQ24
DM3
VSS_22
DQ27
VSS_24
CK1*
RAS*
S0*
ODT1
VSS_33
VSS_48
KEY
(2 OF 2)
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
DIMM1 SPD ADDR=0XA4(WR)/0XA5(RD)
DIMM 3
DIMM 1
DIMM3 SPD ADDR=0XA6(WR)/0XA7(RD)
BOM options provided by this page:
- =I2C_SODIMMB_SDA
- =PPSPD_S0_MEM_B (2.5 - 3.3V)
- =PP0V75_S0_MEM_VTT_B
- =PP1V5_S3_MEM_B
- =PP1V5_S0_MEM_B
Page NotesPower aliases required by this page:
(NONE)
- ALL DQ, DQS, DM SIGNALS;TO FACILITATE BITSWAPS WITH ALIASES
Signal aliases required by this page:
- =I2C_SODIMMB_SCL
32 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
MEM_B_CAS_L
MEM_B_A<13>
=MEM_B_DQ<61>
=MEM_B_DQ<32>
PP0V75_S3_MEM_VREFCA_B
=MEM_B_DQ<31>
=MEM_B_DQ<13>
MEM_DIMM1_SA<0>
MEM_DIMM1_SA<1>
MEM_B_WE_L
=MEM_B_DQ<27>
MEM_B_CKE<0>
MEM_B_A<9>
MEM_B_A<12>
MEM_B_BA<2>
=MEM_B_DQ<25>
=PPSPD_S0_MEM_B
=PP0V75_S0_MEM_VTT_B
PP0V75_S3_MEM_VREFDQ_B
PP0V75_S3_MEM_VREFCA_B
=PPSPD_S0_MEM_B =PPSPD_S0_MEM_B
MEM_DIMM3_SA<1>
MEM_DIMM3_SA<0>
=PPSPD_S0_MEM_B
MEM_DIMM1_SA<1>
=PP0V75_S0_MEM_VTT_B
=MEM_B_DQ<51>
MEM_DIMM1_SA<0>
=MEM_B_DQ<59>
=MEM_B_DQ<58>
=MEM_B_DM<7>
=MEM_B_DQ<57>
=MEM_B_DQ<56>
=MEM_B_DQ<50>
=MEM_B_DQ<49>
=MEM_B_DQS_P<6>
=MEM_B_DQS_N<6>
=MEM_B_DQ<48>
=MEM_B_DQ<42>
=MEM_B_DQ<43>
=MEM_B_DM<5>
=MEM_B_DQ<40>
=MEM_B_DQ<41>
=MEM_B_DQ<35>
=MEM_B_DQS_N<4>
=MEM_B_DQS_P<4>
=MEM_B_DQ<34>
=MEM_B_DQ<33>
=MEM_B_CLK_P<0>
=MEM_B_DM<3>
=MEM_B_DQ<26>
=MEM_B_DQ<19>
=MEM_B_DQ<24>
=MEM_B_DQS_N<2>
=MEM_B_DQS_P<2>
=MEM_B_DQ<18>
=MEM_B_DQ<17>
=MEM_B_DQ<10>
=MEM_B_DQ<11>
=MEM_B_DQ<16>
=MEM_B_DQS_P<1>
=MEM_B_DQS_N<1>
=MEM_B_DQ<9>
=MEM_B_DQ<8>
=MEM_B_DQ<3>
=MEM_B_DQ<2>
=I2C_SODIMMB_SCL
=I2C_SODIMMB_SDA
=MEM_B_DQ<62>
=MEM_B_DQ<63>
MEM_EVENT_L
=MEM_B_DQS_P<7>
=MEM_B_DQS_N<7>
=PP0V75_S0_MEM_VTT_B
=MEM_B_DM<6>
=MEM_B_DQ<53>
=MEM_B_DQ<60>
=MEM_B_DQ<52>
=MEM_B_DQ<45>
=MEM_B_DQS_N<5>
=MEM_B_DQS_P<5>
=MEM_B_DQ<46>
=MEM_B_DQ<44>
=MEM_B_DQ<47>
=MEM_B_DM<4>
=MEM_B_DQ<36>
=MEM_B_DQ<37>
=MEM_B_DQ<38>
=MEM_B_DQ<39>
MEM_B_CS_L<0>
MEM_B_BA<1>
=MEM_B_CLK_N<1>
MEM_B_RAS_L
MEM_B_ODT<0>
MEM_B_ODT<1>
=MEM_B_CLK_P<1>
MEM_B_A<0>
MEM_B_A<2>
MEM_B_A<11>
MEM_B_CKE<1>
=MEM_B_DQ<30>
=MEM_B_DQS_P<3>
=MEM_B_DM<2>
=MEM_B_DQ<29>
=MEM_B_DQ<28>
=MEM_B_DQ<23>
=MEM_B_DQ<21>
=MEM_B_DM<1>
MEM_RESET_L
=MEM_B_DQ<14>
=MEM_B_DQ<15>
=MEM_B_DQ<20>
=MEM_B_DM<0>
=MEM_B_DQ<1>
=MEM_B_DQ<0>
PP0V75_S3_MEM_VREFDQ_B
=MEM_B_DQ<7>
=MEM_B_DQ<6>
=MEM_B_DQ<4>
=MEM_B_DQ<5>
=MEM_B_DQS_N<0>
=MEM_B_DQS_P<0>
=MEM_B_DQ<55>
=MEM_B_DQ<54>
MEM_B_A<3>
MEM_B_CS_L<1>
=MEM_B_DQ<27>
=MEM_B_DM<3>
=MEM_B_DQ<24>
=MEM_B_DQ<25>
=MEM_B_DQ<19>
=MEM_B_DQ<18>
=MEM_B_DQS_P<2>
=MEM_B_DQS_N<2>
=MEM_B_DQ<17>
=MEM_B_DQ<31>
=MEM_B_DQ<30>
=MEM_B_DQS_N<3>
=MEM_B_DQS_P<3>
=MEM_B_DQ<29>
=MEM_B_DQ<28>
=MEM_B_DQ<23>
=MEM_B_DQ<22>
=MEM_B_DM<2>
=MEM_B_DQ<21>
=MEM_B_DQS_P<0>
=MEM_B_DQS_N<0>
=MEM_B_DQ<4>
=MEM_B_DQ<5>
=MEM_B_DQ<6>
=MEM_B_DQ<7>
=MEM_B_DQ<12>
=MEM_B_DQ<20>
MEM_RESET_L
=MEM_B_DQ<13>
=MEM_B_DQ<14>
=MEM_B_DQ<15>
=MEM_B_DM<1>
MEM_B_CKE<3>
MEM_B_A<14>
MEM_B_A<15>
MEM_B_A<11>
MEM_B_A<7>
MEM_B_A<4>
MEM_B_A<6>
MEM_B_A<2>
=MEM_B_DQ<39>
=MEM_B_DQ<38>
=MEM_B_DQ<37>
PP0V75_S3_MEM_VREFCA_B
=MEM_B_DQ<36>
=MEM_B_DM<4>
=MEM_B_DQS_P<5>
=MEM_B_DQ<45>
=MEM_B_DQ<47>
=MEM_B_DQ<46>
=MEM_B_DQS_N<5>
=MEM_B_DQ<44>
=MEM_B_DQ<52>
=MEM_B_DQ<61>
=MEM_B_DQ<54>
=MEM_B_DQ<55>
=MEM_B_DQ<53>
=MEM_B_DQ<60>
=MEM_B_DM<6>
=MEM_B_DQ<62>
MEM_EVENT_L
=MEM_B_DQS_N<7>
=MEM_B_DQS_P<7>
=MEM_B_DQ<63>
=PP0V75_S0_MEM_VTT_B
=I2C_SODIMMB_SDA
=I2C_SODIMMB_SCL
=MEM_B_DQ<1>
=MEM_B_DQ<0>
PP0V75_S3_MEM_VREFDQ_B
=MEM_B_DQ<2>
=MEM_B_DM<0>
=MEM_B_DQ<8>
=MEM_B_DQ<10>
=MEM_B_DQ<16>
=MEM_B_DQ<11>
MEM_B_A<12>
MEM_B_A<5>
MEM_B_A<3>
MEM_B_A<1>
=MEM_B_CLK_P<2>
MEM_B_WE_L
MEM_B_CAS_L
MEM_B_A<13>
MEM_B_CS_L<3>
=MEM_B_DQ<33>
=MEM_B_DQ<32>
=MEM_B_DQS_N<4>
=MEM_B_DQS_P<4>
=MEM_B_DQ<34>
=MEM_B_DQ<35>
=MEM_B_DQ<40>
=MEM_B_DQ<41>
=MEM_B_DM<5>
=MEM_B_DQ<42>
=MEM_B_DQ<43>
=MEM_B_DQ<48>
=MEM_B_DQ<49>
=MEM_B_DQS_N<6>
=MEM_B_DQS_P<6>
=MEM_B_DQ<50>
=MEM_B_DQ<51>
=MEM_B_DQ<56>
=MEM_B_DQ<57>
=MEM_B_DQ<59>
=MEM_B_DQ<58>
=MEM_B_DM<7>
=PPSPD_S0_MEM_B
MEM_DIMM3_SA<1>
=PP0V75_S0_MEM_VTT_B
MEM_DIMM3_SA<0>
MEM_B_BA<0>
MEM_B_A<10>
=MEM_B_CLK_N<2>
=PP1V5_S3_MEM_B
MEM_B_A<8>
MEM_B_A<9>
MEM_B_BA<2>
MEM_B_CKE<2>
=MEM_B_DQ<26>
=MEM_B_DQS_P<1>
=MEM_B_DQS_N<1>
=MEM_B_DQ<9>
=MEM_B_DQ<3>
MEM_B_A<0>
=PP1V5_S3_MEM_B
MEM_B_ODT<3>
MEM_B_ODT<2>
MEM_B_CS_L<2>
MEM_B_RAS_L
MEM_B_BA<1>
=MEM_B_CLK_N<3>
=MEM_B_CLK_P<3>
=MEM_B_DQ<12>
=MEM_B_DQ<22>
=MEM_B_DQS_N<3>
=PP1V5_S3_MEM_B
MEM_B_BA<0>
MEM_B_A<10>
=PP1V5_S3_MEM_B
=MEM_B_CLK_N<0>
MEM_B_A<1>
MEM_B_A<5>
MEM_B_A<8>
MEM_B_A<4>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<14>
MEM_B_A<15>
DDR3 SO-DIMM CONNECTOR BSYNC_MASTER=K60_SIJI SYNC_DATE=07/01/2009
F-RT-TH
CRITICAL
DDR3-SODIMM-DUAL
J3200
98B
107B
84B83B
119B
80B
78B
97B
96B95B
92B91B
90B
86B
89B
85B
109B
108B
79B
115B
101B
103B
102B
104B
73B 74B
11B
28B
46B
63B
136B
153B
170B
187B
5B
33B
35B
22B
24B
34B
36B
39B
41B
51B
53B
7B
40B
42B
50B
52B
57B
59B
67B
69B
56B
58B
15B
68B
70B
129B
131B
141B
143B
130B
132B
140B
142B
17B
147B
149B
157B
159B
146B
148B
158B
160B
163B
165B
4B
175B
177B
164B
166B
174B
176B
181B
183B
191B
193B
6B
180B
182B
192B
194B
16B
18B
21B
23B
12B
10B
29B
27B
47B
45B
64B
62B
137B
135B
154B
152B
171B
169B
188B
186B
198B
77B
122B
116B
120B
110B
30B
114B
121B
197B
201B 202B
200B
125B
75B
105B 106B
111B 112B
117B 118B
123B 124B
76B
81B 82B
87B 88B
93B 94B
99B 100B
199B
126B
1B 2B
31B 32B
37B 38B
43B 44B
48B
49B
54B
55B
3B
60B
61B
65B 66B
71B 72B
127B 128B
133B 134B
8B
138B
139B
144B
145B
150B
151B
155B 156B
161B 162B
9B
167B 168B
172B
173B
178B
179B
184B
185B
189B 190B
13B
195B 196B
14B
19B 20B
25B 26B
203B 204B
113B
DDR3-SODIMM-DUAL
F-RT-TH
CRITICALJ3200
98A
107A
84A83A
119A
80A
78A
97A
96A95A
92A91A
90A
86A
89A
85A
109A
108A
79A
115A
101A
103A
102A
104A
73A 74A
11A
28A
46A
63A
136A
153A
170A
187A
5A
33A
35A
22A
24A
34A
36A
39A
41A
51A
53A
7A
40A
42A
50A
52A
57A
59A
67A
69A
56A
58A
15A
68A
70A
129A
131A
141A
143A
130A
132A
140A
142A
17A
147A
149A
157A
159A
146A
148A
158A
160A
163A
165A
4A
175A
177A
164A
166A
174A
176A
181A
183A
191A
193A
6A
180A
182A
192A
194A
16A
18A
21A
23A
12A
10A
29A
27A
47A
45A
64A
62A
137A
135A
154A
152A
171A
169A
188A
186A
198A
409 410
77A
122A
116A
120A
110A
30A
114A
121A
197A
201A 202A
200A
125A
75A
105A 106A
111A 112A
117A 118A
123A 124A
76A
81A 82A
87A 88A
93A 94A
99A 100A
199A
126A
1A 2A
31A 32A
37A 38A
43A 44A
48A
49A
54A
55A
3A
60A
61A
65A 66A
71A 72A
127A 128A
133A 134A
8A
138A
139A
144A
145A
150A
151A
155A 156A
161A 162A
9A
167A 168A
172A
173A
178A
179A
184A
185A
189A 190A
13A
195A 196A
14A
19A 20A
25A 26A
203A 204A
113A
10K
402
5%1/16WMF-LF
R32411
2
MF-LF1/16W
402
5%10KR32401
2
CERM402-LF
6.3V
2.2UF20%
C32401
2
402
5%1/16WMF-LF
10KR32421
2402MF-LF1/16W5%10KR32431
2
CERM402-LF
20%2.2UF
6.3V
C32501
2
2.2UF20%6.3V
402-LFCERM
C32511
2
2.2UF
6.3VCERM
20%
402-LF
C32351
2
20%0.1UF
CERM402
10V
C32361
2
402-LF
6.3V20%2.2UF
CERM
C32301
2
402CERM10V20%0.1UFC32311
2
83 31 12
83 31 12
32 31
32 31
89 31 28
32 31
32 31
31
31
83 31 12
32 31
83 12
83 31 12
83 31 12
83 31 12
32 31
31 6
31 6
89 31 28
89 31 28
31 6 31 6
31
31
31 6
31
31 6
32 31
31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
48 31
48 31
32 31
32 31
46 31 30
32 31
32 31
31 6
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
83 12
83 31 12
32
83 31 12
83 12
83 12
32
83 31 12
83 31 12
83 31 12
83 12
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
91 32 31 30
32 31
32 31
32 31
32 31
32 31
32 31
89 31 28
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
83 31 12
83 12
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
91 32 31 30
32 31
32 31
32 31
32 31
83 12
83 31 12
83 31 12
83 31 12
83 31 12
83 31 12
83 31 12
83 31 12
32 31
32 31
32 31
89 31 28
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
46 31 30
32 31
32 31
32 31
31 6
48 31
48 31
32 31
32 31
89 31 28
32 31
32 31
32 31
32 31
32 31
32 31
83 31 12
83 31 12
83 31 12
83 31 12
32
83 31 12
83 31 12
83 31 12
83 12
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
32 31
31 6
31
31 6
31
83 31 12
83 31 12
32
31 29 28 6
83 31 12
83 31 12
83 31 12
83 12
32 31
32 31
32 31
32 31
32 31
83 31 12
31 29 28 6
83 12
83 12
83 12
83 31 12
83 31 12
32
32
32 31
32 31
32 31
31 29 28 6
83 31 12
83 31 12
31 29 28 6
32
83 31 12
83 31 12
83 31 12
83 31 12
83 31 12
83 31 12
83 31 12
83 31 12
G
D
S
G
D
S
DS
G
G S
D
G
D
SG
D
S
G S
D
PAD
VCC
THRMGND
1RD*
1Q
2SD*
2D
2CP
2RD*
2Q
2Q*
1CP
1D 1Q*
1SD*
G
S D
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
S R CLK D Q QB
H L X X L H
L L X X H H
H H POSEDGE L L H
H H POSEDGE H H L
S3
S0
S0
S5
S0
1.5V 3.3V 1.5V
0 3.3V 0
CPU_RESET_L ISOLATE_L MEM_RESET_L
0 3.3V 0
0 3.3V 0
1.5V 3.3V 1.5V
0 0 1.5V
L H X X H LLFD CANNOT CONTROL THIS SIGNAL DIRECTLY SINCE IT MUST BE HIGH IN SLEEP AND CPU MEM RAILS ARE NOT POWERED IN SLEEP.
DDR3 RESET Support
MEMORY CLOCK ALIASING
CPU CHANNEL B DQS 5 -> DIMM B DQS 2
CPU CHANNEL A DQS 1 -> DIMM A DQS 6
CPU CHANNEL A DQS 0 -> DIMM A DQS 7
CPU CHANNEL B DQS 7 -> DIMM B DQS 0
CPU CHANNEL B DQS 4 -> DIMM B DQS 3
CPU CHANNEL B DQS 3 -> DIMM B DQS 4
CPU CHANNEL A DQS 7 -> DIMM A DQS 0
CPU CHANNEL A DQS 6 -> DIMM A DQS 1
CPU CHANNEL A DQS 4 -> DIMM A DQS 3
CPU CHANNEL A DQS 3 -> DIMM A DQS 4
CPU CHANNEL A DQS 2 -> DIMM A DQS 5
CPU CHANNEL B DQS 0 -> DIMM B DQS 7
CPU CHANNEL B DQS 6 -> DIMM B DQS 1
CPU CHANNEL A DQS 5 -> DIMM A DQS 2
CPU CHANNEL B DQS 1 -> DIMM B DQS 6
CPU CHANNEL B DQS 2 -> DIMM B DQS 5
S5
33 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
=MEM_B_DQ<46>
=MEM_B_DQ<43>
=PP3V3_S5_MEMRESET
TP_ISOLATE_CPU
ISOLATE_CPU_MEMHW_L
=MEM_B_DQ<48>
=MEM_B_DQ<50>
PM_SLP_S4_L
PM_SYS_PWRGD
=PP3V3_S3_MEMRESET
PM_SLP_S3_L
CPU_MEM_RESET_L
ISOLATE_CPU_MEM_L
ISOLATE_CPU_MEM_L_R1
PM_SLP_S3_5V_LPM_SLP_S3_5V
=PP5V_S3_MEMRESET
PM_SLP_S3_5V_R2
CPU_MEM_RESET3V3_L
=PP3V3_S5_MEMRESET
=MEM_B_DQ<39>
=MEM_B_DQ<62>
MEM_B_DQ<7>MAKE_BASE=TRUE
=MEM_A_DQ<53>
=MEM_A_DQ<31>
CPU_MEM_RESET_R_L
TP_PM_SLP_S4_D
CPU_MEM_RESET3V3_L
=PP3V3_S3_MEMRESET
PM_SLP_S4_D_L
PM_SLP_S4_D_L
DDRVTT_EN
ALL_SYS_PWRGD_R
SLP_S3_CTL_L
PM_SLP_S3_L
PM_SLP_S3_L
=PP3V3_S5_MEMRESET
ISOLATE_CPU_MEM_5V_LISOLATE_CPU_MEM_L_R1
ISOLATE_CPU_MEM
=PP3V3_S3_MEMRESET =PP5V_S3_MEMRESET
MEM_B_DQ<4>MAKE_BASE=TRUE
MEM_B_DQ<3>MAKE_BASE=TRUE
=MEM_B_DQ<58>
=MEM_B_DQS_N<3>
MEM_RESET_L
=PP1V5_S3_MEMRESET
CPU_MEM_RESET_L
PPVTT_S0_DDR_FET
=MEM_B_DQ<28>
=MEM_B_DQ<24>
=MEM_B_DQ<29>
=MEM_B_DQ<25>
=PP0V75_S0_MEM_VTT_S0FET
=MEM_B_DQ<27>
=MEM_A_DQ<12>
=MEM_A_DQ<3>
=MEM_A_DQ<57>
=MEM_A_DQ<61>
MAKE_BASE=TRUEMEM_A_DQS_N<1>
=MEM_A_DQS_P<6>
=MEM_A_DM<6>
=MEM_A_DQ<49>
MAKE_BASE=TRUEMEM_A_DQS_N<0>
=MEM_A_DM<7>
MEM_B_DQ<18>MAKE_BASE=TRUE
=MEM_A_DQ<58>
=MEM_A_DQ<52>
=MEM_A_DQ<45>
=MEM_A_DQ<44>
MEM_A_DQS_N<3>MAKE_BASE=TRUE
MEM_A_DQ<11>MAKE_BASE=TRUE
=MEM_B_DQ<40>
=MEM_B_DQ<45>
=MEM_B_DM<5>
=MEM_B_DQS_P<5>
=MEM_B_DQ<53>
MAKE_BASE=TRUEMEM_B_DQS_P<0>
MEM_B_DM<6>MAKE_BASE=TRUE
=MEM_A_CLK_N<1>
=MEM_A_CLK_N<2>
MAKE_BASE=TRUEMEM_B_DQS_N<0>
MEM_B_CLK_N<3>MAKE_BASE=TRUE
=MEM_B_CLK_N<3>
MEM_B_CLK_P<3>MAKE_BASE=TRUE
=MEM_B_CLK_P<3>
MEM_B_CLK_N<1>MAKE_BASE=TRUE
=MEM_B_CLK_N<1>
MEM_B_CLK_P<2>MAKE_BASE=TRUE
=MEM_B_CLK_P<2>
MEM_B_CLK_N<2>MAKE_BASE=TRUE
=MEM_B_CLK_N<2>
MEM_B_CLK_P<1>MAKE_BASE=TRUE
=MEM_B_CLK_P<1>MAKE_BASE=TRUE
MEM_B_CLK_N<0> =MEM_B_CLK_N<0>
MEM_A_CLK_N<3>MAKE_BASE=TRUE
=MEM_A_CLK_N<3>
MAKE_BASE=TRUEMEM_B_CLK_P<0> =MEM_B_CLK_P<0>
MEM_A_CLK_N<2>MAKE_BASE=TRUE
MEM_A_CLK_P<3>MAKE_BASE=TRUE
=MEM_A_CLK_P<3>
MEM_A_CLK_P<2>MAKE_BASE=TRUE
=MEM_A_CLK_P<2>
MEM_A_CLK_N<1>MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_A_CLK_P<0> =MEM_A_CLK_P<0>
MEM_A_CLK_N<0>MAKE_BASE=TRUE
=MEM_A_CLK_N<0>
MEM_A_CLK_P<1>MAKE_BASE=TRUE
=MEM_A_CLK_P<1>
=MEM_B_DQ<22>
=MEM_B_DQ<19>
=MEM_B_DQ<23>
=MEM_B_DQ<20>
=MEM_B_DQ<18>
=MEM_B_DM<2>
=MEM_B_DQS_P<2>
=MEM_B_DQS_N<2>MAKE_BASE=TRUE
MEM_B_DQS_N<5>
MAKE_BASE=TRUEMEM_B_DQS_P<5>
MAKE_BASE=TRUEMEM_B_DM<5>
MEM_B_DQ<47>MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_B_DQ<46>
MEM_B_DQ<45>MAKE_BASE=TRUE
MEM_B_DQ<44>MAKE_BASE=TRUE
MEM_B_DQ<43>MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_B_DQ<32>
MEM_B_DQ<41>MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_B_DQ<40> =MEM_B_DQ<16>
MAKE_BASE=TRUEMEM_B_DQ<42>
=MEM_B_DQS_N<1>
=MEM_B_DQS_P<1>
=MEM_B_DM<1>
=MEM_B_DQ<8>
=MEM_B_DQ<14>
=MEM_B_DQ<12>
=MEM_B_DQ<13>
=MEM_B_DQS_N<0>
=MEM_B_DM<0>
=MEM_B_DQ<2>
=MEM_B_DQ<1>
=MEM_B_DQ<3>
=MEM_B_DQ<7>
=MEM_B_DQ<11>
=MEM_B_DQ<21>
=MEM_B_DQ<9>
MAKE_BASE=TRUEMEM_B_DQS_N<7>
MEM_B_DQ<63>MAKE_BASE=TRUE
MEM_B_DQ<61>MAKE_BASE=TRUEMEM_B_DQ<60>MAKE_BASE=TRUE
=MEM_B_DQS_P<0>
=MEM_B_DQ<10>
MAKE_BASE=TRUEMEM_B_DQS_N<6>
MAKE_BASE=TRUEMEM_B_DQ<54>
MAKE_BASE=TRUEMEM_B_DQ<53>
MAKE_BASE=TRUEMEM_B_DQ<52>
MAKE_BASE=TRUEMEM_B_DQ<51>
MEM_B_DQS_P<6>MAKE_BASE=TRUE
=MEM_B_DQ<17>
=MEM_B_DQ<26>
MAKE_BASE=TRUEMEM_B_DQ<49>
MAKE_BASE=TRUEMEM_B_DQ<48>
MEM_B_DQS_P<7>MAKE_BASE=TRUE
MEM_B_DM<7>MAKE_BASE=TRUE
MEM_B_DQ<62>MAKE_BASE=TRUE
=MEM_B_DQ<15>
MAKE_BASE=TRUEMEM_B_DQ<55>
=MEM_A_DQ<13>
=MEM_A_DM<1>
MAKE_BASE=TRUEMEM_B_DQ<50>
MEM_B_DQ<1>MAKE_BASE=TRUE
=MEM_B_DQ<56>
MEM_A_DQ<7>MAKE_BASE=TRUE
=MEM_A_DQ<59>
=MEM_A_DQ<62>
=MEM_A_DQ<56>
=MEM_B_DQ<61>
=MEM_A_DQS_N<7>
MAKE_BASE=TRUEMEM_A_DQ<5>
MAKE_BASE=TRUEMEM_A_DQ<3>
=MEM_A_DQ<51>
=MEM_A_DQ<48>
=MEM_A_DQ<55>
MAKE_BASE=TRUEMEM_B_DQ<20>
=MEM_B_DQ<44>
=MEM_A_DQ<19>
=MEM_A_DQ<18>
=MEM_A_DQ<20>
MAKE_BASE=TRUEMEM_A_DM<3>
MEM_A_DQ<27>MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_A_DQS_N<4>
=MEM_A_DQ<38>
=MEM_A_DQ<32>
=MEM_A_DQ<36>
=MEM_A_DQ<34>
=MEM_A_DQS_P<3>
=MEM_A_DQ<35>
=MEM_A_DQ<33>
=MEM_A_DQ<37>
=MEM_A_DQS_P<4>
=MEM_A_DQS_N<4>
MEM_A_DQ<31>MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_A_DQ<30>
MEM_A_DQ<29>MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_A_DQ<28>
MAKE_BASE=TRUEMEM_A_DQS_P<3>
MEM_A_DQ<21>MAKE_BASE=TRUE
MEM_A_DQ<19>MAKE_BASE=TRUE
MEM_A_DM<2>MAKE_BASE=TRUE
MEM_A_DQS_N<2>MAKE_BASE=TRUE
MEM_A_DQ<18>MAKE_BASE=TRUE
=MEM_A_DQS_P<7>
MAKE_BASE=TRUEMEM_B_DQ<8> =MEM_B_DQ<55>
MEM_B_DQ<14>MAKE_BASE=TRUE
MEM_B_DQ<15>MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_B_DM<1>
=MEM_A_DQS_N<6>
MAKE_BASE=TRUEMEM_A_DQ<0>
MEM_B_DQS_N<2>MAKE_BASE=TRUE
=MEM_A_DQ<63>
MAKE_BASE=TRUEMEM_A_DM<0>
MAKE_BASE=TRUEMEM_A_DQ<4>
MAKE_BASE=TRUEMEM_A_DQ<6>
MAKE_BASE=TRUEMEM_A_DQ<2>
MEM_A_DQ<1>MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_A_DQ<14>
MAKE_BASE=TRUEMEM_A_DQ<13>
MEM_A_DQ<39>MAKE_BASE=TRUE
=MEM_B_DQ<34>
=MEM_B_DM<4>
=MEM_B_DQ<38>
=MEM_B_DQ<35>
=MEM_B_DQ<36>
=MEM_B_DQ<33>
=MEM_B_DM<3>
=MEM_B_DQ<31>
=MEM_B_DQ<30>
=MEM_B_DQ<47>
=MEM_B_DQ<0>
=MEM_B_DQ<4>
=MEM_B_DQ<5>
=MEM_B_DQ<6>
=MEM_B_DM<7>
=MEM_B_DQS_P<7>
=MEM_B_DQS_N<7>
=MEM_A_DM<4>
MAKE_BASE=TRUEMEM_B_DQ<22>
MAKE_BASE=TRUEMEM_B_DQ<19>
=MEM_A_DQ<30>
=MEM_A_DQ<25>
=MEM_A_DQ<29>
=MEM_A_DQS_N<3>
=MEM_A_DM<3>
=MEM_A_DQ<28>
=MEM_A_DQ<27>
=MEM_A_DQ<24>
=MEM_A_DQ<26>
=MEM_A_DQ<17>
=MEM_A_DQ<22>
=MEM_A_DQ<21>
=MEM_A_DQ<23>
=MEM_A_DQ<16>
=MEM_A_DM<2>
=MEM_A_DQS_P<2>
=MEM_A_DQS_N<2>
MAKE_BASE=TRUEMEM_B_DQ<21>
=MEM_A_DQ<42>
=MEM_A_DQ<43>
=MEM_A_DM<5>
=MEM_A_DQ<41>
=MEM_A_DQ<47>
=MEM_A_DQ<46>
=MEM_A_DQ<50>
=MEM_A_DQ<14>
=MEM_A_DQ<10>
=MEM_A_DQS_P<1>
=MEM_A_DQS_N<1>
=MEM_A_DQ<11>
=MEM_A_DQ<9>
=MEM_A_DQ<15>
=MEM_A_DQS_N<0>
=MEM_A_DQ<5>
=MEM_A_DQ<6>
=MEM_A_DQ<4>
=MEM_A_DQ<1>
=MEM_A_DQ<7>
=MEM_A_DQ<0>
=MEM_A_DM<0>
=MEM_A_DQ<2>
MEM_B_DQS_N<1>MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_B_DQ<33>
MEM_B_DM<2>MAKE_BASE=TRUE
MEM_B_DQ<23>MAKE_BASE=TRUE
MEM_B_DQ<12>MAKE_BASE=TRUE
MEM_A_DQS_N<5>MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_A_DQS_P<5>
MAKE_BASE=TRUEMEM_A_DM<5>
MEM_A_DQ<47>MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_A_DQ<45>
MAKE_BASE=TRUEMEM_A_DQ<44>
MEM_A_DQ<51>MAKE_BASE=TRUE
MEM_A_DQ<50>MAKE_BASE=TRUE
MEM_A_DQ<49>MAKE_BASE=TRUE
MEM_A_DQ<54>MAKE_BASE=TRUE
MEM_A_DQ<42>MAKE_BASE=TRUE
MEM_A_DQ<41>MAKE_BASE=TRUE
MEM_B_DQS_N<4>MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_A_DQ<25>
MAKE_BASE=TRUEMEM_B_DM<4>
MEM_A_DQS_P<2>MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_A_DQ<12>
MEM_A_DQ<56>MAKE_BASE=TRUE
MEM_A_DQ<57>MAKE_BASE=TRUE
MEM_A_DQ<58>MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_A_DQ<60>
MEM_A_DQ<53>MAKE_BASE=TRUE
MEM_A_DQ<55>MAKE_BASE=TRUE
MEM_A_DQS_P<6>MAKE_BASE=TRUE
MEM_A_DQS_N<6>MAKE_BASE=TRUE
MEM_A_DQ<33>MAKE_BASE=TRUE
MEM_A_DQ<34>MAKE_BASE=TRUE
MEM_A_DQ<38>MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_B_DQ<56>
MAKE_BASE=TRUEMEM_B_DQ<35>
MAKE_BASE=TRUEMEM_B_DQ<38>
MAKE_BASE=TRUEMEM_B_DQS_P<4>
MAKE_BASE=TRUEMEM_B_DQ<27>
MAKE_BASE=TRUEMEM_B_DQ<30>
MAKE_BASE=TRUEMEM_B_DQS_N<3>
MEM_B_DM<3>MAKE_BASE=TRUE
MEM_B_DQS_P<3>MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_B_DQ<17>
MAKE_BASE=TRUEMEM_B_DQ<37>
MAKE_BASE=TRUEMEM_A_DQ<8>
MEM_B_DQS_P<2>MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_B_DQ<28>
MAKE_BASE=TRUEMEM_B_DQ<39>
MAKE_BASE=TRUEMEM_B_DQ<36>
MEM_B_DQ<58>MAKE_BASE=TRUE
MEM_B_DQ<57>MAKE_BASE=TRUE
MEM_B_DQ<59>MAKE_BASE=TRUE
MEM_A_DQ<52>MAKE_BASE=TRUE
MEM_A_DQ<48>MAKE_BASE=TRUE
MEM_A_DQS_P<7>MAKE_BASE=TRUE
MEM_A_DM<7>MAKE_BASE=TRUE
MEM_A_DQ<15>MAKE_BASE=TRUE
MEM_A_DQ<37>MAKE_BASE=TRUE
MEM_A_DM<6>MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_A_DQ<40>
MAKE_BASE=TRUEMEM_A_DQ<43>
MEM_A_DQ<35>MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_A_DQ<36>
MAKE_BASE=TRUEMEM_A_DM<4>
MAKE_BASE=TRUEMEM_A_DQ<26>
MAKE_BASE=TRUEMEM_A_DQ<23>
MEM_A_DQ<10>MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_A_DQ<24>
MAKE_BASE=TRUEMEM_A_DQ<32>
MAKE_BASE=TRUEMEM_B_DQ<34>
MEM_A_DQ<22>MAKE_BASE=TRUE
MEM_A_DQ<20>MAKE_BASE=TRUE
MEM_A_DQ<16>MAKE_BASE=TRUE
MEM_A_DQ<17>MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_B_DQ<9>
MEM_B_DQ<31>MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_B_DQ<29>
MEM_A_DQS_P<4>MAKE_BASE=TRUE
MEM_A_DQS_P<1>MAKE_BASE=TRUE
MEM_A_DM<1>MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_A_DQS_N<7>
MEM_A_DQ<59>MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_A_DQ<61>
MAKE_BASE=TRUEMEM_A_DQ<62>
MAKE_BASE=TRUEMEM_A_DQ<63>
=MEM_B_DQS_N<5>
=MEM_B_DQ<37>
MAKE_BASE=TRUEMEM_B_DQ<24>
MEM_B_DQ<25>MAKE_BASE=TRUE
MEM_B_DQ<26>MAKE_BASE=TRUE
=MEM_B_DQ<52>
=MEM_B_DM<6>
MAKE_BASE=TRUEMEM_B_DQ<10>
MEM_B_DQ<11>MAKE_BASE=TRUE
MAKE_BASE=TRUEMEM_B_DQ<13>
=MEM_A_DQ<60>
=MEM_A_DQ<54>
=MEM_A_DQ<40>
=MEM_A_DQS_P<5>
=MEM_B_DQ<49>
MEM_A_DQ<9>MAKE_BASE=TRUE
=MEM_A_DQS_N<5>
MAKE_BASE=TRUEMEM_B_DQ<16>
=MEM_B_DQS_N<4>
=MEM_B_DQ<42>
=MEM_B_DQS_P<4>
=MEM_B_DQ<32>
=MEM_B_DQ<60>
=MEM_B_DQ<57>
MEM_A_DQS_P<0>MAKE_BASE=TRUE
=MEM_A_DQ<39>
=MEM_A_DQS_P<0>
=MEM_A_DQ<8>
MEM_A_DQ<46>MAKE_BASE=TRUE
MEM_B_DQ<2>MAKE_BASE=TRUE
MEM_B_DQ<0>MAKE_BASE=TRUE
=MEM_B_DQ<51>
=MEM_B_DQ<54>
=MEM_B_DQ<63>
MEM_B_DQ<6>MAKE_BASE=TRUE
MEM_B_DQS_P<1>MAKE_BASE=TRUE
=MEM_B_DQS_P<6>
PM_SLP_S3_5V
=MEM_B_DQ<41>
=MEM_B_DQS_P<3>
PM_SLP_S3_5V_L
VTT_R
MAKE_BASE=TRUEMEM_B_DM<0>
MAKE_BASE=TRUEMEM_B_DQ<5>
=MEM_B_DQ<59>
=MEM_B_DQS_N<6>
CPU_MEM_RESET3V3
SYNC_MASTER=K60_SIJI
DDR3 SUPPORT AND BITSWAPSSYNC_DATE=07/01/2009
NOSTUFF
402MF-LF
5%
0
1/16W
R33931 2
402
5%
0
1/16WMF-LF
R33941 2
NOSTUFF
0
5%
MF-LF1/16W
402
R33901 2
MF-LF1/16W
0
5%
402
NOSTUFFR33911 2
NOSTUFFMC74VHC1G08SOT23-5-HF
U3390
3
2
1
4
5
CERM
20%10V
0.1UF
402
C3390 1
2
5%
402MF-LF1/16W
100KR33401
2
POWER33FDMC8296Q3375
5
4
1
2
3
MEM_RESET_HW
402
0.1UF20%
CERM10V
C3300 1
2
MEM_RESET_HW
74LVC74ABQDHVQFN
U3300
3
11
2
12
7
5
9
6
8
1
13
4
10
15
14
MF-LF402
5%1/16W
0
NOSTUFFR33861 2
SOT23-HF12N7002Q3380
3
1
2
SOT-3632N7002DW-X-GQ3370
6
2
1
SOT-3632N7002DW-X-GQ3370
3
5
4
20K5%1/16W
402MF-LF
R33871
2MF-LF402
5%20K
1/16W
R33841
2
5%
0
1/16WMF-LF402
R33851 2
SOT23-HF
MEM_RESET_HW
2N3904Q33601
3
2
MEM_RESET_HW
SOT23-HF12N7002Q3350
3
1
2
402MF-LF
NOSTUFF
5%
0
1/16W
R33831 2
MEM_RESET_HW
402
5%
MF-LF1/16W
10KR33801 2
MEM_RESET_HW
10K
MF-LF1/16W
402
5%
R33811
2
MEM_RESET_HW
5%
402
1/16WMF-LF
10K
R33821
2
5%
402MF-LF
10
1/16W
R33881
2
NOSTUFF
402
5%
0
1/16WMF-LF
R33551 2
2N7002SOT23-HF1
Q33043
1
2
MF-LF1/16W
20K
402
5%
R33521
2
2N7002DW-X-GSOT-363
Q3306
3
5
4
402MF-LF
5%20K
1/16W
R33531
2
5%1/16W
20K
402MF-LF
R33511
21/16W5%
402MF-LF
20KR33501
2
SOT-3632N7002DW-X-GQ3306
6
2
1
31
31
32 6
31
31
91 19
91 63 19
32 6
91 63 62 46 37 33 32 19 5
91 32 11
25 21
32
32
32
32 6
32
32 6
31
31
83 12
30
30
32
32 6
32
32
91 70 62
91 63 25 6
91 63 62 46
37
33 32 19 5
91
63 62
46 37 33 32 19 5
32 6
28
32
32 6 32 6
83 12
83 12
31
31
91 31 30
6
91 32 11
6
31
31
31
31
6
31
30
30
30
30
83 12
30
30
30
83 12
30
83 12
30
30
30
30
83 12
83 12
31
31
31
31
31
83 12
83 12
30
30
83 12
83 12 31
83 12 31
83 12 31
83 12 31
83 12 31
83 12 31
83 12 31
83 12 30
83 12 31
83 12
83 12 30
83 12 30
83 12
83 12 30
83 12 30
83 12 30
31
31
31
31
31
31
31
31 83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12 31
83 12
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
83 12
83 12
83 12
83 12
31
31
83 12
83 12
83 12
83 12
83 12
83 12
31
31
83 12
83 12
83 12
83 12
83 12
31
83 12
30
30
83 12
83 12
31
83 12
30
30
30
31
30
83 12
83 12
30
30
30
83 12
31
30
30
30
83 12
83 12
83 12
30
30
30
30
30
30
30
30
30
30
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
30
83 12 31
83 12
83 12
83 12
30
83 12
83 12
30
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
30
83 12
83 12
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
83 12
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
83 12
31
31
83 12
83 12
83 12
31
31
83 12
83 12
83 12
30
30
30
30
31
83 12
30
83 12
31
31
31
31
31
31
83 12
30
30
30
83 12
83 12
83 12
31
31
31
83 12
83 12 31
32
31
31
32
83 12
83 12
31
31
IN
OUT
OUT
IN
IN
OUT
OUT
SYM_VER-1
IN
IN
SYM_VER-2
G
D
S
G S
DS
G
D
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
518S0731
AP POWER ENABLE CIRCUITAP_PWR_ON = S0 || (S3 && AP_EN)
34 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
PP3V3_MINI
PCIE_CLK100M_MINI_CON_P
MINI_CLKREQ_L
AP_PWR_ENABLEAP_PWR_EN_L
PM_SLP_S3_L
AP_PWR_EN
PCIE_WAKE_LMINI_RESET_L
PCIE_MINI_D2R_PPCIE_MINI_D2R_N
PCIE_CLK100M_MINI_N
PCIE_CLK100M_MINI_P
PCIE_MINI_R2D_C_P
PCIE_MINI_R2D_C_N
PCIE_MINI_R2D_PPCIE_MINI_R2D_N
PCIE_MINI_R2D_L_N
PCIE_CLK100M_MINI_CON_N
PCIE_MINI_R2D_L_P
PP3V3_MINI_FILTVOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.5 mm
PP3V3_MINIMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MM
VOLTAGE=3.3V
=PP3V3_S3_MINI
PCI-E Wireless ConnectorSYNC_MASTER=K23_AARON SYNC_DATE=07/16/2009
0
805
1/8WMF-LF
5%
R34661 2
NOSTUFF
10%
0.1UF
X5R16V402
C3462
1 2
NOSTUFF
SOT-6
FDC606P_GQ3401
12
56
3
4
NOSTUFF
0.1UF
X5R402
16V10%
C34611
2
NOSTUFF
10K1/16W
402MF-LF
5%
R34611
2NOSTUFF
MF-LF
5%1/16W
100K
402
R34621 2
NOSTUFF
SOT23-HF12N7002Q3407
3
1
2
NOSTUFF
2N7002DW-X-GSOT-363
Q34036
2
1
PLACEMENT_NOTE=PLACE CLOSE TO J3400.
12-OHM-100MATCM1210-4SM
L3440
1
23
4
20247-916E-01F
CRITICAL
F-ST-SM
J3400
1
10
11
12
13
14
15
16
17
18
2
3
4
5
6
7
8
9
84 18
84 18
PLACEMENT_NOTE=PLACE CLOSE TO J3400.
90-OHM-100MADLP11S
L3430
1 2
34
0402-LF
FERR-120-OHM-1.5AL3400
1 2
84 18
84 18
84 18
84 18
25 18 15
37 19
91 27
16VX5R
PLACEMENT_NOTE=PLACE CLOSE TO U1400.
10%
402
0.1uFC3430
1 2
PLACEMENT_NOTE=PLACE CLOSE TO U1400.
402X5R
10%16V
0.1uFC3431
1 2
10uF6.3VX5R
20%
603
C3402 1
2CERM
0.1uF10V20%
402
C3401 1
210V
0.1uF
402
20%
CERM
C3400 1
2
89 33
91 63 62 46 37 32 19 5
21 15
89 33
6
IN
IN
IN
G
D
SG
D
S
SCL
A2
A1
A0
WP
SDA
GND
VCC
SUSP_IND/LOCAL_PWR/NON_REM0
SDA/SMBDATA/NON_REM1
SCL/SMBCLK/CFG_SEL0
HS_IND/CFG_SEL1
XTAL2
XTAL1/CLKIN
RESET*
TEST
USBUP_DP
USBUP_DM
VBUS_DET
RBIAS
OSC4*
OSC3*
OCS2*
PRTPWR4
OCS1*
PRTPWR3
PRTPWR2
USBDN4_DP/PRT_DIS_P4
PRTPWR1
USBDN4_DM/PRT_DIS_M4
USBDP3_DP/PRT_DIS_P3
USBDN3_DM/PRT_DIS_M3
USBDP2_DPPRT_DIS_P2
USBDP1_DP/PRT_DIS_P1
USBDN2_DM/PRT_DIS_M2
USBDN1_DM/PRT_DIS_M1
VDD33PLL
VDD33CR
VDD33
VDD18
VDD18PLL
THRML_PAD
VDDA33
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
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DRAWING NUMBER SIZE
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SHEET
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Apple Inc.
PAGE
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345678
D
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8 7 5 4 2 1
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)TABLE_5_ITEM
1 1 EEPROM Supported
0 1 SMBUS Slave Config
0 0 All ports are Non removable
0 1 Port1 is non removable
1 0 Port 1 and 2 are non removable
1 1 Port1,2 and 3 are non Removable
NON_REM1 NON_REM0 DESCRIPTION
DEFAULT K23F ==>
BOM TABLE
0 0 Internal Default with Self powered Operation
1 0 Internal Default with Bus powered Operation
SEL1 SEL0 DESCRIPTION
DEFAULT K23F ==>
USB HUB-1
35 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
=PP3V3_S3_USB_HUB
USB_HUB1_TEST
USB_HUB_RESET
PGOOD_P3V3_S3
USB_HUB_RESET_L
USB_HUB_SOFT_RESET_L
=PP3V3_S3_USB_RESET
MIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.5MM
USB_HUB1_VDD1V8
USB_HUB1_SMBCLK
USB_HUB1_SMBDATA
=PP3V3_S3_USB_HUBUSB_HUB1_CFG_SEL1
=PP3V3_S3_USB_HUB
USB_HUB1_LOCAL_PWR
MIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM USB_HUB1_VDDA3V3
MIN_LINE_WIDTH=0.5MM
USB_HUB1_VDD1V8PLLMIN_NECK_WIDTH=0.25MM
USB_HUB1_VDDPLL3V3
MIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM
=PP3V3_S3_USB_HUB
USB_EXTC_OC_L
USB_HUB1_RBIAS
USB_EXTA_OC_L
MIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM
USB_HUB1_VBUS_DET
USB_HUB1_UP_P
USB_HUB1_UP_N
TP_USB_HUB1_OCS2_L
TP_USB_HUB1_PRTPWR4
TP_USB_HUB1_OCS1_L
TP_USB_HUB1_PRTPWR3
TP_USB_HUB1_PRTPWR2
USB_EXTC_P
TP_USB_HUB1_PRTPWR1
USB_EXTC_N
USB_EXTA_P
USB_EXTA_N
USB_IR_P
USB_CAMERA_P
USB_IR_N
USB_CAMERA_N
USB_HUB_RESET_L
=PP3V3_S3_USB_HUB
WP_HUB1
USB_HUB1_XTAL1
USB_HUB1_XTAL2
SYNC_MASTER=K60_AARON SYNC_DATE=07/01/2009
USB HUB 1
CRITICAL2 U3500,U3600SMSC USB2514338S0720
USB2514-AEZG
OMIT
QFN
U3500
25
13
17
19
21
12
16
18
20
35
26
24
22
28
11
37
1
3
6
8
9
2
4
7
30
31
27
14
34
23
15
36
5 10
29
33
32
FERR-120-OHM-1.5A
0402
L3558
1 2
10UF20%6.3V
603X5R
C35441
2
603X5R6.3V20%10UFC35381
2
10%16V
1UF
X5R402
C35271
210%16VX5R402
1UFC35301
2
10K5%
1/16WMF-LF
402
R35011
2
0
402
5%1/16WMF-LF
CRITICAL
R35451 2
402
10K5%1/16WMF-LF
R35671
2402
10K5%1/16WMF-LF
NOSTUFF
R35661
2
10K1/16WMF-LF402
5%
R35651
2
SOIAT24C02B
NOSTUFF
U35141
2
3
4
6
5
8
7
10K5%1/16WMF-LF402
R35811
2402MF-LF1/16W5%10KR35801
2 402
10K5%1/16WMF-LF
R35501
21/16WMF-LF
10K5%
402
R35041
2
NOSTUFF
10K
MF-LF402
1/16W5%
R35941
2
10K5%
1/16WMF-LF
402
R35921
2402MF-LF1/16W
10K5%
R35981
2
0402
FERR-120-OHM-1.5AL3559
1 2
X5R
10UF6.3V
603
20%
C35181
2
CERM-X5R
0.47UF
NOSTUFF
10%
402
6.3V
C35401
2
CERM
100PF5%
402
50V
NOSTUFF
C3541 1
2
SOT-363
2N7002DW-X-GQ3540 6
2
1
20K
1/16W5%
402MF-LF
R35401
2
SOT-3632N7002DW-X-GQ3540
3
5
4
MF-LF
5%1/16W
402
10KR35411
2
402
1/16WMF
CRITICAL
12K
1%
R35001 2
91 35 34
85 20
85 20
402
0.01UF16VCERM
10%
C35261
2 CERM16V
402
10%0.01UFC35291
2
402CERM16V10%0.01UFC35421
2
402CERM16V10%0.01UFC35361
2
0.1UF10%
X7R-CERM402
16V
C35281
2402
10%16VX7R-CERM
0.1UFC35241
2
10%
402
16V
0.1UF
X7R-CERM
C35231
2 16V10%
X7R-CERM402
0.1UFC35251
2
402X7R-CERM16V10%0.1UFC35471
2
0.1UF10%16VX7R-CERM402
C35461
2X7R-CERM402
10%16V
0.1UFC35451
2
0.1UF10%
402X7R-CERM16V
C35391
2
402MF-LF1/16W
5%10K
NOSTUFF
R35971
2
50VCERM
5%
402
100PFC35431
2
402CERM
5%50V
100PFC35371
2
NOSTUFF
MF-LF1/16W5%100K
402
R35991
2
0.1UF10%16V
402X5R
C35341
2
50VCERM
5%
402
18PF
CRITICAL
C35191
2
MF-LF
CRITICAL
1/16W5%
402
1MR35911 2 5%
18PF
CERM50V
402
CRITICAL
C35201
2
CRITICAL
5X3.2X1.4-SM
24.000M-60PPM-16PFY35001 2
35 34 6
91 72
91 35 34
25 20
6
35 34 6
35 34 6
35 34 6
43
85
43
85 43
85 43
85 43
85 43
85 44
85 44
85 44
85 44
35 34 6
85
85
IN
IN
IN
SCL
A2
A1
A0
WP
SDA
GND
VCC
SUSP_IND/LOCAL_PWR/NON_REM0
SDA/SMBDATA/NON_REM1
SCL/SMBCLK/CFG_SEL0
HS_IND/CFG_SEL1
XTAL2
XTAL1/CLKIN
RESET*
TEST
USBUP_DP
USBUP_DM
VBUS_DET
RBIAS
OSC4*
OSC3*
OCS2*
PRTPWR4
OCS1*
PRTPWR3
PRTPWR2
USBDN4_DP/PRT_DIS_P4
PRTPWR1
USBDN4_DM/PRT_DIS_M4
USBDP3_DP/PRT_DIS_P3
USBDN3_DM/PRT_DIS_M3
USBDP2_DPPRT_DIS_P2
USBDP1_DP/PRT_DIS_P1
USBDN2_DM/PRT_DIS_M2
USBDN1_DM/PRT_DIS_M1
VDD33PLL
VDD33CR
VDD33
VDD18
VDD18PLL
THRML_PAD
VDDA33
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
USB HUB-2
36 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
USB_SDCARD_N
USB_HUB2_VDD1V8
MIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM
USB_BT_N
USB_BT_P
USB_EXTD_N
USB_HUB2_VDDPLL3V3
MIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.5MM
=PP3V3_S3_USB_HUB
USB_HUB2_UP_N
USB_HUB2_VDDA3V3MIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM
USB_SDCARD_P
USB_EXTB_N
TP_USB_HUB2_PRTPWR2
TP_USB_HUB2_PRTPWR1
USB_EXTB_P
TP_USB_HUB2_OCS2
TP_USB_HUB2_OCS1
TP_USB_HUB2_PRTPWR4
TP_USB_HUB2_PRTPWR3
USB_HUB2_VDD1V8PLLMIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM
USB_EXTD_P
USB_HUB2_RBIAS
USB_HUB2_UP_P
=PP3V3_S3_USB_HUB
WP_HUB2
=PP3V3_S3_USB_HUB
USB_HUB2_SMBCLK
USB_HUB2_SMBDATA
USB_HUB_RESET_L
USB_HUB2_CFG_SEL1
=PP3V3_S3_USB_HUB
USB_HUB2_LOCAL_PWR
=PP3V3_S3_USB_HUB
USB_HUB2_VBUS_DET
USB_EXTD_OC_L
USB_EXTB_OC_L
USB_HUB2_XTAL1
USB_HUB2_XTAL2
USB HUB 2SYNC_DATE=07/01/2009SYNC_MASTER=K60_AARON
OMIT
QFN
USB2514-AEZGU3600
25
13
17
19
21
12
16
18
20
35
26
24
22
28
11
37
1
3
6
8
9
2
4
7
30
31
27
14
34
23
15
36
5 10
29
33
32
402MF
CRITICAL
1/16W
12K
1%
R36001 2
0402
FERR-120-OHM-1.5AL3658
1 2
20%
603X5R6.3V
10UFC36441
2
603
6.3V
10UF
X5R
20%
C36381
2
1UF
X5R16V
402
10%
C36271
2
1UF10%16VX5R402
C36301
2
1/16W5%
10K
402MF-LF
R36011
2
MF-LF402
5%1/16W
10KR36671
2MF-LF1/16W5%
402
10K
NOSTUFF
R36651
2
10K
402
5%1/16WMF-LF
R36661
2
AT24C02BSOI
NOSTUFF
U36141
2
3
4
6
5
8
7
402
1/16W5%
MF-LF
10KR36811
2
10K
MF-LF
5%1/16W
402
R36801
2MF-LF
10K
1/16W
402
5%
R36821
2
10K
402MF-LF1/16W
5%
R36041
2
5%1/16WMF-LF402
10K
NOSTUFF
R36941
2
1/16W
10K5%
MF-LF402
R36921
2
0402
FERR-120-OHM-1.5AL3629
1 2
5%1/16WMF-LF402
100K
NOSTUFF
R36991
2
402
1/16W5%10K
MF-LF
R36981
2
NOSTUFF
MF-LF402
10K5%
1/16W
R36971
2
20%
603X5R6.3V
10UFC36181
2
91 34
85 20
85 20
0.01UF
402CERM16V10%
C36261
210%0.01UF
402CERM16V
C36291
2
CERM
0.01UF
402
16V10%
C36421
2
CERM16V10%
402
0.01UFC36361
2
16V
402
10%
X7R-CERM
0.1UFC36281
2
0.1UF16V10%
402X7R-CERM
C36241
2
X7R-CERM402
0.1UF10%16V
C36231
2 16VX7R-CERM
0.1UF
402
10%
C36251
2
16V10%0.1UF
402X7R-CERM
C36471
2
0.1UF10%
402X7R-CERM16V
C36461
2
0.1UF10%16V
402X7R-CERM
C36451
2
X7R-CERM16V
402
10%0.1UFC36391
2
50V5%100PF
402CERM
C36431
2
100PF
402CERM
5%50V
C36371
2
402X5R16V10%0.1UFC36341
2
CRITICAL
CERM50V
18PF5%
402
C36191
2
CRITICAL
MF-LF
5%1/16W
402
1MR36911 2
CRITICAL
CERM50V5%
402
18PFC36201
2
CRITICAL
24.000M-60PPM-16PF
5X3.2X1.4-SM
Y3600
1
1 2
85 44
85 44
85 44
85 43
35 34 6
85 44
85 43
85 43
85 43
85
35 34 6
35 34 6
35 34 6
35 34 6
43
43
85
85
OUT
OUT
IN
IN
IN
OUT
IN
IN
AVDDH AVDDL
THRM_PADNC
SPD1000LED*
TRAFFICLED*
SCLK/EECLK
SO/EEDATA
SI
CS*
ENERGY_DET
SMB_CLK
SMB_DATA
VAUX_PRSNT
VMAIN_PRSNT
DC1
TRD3_P
TRD3_N
TRD2_N
TRD2_P
TRD1_P
TRD1_N
TRD0_N
TRD0_P
DC0
RDAC
BIASVDDH
GPHY_PLLVDDL
PCIE_RXD_N
PCIE_RXD_P
PCIE_REFCLK_P
PCIE_REFCLK_N
PCIE_TXD_P
PCIE_TXD_N
PCIE_VDDL
XTALVDDH
XTALO
XTALI
REGOUT12_IO
SUPER_IDDQ
REGCTL12
VDDC
UART_MODE
GPIO_2
GPIO_1/SERIAL_DI
VDDIOVDDC_IO
GPIO_0/SERIAL_DO
LOW_PWR
SPD100LED*
WAKE*
PERST*
CLKREQ*LINKLED*
PCIE_PLLVDDL
NCNC
NC
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
NCNCNC
OUT
OUT
RESET*
CS*
SCK
SOWP*
SI
GND
VCC
OUT
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
Power aliases required by this page:
WAKE#
Phy is powered-down in S3/S5.Must Isolate from PCIE WAKK# if
ST Micro CS logic high; SCLK, SI, SO logic low
Flash Strapping Support
AT45DB011D, AND VICE VERSA
SI PIN OF CAESAR II SHOULD BE CONNECTED TO SO OF
Pullup provisions will be removed in Proto 2
Atmel SO, CS, SCLK logic high; SI logic low
Note: CAESAR II has internal pullups on SPI pins
- PP3V3_ENET
Page Notes
CL = 20PF
197S0167
- =PP1V2_ENET
(CAESAR II)
37 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
ENET_WAKE_L BCM5764M_WAKE_L
ENET_RDAC
PP1V2_ENET_VDDCIO
=PP1V2_ENET
PP3V3_ENET
ENET_MISO
ENET_MOSI
PP3V3_ENET
=PP1V2_ENET
MIN_LINE_WIDTH=0.4MMMIN_NECK_WIDTH=0.2MMVOLTAGE=1.2V
PP1V2_LAN_GPHY_PLLVDDL
PP3V3_ENET
PP3V3_ENET
=PP1V2_ENET
=PP1V2_ENET
PP1V2_LAN_VDDLVOLTAGE=1.2V
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.4MM
PP1V2_LAN_PLL_VDDL MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.4MMVOLTAGE=1.2V
VOLTAGE=3.3VMIN_LINE_WIDTH=0.4MMMIN_NECK_WIDTH=0.2MMPP3V3_LAN_AVDDH
PP1V2_LAN_AVDDLVOLTAGE=1.2VMIN_LINE_WIDTH=0.4MMMIN_NECK_WIDTH=0.2MM=PP1V2_ENET
PCIE_ENET_R2D_C_N
PCIE_ENET_R2D_C_P
PCIE_ENET_D2R_P
PCIE_ENET_D2R_N
PCIE_ENET_R2D_N
PCIE_ENET_R2D_P
PCIE_ENET_D2R_C_N
PCIE_ENET_D2R_C_P
PP3V3_ENET
ENET_CLK25M_XTALI
PP3V3_ENET
=PP3V3_S0_ENET VMAIN_PRSNT
VAUX_PRSNT
ENET_LOW_PWR
PP3V3_ENETUART_MODE
ENET_MDI_P<2>
ENET_MDI_N<1>
ENET_SMB_CLK
ENET_MDI_P<0>
ENET_ENERGY_DET
ENET_LED_ACT_L
ENET_MDI_N<0>
ENET_MDI_P<1>
PP3V3_LAN_BIASVDDH
MIN_NECK_WIDTH=0.2MMVOLTAGE=3.3V
MIN_LINE_WIDTH=0.4MM
ENET_CLK25M_XTALO
ENET_CLKREQ_L
ENET_MISO
ENET_CTRL12
VOLTAGE=1.2VMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.4MM
PP1V2_ENET_VDDCIO
PP3V3_ENET
ENET_LED_LINK1000_L
ENET_SCLK
ENET_LED_LINK10_100_L
ENET_SCLK
ENET_CS
ENET_MDI_N<3>
ENET_MDI_P<3>
ENET_MDI_N<2>
ENET_SMB_DATA
ENET_CS
ENET_MOSI
ENET_LED_LINK_L
MIN_LINE_WIDTH=0.4MM
VOLTAGE=3.3VMIN_NECK_WIDTH=0.2MM
PP3V3_LAN_XTALVDDH
PCIE_CLK100M_ENET_P
LAN_RESET_L
PCIE_CLK100M_ENET_N
ENET_CLK25M_XTAL
ETHERNET (CAESAR II)SYNC_DATE=07/01/2009SYNC_MASTER=K60_AARON
CERM50V5%
402
27PFC3720 1
2
0
1/16W
402
5%
MF-LF
R37231 2
18 15
1/16W5%4.7K
402MF-LF
NOSTUFFR37191
2
5%1/16WMF-LF
4.7K
402
NOSTUFF
R37181
2
X7R-CERM402
0.1UF
16V10%
C37881
2
200
5%
402
1/16WMF-LF
R37041 2
6.3VX5R-CERM
10%
603
4.7UFC37141
2
402
10%0.1UF
X7R-CERM16V
C37151
2
10K5%1/16W
402MF-LF
R37661
2402MF-LF
5%1/16W
10KR37651
2
X5R805
10%10UF
6.3V
C37261
2
603
10%4.7UF
6.3VX5R-CERM
C37271
2
0.1UF
16V10%
402X7R-CERM
C37251
2
SM
CRITICAL
FERR-600-OHM-0.5AL3710
1 2
0.1UF
402X7R-CERM16V10%
C37241
2
X7R-CERM16V
0.1UF10%
402
C37231
2 CRITICAL
FERR-600-OHM-0.5A
SM
L3711
1 2
CRITICAL
SM
FERR-600-OHM-0.5AL3718
1 2
402
10%
X7R-CERM
0.1UF
16V
C37621
2
FERR-600-OHM-0.5A
SM
CRITICALL3703
1 2
4.7UF
X5R-CERM
10%
603
6.3V
C37461
2
10%
X7R-CERM402
16V
0.1UFC37471
2
4.7UF
603X5R-CERM6.3V10%
C37481
2
402
10%0.1UF
X7R-CERM16V
C37491
2
FERR-600-OHM-0.5A
CRITICAL
SM
L3702
1 2
16V10%
402
0.1UF
X7R-CERM
C37521
2
4.7UF
6.3VX5R-CERM603
10%
C37501
2
CRITICAL
FERR-600-OHM-0.5A
SM
L3701
1 2
16V
0.1UF
402
10%
X7R-CERM
C37511
2
X7R-CERM402
10%0.1UF
16V
C37531
2
CRITICAL
SM
FERR-600-OHM-0.5AL3700
1 2
402
10%0.1UF
X7R-CERM16V
C37121
2
402
10%0.1UF
X7R-CERM16V
C37131
2
NOSTUFF
4.7K
1/16WMF-LF
5%
402
R37171
2
5%1/16W
402MF-LF
4.7KR37161
2
1/16W
4.7K
MF-LF
5%
402
NOSTUFF
R37141
2
MF-LF
4.7K
1/16W
402
5%
NOSTUFF
R37151
2
OMIT
AT45DB011DSOIC-8S1
U3701
4
7
3
2 1
8
6
5
36
37
86 38
86 38
86 38
86 38
86 38
86 38
86 38
86 38
89 37 36
6
402
1%
MF-LF1/16W
1.24KR37011 2
NOSTUFF0
1/16W
402
5%
MF-LF
R37001 2
1K
5%1/16WMF-LF402
R37021 2
402
1/16W5%
1K
MF-LF
R37031 2
CRITICAL
QFNBCM5764M
OMIT
U3700
42
48
39
45
51
36
11
62
38
52
59
35
4
7
8
2
3
68
27
30
28
29
32
31
25
26
24
33
10
37
14
18
65
63
58
57
64
67
1
16
69
66
41
40
43
44
47
46
49
50
9
54
13
20
34
60
5 17
55
6 15
19
56
61
53
12
21
22
23
25.0000M
SM-3-LF
CRITICAL
Y37001 2
84 18
84 18
18 15
91 27
86 18
86 18
PLACEMENT_NOTE=PLACE C3718,C3719 CLOSE TO SB
X5R 40216V10%0.1uF
C3719 1 2
0.1uFX5R16V10% 402
C3718 1 2
40216V0.1uF
10% X5R
C3717 1 2
0.1uF10% 16V X5R 402
C3716 1 2
86 18
86 18
CERM402
50V5%27PFC37211
2
37
86
36
37 36
89 37 36
36
36
89 37 36
37 36
89 37 36
89 37 36
37 36
37 36
37 36
86
86
86
86
89 37 36
86
21 15
89 37 36
37
86
36
89 37 36
37
36
37
36
36
36
36
37
86
G
D
S
G
D
S
D
G
S
D
GS
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
ENET_PWR_ON = "S0" || (S3 power && WOL_EN)
ENET POWER ENABLE CIRCUIT
CAESAR II DECOUPLING
CAESAR II 1V2 RAIL SUPPLY
MAX CURRENT = 396MA
SILKSCREEN:LINKSILKSCREEN:10/1000
CAESAR II LED SUPPORT
SILKSCREEN:10/100SILKSCREEN:ACT
38 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
=PP3V3_S3_ENET
ENET_PWR_L
ENET_WAKE_L
MIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MM
PP_ENET_CTRL12
VOLTAGE=3.3V
PP3V3_ENET
ENET_LED_LINK1000_L
ENET_LED_LINK_L
ENET_LED_ACT_L
ENET_LED_LINK10_100_L
ENET_LINKENET_LINK1000ENET_LINK10
PP3V3_ENET
ENET_ACT
PP3V3_ENETMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MM
VOLTAGE=3.3V
=PP1V2_ENET
ENET_CTRL12
PP3V3_ENET
WOL_EN_L
WOL_EN
MIN_LINE_WIDTH=0.6MM
PP1V2_S5_ENETMAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2MMVOLTAGE=1.2V
=PP1V2_ENET
PM_SLP_S3_L
ENET_WAKE_LPCIE_WAKE_L
PP3V3_ENET
SYNC_DATE=07/01/2009
CAESAR II SUPPORTSYNC_MASTER=K60_AARON
SSM3K15FV
SOD-VESM-HF
Q3841
3
12
5%
MF-LF402
10K1/16W
R38411
2
CRITICAL
SOT-23-HFNTR4101PQ3802
3
1
2
SOT-363
2N7002DW-X-GQ38033
5
4SOT-3632N7002DW-X-GQ3803
6
2
1
402
CERM
0.01UF
16V
10%
C3832
1 2
10%
X5R402
0.1UF16V
C38311
2
5%
MF-LF402
10K1/16W
R38311
2
5%
100K
402
1/16WMF-LF
R38321 2
16VX7R-CERM
0.1UF10%
402
C38131
216VX7R-CERM
0.1UF10%
402
C38121
2
402
10%0.1UF
X7R-CERM16V
C38111
2CERM6.3V
4.7UF20%
603
C3810 1
2
402
16V10%0.1UF
X7R-CERM
C38081
2
402
10%0.1UF
X7R-CERM16V
C38071
216V
0.1UF
402
10%
X7R-CERM
C38061
216VX7R-CERM
0.1UF10%
402
C38051
2
402
10%0.1UF
16VX7R-CERM
C38041
2
402
0.1UF
X7R-CERM16V10%
C38031
2
402
10%0.1UF
X7R-CERM16V
C38021
2
402
10%0.1UF
X7R-CERM16V
C38011
2
4.7UF
6.3V20%
603CERM
C3800 1
2
DEVELOPMENT
2.0X1.25MM-SMGREEN-3.6MCD
LED3804
A
K
330
DEVELOPMENT
5%
MF-LF402
1/16W
R38081
2
DEVELOPMENT
2.0X1.25MM-SMGREEN-3.6MCD
LED3803
A
K
330
DEVELOPMENT
5%1/16WMF-LF402
R38071
2
DEVELOPMENT
GREEN-3.6MCD2.0X1.25MM-SM
LED3802
A
K
DEVELOPMENT
3305%1/16WMF-LF402
R38061
2
330
DEVELOPMENT
5%1/16WMF-LF402
R38051
2
DEVELOPMENT
GREEN-3.6MCD2.0X1.25MM-SM
LED3801
A
K
1.5
MF-LF
5%1/4W
1206
R38021 2
4.7UF
603
20%6.3VCERM
C38171
2402
10%
X5R16V
0.1UFC38181
2
603-2
10UF
X5R6.3V20%
C38251
2
PBSS5540ZDG
CRITICAL
SOT223
Q38101
24
3
X5R402
0.1UF10%16V
C38261
2
6
37 36
89
89 37 36
36
36
36
36
89 37 36
89 37 36
37 36
36
89 37 36
21 15
89
37 36
91 63 62 46 33 32 19 5
37 36 33 19
89 37 36
MCT1
MX1+
MX1-
MCT2
MX2+
MX2-
MCT3
MX3+
MX3-
MCT4
MX4+
MX4-
TD1+
TCT1
TCT2
TD1-
TD2+
TD2-
TD3+
TCT3
TD3-
TD4+
TCT4
TD4-
1CT:1CT
1CT:1CT
1CT:1CT
1CT:1CT
ENET_MDITRAN_P0
TRAN_N0
TRAN_P1
TRAN_P2
TRAN_N2
TRAN_N1
TRAN_P3
TRAN_N3
PINSSHIELD
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
NOTE: DELTA RECOMMENDS CENTER-TAP BE FLOATING
PLACE ONE CAP PER TCT PIN
NOTE: BOB SMITH TERMINATION FOR EMC INVESTIGATION.
514-0654
39 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
ENET_TCT
ENET_MDI_T_N<1>
ENET_MCT2
ENET_MDI_T_P<2>
ENET_MDI_T_P<0>
ENET_MDI_T_N<0>
ENET_MDI_T_P<1>
ENET_MCT0
ENET_MCT1
ENET_MCT_BS
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 MM
ENET_MCT3
ENET_MDI_T_P<0>
ENET_MDI_T_P<1>
ENET_MDI_T_N<2>
ENET_MDI_T_P<3>
ENET_MDI_T_N<3>
ENET_MDI_T_N<0>
ENET_MDI_T_P<3>
ENET_MDI_T_N<2>
ENET_MDI_T_N<1>
ENET_MDI_T_N<3>
ENET_MDI_T_P<2>
ENET_MDI_P<0>
ENET_MDI_N<0>
ENET_MDI_P<1>
ENET_MDI_N<1>
ENET_MDI_P<2>
ENET_MDI_N<2>
ENET_MDI_P<3>
ENET_MDI_N<3>
SYNC_MASTER=K60_AARON SYNC_DATE=07/01/2009
ETHERNET CONNECTOR
CRITICAL
F-ANG-THRJ45-10/100TX-K22
J3900
10
9
2
6
5
8
1
3
4
7
LFE9287APFSOI
T3900
24
21
18
15
22
23
19
20
16
17
13
14
1
4
7
10
3
2
6
5
9
8
12
11
402
20%0.1UF10VCERM
C39041
2402
20%0.1UF10VCERM
C39031
2
0.1UF20%
402
10VCERM
C39021
210V
402
20%0.1UF
CERM
C39011
2
NOSTUFF
1206
1000PF10%2KVCERM
C39001
2
MF-LF402
1/16W5%75R39031
2
751/16WMF-LF402
5%
R39021
2MF-LF
75
402
5%1/16W
R39011
2
755%
MF-LF402
1/16W
R39001
2
86 38
86 38
86 38
86 38
86 38
86 38
86 38
86 38
86 38
86 38
86 38
86 38
86 38
86 38
86 38
86 38
86 36
86 36
86 36
86 36
86 36
86 36
86 36
86 36
OUT TRI-ST/NC
VCC
GND
NC
NCNC
NCNCNCNCNCNCNCNC
NCNCNCNCNCNCNCNCNC
NCNCNC
NCNCNCNCNCNCNCNC
OUT
IN
IN
OUT
IN
OUT
OUT
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
RSVD_19
LKON_DS2_P
XI
CNA
CPS
PD
R1
R0
D6
D5
D4
D3
D2
D1
D0
CTL0
CTL1
LREQ_P
LREQ_L
LPS_P
LPS_L
PINT_P
PCLK_P
PINT_L
LCLK_P
LCLK_L
LINKON_L
DS1
DS0
PC2
PC0
PC1
PHY_RESET*
TPB2_N
TPB2_P
TPB1_N
TPB1_P
TPB0_N
TPB0_P
TPA2_N
TPA2_P
TPA1_N
TPA1_P
TPA0_N
TPA0_P
TPBIAS2
TPBIAS1
TPBIAS0
SE
TESTW_VREG_PD
SM
TESTM
BMODE
PLLGNDGND
DVDD_3_3
PLLVDD_3_3
VDDA_33 AVDD_3_3 VDD_15 VDDA_15 DVDD_CORE
VDD_15_COMB
VDD_33_COM_IO
VDD_33_COMB
VDD_33
PLLVDD_CORE
PCLK_L
VSSA_PCIEVSSAVSS
REF0_PCIE
REF1_PCIE
PERST*
RXN
RXP
TXN
TXP
CLKREQ*
REFCLK_P
REFCLK_M
REFCLK_SEL
SCL
SDA
GPIO0
GPIO2
GPIO1
GPIO3
GPIO4
GPIO5
GPIO7
GPIO6
OHCI_PME*
GRST*
RSVD_1
RSVD_0
RSVD_3
RSVD_2
RSVD_4
RSVD_6
RSVD_5
RSVD_9
RSVD_7
RSVD_8
RSVD_10
RSVD_11
RSVD_14
RSVD_12
RSVD_13
RSVD_16
RSVD_17
RSVD_18
RSVD_15
D7
CYCLEOUT
PCI EXPRESS
1394B OHCI & PHY
IN
IN
IN
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
(Snoop Enable, for FireBug)
(JTAG_TRST)
(IPU)
multi-port systems must come from bus power.
FW_FWPHY nets are PHY power, and for
be tied together and powered by S0 or by the
For single-port systems, all FW power should
5K pull-down device detect circuit.
can be S0.
FWRS0_FWXIO nets are OHCI/PCIe power, and
Power Aliases:
(VDD_33_AUX)
as appropriate
PC[0:2] = ’000’
Strap DSx high on unused ports.
2 FW800 connectors
page assumes no more than
DS2 hard-strapped to 1,
Single-port:
TP/NC TPBIASx
TP/NC TPAx_P/TPAx_N
Unused Ports:
Multiple-ports:
PC[0:2] = ’100’
Ground TPBx_P/TPBx_N
(IPU)
(IPU)
(JTAG_TMS)
(JTAG_TDO)
(JTAG_TDI)
(JTAG_TCK)
Alias =FWPHY_PC0
41 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
FWPHY_TESTW
=PP3V3_FW_FWPHY
FWPHY_BMODE
FWPHY_TESTM
TP_FWXIO_JTAG_TDI
FWXIO_SNOOP_EN
FW_P0_TPB_N
=PP1V5_FWRS0_FWXIO
VOLTAGE=1.5VMIN_NECK_WIDTH=0.2 mm
PP1V5_FW_VDDAMIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mmVOLTAGE=1.96V
MIN_LINE_WIDTH=0.3 mmPP1V96_FW_PLLVDD
=PP3V3_FW_FWPHY
FWXIO_VDD15COMB
FWXIO_VDD33COMB
FWXIO_VDD33COMIO
PP1V95_FW_FWPHY
MIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.2 mm
PP3V3_FW_VDDA
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.3 mmPP3V3_FW_AVDD
VOLTAGE=3.3V
PCIE_FW_R2D_P
PCIE_FW_R2D_N
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.3 mmPP1V96_FW_XTAL
VOLTAGE=1.96V
=PP3V3_FWRS0_FWXIO
MIN_LINE_WIDTH=0.3 mmPP3V3_FW_PLLVDD
VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 mm
TP_FWPHY_CNA
FWPHY_CPS
FWPHY_RESET_L
FWPHY_R0
FWPHY_R1
FWPHY_CLK98M_PCLK
FWOHCI_CLK98M_LCLK
FWPHY_PINT
FWOHCI_LPS
FWOHCI_LINKON_L
=FWPHY_PC0
=PP3V3_FW_FWPHY
FWPHY_LKON_DS2
CLK98M_FW_XI_R
FWXIO_CYCLEOUT
PCIE_FW_D2R_N
PCIE_FW_D2R_P
PCIE_FW_R2D_C_N
PCIE_FW_R2D_C_P
=FW_PME_L
PCIE_CLK100M_FW_N
PCIE_CLK100M_FW_P
=FW_CLKREQ_L
FW_P1_TPA_N
FW_P0_TPA_N
FW_P0_TPBIAS
FWXIO_REF0_PCIE
=FWPHY_DS0
=FWPHY_DS1
TP_FWOHCI_XO
PCIE_FW_D2R_C_N
PCIE_FW_D2R_C_P
FWXIO_REF_PCIE
FWXIO_REF1_PCIE
FW_P0_TPA_P
=PPVP_FW_PHY_CPS
FW_P0_TPB_P
FW_P1_TPA_P
FW_P2_TPA_P
FW_P2_TPA_N
FW_P2_TPBIAS
FW_P1_TPBIAS
FWXIO_SCL
FWXIO_SDA
FWXIO_REFCLK_SEL
FW_RESET_L
TP_FWXIO_GRST_L
TP_FWXIO_JTAG_TMS
TP_FWXIO_JTAG_TDO
CLK98M_FW_XI
FWOHCI_LREQ
SYNC_DATE=07/16/2009SYNC_MASTER=K23_AARON
FireWire LLC/PHY (XIO2213B)
CERM402
1UF10%6.3V
C4131 1
26.3V10%
402
1UF
CERM
C4132 1
2
CERM402
1UF10%6.3V
C4121 1
2
10%
402CERM
1UF
6.3V
C4122 1
2
10%1UF
6.3V
402CERM
C4123 1
2
1UF
402
10%
CERM6.3V
C4126 1
2
402CERM6.3V
1UF10%
C4127 1
2CERM
1UF
6.3V10%
402
C4128 1
2
402CERM6.3V10%1UF
C4124 1
2
MF-LF1/16W5%
402
470R41711
2
22
MF-LF
5%
402
1/16W
R41911 2
10%6.3VCERM402
1UFC4135 1
2
10%6.3VCERM402
1UFC41391
2
40
40
1K
1/16WMF-LF
5%
402
R41701 2
40
402
1/16W5%10K
MF-LF
R41751
2
6.3V10%
402
1UF
CERM
C41381
2
10%1UF
CERM6.3V
402
C4137 1
2
XIO2213B
BGA
OMIT
CRITICAL
U4100
E10
F10
J9
K9
M10
M4
A5
J12
A2
P12
H1
J1
N8
J2
K2
K1
L1
L2
L3
M2
M3
N9
P9
C8
J3
K3
C9
F3
M9
E6
E7
G9
H5
H6
H7
H8
H9
J5
J6
J7
J8
F6
K5
K6
K7
K8
F7
F8
F9
G5
G6
G7
G8
P1
N2
P2
N3
N4
P5
P6
N6
C13
G2
H2
E1
D1
C1
C2
F2
E2
P8
E9
E8
A11
G1
F1
B3
B13
B4
D2
D3
N5
N7
M7
N1
M1
A13
A12
B1
A1
H13
E12
F12
M13
N10
N11
N12
N13
P10
P11
D12
D13
P3
F13
G12
K12
L12
L13
M8
M11
M12
A3
A4
J13
H12
P13
P14
B2
A6
L14
K14
G14
F14
C14
B14
N14
M14
J14
H14
E14
D14
K13
G13
E13
A8
A9
G3
H3
K10
M6
P7
B8
C12
E3
G10
H10
J10
M5
B12
C11
B11
B10
B9
B7
B5
C3
A10
A14
A7
F5
C10
B6
C4
C5
C6
C7
P4
390K
402
1/16WMF-LF
5%
R41861
2
MF-LF1/16W
402
6.34K1%
R41851
2
84 18
402CERM-X5R6.3V
0.22UF10%
C41891
240
40
40
40
40
86 40
86 40
86 40
86 40
84 18
40
10%6.3VCERM402
1UFC4105 1
2
10%6.3VCERM402
1UFC4104 1
2
10%6.3VCERM402
1UFC4103 1
2
84 18
10%6.3VCERM402
1UFC4108 1
2
1UF10%6.3VCERM402
C4115 1
2
10%6.3VCERM402
1UFC4107 1
2
10%6.3VCERM402
1UFC4106 1
2
10%6.3VCERM402
1UFC4114 1
2
10%6.3VCERM402
1UFC4113 1
2
10%6.3VCERM402
1UFC4102 1
2
10%6.3VCERM402
1UFC4101 1
2
10%6.3VCERM402
1UFC4100 1
2
10%
CERM402
1UF
6.3V
C4112 1
2
84 18
402
10%6.3VCERM
1UFC4111 1
26.3V10%
CERM402
1UFC4110 1
2
402
1/16W5%1
MF-LF
R41101
2
402
1/16WMF-LF
5%1R4117
1
2
402
1/16W5%1
MF-LF
R41191
2
10%6.3VCERM402
1UFC4119 1
2
10%6.3VCERM402
1UFC4118 1
2
402MF-LF1/16W
1%14.3K
R41401
2
91 27
1K5%
402
1/16WMF-LF
R41801
2
40
84 18
84 18
10%6.3VCERM402
1UFC4117 1
2
2321%1/16W
402MF-LF
R41411
2
0.1uFX5R 40210% 16V
PLACEMENT_NOTE=Place C4140 close to U1400
C4140 1 2
X5R 40210% 16V0.1uF
PLACEMENT_NOTE=Place C4141 next to C4140
C4141 1 2
220
MF-LF402
5%1/16W
R41521
2
220
MF-LF402
5%1/16W
R41511
2
1K
1/16WMF-LF
5%
402
R41821
2
0.1uF X5R 40210% 16V
PLACEMENT_NOTE=Place C4145 close to UA200
C4145 1 2
0.1uFX5R 40210% 16V
PLACEMENT_NOTE=Place C4146 next to C4145
C4146 1 2
MF-LF1/16W
402
5%1K
R41501
2
40
MF-LF
1K5%
402
1/16W
NO STUFFR41891
2
47K5%
402
1/16WMF-LF
NO STUFF
R41531
2
1/16W
1K
MF-LF402
5%
R41601
2
402
1/16WMF-LF
5%1
R41351
2
0.22UF
402CERM-X5R
6.3V10%
C4190 1
2
SM98P3040MHZY4190
2
3 1
4
402
1/16W5%
MF-LF
4.7R41901
2
5%1/16WMF-LF
1
402
R41251
2
CERM
1UF
402
6.3V10%
C4120 1
2
10%6.3VCERM
1UF
402
C4130 1
2
1UF10%
402
6.3VCERM
C4125 1
2
1/16W
402
5%1K
MF-LF
R41811
2
41 40 39 6
91
6
89
89
41 40 39 6
89 40
89
89
84
84
6
89
91
41 40 39 6
84
84
40
OUTINNR
NC THRML
EN
GND PAD
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
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REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
FireWire Aliases For Connectivity
1394 PHY STRAPPING OPTIONS
IT IS IN BILINGUL MODE PULL-UPS ASSERT/ENABLE DATA STROBE ONLY MODE.
2ND & 3RD TPA/TPB PAIR UNUSED
Place close to FireWire PHY
Termination
iMacs are now one port only and have Power Code "000"
THERE ARE THREE FIREWIRE PORTS, BUT ONLY ONE IS USED.NO STUFF MEANS THAT
TI PHY requires 1UF, not 0.33uF spec value.
TI PHY "Peaking Inductors" To improve Data Eye.
1394 PHY 1.95V SUPPLY
42 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
PP1V95_FW_FWPHY
MAX_NECK_LENGTH=3 MM
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.5 mmMAKE_BASE=TRUE
NET_SPACING_TYPE=POWER
VOLTAGE=1.96V
FW_P2_TPA_P
FW_P2_TPBIAS
FW_CLKREQ_LMAKE_BASE=TRUE
FW_PORT0_TPB_PMAKE_BASE=TRUE
FW_P0_TPB_PFW_PORT0_TPB_N
MAKE_BASE=TRUE
FW_PORT0_TPA_NMAKE_BASE=TRUE
FW_P0_TPA_C
FW_PHY_DS1MAKE_BASE=TRUE
MAKE_BASE=TRUEFW_PHY_DS0
P1V95_FW_NR
FW_P2_TPA_N NC_FW_PORT2_TPA_NNO_TEST=TRUEMAKE_BASE=TRUE
NC_FW_PORT2_TPA_PNO_TEST=TRUEMAKE_BASE=TRUE
MAKE_BASE=TRUENC_FW_PORT2_TPBIAS
NO_TEST=TRUE
FW_P1_TPA_NNO_TEST=TRUEMAKE_BASE=TRUENC_FW_PORT1_TPA_N
FW_P1_TPA_PNO_TEST=TRUEMAKE_BASE=TRUENC_FW_PORT1_TPA_P
FW_P1_TPBIASNO_TEST=TRUEMAKE_BASE=TRUE
NC_FW_PORT1_TPBIAS
=FW_CLKREQ_L
=PP3V3_FW_FWPHY
=FWPHY_PC0MAKE_BASE=TRUE
FW_PHY_PC0
=FWPHY_DS1
=FWPHY_DS0
=PP3V3_FW_FWPHY
=FW_PME_LMAKE_BASE=TRUE
FW_PME_L
PPVP_FW_PHY_CPSMAKE_BASE=TRUE
=PPVP_FW_PHY_CPS
FW_PORT0_TPA_PMAKE_BASE=TRUE
MIN_LINE_WIDTH=0.1MM
FW_P0_TPBIAS
MIN_NECK_WIDTH=0.08MM
VOLTAGE=1.86V
FW_P0_TPA_PFW_P0_TPA_N
FW_P0_TPB_N
FW_P0_TPB_L_N
NO_TEST=TRUEVOLTAGE=0V
FW_P0_TPA_L_NNO_TEST=TRUEVOLTAGE=1.86V
NO_TEST=TRUEVOLTAGE=0V
FW_P0_TPB_L_P
NO_TEST=TRUEVOLTAGE=1.86V
FW_P0_TPA_L_P
FW: 1394B MISCSYNC_MASTER=K23_AARON SYNC_DATE=07/16/2009
0402
18NH-250MAL4251
1 2
0402
18NH-250MAL4250
1 2
18NH-250MA
0402
L4253
1 2
18NH-250MA
0402
L4252
1 2
10%1UF
CERM402
6.3V
C4200 1
2 10%0.01UF
CERM16V
402
C4201 1
2 X5R
2.2UF20%4V
402
C42021
2
TPS799195SON
CRITICAL
U4200
4
3
6
5
2
1
7
10K
402MF-LF
5%1/16W
R42571
2
10K
402MF-LF
5%1/16W
R42581
2
402
220PF
CERM
5%25V
C4254 1
2MF-LF1/16W1%4.99K
402
R42541
2
56.21%
MF-LF402
1/16W
R42521
2
56.21%1/16W
402MF-LF
R42531
2
1%
MF-LF402
1/16W
56.2R42501
2MF-LF402
1%1/16W
56.2R42511
2
CERM
1UF6.3V10%
402
C42501
2
10K5%1/16WMF-LF402
R42561
2
10K1/16W5%
NOSTUFF
MF-LF402
R42551
2
89 39
86 39
39
25 18 15
86 41 39
86 41
86 41
86 39
86 39
86 39
39
39
41 40 39 6
39
39
39
41 40 39 6
39 21 15
89 41 39
86 41
39
39
39
39
86
86
86
86
V+
GND
SHIELDPINS
VGTPA-
TPA(R)
TPB- TPB(R)
TPB+ VP
TPA+
SC/NC
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
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REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
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Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
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B
8 7 5 4 2 1
7 WATTS MAX PER PORT
POUR COPPER TO SINK HEAT
"Snapback" & "Late VG" Protection
IT IS HERE FOR SAFETY ONLYTHIS FUSE WILL NOT BLOW
FAST NON-RESETABLE FUSE
SHOULD BE DONE AS A POWER STRIP(SUBPLANE)
1394B
5.1VNC
PLACE CLOSE TO COMPARATOR
ESD Rail
IT IS 2.2V INSTEAD OF 2.7V BECAUSE THE SNAPBACK ESD DIODES HAVE A .5V DROP
CURRENT THROUGH THE BIAS RESISTOR SHOULD BE 5MA FOR A VOLTAGE DROP TO 2.2V
[ LATE VG NOTES ]
514-0656
PORT 0
12 VOLTS
5.1V
PLACE CLOSE TO COMPARITOR
INRUSH RESETABLE PTC
43 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
=PP12V_S5_FWMIN_LINE_WIDTH=1.7MMP12V_S5_FW_R
VOLTAGE=12VMIN_NECK_WIDTH=0.5MM
PP3V3_FW_ESD
MIN_NECK_WIDTH=0.5MM
P12V_S5_FW_DMIN_LINE_WIDTH=1.7MM
VOLTAGE=12V
FW_PORT0_VP
MIN_NECK_WIDTH=0.5MMVOLTAGE=12V
MIN_LINE_WIDTH=1.7MM
FW_PORT0_VP_F
MIN_NECK_WIDTH=0.5MMMIN_LINE_WIDTH=1.7MM
VOLTAGE=12V
FW_CURRENT_LIMIT
=PP12V_S5_FW
FW_CURRENT_LIMIT
FW_FET_LINEAR_LIMIT_OUTFW_FET_LINEAR_LIMIT_IN
FW_CURRENT_LIMIT_R
PP3V3_FW_ESD
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.38 mmVOLTAGE=3.3V
=PP3V3_FW_FWPHY
FW_FET_LINEAR_LIMIT_FB
FW_CURRENT_LIMIT_RD
FW_PORT0_TPA_N
FW_PORT0_TPA_PFW_PORT0_TPA_R
FW_PORT0_TPB_P
FW_PORT0_TPB_N
FW_FET_LINEAR_LIMIT_IN
FW_FET_LINEAR_LIMIT_OUT
FW_CURRENT_LIMIT_Q
FW_TURN_ON_V
P12V_S5_FW_CLMIN_LINE_WIDTH=1.7MMMIN_NECK_WIDTH=0.5MMVOLTAGE=12V
PPVP_FW_PHY_CPSVOLTAGE=12V
MIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.5MM
PP3V3_FW_ESD
SYNC_DATE=07/16/2009SYNC_MASTER=K23_AARON
FIREWIRE CONNECTOR
F-ANG-TH
CRITICAL
1394B-K22J4300
10
11
7
3
4
5
1
2
9
6
8
SM
PLACEMENT_NOTE=PLACE CLOSE TO F4300
XW43001 2
3AMP-32V
603
CRITICAL
F43001 2
100K
1/16W
402MF-LF
5%
R43051 2
SOT23
MMBZ5231BXG
D430313
16VX5R
10%2.2UF
603
C4305 1
2
200K1/16WMF-LF
5%
402
R43061
2
402MF-LF1/16W5%
100KR43041 2
SOI-HFLM393U4300
4
6
2
5
3
7
1
810%16V
402
0.1UF
X7R-CERM
C43041
2
BAS40XG
SOT23
D43021 3
SOT23MMBT2222A7F
Q43021
3
2
5%1/16W
10K
MF-LF402
R43011
2
20%
CERM402
16V
0.01UFC43021
2402MF-LF1/16W5%20KR43071
2
603
1/10W5%
MF-LF
15KR43021
2MF-LF1/16W
402
5%20KR43031
2
SM
CRITICAL
CRS08-1.5A-30V
D43001 2
MF-LF
1%1/16W
51.1K
402
R43521 2
SOT2360V-600MA
MMBT2907AXGQ43011
32
5%
0.33
MF1W
2512
R43001 2
SSOT6
FDC610PZ
CRITICAL
Q4300
12
56
3
4
0.3AMP-60V
CRITICAL
SMD030F-SM
F43011 2
MMBZ5231BXGSOT23
D4301
1
3
10%50VX7R
0.01UF
603-1
C43001
2
402
1%
MF-LF1/16W
1MR43351
2 603-1
0.1UF10%50VX7R
C43351
2
10%
402
0.001UF
CERM50V
NOSTUFF
C4332 1
2
SM
CRITICAL
FERR-250-OHML4300
1 2
0.01UF50V
402
10%
X7R
C4311 1
2402
0.01UF50V10%
X7R
C4310 1
2
X7R
0.01UF50V
402
10%
C4313 1
2X7R402
50V10%
0.01UFC4312 1
2
1/16WMF-LF
1%
402
332R43901 2
MMBZ5227BLT1HSOT23
CRITICAL
D4390
13
CRITICAL
BAV99DW-X-GSOT-363
DP4311
1
2
6
BAV99DW-X-G
CRITICAL
SOT-363
DP4310
1
2
6
BAV99DW-X-G
CRITICAL
SOT-363
DP4311
4
5
3
CRITICAL
SOT-363BAV99DW-X-GDP4310
4
5
3
41 6
89 41
89 89
41
41 6
41
41 41
89 41 40 39 6
86 40
86 40
86 40
86 40
41
41
89 40
89 41
OUTKEY
GNDGND
MD
+5V
+5V
DP
B-B+
GND
GND
A-
A+
GNDIN
IN
OUT
OUT
SG
D
G
D
S
G
D
S
IN
IN
OUT
OUT
IN
IN
OUT
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
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345678
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8 7 5 4 2 1
SATA PORT A1 FOR SLIMLINE ODD
518S0251
SATA PORT A0 FOR HDD
SATA PORT A2 FOR SSD
SATA Activity LED
518-0361
SILKSCREEN:HDD
518S0251
SILKSCREEN:ODD
ODD PWR CONTROL
45 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
PP5V_S0_SATA_FETNET_PHYSICAL_TYPE=POWER
SATA_ODD_R2D_N
SATA_ODD_D2R_C_N
SATA_ODD_D2R_C_PSATA_SSD_D2R_C_N
SATA_SSD_D2R_C_P
SMC_ODD_DETECT
=PP5V_S0_SATA
=PP3V3_S0_ODD ODD_PWR_SS
SATA_ODD_R2D_P
PCH_SATALED_L
=PP3V3_S0_ODD
SATA_SSD_R2D_N
SATA_SSD_R2D_P
SATALED_R_L
=PP3V3_S0_SATALED
SATA_HDD_R2D_N
SATA_HDD_R2D_P
SATA_HDD_D2R_C_N
SATA_HDD_D2R_C_P
SATALED_LMAKE_BASE=TRUE
SATA_SSD_R2D_C_P
SATA_SSD_R2D_C_N
SATA_SSD_D2R_N
SATA_SSD_D2R_P
SATA_HDD_R2D_C_P
SATA_HDD_D2R_P
SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N
SATA_ODD_D2R_N
SATA_ODD_D2R_P
SATA_HDD_D2R_N
ODD_PWR_EN_L
SATA_HDD_R2D_C_N
ODD_PWR_LS5V_L
ODD_PWR_EN
SATA ConnectorsSYNC_DATE=07/01/2009SYNC_MASTER=K60_JERRY
84 18
84 18
84 18
DEVELOPMENT
GREEN-3.6MCD2.0X1.25MM-SM
SILK_PART=SATA ACTIVE
DS4599A
K
MF-LF603
3305%
DEVELOPMENT
1/10W
R45991
2
84 18
84 18
84 18
84 18
10%0.01UF 40216V CERM
C4516 1 2
402CERM16V0.01UF 10%
C4515 1 2
CERM 4020.01UF 16V10%
C4511 1 2
CERM 40210%0.01UF 16V
C4510 1 2
MF-LF
5%1/8W
805
0R45501 2
SOT-3632N7002DW-X-G
NOSTUFF
Q4502
3
5
4
2N7002DW-X-GSOT-363
Q4502
6
2
1
10%16VCERM402
0.01UF
NOSTUFF
C45001 2
402
10%10VCERM
0.068UF
NOSTUFF
C45011
2
402MF-LF1/16W
5%100K
NOSTUFFR45021
2
MF-LF1/16W
402
5%
100K
NOSTUFF
R45001 2
402
1/16W5%
100K
MF-LF
NOSTUFFR45011
2
TPCP810223V1K-SM
NOSTUFFQ4500
56
78
4
12
3
CRITICAL
M-ST-SMEP00-081-91
NOSTUFF
J4530
1
2
3
4
5
6
7
CERM 40216V10%0.01UFNOSTUFF
C4533 1 2
0.01UF 16V CERM10% 402
NOSTUFF
C4532 1 2
10% 16V0.01UF 402CERM
NOSTUFF
C4531 1 2
NOSTUFF
10%0.01UF 16V 402CERM
C4530 1 2
84 18
84 18
84 18
84 18
1735574M-ST-TH
J4520
S3
S2
S5
S6
P1
P5
P6
S1
S4
S7
14
15
P4
P2
P3
EP00-081-91M-ST-SM
CRITICAL
J4510
1
2
3
4
5
6
7
1/10WMF-LF603
33K5%
R45201
2
10%6.3VCERM402
1UFC45251
2CERM
10%6.3V
402
1UFC45241
2
10%0.01UF 402CERM16V
C4522 1 2
10% 402CERM16V0.01UF
C4523 1 2
16V 402CERM10%0.01UF
C4520 1 2
10% 402CERM16V0.01UF
C4521 1 2
84 18
89
92 84
92 84
92 84
84
84
92 45
6
42 6
92 84
18
42 6
84
84
18 6
92 84
92 84
92 84
92 84
21 15
EN1*
OC1*
IN OUT1
GND TPAD
OUT2
OC2*
EN2*
G S
D
EN1*
OC1*
IN OUT1
GND TPAD
OUT2
OC2*
EN2*
IO
IO
NC
GND
VBUS
NC
SYM_VER-1
SYM_VER-1
SYM_VER-1
SYM_VER-1
VCC
GND
SELOE*
D+
D-
Y+
Y-
M+
M-
VBUS
DATA-
GND
DATA+
VBUS
DATA-
GND
DATA+
VBUS
DATA-
GND
DATA+
VBUS
DATA-
GND
DATA+
IO
IO
NC
GND
VBUS NC
IO
IO
NC
GND
VBUS
NC
IO
IO
NC
GND
VBUS NC
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
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Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PORT 1
(PUT CAP ON CONNECTOR SIDE)
D+
(PUT CAP ON CONNECTOR SIDE)
SEL=1: CHOOSE USB
(PUT CAP ON CONNECTOR SIDE)
GND
PORT 0
D-
VDD
GND
GND
D+
D-
VDD
VDD
D-
D+
PORT 2
VDD
D-
GND
D+
PORT 3
SEL=0: CHOOSE SMC
(PUT CAP ON CONNECTOR SIDE)
514-0672
514-0672
514-0659
514-0659
USB/SMC DEBUG MUX
46 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
PP5V_USB2_PORT2_F
MIN_LINE_WIDTH=0.6MMVOLTAGE=5V
MIN_NECK_WIDTH=0.2MMMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MMVOLTAGE=5VPP5V_USB2_PORT2
USB_PORT1_N
PP5V_USB2_PORT1_F
MIN_LINE_WIDTH=0.6MMVOLTAGE=5V
MIN_NECK_WIDTH=0.2MM
USB_EXTD_N
PP5V_USB2_PORT1VOLTAGE=5V
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MMUSB_EXTB_OC_L
USB_EXTC_OC_L
USB_EXTD_OC_L
USB_D_MUXED_P
USB_D_MUXED_N
=PP3V3_G3H_SMCUSBMUX
USB_EXTC_P
PP5V_USB2_PORT0
MIN_LINE_WIDTH=0.6MMVOLTAGE=5V
MIN_NECK_WIDTH=0.2MM
USB_EXTC_N
USB_EXTB_N
USB_EXTB_P
USB_EXTA_N
USB_EXTA_P
PM_EN_USB_PWR
USB_EXTA_OC_L
USB_EXTD_P
USB_DEBUGPRT_EN_L
=PP5V_S3_USB
SMC_TX_L
SMC_RX_L
USB_PORT0_P
USB_PORT0_N
MIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MM
PP5V_USB2_PORT0_FVOLTAGE=5V
USB_PORT1_P
USB_PORT3_P
USB_PORT3_N
MIN_LINE_WIDTH=0.6MMVOLTAGE=5V
MIN_NECK_WIDTH=0.2MM
PP5V_USB2_PORT3_F
USB_PORT2_P
USB_PORT2_N
MIN_LINE_WIDTH=0.6MM
PP5V_USB2_PORT3
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V
USB_PWR_ENA_L
=PP5V_S3_USB
EXTERNAL USB CONNECTORSSYNC_DATE=07/01/2009SYNC_MASTER=K60_JERRY
SLP1210N6RCLAMP0502N
CRITICAL
D4600
1
5 42 3
6
SLP1210N6
CRITICAL
RCLAMP0502ND4610
1
5 42 3
6
RCLAMP0502NSLP1210N6
CRITICAL
D4620
1
5 42 3
6
SM
CRITICAL
FERR-250-OHML4600
1 2
USB-K22
CRITICAL
F-ANG-TH
J4620
2
3
4
5
6
1
CRITICAL
USB-K22F-ANG-TH
J4630
2
3
4
5
6
1
USB-K22
CRITICAL
F-ANG-TH1
J4610
2
3
4
5
6
1
CRITICAL
USB-K22F-ANG-TH1
J4600
2
3
4
5
6
1
CRITICAL
PI3USB102ZLE
MOJOMUX
TQFN
U4650
6
7
3
4
5
8 10
9
2
1
CRITICAL
DLP0NS120-OHM-90MAL4631
1 2
34
DLP0NS120-OHM-90MA
CRITICAL
L4621
1 2
34
CRITICAL
DLP0NS120-OHM-90MAL4611
1 2
34
DLP0NS120-OHM-90MA
CRITICAL
L4601
1 2
34
0.01uF
CERM402
16V20%
C46001
2
402CERM16V20%
0.01uFC46101
2
20%0.01uF
16VCERM402
C46201
2
6.3V
CRITICAL
20%150UF
POLY-TANTCASE-D2-SM
C46061
2
0.1UF20%
402
10VCERM
C46211
2
SM
FERR-250-OHM
CRITICALL4630
1 2
SLP1210N6RCLAMP0502N
CRITICAL
D4630
1
5 42 3
6
402
16VCERM
20%0.01uFC46301
2
0.1UF20%10V
402CERM
C46311
2
CRITICAL
TPS2060
MSOP
U4601
3
4
1
2
8
5
7
6
9
402CERM
20%10V
0.1UFC46111
2CERM
0.1UF20%
402
10V
C46031
2
10V20%0.1UF
CERM402
C46011
2
0.1UF10V
402CERM
20%
C46051
2
5%1/16W
402
10K
MF-LF
R46001
2
SOT23-HF12N7002Q4600
3
1
2
CRITICAL
20%6.3VPOLY-TANTCASE-D2-SM
150UFC46021
2
MSOP
TPS2060
CRITICAL
U4600
3
4
1
2
8
5
7
6
9
PRODUCTION
0
MF-LF
5%
402
1/16W
R46521 2
PRODUCTION
1/16WMF-LF
5%
0
402
R46511 2
402CERM
20%0.1UF10V
C46501
2
CRITICAL
SM
FERR-250-OHML4610
1 2
FERR-250-OHM
SM
CRITICAL
L4620
1 2 89 89
85
89
85 35
89
35
34
35
85
85
6
85 34
89
85 34
85 35
85 35
85 34
85 34
62
34
85 35
46 45
43 6
47 46 45
47 46 45
85
85
89
85
85
85
89
85
85
89
43 6
SYM_VER-1
SYM_VER-1
SYM_VER-1
SYM_VER-1
NC
NC
NCNCNC
SYM_VER-1
SYM_VER-1
NC
G
D
S
G
D
S
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
SD Card Reader Board Connector
516S0823
518S0667
WM CONNECTOR
518S0690
GNDBRAID
518S0761
K37L (BLUETOOTH) CONNECTOR
518S0688
LAYOUT NOTE:
BOTH SIDES OF THE PIN.ORDER LISTED, AND NOT ONNEAR J4700 PINS 4 AND 5 IN THEPLACE C4700, C4701 & L4700
CAMERA CONNECTOR & FILTER
518S0668
BLURAY DECRYPTOR CONN & FLTR
IR RECEIVER CONNECTOR
47 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
NET_PHYSICAL_TYPE=POWER
=PP3V3_S3_SDCARD
SDCARD_RESET
SDCARD_RESET_L
USB_BRCRYPT_L_NUSB_BRCRYPT_L_P
=PP5V_S3_BRAY
BRCRYPT_PWR_EN
USB_BRCRYPT_N
USB_SDCARD_L_NUSB_SDCARD_N
USB_SDCARD_L_P
VOLTAGE=12V
MIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MMPP12V_S3_WM_FLT
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MM
VOLTAGE=3.3V
PP3V3_S3_WM_FLT=PP3V3_S3_WM
NET_PHYSICAL_TYPE=POWER
NET_PHYSICAL_TYPE=POWER
=PP12V_S3_WM
USB_WM_P
USB_WM_N USB_WM_L_NUSB_WM_L_P
USB_BT_L_NUSB_BT_L_P
MIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.2MM
VOLTAGE=3.3V
PP3V3_S3_BT_FLT
USB_BT_P
USB_BT_N
=PP3V3_S3_BTNET_PHYSICAL_TYPE=POWER
NET_PHYSICAL_TYPE=POWER
=PP5V_S3_IR
USB_IR_P
PP5V_S3_CAMERA_FLT
VOLTAGE=5VMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MM
USB_CAMERA_L_PUSB_CAMERA_N
USB_CAMERA_P
USB_CAMERA_L_N
=PP5V_S3_CAMERANET_PHYSICAL_TYPE=POWER
USB_IR_L_PUSB_IR_L_N
USB_BRCRYPT_P
=PP3V3_S3_BRCRYPT
BRCRYPT_RESET
USB_IR_N
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MMVOLTAGE=5VPP5V_S3_IR_FLT
PP3V3_S3_SDCARD_FLT
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MM
VOLTAGE=3.3V
USB_SDCARD_P
SDCARD_PLT_RST_R_L
SDCARD_PLT_RST_L
SYNC_MASTER=K60_JERRY SYNC_DATE=07/01/2009
Internal USB Connections
SOT-3632N7002DW-X-GQ4710
3
5
4
SOT-3632N7002DW-X-GQ4710
6
2
1
BRAY
AXK820225WGM-ST-SM
J4760
1
10
11 12
13 14
15 16
17 18
19
2
20
21
22
3 4
5 6
7 8
9
MF-LF1/16W1%10K
402
R47511
2
M-RT-SM
CRITICAL
53261-8605J4720
6
7
1
2
3
4
5
CRITICAL
53261-8606M-RT-SM
J4750
7
8
1
2
3
4
5
6
CERM402
10V20%0.1UFC47211
2
10UF
CERM6.3V
805-1
20%
C47201
2
CRITICAL
SM
FERR-250-OHML4721
1 2
CRITICAL
DLP0NS120-OHM-90MAL4720
1 2
34
M-RT-SM53780-8605
CRITICALJ4700
6
7
1
2
3
4
5
0.1UF20%10V
402CERM
C4701 1
2
DLP0NS120-OHM-90MA
CRITICAL
L4701
1 2
34
FERR-250-OHM
CRITICAL
SM
L4700
1 2
CERM
10UF6.3V20%
805-1
C47001
2
NOSTUFF
M-RT-SMSM07B-SRKHFS-G
J4740
8
9
1
2
3
4
5
6
7
DLP0NS
BRAYCRITICAL
120-OHM-90MAL4760
1 2
34
402MF-LF
10K
1%1/16W
R47501 2
NOSTUFF 10%1UF
603X5R16V
C47411
2
FERR-250-OHM
NOSTUFF
SM
L4742
1 2
NOSTUFF
SM
FERR-250-OHML4741
1 2
NOSTUFF
120-OHM-90MADLP0NS
L4740
1 2
34
NOSTUFF 1UF
402CERM6.3V10%
C47401
2
402CERM6.3V
1UF10%
C4750 1
2
FERR-250-OHM
SM
CRITICAL
L4751
1 2
CRITICAL
120-OHM-90MADLP0NS
L4750
1 2
34
CRITICAL
M-RT-SM53261-8604J4780
5
6
1
2
3
4
CRITICAL
DLP0NS120-OHM-90MAL4702
1 2
34
CRITICAL
FERR-250-OHM
SM
L4703
1 2
4026.3VCERM
10%1UFC4781
1
2
6
92 91 25 21
85
85
6
18 15
85 20
92 85 85 35
92 85
89
89 6
6
85 20
85 20 85
85
92 85
92 85
89
85 35
85 35
6
6
85 34
89
92 85
85 34
85 34
92 85
6
92 85
92 85
85 20
6
18 15
85 34
89
89
85 35
91 27
IN IN
IN
OUT
OUT
OUT
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
BI
IN
IN
OUT
OUT
IN
IN
OUT
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
IN
IN
OUT
ININ
BI
OUT
IN
OUT
OUT
OUT
OUT
OUTNC
NC
NCNC
NCNCNC
NC
NC
NC
NC
NCNC
IN
OUT
OUT
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
NC
IN
NC
OUT
OUT
BI
IN
OUT
ININ
OUT
IN
IN
P13
P14
P15
P16 P66
P10
P11
P12
P17
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
P32
P33
P34
P36
P37
P40
P41
P42
P43
P44
P45
P46
P47
P50
P51
P52
P60
P61
P62
P63
P64
P65
P67
P70
P71
P72
P73
P74
P75
P76
P77
P80
P81
P84
P85
P86
P90
P91
P92
P93
P94
P95
P96
P97
P35
P83
P82
(1 OF 3)
PH5
PH4
PH3
PH2
PH1
PH0
PG7
PG6
PG5
PG4
PG3
PG2
PG1
PG0
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
PE0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PC7
PC6
PC5
PC4
PC3
PC2
PB2
PB1
PB0
PA7
PA6
PA3
PA2
PA1
PA0
PA4
PA5
PB3
PB4
PB5
PB6
PB7
PC1
PC0
PE4*
PE3*
PE2*
PE1*
(2 OF 3)
AVCC AVREF
AVSS
MD1
MD2
VCC VCL
VSS
NMI
XTAL
RES*
EXTAL
ETRST*
(3 OF 3)BI
BI
BI
BI
IN
IN
IN
BI
IN
IN
BI
BI
IN
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
NOTE: Unused pins have "SMC_Pxx" names. Unused
those designated as inputs require pull-ups.
pins designed as outputs can be left floating,
NOTE: Rename to BaseArch
NOTE: P94 and P95 are shorted, P95 could be spare.
REMOVE R4953/4/5 AFTER PROTO-1
Remove R4950,R4951 after Proto-1
(OC)
Peak/Ave/Standby = 2mA/1mA/5uA
Peak/Ave/Sleep/Standby = 40mA/25mA/20mA/50uA
Peak/Ave/Standby= 2mA/1mA/5uA
(OC)
(OC)
(OC)
SMC_PB3:
(DEBUG_SW_2)(DEBUG_SW_1)
(OC)
SMC_IG_THROTTLE_L for MG systems.
Otherwise, TP/NC okay (was ISENSE_CAL_EN)
(OC)
(OC)
(See below)
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
If SMS interrupt is not used, pull up to SMC rail.
NOTE: SMS Interrupt can be active high or low, rename net accordingly.
49 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
BIDIVI_AUDIO_MUX_SEL
LPC_AD<3>
SMC_LRESET_L
ALS_GAIN
SMC_PH2
SMC_THRMTRIP
SMC_PROCHOT
SMB_B_S0_CLK
SMB_B_S0_DATA
SMB_A_S3_CLK
SMB_A_S3_DATA
SMB_BSA_CLK
SMB_BSA_DATA
=SMC_SMS_INT
SMC_PNL_BL_PWM
BIDIVI_BKL_PWM
BIDIVI_BKL_ON
SMC_PF5
BIDIVI_PNL_PWR_EN
BIDIVI_AUX_TERM_EN
SMC_LID
SMC_SYS_LED
G3_POWERON_L
SMC_CASE_OPEN
ALS_RIGHT
ALS_LEFT
SMC_NB_DDR_ISENSE
SMC_NB_CORE_ISENSE
SMC_ANALOG_ID
SMS_Z_AXIS
SMS_Y_AXIS
SMS_X_AXIS
SMC_FAN_3_TACH
SMC_FAN_2_TACH
SMC_FAN_1_TACH
SMC_FAN_0_TACH
SMC_FAN_3_CTL
SMC_FAN_2_CTL
SMC_ODD_DETECT
SMC_RUNTIME_SCI_L
PM_BATLOW_L
SYS_ONEWIRE
USB_DEBUGPRT_EN_L
PM_SYSRST_L
SPI_DESCRIPTOR_OVERRIDE_L
SMC_PA0
MEM_EVENT_A_L
MEM_EVENT_B_L
SMC_PB3
SMC_EXCARD_CP
SMC_EXCARD_OC_L
SMC_GFX_OVERTEMP_L
SMC_FAN_1_CTL
SMC_FAN_0_CTL
SMC_TMS
SMC_TDO
SMC_TDI
SMC_TCK
MIN_LINE_WIDTH=0.25 MMMIN_NECK_WIDTH=0.20 MM
PP3V3_G3H_SMC_AVCC
VOLTAGE=3.4V
PP3V3_G3H_AVREF_SMC
GND_SMC_AVSS
SMC_MD1
SMC_KBC_MDE
=PP3V3_G3H_SMC
SMC_VCL
SMC_NMISMC_XTAL
SMC_RESET_L
SMC_EXTAL
SMC_TRST_L
RSMRST_PWRGD
PM_RSMRST_L
CPUIMVP_VR_ON SMC_PROCHOT_3_3_L
SMC_EXCARD_PWR_EN
SMC_RSTGATE_L
ALL_SYS_PWRGD_SMC
PM_PWRBTN_L
ESTARLDO_EN
SMC_VIDEO_ON
AUXCH_P_STATE
AUXCH_N_STATE
SMC_DP_HPD
DPMUX_VIDEO_IN_SEL
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_FRAME_L
LPC_CLK33M_SMC
LPC_SERIRQ
SMC_P41
SMB_MGMT_DATA
SMS_ONOFF_L
SMC_GFX_THROTTLE_L
SMC_TX_L
SMC_RX_L
SMB_0_S0_CLK
SMC_PM_G2_R
SMC_ADAPTER_EN
SMC_BIL_BUTTON_L
SMC_CPU_ISENSE
SMC_CPU_VSENSE
SMC_GPU_ISENSE
SMC_GPU_VSENSE
SMC_DCIN_ISENSE
SMC_PBUS_VSENSE
SMC_BATT_ISENSE
SMC_NB_MISC_ISENSE
SMC_WAKE_SCI_L
SMC_TX_L
SMC_RX_L
SMB_MGMT_CLK
SMC_ONOFF_L
SMC_BC_ACOK
SMC_BS_ALRT_L
PM_SLPS3_BUF2_L
SMC_P94
PM_SLP_S4_S5
PM_CLK32K_SUSCLK
SMB_0_S0_DATA
LPC_PWRDWN_L
PM_CLKRUN_L
PM_SLP_S4_2_L
SMC_PM_G2_EN
PM_SLP_S5_L
=PP3V3_G3H_SMC
=PP3V3_G3H_SMC
SMCSYNC_DATE=07/01/2009SYNC_MASTER=K60_JERRY
46
48
48
91 85 9
46 6
48
85 27
91 27
85 47 18
85 47 18
85 47 18
85 47 18
85 47 18
TQFP
OMIT
H8S2117U4900
76
77
67
27
144
9
25
11
8
1 36
86
13
7
42
95
111
139
143
TQFP
OMIT
H8S2117U4900
41
40
39
38
37
35
34
33
120
119
118
117
116
115
114
113
94
93
92
91
90
89
88
87
66
65
64
63
62
61
60
59
32
31
30
29
28
50
49
48
47
46
45
44
43
58
57
56
55
54
53
52
51
10
12
26
140
141
142
TQFP
OMIT
H8S2117U4900
112
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
121
122
123
124
125
126
127
128
136
137
138
2
3
4
5
6
16
15
14
78
79
80
81
82
83
84
85
68
69
70
71
72
73
74
75
129
130
131
132
133
134
135
24
23
22
21
20
19
18
17
402
5%
MF-LF1/16W
0R49551 2
NOSTUFF
5%
402MF-LF1/16W
0R49531 2
91 46 19
91 19
0
1/16WMF-LF402
5%
R49541 2
NOSTUFF
1/16WMF-LF
5%10K
402
R49521
2
3
402
5%
MF-LF1/16W
0R49501 2
1/16W
402MF-LF
5%10K
NOSTUFF
R49511
2
46 46
46
46
46
18 15
81 78
81
81
46
81
81
81
81
81
81
81
46
46
46
46 19
46
46
91 47 19 15
18
47
91 27 19
47 18
46 46
47 46 45 43
47 46 45 43
46
46
46
46
48
48
48
48
48
48
81 46
47 46
47 46
47 46
46
47 46
46
46
46
46
46
46
46
52
52
53
46
46
53
52
52
46
21 15
51
92 42
91 19 15
46 43
10K
1/16WMF-LF402
5%
R49981
2 402
1/16W5%
MF-LF
0
NOSTUFF
R49031
2402
10K5%
MF-LF1/16W
R49021
2
10K
MF-LF
5%1/16W
402
R49011
2
47
47
402
10K
MF-LF
5%1/16W
R49091
2
48
47 46 45 43
47 46 45 43
46
46
46
46
46
46
88 50
88 50
88 49
88 49
402
20%
CERM
0.1UF
10V
C49061
2
46
91 63
91 63
91 62
10V
402
0.1UF
CERM
20%
C49051
2
46
91 25 19
SMXW4900
12
10V
402
0.1UF
CERM
20%
C49041
2
4.7
1/16W5%
MF-LF402
PLACEMENT_NOTE=Place R4999 close to U4900 pin 76
R49991 2
PLACEMENT_NOTE=Place C4920 close to U4900 pin 76
10V
402
0.1UF
CERM
20%
C4920 1
2
0.1UF
10V
402CERM
20%
C49031
2
402CERM-X5R
0.47UF
6.3V10%
PLACEMENT_NOTE=Place C4907 close to U4900 pin 13
C4907 1
2
46
91 47 46 47 19
805
22UF
CERM
20%6.3V
C4902 1
2
46
46
46
46
89
89 46
88 50 49 46
46 45 6
88 46
88 46
46
46 45 6
46 45 6
G
D
S
GND
OUTIN
OUT
IN
BI
OUT
G
D
S
OUT
ININ G
D
S
G
D
S
CD
GNDNC
OUTIN
G
D
SIN
G
D
S
OUT
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
SMC PROCHOT 3.3V LEVEL SHIFTING
SMC AVREF Supply
518S0665
SMC Crystal Circuit
SMC Reset Button / Brownout Detect
UNUSED TP/NC ALIASES
PORT D ANALOG SENSORS (INTERNAL PULLUPS)
PORT 7 ANALOG SENSORS
POWER BUTTON
FROM DIMMS
TO/FROM SMC
1.3uA
NC
5uA
TO SMCTO CPU
FROM SMC
PULL-UP ON PAGE 14
SMC & MXM THERMTRIP LEVEL SHIFTING
FROM MXM FROM SMC
MISC. SIGNAL ALIASES
TO CPU
PM_EXTTS_L / MEM_EVENT LEVEL SHIFTING
50 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
SMC_CASE_OPEN
PM_SLPS3_BUF2_L
PM_SLPS3_BUF1_LMAKE_BASE=TRUEPM_SLP_S3_L
SMC_FAN_3_CTL
SMC_FAN_3_TACH
USB_DEBUGPRT_EN_L
MEM_EVENT_B_L
MAKE_BASE=TRUENC_ALS_RIGHT
SMC_CPU_1V8_VSENSEMAKE_BASE=TRUE
POWER_BUTTON_L
MIN_NECK_WIDTH=0.2 mm
PP3V3_G3H_AVREF_SMC
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.4 mm
SMC_XTAL
SMC_MANUAL_RST_L
SMC_PA0
SMC_TCK
SMC_EXCARD_OC_L
=PP3V3_G3H_SMC
GND_SMC_AVSS
SMC_TDI
MAKE_BASE=TRUESMC_CPU_VTT_ISENSE
MAKE_BASE=TRUETP_SMC_RSTGATE_L
SMC_SYS_LED
NC_ALS_LEFTMAKE_BASE=TRUE
SMC_BC_ACOK
SMC_PBUS_VSENSE
MAKE_BASE=TRUESMC_CPU_1V5_VSENSE
PM_SLP_S4_2_L MAKE_BASE=TRUE
SMC_DIMM_1V5_VSENSEMAKE_BASE=TRUE
MAKE_BASE=TRUESMC_CPU_1V8_ISENSE
MAKE_BASE=TRUETP_SMC_P41
SMC_RSTGATE_L
GND_SMC_AVSS
MAKE_BASE=TRUENC_ALS_GAIN
NO_TEST=TRUE
=PP3V42_G3H_AVREF
=PPSPD_S0_MEM_A
MAKE_BASE=TRUEMEM_EVENT_A_L
MEM_EVENT_L
=PP3V3_S0_SMC
=PP3V3_G3H_SMC
SMC_ONOFF_L
SMC_EXTAL
VOLTAGE=0VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 mmGND_SMC_AVSS
SMC_RESET_L
CPU_PROCHOT_L_R
SMC_PROCHOT
MXM_THRMTRIP_L PM_THRMTRIP_L
=PP3V3_S0_SMC_LS
MXM_THRMTRIP
MXM_OVERT_LSMC_THRMTRIP
SMC_PROCHOT_3_3_L
CPU_PROCHOT_BUF
=PPVTT_S0_CPU
=PP3V3_S0_SMC_LS
SMC_DCIN_ISENSE
SMC_BATT_ISENSE
SMS_X_AXIS
SMS_Z_AXIS
SMS_Y_AXIS
MAKE_BASE=TRUESMC_CPU_VTT_VSENSESMC_NB_MISC_ISENSE
SMC_NB_CORE_ISENSE
SMC_ANALOG_ID
MAKE_BASE=TRUESMC_DIMM_1V5_ISENSESMC_NB_DDR_ISENSE
ALS_LEFT
ALS_RIGHT
MEM_EVENT
PM_EXT_TS_L<0>
PM_EXT_TS_L<1>
=PPVTT_S0_CPU
MAKE_BASE=TRUESMC_CPU_1V5_ISENSE
MAKE_BASE=TRUESMC_CPU_INPUT_ISENSE
MAKE_BASE=TRUESMC_CPU_INPUT_VSENSE
SMS_ONOFF_L
ALS_GAIN
SMC_P41
SMC_EXCARD_PWR_EN
SMC_PF5
SMC_PB3
ESTARLDO_EN
MAKE_BASE=TRUETP_SMS_ONOFF_L
TP_SMC_EXCARD_PWR_ENMAKE_BASE=TRUE
TP_SMC_SYS_LEDMAKE_BASE=TRUE
MAKE_BASE=TRUETP_SMC_PF5
TP_SMC_PB3MAKE_BASE=TRUE
MAKE_BASE=TRUETP_ESTARLDO_EN
CPUIMVP_VR_ON
SMC_GFX_THROTTLE_L
SMC_GFX_OVERTEMP_L
SMC_DELAYED_PWRGDMAKE_BASE=TRUE
MAKE_BASE=TRUEMXM_PWR_LEVEL
MAKE_BASE=TRUEMXM_ALERT_L
CPU_PROCHOT_L
=PP3V3_S0_SMC
SMC_ONOFF_L
SMC_PH2
SMC_PNL_BL_PWM
SMC_TX_L
SYS_ONEWIRE
SMC_TMS
SMC_BS_ALRT_L
SMC_TDO
SMC_BIL_BUTTON_L
SMC_ADAPTER_EN
SMC_LID
G3_POWERON_L
SMC_GFX_OVERTEMP_L
SMC_SMS_INTMAKE_BASE=TRUE
=SMC_SMS_INT
SMC_RX_L
SYNC_MASTER=K60_JERRY SYNC_DATE=07/01/2009
SMC Support
Intersil ISL60002-33353S1381 ALL353S1912
16VCERM
0.01UF
402
10%
C5001 1
2
402
22PF
5%
CERM50V
C5021
1 2
22PF
CERM402
5%50V
C5020
1 2
46 45
SILK_PART=SYS POWER
SM
DEVELOPMENT
NTC020-CC1J-B260TS50101 2
3 4
SILK_PART=SMC RESET
NTC020-CC1J-B260T
DEVELOPMENT
SM
S50001 2
3 4
1/16WMF-LF402
5%
10KR5003
12
1/16W5%
10K
402MF-LF
R500412
402
5%
MF-LF1/16W
10KR5002
12
10K
1/16W5%
402MF-LF
R500112
MF-LF1/16W
10K4025%
R5093 1 2
1/16W
NOSTUFF
MF-LF
5%
0
402
R50791 2
402
5%10K1/16WMF-LF
R50851
2
5% 1/16W
10K402MF-LF
R5086 1 2
SOT-3632N7002DW-X-G
NOSTUFF
Q50806
2
1
402
10K5%1/16WMF-LF
R50831
2
402MF-LF1/16W5%10K
NOSTUFF
R50821
2
31 30
1/16W
402MF-LF
5%10K
R50801
2NOSTUFF
2N7002DW-X-GSOT-363
Q50803
5
4
402
10KMF-LF1/16W5%
R5087 1 2
CRITICAL
M-RT-SM53261-8602
SILK_PART=PWR BTNJ5010
3
4
1
2
NCP303LSN
CRITICAL
SOT23-5-HF
U5000
5
3
24
1
MXM
10K5%1/16WMF-LF402
R50681
2
1/16WMF-LF402
5%3.3K
MXM
R50691
2SOT-3632N7002DW-X-G
MXM
Q5096
3
5
4
2N7002DW-X-G
MXM
SOT-363
Q5096
6
2
1
5% 402
10K1/16W MF-LF
R5099 1 2
MXM
402
0
5%
MF-LF1/16W
R50181 2
74 45
91 21 11
SOT-3632N7002DW-X-GQ5095
6
2
1
5% MF-LF 4021/16W
10KR5098 1 2MF-LF1/16W 402
10K5%
R5049 1 2
10K5% 1/16W 402MF-LF
R5047 1 2
100K5% 4021/16W MF-LF
R5097 1 24021/16W MF-LF5%
100KR5095 1 2
10K402MF-LF5% 1/16W
R5092 1 2
1/16W
100K5% MF-LF 402
R5089 1 2
MF-LF5%
10K4021/16W
R5096 1 2
1/16WMF-LF402
1K5%
R50001
2
10K5% MF-LF 4021/16W
R5091 1 2
45
11
4705%
MF-LF1/16W
402
R50781
23.3K5%
MF-LF402
1/16W
R50701
2
MMDT3904-X-GSOT-363-LF
Q50775
3
4
3.3K
402
5%1/16WMF-LF
R50711 2
SOT-363-LFMMDT3904-X-GQ5077
2
6
1
5% 4021/16W MF-LF
10KNO STUFF R5043 1 2
5%
MF-LF1/16W
402
1KR5010
1 2
10V
0.1UF20%
CERM402
C50101
2
45
91 47 45
1/16W5% 402MF-LF
100KR5094 1 2
SM-4
CRITICAL
20.000MY5020
1
21/16W
10K5% 402MF-LF
R5046 1 2
10K5% MF-LF 4021/16W
R5042 1 2
10K5% MF-LF 4021/16W
R5041 1 2
10K5% 1/16W 402MF-LF
R5040 1 2
10K5% 4021/16W MF-LF
R5039 1 2
100K5% MF-LF1/16W 402
R5038 1 2
2.0K1/16W MF-LF5% 402
R5037 1 21/16W MF-LF 402
100K5%
R5036 1 25% 402
10KMF-LF1/16W
R5035 1 2
10K5% 402MF-LF1/16W
R5034 1 2402MF-LF1/16W5%
100KR5033 1 2MF-LF1/16W
10K5% 402
R5032 1 2
SOT23-3REF3333
CRITICAL
VR5065
3
1 2
20%10uF
603
6.3VX5R
C5066 1
2
0.01UF
16V
402CERM
10%
C50671
26.3V10%
CERM-X5R402
0.47UFC50651
2
SOT-3632N7002DW-X-GQ5095
3
5
4
402
10V20%
0.1uF
CERM
C5000 1
2
45
45 6
80
91 63 62 37 33 32 19 5
45
45
45 43
45
88 49
89 45
88 45
45
47 45
46 45 6
88 50 49 46 45
47 45
88 49
45
45
45
88 49
91 45 19
88 50
88 49
45
88 50 49 46 45
6
30 6
45
50 49 46 6
46 45 6
88 45
88 50 49 46 45
51 46 6
64 46 16 13 11 6
51 46 6
45
45
45
45
45
88 49 45
45
45
88 50 45
45
45
91 11
91 11
64 46 16 13 11 6
88 49
88
88
45
45
45
45
45
45
45
45
45
46 45
91 63
74
74
50 49 46 6
46 45
45
81 45
47 45 43
45
47 45
45
47 45
45
45 19
45
45
46 45
45
47 45 43
IN
IN
OUT
OUT
IN
IN
OUT
OUT
OUT
IN
BI
IN
BI
OUT
OUT
OUT
OUT
OUT
OUT
IN
BI
IN
IN
OUT
BI
BI
IN
INOUT
INOUT
OUTIN
OUT
OUT
VER 1
VCC
A
1
0
B1
GND
B0
SEL
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
LPC+SPI Connector
Pull-up on debug card
SPI Bus Series Resistance Option
FRANK CONNECTOR
Alternate SPI ROM Support
516S0573
51 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
SMC_MD1
MAKE_BASE=TRUESPIROM_USE_MLB
SPI_CS0_R_L
=PP3V3_S5_LPCPLUS
SMC_RX_L
SMC_TCK
SPI_CLK_R
SPI_ALT_MOSI
SPI_ALT_MISO
=PP3V3_S5_LPCPLUS
SPI_MOSI_R
SPI_MISO
SMC_RESET_LSMC_NMI
SPI_ALT_MISO
SMC_TMSDEBUG_RESET_LSMC_TDO
SPI_ALT_CLK
SMC_TDILPC_PWRDWN_L
SPI_ALT_CLK
LPC_AD<3>
LPC_FRAME_LPM_CLKRUN_L
SPI_ALT_CS_L SPI_CS0_L
=PP3V3_S5_ROM
SPI_MLB_CS_L
LPC_AD<0>
LPC_SERIRQSPI_ALT_CS_L
SPIROM_USE_MLB
LPC_AD<2>LPC_CLK33M_LPCPLUS
LPCPLUS_GPIO
SPI_ALT_MOSI
LPC_AD<1>
SMC_TX_L
SMC_TRST_L
=PP5V_S0_LPCPLUS=PP3V3_G3H_LPCPLUS
LPC+SPI Debug ConnectorSYNC_DATE=07/01/2009SYNC_MASTER=K60_SIJI
PLACEMENT_NOTE=PLACE NEXT TO U51001/16W
402
0
MF-LF
5%
PRODUCTION
R51461 2
20K5%
1/16WMF-LF
402
R51441
2NC7SB3157P6XG
CRITICAL
SC70PATH=I96
LPCPLUS
U5100
43
1
2
6
5
85 54
85 47
100K
1/16W5%
402MF-LF
R51401
2
85 47
LPCPLUS
0
MF-LF
5%1/16W
402
PLACEMENT_NOTE=Place next to R6105
R51581 2 85 54 18
85 47
LPCPLUS
1/16W5%
MF-LF
0
402
PLACEMENT_NOTE=Place next to R6152
R51571 2 85 54 18
85 47
1/16W
0
MF-LF
5%PLACEMENT_NOTE=Place next to R6150
402
LPCPLUS
R51561 2 85 54 18
85 27
85 45 18
85 45 18
85 47 21
85 47
85 47
45 18
45 19
46 45
46 45
91 46 45
45
46 45 43
21
M-ST-SM
LPCPLUSCRITICAL
55909-0374J5100
1
10
11 12
13 14
15 16
17 18
19
2
20
21 22
23 24
25 26
27 28
29
3
30
31 32
33 34
4
5 6
7 8
9
85 45 18
85 47
85 45 18
85 45 18
85 47
91 45 19 15
46 45
91 27
45
46 45
45
46 45 43
85 18
1/16W
0
MF-LF
5%
402
LPCPLUS
PLACEMENT_NOTE=Place near U1400
R51451 2
CERM402
20%10V
0.1UFC51441
2
85 47 21
47 6
47 6
85
54 6
6
6
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
U9200
(WRITE: 0X92 READ: 0X93)
AC/DC PS TEMPSEMC1403-[1,2]: ACDC THRU J600
DIODE1: CPU
(WRITE: 0X9A READ: 0X9B)
EMC1402-2: U5535DIE TEMPS
Also reserve 0x56 and 0x32 per spec
SMC "A" SMBus ConnectionsNOTE: SMC RMT BUS REMAINS POWERED AND MAY BE ACTIVE IN S3 STATE
REMOTE TEMPS
SMC "B" SMBus Connections
U6808
CK505U2600
U4900
(MASTER)
NV INSIDE (WRITE: 0X9E READ: 0X9F)
(MASTER)
U1800
(SLAVE)
PCH
(MASTER)
SMCU4900
MXM CARD (WRITE: 0X98 READ: 0X99)
SMC "0" SMBus Connections
GPU ON CARD - J8400
MXM TEMP
XDP
(MASTER)
(WRITE: 0X72 READ: 0X73)
MIKEY
(WRITE: 0XA6 READ: 0XA7)
J3100-A/B
J3200-A/B
PCHU1800
U2910
MEMORY B VREF
(WRITE: 0X7C READ: 0X7D)
U2900
SMC
(MASTER)
SMCU4900
(MASTER)
SMCU4900
(MASTER)
U1800
PCH
5
DIODE
2
1
4
3
EMC1047-2 HEX DIODE SENSOR
AMBIENT TEMP
LCD TEMP
ODD TEMP
FUNCTION
INA219: ACDC THRU J600
(WRITE: 0X80, READ: 0X81))
AC/DC PS POWER
OUTPUT VOLTAGE, CURRENT, POWER
(MASTER)
U4900
SMC
MXM HEATSINK
CPU HEATSINK
J2500/J2550
(WRITE: 0X90 READ: 0X91)
PCH "SML 1" CONNECTIONS
PCH "SMBUS" CONNECTIONS
(WRITE: 0X5C READ: 0X5D)
MEMORY A VREF
MEMORY A DIMMS
(Write: 0xA0 Read: 0xA1)
MEMORY B DIMMS
(WRITE: 0XA2 READ: 0XA5)
(WRITE: 0XA4 READ: 0XA3)
3 SENSE POINTS - PRIMARY, SECONDARY, AMB
(WRITE: 0X98 OR 0X9A, READ: 0X99 OR 0X9B)
PCH "SML 0" CONNECTIONS
POTENTIAL SMC SLAVE SMBUS CONNECTIONS
SMC SLAVE ADDRESS TBD
DP RX MASTER FOR MCCS
ALS(WRITE: 0X72 READ: 0X73)
EMC1047-2, U5500, SEE TABLE
(WRITE: 0X90 READ: 0X91)
DISPLAY TCONNOSTUFF RESISTORS ON PAGE 90
THIS CONNECTION IS BROKEN THROUGH
(WRITE: 0XD2 READ: 0XD3)
(WRITE: 0X9C READ: 0X9D)
U9100
DP RX EQLZ CONTROL
DP TX EQLZ CONTROL
SMC "MANAGEMENT" SMBUS CONNECTIONS
52 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
=I2C_DP_DRV_SCL
=I2C_DP_DRV_SDA
=I2C_DP_EQLZ_SCL
=PP3V3_S0_SMBUS_SMC_MGMT
MAKE_BASE=TRUESMBUS_SMC_0_S0_SCL
=SMB_CPU_THRM_SDA
=SMB_CPU_THRM_SCL
MAKE_BASE=TRUESMBUS_PCH_DATA
MAKE_BASE=TRUESMBUS_SMC_A_S3_SCL TP_I2C_ALS_SCL
SMB_MGMT_DATA
SMB_MGMT_CLK
=SMB_MXM_THRM_SCL
MAKE_BASE=TRUESMBUS_SMC_0_S0_SDA
=I2C_SODIMMA_SCL
=SMBUS_CK505_SDA
=PP3V3_S3_SMBUS
SMB_0_S0_DATA
SMB_0_S0_CLK
=SMB_MXM_THRM_SDA
MAKE_BASE=TRUESML_PCH_1_DATAMAKE_BASE=TRUESML_PCH_1_CLK
=PP3V3_S0_SMBUS
=PP3V3_S0_SMBUS_SMC_0_S0
=SMBUS_XDP_SCL =SMBUS_CK505_SCL
=I2C_AUDIO_SDA
=I2C_AUDIO_SCL
=I2C_SODIMMB_SDA
=I2C_SODIMMB_SCL
=I2C_VREFMRGN_B_SDA
=I2C_VREFMRGN_B_SCL
=I2C_VREFMRGN_A_SDA
=I2C_VREFMRGN_A_SCL
=PP3V3_S0_SMBUS
=PP3V3_S0_SMBUS_SMC_B_S0
SMBUS_SMC_B_S0_SCLMAKE_BASE=TRUE
SMB_A_S3_CLK
SMB_A_S3_DATAMAKE_BASE=TRUESML_PCH_0_CLK
=PP3V3_S0_SMBUS
SMB_B_S0_CLK
SMB_B_S0_DATA
=SMB_ACDC_SDA
=SMB_ACDC_SCL
=SMB_REMOTE_TEMP_SDA
=SMB_REMOTE_TEMP_SCL
SMB_BSA_CLK
SML_PCH_0_DATAMAKE_BASE=TRUE
=SMBUS_XDP_SDA
=I2C_SODIMMA_SDA
SMBUS_PCH_CLKMAKE_BASE=TRUE
MAKE_BASE=TRUESMBUS_PCH_S0_CLK
PGOOD_P3V3_S0
SMBUS_PCH_S0_DATAMAKE_BASE=TRUE
SMBUS_SMC_B_S0_SDAMAKE_BASE=TRUE
SMBUS_SMC_BSA_SCLMAKE_BASE=TRUE
TP_I2C_ALS_SDA
=PP3V3_S3_SMBUS_SMC_A_S3
SMB_BSA_DATAMAKE_BASE=TRUESMBUS_SMC_BSA_SDA =SMB_DP_TCON_SDA
=SMB_DP_TCON_SCL
MAKE_BASE=TRUESMBUS_SMC_A_S3_SDA
=PP3V3_S0_SMBUS_SMC_BSA
SMBUS_SMC_MGMT_SCLMAKE_BASE=TRUE
=I2C_DP_EQLZ_SDASMBUS_SMC_MGMT_SDAMAKE_BASE=TRUE
SYNC_DATE=07/01/2009SYNC_MASTER=K60_JERRY
SMBus Connections
1/16W
402MF-LF
5%4.7KR52711
2MF-LF1/16W
4.7K5%
402
R52701
2
NOSTUFF
SOT23-3-HFSI2302ADSE3Q5200
3
1
2
NOSTUFF
SOT23-3-HFSI2302ADSE3Q5201
3
1
2
MF-LF402
05%1/16W
R52111
2
1/16W
402MF-LF
5%0
R52101
2
MF-LF1/16W
5%3.3K
402
R52081
2
MF-LF1/16W5%3.3K
402
R52091
2
1/16WMF-LF
0
5%
402
R52071 2
1/16WMF-LF402
5%
0R52061 2
8.2K
NOSTUFF
5%
402
1/16WMF-LF
R52051
2
8.2K5%
402
1/16WMF-LF
NOSTUFF
R52041
2
402MF-LF1/16W
8.2K5%
R52021
2
8.2K5%1/16WMF-LF402
R52031
2
1/16W
402
5%
MF-LF
4.7KR52501
2
1/16WMF-LF
5%
402
4.7KR52511
2
MF-LF
2.2K
1/16W5%
402
R52601
2
2.2K
1/16W5%
402MF-LF
R52611
2
4.7K
MF-LF1/16W
5%
402
R52901
2
4.7K5%1/16W
402MF-LF
R52911
2
100K
MF-LF
5%
402
1/16W
R52811
2
100K
1/16W5%
MF-LF402
R52801
2
402
6.8K5%
NOSTUFF
MF-LF1/16W
R52011
2402
6.8K
MF-LF
5%1/16W
NOSTUFF
R52001
2
78
78
79
6
88
51
51
88 18
88
45
45
74
88
30
26
6
45
45
74
88 18
88 18
48 6
6
25 26
61
61
31
31
28
28
28
28
48 6
6
88
45
45
88 18
48 6
45
45
6
6
51
51
45
88 18
25
30
88 18
88
91 72 63
88
88
88
6
45 88 77
77
88
6
88
79 88
OUT
IN
V+
REFIN+
IN- OUT
GND
OUTIN-
IN+ REF
V+
GND
OUT
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
CPU 1.5V VOLTAGE SENSE
GAIN = 200V/V353S2073
IMAX = 6A
CPU VTT VOLTAGE SENSE
AMPLIFIED AND FILTERED ISNS TO SMC
IMAX = 2.79V
IMAX = 35A
GAIN = 100V/V
353S2208
WOULD PREFER A GAIN OF 150V/V
PLACE R CLOSE TO CPU
CPU Voltage Sense / Filter
IMAX = 0.9V
PLACE C CLOSE TO SMC
CPU CURRENT SENSE AMP & FILTER
PCB: PLACE R5364, C5362 WITHIN 1" OF SMC (U4900)
CPU 1.8V CURRENT SENSE
CPU 1.5V CURRENT SENSE
CPU VTT CURRENT SENSE
CPU 1.8V VOLTAGE SENSE
IMAX = 1.35A
53 OF 110
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<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
GND_SMC_AVSS
SMC_CPU_1V5_ISENSE_R
=PP3V3_S0_SMC
SENSE_CPU_1V5_N
GND_SMC_AVSS
SMC_CPU_1V5_VSENSE
PP1V5_CPU_MEMPP1V5_S3_REG
SENSE_CPU_1V5_S3_P
CPU_VTTSENSE_P SMC_CPU_VTT_VSENSE
GND_SMC_AVSS
PPVTT_S0_CPU_REG
SENSE_CPU_VTT_N
=PP3V3_S0_SMC
GND_SMC_AVSS
GND_SMC_AVSS
SMC_CPU_VTT_ISENSE
GND_SMC_AVSS
SMC_CPU_ISENSE
SNS_PS_CPU_ISNS
SMC_CPU_VTT_ISENSE_R
PP1V5_S0_FET
SENSE_CPU_1V5_S0_P
SENSE_CPU_1V5_S0_N
GND_SMC_AVSS
SMC_CPU_VSENSECPU_VCC_PKG_SENSE_P
=PP5V_S0_ISENSE
VR_ISNS_CPU_PVR_CPU_IMON
VR_ISNS_CPU_N
SMC_CPU_1V8_VSENSE
SENSE_CPU_1V5_P
SMC_CPU_1V5_ISENSE
SENSE_CPU_1V5_S3_N
PPVTT_S0_CPU
SENSE_CPU_VTT_P
SMC_CPU_1V8_ISENSE
GND_SMC_AVSS
PP1V8_S0_CPU
PP1V8_S0_REG
CPU POWER SENSESYNC_DATE=07/01/2009SYNC_MASTER=K60_JERRY
X5R
0.22UF20%6.3V
402
C53591
2
MF-LF
4.53K
402
1%1/16W
R53591 2 88 45
1/8W5%
0
805MF-LF
R53201 2
0612
1%1WMF
0.0005R5319
12
34
0
MF-LF1/16W
5%
402
R53061
2MF-LF
5%01/16W
402
R53051
2
NOSTUFF
1/16W
402
5%
MF-LF
0R53081
2
1/16W
NOSTUFF
402MF-LF
05%
R53071
2
NOSTUFF
1%1/4WMF-LF1206
0.002R5309
1 2
3 4
402
10K5%
1/16WMF-LF
R53241
2
CRITICAL
SC70INA214U5310
2
5
4
6
1
3
NOSTUFF
MF-LF
5%10K
402
1/16W
R53031
2
0.22UF6.3V20%
402X5R
C53221
2
4.53K
MF-LF1/16W1%
402
R53221 2
0.22UF20%
402X5R6.3V
NOSTUFF
C53211
2
0.22UF20%
402X5R6.3V
C53121
2
4.53K
1%
MF-LF1/16W
402
R53121 2
4.53K
1%
402
1/16WMF-LF
R53111 2
402X5R6.3V20%0.22UFC53101
2
0.22UF20%
402X5R6.3V
C53111
2
402
20%6.3VX5R
0.22UFC53021
2
1/16WMF-LF402
4.53K
1%
R53021 2
MF-LF1/16W
4.53K
402
1%
R53011 2
0.22UF
X5R
20%6.3V
402
C53001
2
0.002
1206MF-LF1/4W1%
R5300
1 2
3 4
X5R402
0.22UF6.3V20%
C53011
2
SC70INA210U5300
2
5
4
6
1
3
1/16W1%
MF-LF402
10KR53611
2
SC70-5OPA348
CRITICAL
U5360
3
1
4
2
589 64
1%1/16WMF-LF402
10KR53601 2
MF-LF1/16W
21K
402
1%
R53631 2
402
16V20%
0.01UF
CERM
C5360
1 2
5.1K
MF-LF1/16W5%
402
R53641 2
CERM-X5R
10%0.22UF6.3V
402
C53621
2
88 45
88 50 49 46 45
88
50 49 46 6
88
88 50 49 46 45
88 46
89 6 70 50 6
88
89 67 13 88 46
88 50 49 46 45
67 6
88
50 49 46 6
88 50 49 46 45
88 50 49 46 45
88 46
88 50 49 46 45
88
88
72 6
88
88
88 50 49 46 45
89 64 13
6
88
88
88 46
88
88 46
88
89 6
88
88 46
88 50 49 46 45
89 6
70 6
V+
REFIN+
IN- OUT
GND
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
1.5V S3 VOLTAGE SENSE
IMAX = 11.3A
MXM PWRSRC CURRENT SENSE MXM PWRSRC VOLTAGE SENSE
IMAX = 6A
353S2073
GAIN = 200V/V
PLACE RC CLOSE TO SMC
54 OF 110
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B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
PP1V5_S3_REG
GND_SMC_AVSS
SMC_DIMM_1V5_ISENSE
SMC_DIMM_1V5_VSENSE
GND_SMC_AVSS
MAKE_BASE=TRUEPPV_S0_MXM_PWRSRC
MXM_ISENSE_P
MXM_ISENSE_N SMC_GPU_ISENSE
GND_SMC_AVSS
SMC_MXM_ISENSE_R
=PP3V3_S0_SMC
SMC_GPU_VSENSE
GND_SMC_AVSS
=PPV_S0_MXM_PWR
=PPV_S0_MXM_PWRSRC
GRAPHICS / DIMM POWER SENSESYNC_MASTER=K60_JERRY SYNC_DATE=07/01/2009
0.22UF20%
402X5R6.3V
C54021
2
MF-LF1/16W
402
4.53K
1%
R54021 2
INA210SC70
MXM
U5430
2
5
4
6
1
3
CRITICAL
1206MF1/4W1%
0.002
MXM
R5430
1 23 4
MXM
402X5R6.3V20%0.22UFC54301
2
MXM
MF-LF1/16W
402
4.53K
1%
R54311 2
NOSTUFF
402
10K5%
1/16WMF-LF
R54321
2
MXM
0.22UF20%
402X5R6.3V
C54311
2
MF-LF1/16W
1%6.04K
402
R54341
2
MXM
0.22UF6.3VX5R402
20%
C54321
2
MXM
MF-LF1/16W1%
18.2K
402
R54331 2
MF-LF
5%10K
402
1/16W
R54031
2
70 49 6
88 50 49 46 45
88 46
88 46
88 50 49 46 45
89
88
88 88 45
88 50 49 46 45
88
49 46 6
88 45
88 50 49 46 45
6
73
DP2/DN3
DN2/DP3
DP1/DN6
DN1/DP6
GND
SMDATA
SMCLK
DN4/DP5
DP4/DN5
VDD
GND
V+
OUT
OUT
DN2/DP3
DP1
DN1
DP2/DN3
SMCLKGND
THERM*
SMDATA
VDD
ALERT*
BI
BI
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
518S0698
518S0677
is on csa 70 with power sequencingpower/gnd and ref for this dual part
Must pull high to 2.5V for compatibility with all drives
Cannot pull low because some drives use this bit todetermine 1.5 Gbps vs. 3.0 Gbps SATA
Drive disconnected = pulled highDrive asleep = HDD drives HDD_OOB_TEMP lowDrive active = valid signal protocol
FROM DRIVE:
LOW: -0.3V TO 0.5V
HIGH: 2.0V TO 3.6V
TO SMC
518S0678
SENSOR CH4
518S0678
SENSOR CH5
HDD OUT OF BAND TEMPERATURE SENSING LEVEL SHIFTINGREMOTE THERMAL SENSORS (HEATSINKS AND ODD)
353S2224
CPU T-DIODE THERMAL SENSOR
Chan-1 is not used
I2C Address is 9A/9B
PLACE HSK SENSOR CONN. TOP SIDE NEAR MXM OR CPU
518S0698
REMOTE THERMAL SENSORS
518S0698
SENSOR CH2
SENSOR CH6SENSOR CH1
SENSOR CH3
518S0665
HEATSINKS, AMBIENT, PANEL AND ODD
55 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
HDD_OOB_TEMP_FILT
SNS_LCD_N
SNS_AMB_P
SMC_EXCARD_CPMAKE_BASE=TRUESMC_HDD_OOB_TEMP
=PP3V3_S0_SMC_LS
HDD_OOB_TEMP_R
1V60_COMP_REF
SNS_T_DP4_DN5
=SMB_REMOTE_TEMP_SDA
SNS_MXM_N
SNS_MXM_P
=SMB_REMOTE_TEMP_SCL
SNS_T_DP4_DN5
SNS_T_DP2_DN3
SNS_T_DN2_DP3SNS_T_DP2_DN3
SNS_T_DN2_DP3
SNS_CPU_H_N
SNS_T_DN4_DP5
SNS_CPU_H_P
DIFFERENTIAL_PAIR=SNS_T2SNS_T_DN2_DP3
DIFFERENTIAL_PAIR=SNS_T3SNS_T_DP4_DN5
DIFFERENTIAL_PAIR=SNS_T2SNS_T_DP2_DN3
SNS_T_DN1_DP6DIFFERENTIAL_PAIR=SNS_T1
PP3V3_S0_TSENS_RVOLTAGE=3.3V
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mm
HDD_OOB_TEMP
=PP3V3_S0_TSENS
DIFFERENTIAL_PAIR=SNS_T3SNS_T_DN4_DP5
CPU_THMSNS_ALERT_L
=SMB_CPU_THRM_SCL
=SMB_CPU_THRM_SDA
CPU_THMSNS_THERM_L
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
PP3V3_S0_CPU_THMSNS
SNS_CPU_THERMD_N
SNS_CPU_THERMD_P
=PP3V3_S0_TSENS
SNS_T_DN1_DP6
SNS_ODD_P
SNS_T_DP1_DN6
SNS_T_DN1_DP6SNS_T_DP1_DN6
SNS_T_DN4_DP5
SNS_T_DP1_DN6DIFFERENTIAL_PAIR=SNS_T1
SNS_LCD_P
SNS_SKIN_PSNS_ODD_N SNS_SKIN_N
SNS_AMB_N
SYNC_MASTER=K60_JERRY SYNC_DATE=07/01/2009
Thermal Sensors
CRITICAL
SILK_PART=SKIN TEMP
M-RT-SM53261-8602J5560
3
4
1
2
0402
FERR-220-OHML5564
1 2
FERR-220-OHM
0402
L5563
1 2
402
CPU_TDIODE
10K
MF-LF1/16W5%
R55391
2402MF-LF1/16W
CPU_TDIODE
5%10KR55381
2
402MF-LF1/16W
5%
CPU_TDIODE
100KR55361
2SIGNAL_MODEL=EMPTY
CERM
0.0022UF10%
402
50V
NOSTUFF
C5536 1
2
48
48
CPU_TDIODE
EMC1403-2-AIZL
CRITICAL
TSSOP
U5535
83
5
2
4
6
10
9
7
1
88 10
88 10
CPU_TDIODE
10%
CERM
0.0022UF
402
50V
SIGNAL_MODEL=EMPTY
C5537 1
2
53780-8602
SILK_PART=LCD TEMP
CRITICAL
M-RT-SM
J5550
3
4
1
2
SILK_PART=LCD TEMP
53780-8602M-RT-SM
CRITICAL
J5520
3
4
1
2
M-RT-SM53780-8602
SILK_PART=ODD TEMP
CRITICAL
J5551
3
4
1
2
5%1/16WMF-LF
CPU_TDIODE
402
22R5535
1 2
CPU_TDIODE
X5R402-1
10%1UF
10V
C55351
2
10K
MF-LF1/16W5%
402
CPU_TDIODER5537
1
2
CRITICAL
SOI-HFLM393U7030
4
2
3
1
8
402
200K
1/16W5%
MF-LF
R55531
2
3.3K
1/16W5%
402MF-LF
R55501 2
402
62K
1/16W5%
MF-LF
R55541
2
402
1K5%1/16WMF-LF
R55511
2
TSSOP
EMC10472AIZL
CRITICAL
U55003
5
7
2
4
8
6
10
9
1
SILK_PART=AMBIENT TEMP
53780-8603M-RT-SM
CRITICAL
J5521
4
5
1
2
3
SILK_PART=MXM HSK
MXM
53398-8602
CRITICAL
M-ST-SM
J5511
3
4
1
2
0402
FERR-220-OHML5511
1 2
0402
FERR-220-OHML5510
1 2
0402
FERR-220-OHML5521
1 2
FERR-220-OHM
0402
L5520
1 2
M-ST-SM53398-8602
CRITICAL
SILK_PART=CPU HSKJ5510
3
4
1
2
0402
FERR-220-OHM
MXM
L5513
1 2
MXM
0402
FERR-220-OHML5512
1 2
FERR-220-OHM
0402
L5523
1 2
0402
FERR-220-OHML5522
1 2
FERR-220-OHM
0402
L5554
1 2
0402
FERR-220-OHML5553
1 2
0402
FERR-220-OHML5552
1 2
10%1UF
402-1X5R10V
C5501 1
2
402
22
1/16WMF-LF
5%
R55001 2
402CERM50V10%
0.0022UFC5502 1
2
50VCERM402
10%0.0022UFC5503 1
2
402
50VCERM
0.0022UF10%
C5504 1
2
92 88
92 88
92 88
45 88
46 6
88
63
88 51
48
88
88
48
88 51
88 51
88 51 88 51
88 51
88
88 51
88
88 51
88 51
88 51
88 51
89
88
51 6
88 51
51 6
88 51
92 88
88 51
88 51 88 51
88 51
88 51
92 88
92 88
92 88 92 88
92 88
G S
D
G S
D
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
518S0730
518S0730
MOTOR CONTROL
GND
TACH
MOTOR CONTROL
GND
FAN 1
NOTE: ADDED TO PROTECT SMC
HD FAN
FAN 0
12V DC
12V DC
ODD FAN
TACH
56 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
FAN_TACH0_L
PP12V_S0_FAN1_LMIN_LINE_WIDTH=0.5MM
VOLTAGE=12VMIN_NECK_WIDTH=0.25MM
VOLTAGE=12V
MIN_LINE_WIDTH=0.5MMPP12V_S0_FAN0_L
MIN_NECK_WIDTH=0.25MM
FAN_1_GNDMIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM
MIN_NECK_WIDTH=0.25MM
FAN_0_GNDMIN_LINE_WIDTH=0.5MM
SMC_FAN_1_CTL
FAN_TACH0
FAN_0_PWR
MIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.5MM
F1_GATESLOWDN
=PP3V3_S0_FAN
SMC_FAN_1_TACH
SMC_FAN_0_TACH
F1_VOLTAGE8R5
=PP3V3_S0_FAN
=PP3V3_S0_FAN
=PP3V3_S0_FAN
FAN_TACH1
F0_GATESLOWDN
=PP12V_S0_FAN
SMC_FAN_0_CTL
MIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.5MM
FAN_0_PWR_L
FAN_1_PWR
MIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM
FAN_TACH1_L
FAN_1_PWR_L
MIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM
F0_VOLTAGE8R5
=PP12V_S0_FAN
HD AND OD FANSYNC_MASTER=K60_DEREK SYNC_DATE=07/01/2009
CRITICAL
20%16VELEC6.3X5.5-SM1-HF
100UFC56051
2
16V10%2.2UF
603X5R
C56281
2
0
603MF-LF1/10W5%
PLACEMENT_NOTE=PLACE R5630 CLOSE TO J5601 Pin3
R56301
2
MF-LF1/10W5%0
603
PLACEMENT_NOTE=PLACE R5620 CLOSE TO J5600 Pin3
R56201
2
220-OHM-1.4A
0603
CRITICAL
L5640
1 2
CRITICAL
220-OHM-1.4A
0603
L5630
1 2
220-OHM-1.4A
0603
CRITICAL
L5620
1 2
220-OHM-1.4A
CRITICAL
0603
L5610
1 2
0402
FERR-220-OHM
CRITICAL
L5601
1 2
0402
CRITICAL
FERR-220-OHML5600
1 2
X5R603
10%16V
2.2UFC56081
2 16V20%0.01UF
402CERM
C56091
2
20%
CERM1206-1
16V
4.7UFC56061
2402
20%
CERM16V
0.01UFC56071
2
CRITICAL
M-RT-SM53780-8604J5600
5
6
1
2
3
4
CRITICAL
53780-8604M-RT-SM
J5601
5
6
1
2
3
4
20%
CRITICAL
16VELEC6.3X5.5-SM1-HF
100UFC56021
2
2N7002SOT23-HF1
Q56053
1
2
2N7002SOT23-HF1
Q56023
1
2
47K
5%1/16WMF-LF402
R56981 2
MF-LF
5%
47K
1/16W
402
R56991 2
10K
MF-LF402
5%1/16W
R56111
2 1/4W
1206
5%
MF-LF
1.5KR56101
2
MMBD914XGSOT23
D5601
1
3
3.9K
MF-LF1/8W5%
805
R56091 2
16VX7R805
10%0.47UFC56031
2
805MF-LF
5%1.5K1/8W
R56071
2
NTHS5443T1H
CRITICAL
1206A-03-HF
Q5603
1 2 3 6 7 8
4
5
5%
402
10K1/16WMF-LF
R56061
23.9K
MF-LF
5%1/8W
805
R56051 2
805
16V10%
X7R
0.47UFC56011
2
SOT23
MMBD914XGD5600
1
3
805
5%1/8W
MF-LF
1.5KR56031
2
NTHS5443T1H
CRITICAL
1206A-03-HF
Q5600
1 2 3 6 7 8
4
51206MF-LF1/4W
1.5K5%
R56021
2
MF-LF
5%10K1/16W
402
R56011
2
402MF-LF1/16W
10K5%
R56001
2
92
92 89
92 89
92
92
45
53 52 6
45
45
53 52 6
53 52 6
53 52 6
53 52 6
45
92
92
92
53 52 6
G S
D
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
518S0730
CPU FAN
MOTOR CONTROL
FAN 2
12V DC
TACH
GND
57 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
PP12V_S0_FAN2_L
MIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.5MM
VOLTAGE=12V
FAN_TACH2_L
=PP12V_S0_FAN
F2_VOLTAGE8R5
FAN_TACH2
SMC_FAN_2_CTL
=PP3V3_S0_FAN
SMC_FAN_2_TACH
=PP3V3_S0_FAN
F2_GATESLOWDN
MIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.5MM
FAN_2_PWR
FAN_2_GNDMIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
FAN_2_PWR_L
MIN_NECK_WIDTH=0.25MM
CPU FANSYNC_MASTER=K60_DEREK SYNC_DATE=07/01/2009
402MF-LF1/16W5%
47KR57971 2
1/16W5%
402
10K
MF-LF
R57051
2 MF-LF1206
1.5K1/4W5%
R57041
2
805MF-LF
3.9K
5%1/8W
R57031 2
0.47UF10%16VX7R805
C57011
2
1/8W
805
5%1.5K
MF-LF
R57011
2
MMBD914XGSOT23
D57001
3
CRITICAL
1206A-03-HFNTHS5443T1HQ5700
1 2 3 6 7 8
4
5
10K5%
402MF-LF1/16W
R57001
2
CRITICAL
53780-8604M-RT-SM
J5700
5
6
1
2
3
4
PLACEMENT_NOTE=PLACE R5720 CLOSE TO J5700 Pin3
MF-LF
05%1/10W
603
R57201
2
220-OHM-1.4A
CRITICAL
0603
L5720
1 2
CRITICAL
220-OHM-1.4A
0603
L5710
1 2
CRITICAL
FERR-220-OHM
0402
L5701
1 2
20%16V
0.01UF
CERM402
C57091
220%16VCERM1206-1
4.7UFC57081
2
CRITICAL
6.3X5.5-SM1-HFELEC16V20%100UFC57021
2
2N7002SOT23-HF1
Q57023
1
2
92 89
92
52 6
45
53 52 6
45
53 52 6
92
92
OUTIN
IN IN
WP*
SI
HOLD*VSS
SCK
CE*
VDD
SO
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
61 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
SPI_CLK_R SPI_MOSI_R
SPI_MISO
SPI_CLK
SPI_MISO_RSPI_WP_L
SPI_MLB_CS_L
SPI_MOSI
=PP3V3_S5_ROM
SPI_HOLD_L
SYNC_MASTER=K60_SIJI
SPI ROMSYNC_DATE=07/01/2009
SST25VF032B
32MBIT
OMIT
CRITICAL
SOIC
U6100
1
7
6 5
2
84
3
PLACEMENT_NOTE=PLACE CLOSE TO U6100
MF-LF
5%1/16W
0
402
R61501 2
PLACEMENT_NOTE=PLACE CLOSE TO U6100
402
0
1/16W5%
MF-LF
R61521 2
0
1/16W5%
MF-LF402
R61051 2
85 47 18 85 47 18
85 47 85 47 18
402
3.3K
MF-LF
5%1/16W
R61001
2 402MF-LF
3.3K5%1/16W
R61011
2 402
20%
CERM
0.1UF10V
C6100 1
2
85
85
85
47 6
IN
IN
IN
IN
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
OUT
NR/FB
NC
IN
EN
GND
IN
OUT
IN
IN
OUT
IN
VL_HD
SENSE_A
GPIO1/DMIC_SDA2
GPIO0/DMIC_SDA1
VHP_FILT+
GPIO2
RESET*
LINEOUT_L1-
VBIAS_DAC
FLYP
VA_REFVD
GPIO3
VHP_FILT-
LINEOUT_R1-
LINEOUT_R1+
LINEOUT_R2-
SPDIF_OUT
LINEIN_C-
FLYC
FLYN
SPDIF_IN
LINEOUT_L1+
THRM_PAD
VA_HP
HPOUT_R
HPREF
VCOM
AGND
VA
LINEIN_R+
LINEIN_L+
MICIN_L+
MICIN_L-
MICBIAS
SYNC
DGND
DMIC_SCL
HPOUT_L
SDI
SDO
VL_IF
BITCLK
MICIN_R-
MICIN_R+
VREF+_ADC
LINEOUT_L2+
LINEOUT_L2-
LINEOUT_R2+
/SPDIF_OUT2IN
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
AUDIO CODEC
K23 LOW = S/PDIF IN, HIGH = DP SPDIF
APPLE P/N 353S2592
K22 = NC
NC
NC
NC
NC
NC
NCNC
DAC2/3 FSOUTPUTDIFF= 2.67VRMS
SE FSINPUT= 1.22VRMS
HP OUT ZOBEL NETWORK
DAC2/3 FSOUTPUTSE= 1.34VRMS
NC
APPLE P/N 353S2456
DIFF FSINPUT= 2.45VRMS
DAC1 FSOUTPUT= 1.34VRMS
4.5V POWER SUPPLY FOR CODEC
62 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
MIN_LINE_WIDTH=0.20MMMIN_NECK_WIDTH=0.10MM
4V5_REG_IN
VOLTAGE=4.5V
AUD_LO1_P_LTP_AUD_LO1_N_L
AUD_LO1_P_R
AUD_LI_COMMAKE_BASE=TRUE
AUD_LI_P_L
TP_AUD_LO1_N_R
AUD_LO2_P_RTP_AUD_LO2_N_R
TP_AUD_LO2_N_LCS4206_FLYP
PP4V5_AUDIO_ANALOG
AUD_LO2_P_L
CS4206_FLYN
AUD_MIC_INP_L
AUD_MIC_INN_RAUD_MIC_INP_R
AUD_SPDIF_OUT
GND_AUDIO_HP_AMP_L
GND_AUDIO_HP_AMP_L
MIN_LINE_WIDTH=0.30MMMIN_NECK_WIDTH=0.20MM
AUD_Z_L
AUD_LI_N_L
=PP3V3_S0_AUDIO
=PP5V_S0_AUDIO
AUD_HP_PORT_RMIN_LINE_WIDTH=0.30MMMIN_NECK_WIDTH=0.20MM
HDA_SDIN0AUD_LI_N_R
4V5_NR
AUD_Z_R
MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.30MM
AUD_HP_PORT_L
MIN_LINE_WIDTH=0.30MMMIN_NECK_WIDTH=0.20MM
AUD_GPIO_1
=PP5V_S0_AUDIO
MIN_NECK_WIDTH=0.20MM AUD_HP_PORT_RMIN_LINE_WIDTH=0.30MM
4V5_REG_EN
=PP3V3_S0_AUDIO
AUD_SPDIF_IN_CODEC
VOLTAGE=4.5V
MIN_LINE_WIDTH=0.20MMMIN_NECK_WIDTH=0.10MM
PP4V5_AUDIO_ANALOG
GND_AUDIO_CODEC
CS4206_FN
CS4206_FLYC
AUD_GPIO_3
VBIAS_DAC
VOLTAGE=4.5V
MIN_NECK_WIDTH=0.10MMMIN_LINE_WIDTH=0.20MM
PP4V5_AUDIO_ANALOG
=PP1V5_S0_AUD_DIG
GND_AUDIO_HP_AMP_L
AUD_MUX_CNTRL
AUD_GPIO_2
AUD_SENSE_A
AUD_CODEC_MICBIAS
TP_AUD_DMIC_CLK
CS4206_VREF_ADC
AUD_MIC_INN_L
CS4206_VCOM
AUD_LI_P_R
AUD_GPIO_1
CS4206_FP
=PP3V3_S0_AUDIO
AUD_HP_PORT_REFMIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM
MIN_NECK_WIDTH=0.20MM AUD_HP_PORT_LMIN_LINE_WIDTH=0.30MM
GND_AUDIO_CODEC
VOLTAGE=0VGND_AUDIO_HP_AMP_L
HDA_RST_LHDA_SDOUT
AUD_SDI_R
HDA_SYNC
HDA_BIT_CLK
GND_AUDIO_CODECMIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.2MMVOLTAGE=0V
AUD_SPDIF_CHIP
SYNC_DATE=07/16/2009SYNC_MASTER=K23_SKIP
AUDIO: CODEC/REGULATOR
402-1
1UF
X5R
10%10V
C62071
2
402-1
1UF
X5R
10%10V
C62021
2
10UF
X5R6.3V20%
603
C62051
2
55
CRITICAL
QFNCS4206ACNZCU6201
26
6
7
4
43
42
45
2
12
14
15
38
40
39
22
21
23
34
35
30
31
37
36
33
32
16
17
18
20
1911
8
5
13
47
48
10
49
25
46
24
29
28
9
41
44
3
1
27
X5R6.3V20%
10UF
603
C6204 1
2
1/16W
402
100K1%
MF-LF
R62951
2
81
85 59
56 55
56 55
X7R-CERM
0.1UF16V
402
10%
C6297 1
2
0.1UF
X7R-CERM
10%16V
402
C6298 1
2
402MF-LF1/16W
5%39
R62971
2MF-LF
5%39
402
1/16W
R62961
2
402
22
1/16W5%
MF-LF
R62571 2
55
61 60 59 58 57 55 6
EDUCATION
1/16WMF-LF
5%10K
402
R62981
2
MF-LF402
5%100K
BETTER
1/16W
R62991
2
16VX7R-CERM
402
10%0.1UF
C6266 1
2
CRITICAL
SONTPS71745VR6201
4
2
6
5
3
1
1UF
402-1
10%10VX5R
C6259 1
2
61 55 6
61 60 59 58 57 55 6
89 55
59
89 55
89 55
61 60 59 58 57 55 6
61 55 6
16V
10UF20%
CASE-B2-SMPOLY-TANT
C6260 1
2
CASE-B2-SM
16V20%
POLY-TANT
10UFC62621
2
CRITICAL
10UF
CASE-B2-SMPOLY-TANT
20%16V
C62631
2
X5R
10%10V
402
0.47UFC6261 1
2
402
5%
MF-LF
22
1/16W
R62541 2
NOSTUFF
100K5%
402MF-LF1/16W
R62671
2
NOSTUFF
MF-LF
05%
402
1/16W
R62631
2
402MF-LF
2.67K1/16W1%
R62551
2
X5R402
10%10V
0.47UFC6265 1
2
402
10VX5R
10%0.47UFC62581
2
0.47UF10%10VX5R402
C6264 1
2
402-1
1UF
X5R
10%10V
C62011
2
1/16WMF-LF402
1%
2.21KR62011 2
FERR-220-OHM
0402
L6201
1 2
56
56
20%
CRITICAL
6.3V
603X5R
10UFC62131
2
60
60
61
61
56
56
60
58
58
57
57
56 55
56 55
61 57
61 58 57
60
85 18
85 18
85 18
85 18
85 18
4.7UF4VX5R402
20%
C6203 1
2
20VTANT
1UF10%
CRITICAL
CASE-P3-HF
C6211 1
2
2.2UF
402-LF
20%6.3VCERM
C62081
26.3V
2.2UF
402-LF
20%
CERM
C6206 1
2
SMXW6201
1 2
89
59 56 55
59 56 55
91
61 60 58 57 56 55
6
59 56 55
81
61 60 58 57 56 55
59 56 55
85
61 60 58 57 56 55
85
IN
IN
OUT
OUT
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
CODEC Nom SE RIN = 20K OHMS
VIN = 2VRMS, CODEC VIN = 1.14 VRMS
1ST ORDER DAC FILTER PLACEHOLDER
FC = 5 HZ Max
NET RIN = 18K OHMS
63 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
AUD_LI_GND
MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MM
AUD_LI_RF
MIN_NECK_WIDTH=.2MMMIN_LINE_WIDTH=.3MM
AUD_LI_GND
MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MM
AUD_LI_LF
MIN_LINE_WIDTH=.3MMMIN_NECK_WIDTH=.2MM
AUD_LI_P_R
MIN_LINE_WIDTH=.3MMMIN_NECK_WIDTH=.2MM
MIN_LINE_WIDTH=0.3MM
AUD_LI_R
MIN_NECK_WIDTH=0.2MM
AUD_HP_PORT_L AUD_HP_L
MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MM
AUD_HP_PORT_R
GND_AUDIO_HP_AMP_L
AUD_HP_R
MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MM
GND_AUDIO_CODEC
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM
AUD_LI_L AUD_LI_P_L
MIN_NECK_WIDTH=.2MMMIN_LINE_WIDTH=.3MM
AUD_LI_N_L
MIN_LINE_WIDTH=.3MMMIN_NECK_WIDTH=.2MM
MIN_LINE_WIDTH=.3MMMIN_NECK_WIDTH=.2MM
AUD_LI_N_R
AUDIO: FILTER/BUFFERSYNC_DATE=07/16/2009SYNC_MASTER=K23_SKIP
10%820PF50V
NOSTUFF
CERM402
C63011
2
10%820PF
CERM50V
NOSTUFF
402
C63041
2
402MF-LF1/16W1%
7.87KR63061 2
21.5K1%
MF-LF402
1/16W
R63051
2
1%
MF-LF402
21.5K1/16W
R63011
2
402
1/16W
7.87K
MF-LF
1%
R63001 2
402
101%1/16WMF-LF
R63031
2
59 56
59
61 60 58 57 55
59 56
59
CERM-X5R
CRITICAL
10V
3.3UF
805-1
10%
C63051 2
CRITICAL
805-1
3.3UF
CERM-X5R
10%10V
C63031 2
CERM-X5R
3.3UF
10%
805-1
10V
CRITICAL
C63021 2
CRITICAL
3.3UF
10V10%
CERM-X5R805-1
C63001 2
55
55
55
55
59 55
1/10W5%
0
MF-LF603
R63251 2 59
59
55
55
NOSTUFF
5%50V
C0G-CERM
2200PF
CRITICAL
603
C6321 1
2
NOSTUFFCRITICAL
603
50V5%
C0G-CERM
2200PFC6320 1
2
603
5%1/10WMF-LF
0R6324
1 2
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
REG
VS
C1P
BOOT
C1N
OUTL1-
OUTL1+
OUTL2-
OUTL2+
OUTR1-
OUTR1+
OUTR2-
OUTR2+
NC1
NC2
NC3
FBL
COM
INL
INR
FBR
MONO
SHDN*
MOD
REGEN
MUTE*
THMPGNDAGND
PVDD
PAD
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
POUT = 6.76 W INTO 8 OHMS @ 1% THD+N
CODEC OUT = 1.335VRMS
TWEETER SPEAKER AMPLIFIERMAX9736B APN:353S2042
GAIN = -4.8(20K/17.4K)
AMP VOUT = 7.355VRMSFC = 19.5 HZ
TURN ON DELAY: 150MSTURN ON TIME: 110MS
RIN = 17.4 OHMS
64 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
0.5MM0.2MMAUD_R_P1
AUD_MAX9736_1COM
AUD_MAX9736_1FBRAUD_MAX9736_1INR
=PP3V3_S0_AUDIO
GND_AUDIO_SPKRAMP_PLANE
MAX9736_INT_1REG
MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MM
PP12V_AUD_SPKRAMP_PLANE
MIN_NECK_WIDTH=0.2MMVOLTAGE=12V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM
L01_P_L
AUD_MAX9736_1INL
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM
AUD_MAX9736_1VREG
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.5MM
AUD_R_N1
MIN_NECK_WIDTH=0.15MM
AUDSAMPCPN1MIN_LINE_WIDTH=0.2MM
AUDSAMPCPP1
MIN_LINE_WIDTH=0.2MMMIN_NECK_WIDTH=0.15MM
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM
L01_P_R
AUD_LO1_P_L
MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MM
AUD_LO1_P_R
MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MM
GND_AUDIO_SPKRAMP_PLANE
GND_AUDIO_SPKRAMP_PLANEMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MMVOLTAGE=0V
AUD_MAX9736_1FBL
AUD_SPKRAMP_1SHDN_L=PP3V3_S0_AUDIO
GND_AUDIO_CODEC
AUD_GPIO_3
AUD_GPIO_2
AUD_SPKRAMP_1MUTE_L
AUD_BOOT1
0.2MM0.5MMAUD_L_N1
MIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.2MM
AUD_L_P1 AUD_SPKR_OUTLO1L_POUT
AUD_SPKR_OUTLO1L_NOUT
AUD_SPKR_OUTLO1R_POUT
AUD_SPKR_OUTLO1R_NOUT
AUDIO: Tweeter Amp 1SYNC_MASTER=K23_SKIP SYNC_DATE=07/16/2009
402
1%
17.4K
MF-LF1/16W
R64011 2
20.0K
1/16WMF-LF402
1%
R64001 2
NOSTUFF
10%50VX7R
0.001UF
402
C64121 2
10V
1UF10%
X5R402-1
C6403 1
2
10%10V
1UF
X5R402-1
C6402 1
2
MAX9736BETJ+
CRITICAL
TQFN
U6400
13
14
3
21
22
12
33
5
19
6
18
20
4
9
7
8
17
1
31
2
32
23
25
24
26
28
29
27
30
15
11
10
16
0.1UF
X7R-CERM50V10%
805
C64101
2
CRITICAL
0603-LF
180-OHM-1.5AL6403
1 2
402
25V
1000PF5%
NP0-C0G
C64071
2
1000PF5%
NP0-C0G402
25V
C6406 1
2
20%16V
603CERM
0.1UFC6401 1
2
0.1UF
603-1
10%50VX7R
C64111
2
180-OHM-1.5ACRITICAL
0603-LF
L6401
1 2
CRITICAL180-OHM-1.5A
0603-LF
L6402
1 2
25V
402NP0-C0G
5%1000PFC6408 1
2
NP0-C0G
5%1000PF25V
402
C64091
2
180-OHM-1.5A
0603-LF
CRITICAL
L6400
1 2
92 85 59
92 85 59
92 85 59
92 85 59
61 55
NOSTUFF
1/16W5%
402MF-LF
0R64071 2
0
MF-LF402
5%1/16W
R64051 2
MF-LF1/16W5%100K
402
R64061
2
20%220UF
SM-CASE-C1-HFELEC16V
C6499 1
2
60 58 57
61 58 55
61 60 59 58 57 55 6
61 60 59 58 57 55 6
55
10VX5R402
10%
0.47UFC6495
1 2
55
60 58 57
10V
402
0.47UF
10%
X5R
C64961 2
60 58 57
89 60 58
402
0
5%1/16WMF-LF
R64041 2
402
1%
17.4K
1/16WMF-LF
R64021 2
100PF5%
CERM50V
402
C64041
2
20.0K
1/16W
402MF-LF
1%
R64031 2
NOSTUFF10%50VX7R
0.001UF
402
C64131 2
10V
1UF
X5R
10%
402-1
C64051
2
61 60 58 56 55
REG
VS
C1P
BOOT
C1N
OUTL1-
OUTL1+
OUTL2-
OUTL2+
OUTR1-
OUTR1+
OUTR2-
OUTR2+
NC1
NC2
NC3
FBL
COM
INL
INR
FBR
MONO
SHDN*
MOD
REGEN
MUTE*
THMPGNDAGND
PVDD
PAD
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
AMP VOUT = 7.355VRMS
TURN ON TIME: 110MSGAIN = -4.8(20K/17.4K) TURN ON DELAY: 150MS
FC = 19.5 HZCODEC OUT = 1.335VRMS
POUT = 6.76 W INTO 8 OHMS @ 1% THD+N
MAX9736B APN:353S2042WOOFER SPEAKER AMPLIFIER
RIN = 17.4 OHMS
65 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
MIN_NECK_WIDTH=0.2MMVOLTAGE=0V
MIN_LINE_WIDTH=0.6MMGND_AUDIO_SPKRAMP_PLANE
AUD_MAX9736_INL AUD_BOOT
AUD_MAX9736_FBRAUD_MAX9736_INR
AUD_MAX9736_COM
AUD_MAX9736_FBL
L02_P_L
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM
AUD_MAX9736_VREG
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM
MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MM
MAX9736_INT_REG
MIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.2MM
AUD_L_POUT
0.2MM0.5MMAUD_L_NOUT
AUD_LO2_P_R
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM
L02_P_R
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM
MIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.2MM
AUD_R_NOUT
AUDSAMPCPPMIN_NECK_WIDTH=0.15MMMIN_LINE_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
AUD_LO2_P_L
MIN_NECK_WIDTH=0.2MM
MIN_NECK_WIDTH=0.15MMMIN_LINE_WIDTH=0.2MM
AUDSAMPCPN
=PP3V3_S0_AUDIO AUD_SPKRAMP_SHDN_L
0.5MM0.2MMAUD_R_POUT
AUD_SPKRAMP_MUTE_L
=PP3V3_S0_AUDIO
AUD_GPIO_3
GND_AUDIO_CODEC
GND_AUDIO_SPKRAMP_PLANE
GND_AUDIO_SPKRAMP_PLANE
PP12V_AUD_SPKRAMP_PLANE
VOLTAGE=12V
MIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MM
AUD_SPKR_OUTLO2L_POUT
AUD_SPKR_OUTLO2L_NOUT
AUD_SPKR_OUTLO2R_POUT
AUD_SPKR_OUTLO2R_NOUT
SYNC_MASTER=K23_SKIP SYNC_DATE=07/16/2009
AUDIO: Woofer Amp
100K5%1/16WMF-LF402
R65061
2
20%220UF
SM-CASE-C1-HFELEC16V
C6599 1
2
10V
1UF
X5R
10%
402-1
C65051
2
10V
1UF10%
X5R402-1
C6503 1
2
10%
402
10VX5R
0.47UFC6595
1 2
10V
402
0.47UF
10%
X5R
C65961 2
60 58 57
60 58 57
60 58 57
61 57 55
61 60 59 58 57 55 6
61 60 59 58 57 55 6
55
55
89 60 57
NO STUFF10%50VX7R402
0.001UFC6513
1 2
50V
0.001UF
NO STUFF
10%
X7R402
C65121 2
20.0K
1/16W
402MF-LF
1%
R65031 2
402
1%
17.4K
1/16WMF-LF
R65021 2
20.0K
1/16WMF-LF402
1%
R65001 2
1/16WMF-LF402
1%
17.4KR65011 2
402
25V
1000PF5%
NP0-C0G
C65071
2
25V
402NP0-C0G
5%1000PFC6508 1
2
180-OHM-1.5A
0603-LF
CRITICAL
L6502
1 2
CRITICAL180-OHM-1.5A
0603-LF
L6501
1 2
92 85 59
92 85 59
92 85 59
92 85 59
402
25V
1000PF5%
NP0-C0G
C65091
2
MF-LF1/16W5%
0
402
R65041 2
0.1UF
603-1
10%50VX7R
C65111
2
CRITICAL
0603-LF
180-OHM-1.5AL6503
1 2
180-OHM-1.5A
0603-LF
CRITICAL
L6500
1 2
10V
1UF
X5R
10%
402-1
C6502 1
2
CERM
20%16V
603
0.1UFC6501 1
2
0
MF-LF402
5%1/16W
R65051 2
100PF5%
CERM50V
402
C65041
2
CRITICAL
MAX9736BETJ+TQFN
U6500
13
14
3
21
22
12
33
5
19
6
18
20
4
9
7
8
17
1
31
2
32
23
25
24
26
28
29
27
30
15
11
10
16
0.1UF
X7R-CERM50V
805
10%
C65101
2
NP0-C0G
1000PF5%
402
25V
C6506 1
2
61 60 57 56 55
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
INOUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
OUT
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
AUD_HP_GND_JACK
AUD_LI_GND_JACK
PP3V3_AUDIO_SPDIF_JACK
APPLE P/N 518S0723
NC
TWEETER (SECONDARY)
PROPERTIES FOR ALL SPKR NETS
WOOFER (PRIMARY)WOOFER (PRIMARY)
TWEETER (SECONDARY)
REMOTE I/O CONNECTOR
SPEAKER CABLE CONNECTORSAPPLE P/N 518S0656APPLE P/N 518S0748INTERNAL MIC CON
APPLE P/N 518S0677
PROPERTIES FOR ALL SPKR NETS
66 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
AUD_SPKR_OUTLO1L_NOUTAUD_SPKR_OUTLO1L_POUT
AUD_SPKR_OUTLO1R_NOUT
AUD_SPKR_OUTLO2L_NOUTAUD_SPKR_OUTLO2R_NOUTAUD_SPKR_OUTLO2R_POUT
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM AUD_HP_GND_JACKAUD_HP_L_JACKMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM
VOLTAGE=3.3VMIN_NECK_WIDTH=0.1MM PP3V3_AUDIO_SPDIF_JACKMIN_LINE_WIDTH=0.2MM
AUD_HP_TIPDET_JACKMIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM
HS_MIC_HI_JACKMIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM
HS_MIC_LO_JACKMIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.5MM
AUD_SPKR_OUTLO1R_POUT
AUD_SPDIF_OUT_JACK
AUD_LI_DET_JACKMIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.2MM
AUD_LI_L_JACKMIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.5MM
AUD_SPKR_OUTLO2L_POUT
NO_TEST NC_J6702_3MIN_NECK_WIDTH=0.1MMVOLTAGE=0VMIN_LINE_WIDTH=0.2MM
GND_AUDIO_MIC1_CONN
AUD_SPDIFIN_JACK
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM
MIN_NECK_WIDTH=0.2MM AUD_LI_GND_JACKMIN_LINE_WIDTH=0.3MMAUD_LI_R_JACKMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.2MM
AUD_MIC_IN1_P_CONN
GND_AUDIO_HP_AMP_LMIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.2MM
AUD_HP_PORT_REF
AUD_HP_TYPEDET_JACKMIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM
VOLTAGE=0VMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM
AUD_HP_R
MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MM
AUD_HP_L
MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.2MM
AUD_HP_TIP_DET
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM
AUD_LI_R
AUD_LI_TIP_DET
MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MMAUD_LI_GND
MIN_LINE_WIDTH=0.2MMMIN_NECK_WIDTH=0.1MMAUD_IP_PERPH_DET
HS_MIC_LOVOLTAGE=0VMIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.15MM
AUD_SPDIF_OUT
MIN_LINE_WIDTH=0.2MMMIN_NECK_WIDTH=0.1MM
AUD_HP_TYPE
AUD_LI_L
MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.15MMMIN_NECK_WIDTH=0.1MM
HS_MIC_HI
AUD_SPDIF_IN
AUD_MIC_IN1_N_EMI
MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.2MM
AUD_MIC_IN1_P_EMI
AUD_MIC1_IN_N
MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MM
=PP3V3_S0_AUDIO
AUD_MIC1_IN_P
MIN_LINE_WIDTH=0.2MMMIN_NECK_WIDTH=0.1MM
AUD_MIC_IN1_N_CONN
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM AUD_HP_R_JACK
AUD_IP_PERPH_JACKMIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.2MM
SYNC_DATE=06/05/2009SYNC_MASTER=K60
Audio: MLB to I/O Conn.
M-RT-SM78048-0473
CRITICAL
J6602
1
2
3
4
CRITICAL
M-RT-SM78048-0573J6603
1
2
3
4
5
220-OHM-0.7A-0.28-OHM
0402
L6618
1 2
220-OHM-0.7A-0.28-OHM
0402
L6616
1 2
603
5%
0
1/10WMF-LF
R66101 2
MF-LF603
5%
0
1/10W
R66171 2
SM
XW6617
1 2
56
56
56
60
55
0402
FERR-1000-OHML6613
1 2
0402
FERR-1000-OHML6612
1 2
FERR-1000-OHM
0402
L6606
1 2
60
85 81
5%1/16W
402
22
MF-LF
R66011 2
0402
FERR-1000-OHML6605
1 2
20143-020E-20F
CRITICAL
F-RT-SM
J6600
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
3
4
5
6
7
8
9
53780-8603
CRITICAL
M-RT-SM
J6601
4
5
1
2
3
FERR-1000-OHM
0402
L6615
1 2
10VX5R
402-1
1UF10%
C6600 1
2
6.8V-100PF402
CRITICAL
DZ6603
1
2
CRITICAL
4026.8V-100PFDZ6615
1
2
6.8V-100PF402
CRITICAL
DZ6606
1
2
6.8V-100PF402
CRITICAL
DZ6608
1
2
6.8V-100PF402
CRITICAL
DZ6610
1
2CRITICAL
4026.8V-100PFDZ6612
1
2
402
CRITICAL
6.8V-100PFDZ6614
1
2
60
56 55
61
61
FERR-1000-OHM
0402
L6609
1 2
56
FERR-1000-OHM
0402
L6608
1 2
56
FERR-1000-OHM
0402
L6607
1 2
10VX5R
10%0.47UF
402
C66011
2
1/16W
0
402MF-LF
5%
R66001
2
86 60
86 60
92 85 58
92 85 58
92 85 57
92 85 57
92 85 57
92 85 58
92 85 58
92 85 57
61 60 58 57 55 6
60
85 55 CRITICAL
4026.8V-100PFDZ6607
1
2
402
CRITICAL
6.8V-100PFDZ6604
1
2
FERR-1000-OHM
0402
L6614
1 2
6.8V-100PF
CRITICAL
402
DZ6609
1
2CRITICAL
4026.8V-100PFDZ6605
1
2
6.8V-100PF402
CRITICAL
DZ6611
1
2CRITICAL
4026.8V-100PFDZ6613
1
2
6.8V-100PF402
CRITICAL
DZ6601
1
2CRITICAL
6.8V-100PF402
DZ6600
1
2
FERR-1000-OHM
0402
L6604
1 2
FERR-1000-OHM
0402
L6601
1 2
0402
FERR-1000-OHML6603
1 2
0402
FERR-1000-OHML6600
1 2
FERR-1000-OHM
0402
L6602
1 2
89
92
92
G
S
D
G
S
D
G
S
D
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN OUT
OUT
OUT
IN
OUT
OUT
G
S
D
IN
IN
G
S
D
G
S
D
IN
G
S
D
G
S
D
IN
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
Place Across Ground Split
NC NC
DP Audio Enable
Headphone OutDigital Out LI Insert Detect
IPHS HS Detect Debounce CKT
Audio Ground ReturnsInternal Microphone Impedance Matching
67 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
GND_AUDIO_CODEC
AUD_MIC_INN_R
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM
AUD_SENSE_AAUD_SENSE_A
=PP3V3_S0_AUDIO
GND_AUDIO_CODEC
AUD_IP_PERPH_DET_DB
MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MM
AUD_MIC1_IN_P
=PP3V3_S0_AUDIO
AUD_IP_PERPH_DET AUD_IP_PER_DEB
AUD_IP_PERPH_DET_INV
AUD_IP_PERIPHERAL_DET
=PP12V_S0_AUDIO_SPKRAMP
MIN_LINE_WIDTH=0.6MM
VOLTAGE=12VMIN_NECK_WIDTH=0.2MM
PP12V_AUD_SPKRAMP_PLANE
=PP3V3_S0_AUDIO
AUD_HP_TIP_DET
=PP3V3_S0_AUDIO
AUD_SENSE_A
GND_AUDIO_CODEC
AUD_Q6702_D3 AUD_Q6701_D6
GND_AUDIO_CODEC
GND_AUDIO_CODEC
AUD_MIC1_IN_G
MIN_NECK_WIDTH=0.2MM
AUD_MIC1_IN_N
MIN_LINE_WIDTH=0.3MM
MIN_LINE_WIDTH=0.3MM
AUD_CODEC_MICBIAS
MIN_NECK_WIDTH=0.2MM
GND_AUDIO_CODEC
MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MM
AUD_MIC_INP_R
=PP3V3_S0_AUDIO
AUD_IP_PERPH_DET_R
AUD_LI_TIP_DAUD_LI_TIP_DET
MUX_CNTRL
AUD_HP_TYPE
AUD_HP_TIP_DET_INV
AUD_HP_TYPE_INV
AUD_LI_TIP_DET_INV
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM
AUD_INTMICBIAS
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM
GND_AUDIO_SPKRAMP_PLANE
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MM
AUDIO: Detects/GroundingSYNC_DATE=07/16/2009SYNC_MASTER=K23_SKIP
1/16W
NOSTUFF
MF-LF
0
5%
402
R67491 2
402
5%
0
MF-LF
NOSTUFF
1/16W
R67481 2
81 NTZD3154NT1HSOT-563-HF
Q6703
3
5
4
NTZD3154NT1HSOT-563-HF
Q6701
6
2
1
1/16W5%
MF-LF402
10KR67681
2
61 60 59 58 57 55 6
402
100K5%1/16WMF-LF
R67621
2
SOT-563-HFNTZD3154NT1HQ6700
3
5
4
NTZD3154NT1HSOT-563-HF
Q6703
6
2
1
61 60 59 58 57 55 6
5%
MF-LF402
1/16W
100KR67301
2
402MF-LF1/16W5%0R67311
2
NOSTUFF
402
5%
0
MF-LF1/16W
R67321 2
59
16VX5R402
10%0.1UFC67401
2
1%1/16WMF-LF402
17.4KR67001 2
MF-LF
5%100K
402
1/16W
R67971
2
NTZD3154NT1HSOT-563-HF
Q6701
3
5
4
3.40K
402
1/16W1%
MF-LF
R67921
2
3.40K
MF-LF1/16W1%
402
R67931
2
55
55
402
5%
0
MF-LF
NOSTUFF
1/16W
R67471 2
603-HF
6.3V20%
TANT
4.7UF
CRITICAL
C6751 1
2
55
402
100K
MF-LF
5%1/16W
R67981
2
61 60 58 57 56 55
58 57
89 58 57 6
60 55
59
60 55
61 60 59 58 57 55 6
59
59
61 60 59 58 57 55 6
60 55
86 59
86 59
MF-LF402
1/16W5%100KR67911
2
10%
X5R402
16V
0.1UFC6796
1 2
1/16W
402
1%10K
MF-LF
R67011
2
0
1/16WMF-LF402
5%
R67961 2
16V10%
NOSTUFF
X5R402
0.1UFC67971
2
MF-LF1/16W5%
0
402
R67991 2 20
MF
CRITICAL
20K1/16W
402
0.1%
R67941
2
1/16W
39.2K
MF-LF
1%
402
R67441
2
402
10%25V
0.0082UF
X7R
C6750 1
2
5%
402
1/16W
100K
MF-LF
R67951
2
MF-LF1/16W5%100K
402
R67901
2
SOT-563-HFNTZD3154NT1HQ6702
3
5
4
SOT-563-HFNTZD3154NT1HQ6702
6
2
1
SOT-563-HFNTZD3154NT1HQ6700
6
2
1
SM-1
FERR-250-OHML6739
1 2
SM-1
FERR-250-OHML6738
1 2
SM OMITXW6704
1 2
SM OMITXW6703
1 2
2.2K
5%
402MF-LF1/16W
R67431 2 OMITSM
XW67051 2
SMXW6702
1 2
0.1UF
402
16VX5R
10%
C67951 2
61 60 58 57 56 55
61 60 58 57 56 55 61 60 58 57 56 55
61 60 58 57 56 55
61 60 58 57 56 55
61 60 59 58 57 55 6
IN
BI
OUT
IN
IN
IN
OUT
OUT
IN
INOUT
OUTIN
IN
GND THMENABLE
AVDD
SDA
MICBIAS
DETECT
BYPASSINT*
SCL
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
0X0C (B)
MCP GPIO_38N/AN/A
MIKEY
MIKEY
HEADPHONES
SPDIF INSPDIF OUT
0X0D (13,V22,B,LEFT)
CONVERTER
0X05
0X07N/A
0X040X030X02
0X060X060X08
N/A
0X02
0X06
N/A
0X03
0X06
N/AN/A
0X05
VOLUMEENABLE/
GPIO 3
0X09 (A)
MCP GPIO_5N/A
N/A
LINE INN/A
N/ADETECT/INTERRUPTTYPE
0X0D(13,B,RIGHT)HEADSET MICROPHONEBUILT-IN MICROPHONELINE INPUT
0X09SECONDARYPRIMARYFUNCTION
0X0F0X10
0X0A
PIN
N/A
0X04
N/A
MICBIAS 80%
FLP = 8.82 KHZ
MIKEY
FHP = 80 HZ
CNTRLGPIO 3
0X0C
WRITE: 0X72 READ: 0X73 APN 353S2256
0X0B
MIKEY RECEIVER CKT
68 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
AUD_IPHS_SWITCH_EN
AUD_I2C_INT_L
=I2C_AUDIO_SDA
=PP5V_S0_AUDIO
AUD_GPIO_2
MIN_LINE_WIDTH=0.15MM
HS_MIC_HIMIN_NECK_WIDTH=0.1MM
AUD_GPIO_3
MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.15MM
AUD_MIC_INP_L
MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.15MM
AUD_MIC_INN_L
MIN_LINE_WIDTH=0.15MMMIN_NECK_WIDTH=0.1MM
HS_MIC_LO
MIN_LINE_WIDTH=0.15MMMIN_NECK_WIDTH=0.1MM
HS_RX_BP
MIN_LINE_WIDTH=0.15MMMIN_NECK_WIDTH=0.1MM
HS_SW_DET
GND_AUDIO_CODEC
MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.15MM
AUD_MIC_INF
=PP3V3_S0_AUDIO
VOLTAGE=3.3VPP3V3_S0_HS_F
MIN_LINE_WIDTH=0.15MMMIN_NECK_WIDTH=0.1MM
HS_RST
HS_INT_L
GND_AUDIO_CODEC
HS_SDA
HS_MIC_BIASMIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.15MM
=I2C_AUDIO_SCL
HS_SCL
SYNC_MASTER=K23_SKIP SYNC_DATE=07/16/2009
AUDIO: Mikey
25VX7R402
10%0.01UFC68991
2
1/16W5%
402
1K
MF-LF
R68521
2MF-LF
2.2K1/16W
402
5%
R68091
2
402-1
10VX5R
1UF10%
C68571
2
50VCERM
0.001UF20%
402
C6850 1
2
402X5R
0.1UF16V10%
C68511
2
CRITICAL
DRCCD3275U6806
3
10
2
8
94
7
16
5
11
X5R
10%16V
402
0.1UFC6802
1 2
0.1UF
402
16VX5R
10%
C68011 2
1N4148WS-X-GSOD-323-HF
NOSTUFF
D68001
2
58 57 55
57 55 57 55
58 57 55
402
25VX7R
10%0.0082UFC68531
2
2.2K
402
5%
MF-LF1/16W
R68101 2
100K1/16WMF-LF402
5%
R68081
2
CRITICAL
10UF6.3VX5R
20%
603
C6852 1
2
60 59 58 57 55 6
55 6
55
55
59
59
4.7UF
603-HF
6.3V20%
TANT
CRITICAL
C68541
2
25 21
20
48
48
5%
0
MF-LF402
1/16W
R68051 2
0
5%1/16W
402MF-LF
R68041 2
MF-LF402
1/16W
0
5%
R68031 2
MF-LF402
5%
0
1/16W
R68021 2
10K
402
5%
MF-LF1/16W
R68061
2
100K5%
MF-LF402
1/16W
R68071
2
0402
FERR-1000-OHML6840
1 2
61 60 58 57 56 55
89
61 60 58 57 56 55
OUTIN
08
08
G
D
S
G
D
S
08
OUT
OUT
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
SLP_S4 ENABLES
ENABLE FET
MEMVTT_EN SEQUENCE
Enable FET
Enable regulator
(PM_SLP_S3_L_BUF)
PCHCORE VREG
Enable regulator
Enable regulator
SLP_M ENABLESTHIS SLP_M CIRCUIT IS A BACKUP IN CASE
VCC_ME IS REQUIRED IN ANY STATE
switch to alias after proto1
Off
Battery Off (G3Hot)
Run (S0/M0)
Sleep (S3/M1)
Soft-Off (S5/M1)
Sleep (S3/M-Off)
Soft-Off (S5/M-Off)
State
N/A
Off
On
On
0
1
1
1
1
1
0
0
1
0
0
0
0
0
0
111N/A
PM_S4_STATE_LSMC_PM_G2_ENABLEManageability PM_SLP_S3_L
0
0
1
1
1
0
0
1
0
1
11
PM_SLP_M_LPM_SLP_S4_L
PP1V8_S0 VREG (CPU PLL)
Enable FET
PLACE TOP SIDE
Enable FET
ENABLE REGULATOR
Enable FET
OTHER RAILS ENABLED BY P3V3_S0 AND P5V_S0:
Enable FET
REWORK TO POWER UP WITH NO CPU
Enable regulator
TO ENABLE OF CPU VREG
CPUVTT VREG
switch to alias after proto1
Enable FET
Enable FET
PLACE SERIES R’S NEAR SOURCE
OTHER THAN S0. DELETE AFTER PROTO1
SLP_S3 ENABLES
69 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
PM_SLP_S4_1_L
=PP3V3_S5_PWRCTL
VTT_REG_PGOOD_R1
CPUVTT_REG_PGOOD
CPU_SKTOCC
S4_ENABLES P3V3S3_EN
P5VS0_EN
PCHCORE_REG_EN
CPUVTT_REG_EN
PGOOD_P5V_S0MAKE_BASE=TRUE
VTT_REG_PGOOD_R2
=PP3V3_S0_PWRCTL
DDRVTT_EN
PM_RSMRST_L PM_RSMRST_PCH_L
PGOOD_P12V_S0
=PP3V3_S0_PWRCTL
CPU_SKTOCC_L
PM_EN_USB_PWR
=DDRREG_EN
=PP5V_S3_PWRCTL
P5VS3_REG_PGOODMAKE_BASE=TRUE
P5VS3_EN
P12V_S3_EN
PM_EN_PVCORE_CPU
PM_PGOOD_DDRREG_S3
MAKE_BASE=TRUECPUVTT_REG_PGOOD
PCHCORE_REG_PGOODMAKE_BASE=TRUE
P1V05_ME_S0_EN
PCHCORE_REG_PGOOD
PM_SLP_S3_BUF_L
PCHCORE_PGOOD_R
=PP3V3_S0_PWRCTL
=PP3V3_S5_PWRCTL
PM_SLP_S3_L
P1V05_ME_SM_DIS
P1V05_SM_DIS_L
=PP3V3_S5_PWRCTL
PM_SLP_S3_B_R
P1V05_ME_SM_EN
P3V3ME_EN
PM_SLP_M_L
=PP3V3_S5_PWRCTL
MAKE_BASE=TRUE
PM_SLP_S3_BUF_L
P3V3S0_EN
DDRVTT_EN
P1V5_S0_EN
SYNC_DATE=07/01/2009
POWER SEQUENCING ENABLESSYNC_MASTER=K60_MIKE
5%
33
402
1/16WMF-LF
R69471 2
NOSTUFF
MF-LF402
1/16W
33
5%
R69201 2
MF-LF
33
402
1/16W5%
R69121 2
5%1/16W
33
MF-LF402
R69111 2
6.3V
10%
0.47UF
NOSTUFF
CERM-X5R
402
C69411
2
402MF-LF
5%
10K
1/16W
NOSTUFFR6941
1
2
91 72
91 72
0
1/16W5%
402MF-LF
R69011 2
10K
402
1/16WMF-LF
5%
R69521
2
402
5%
MF-LF1/16W
100KR69501 2
16V
402X5R
10%0.1UF
NOSTUFFC69531
2
0
1/16WMF-LF
5%
402
R69531 2
MMDT3904-X-GSOT-363-LF
Q69115
3
4
5%
MF-LF1/16W
402
10KR69511
2
NOSTUFF
100PF50V5%
402CERM
C69511
2
SOT-363-LFMMDT3904-X-GQ6911
2
6
1
6.3V10%
402
0.47UF
CERM-X5R
NOSTUFF
C69521
2
05%1/16WMF-LF402
R69271
2
CERM
402
1UF10%
6.3V
C69251
2
6.3V
402
10%
1UF
CERM
C69261
2
1/16W
402MF-LF
5%
10KR69261 2
10K
1/16W
402MF-LF
5%
R69251 2 TSSOP-HF
74LVC08
U6900
7
4
5
6
14
0
MF-LF402
1/16W5%
R69491 2
402MF-LF1/16W
10K 5%
R6942
1
2
1UF10%
6.3V
CERM
402
C69421
2
0.47UF
402
10%
CERM-X5R
6.3V
NOSTUFF
C69471
2
0
5%
MF-LF402
1/16W
R69481 2
CERM-X5R
6.3V
10%
402
0.47UF
NOSTUFF
C69241
2
100K
MF-LF402
5%1/16W
R69101
2
NOSTUFF
CERM-X5R
10%
6.3V
402
0.47UF
C69451
2
402
CERM-X5R
6.3V
0.47UF10%
NOSTUFF
C69461
2
NOSTUFF
0.47UF
CERM-X5R
402
6.3V
10%
C69201
2
NOSTUFF
10%
402
0.47UF
CERM-X5R
6.3V
C69211
2CERM-X5R
0.47UF10%
6.3V
402
NOSTUFF
C69231
2
402
10VCERM
20%
0.1UF
C6910
12
2N7002DW-X-GSOT-363
Q6910
3
5
4
2N7002DW-X-GSOT-363
Q6910
6
2
1
33
MF-LF1/16W5%
402
R69141 2
10K 1%
1/16W
402MF-LF
R6944
1
2
0.47UF10%
CERM-X5R
6.3V
NOSTUFF
402
C69441
2
1/16W
402MF-LF
1K
5%
R69221 2
5%0
NOSTUFF
MF-LF402
1/16W
R69171
2
TSSOP-HF74LVC08
U6900
7
1
2
3
14
74LVC08TSSOP-HF
U6900
7
10
9
8
14
5%1/16WMF-LF
10K
402
R69151
2100K1/16W5%
MF-LF402
R69161
2
MF-LF402
1/16W
33
5%
R69461 2
91 45 91 19
91 19
63 62 6 5
91 67 63 62 11
91 72
91 68
91 67
91 72
72 63 62 6 5
91 70 62 32
63
72 63 62 6 5
11
43
70
6
69
91 69
91 72
64
91 70 5
91 67 63 62 11
91 68 63 62 5 72
91 68 63 62 5
62
72 63 62 6 5
63 62 6 5
91 63 46 37 33 32 19 5
63 62 6 5
91 72
91 72
91 19 5
63 62 6 5
62
91 70 62 32
91 72
OUT
OUT
OUT
08
08
08
08
GND
V+
08
GND
V+
GND
V+
G
D
S
G
D
S
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
DELAYED PWRGD (BY 99MS)
DELAY REQUIREMENTS
8.3 MS ON RISE/ 2.8MS ON FALL
COMPONENT VALUES FROM CRB
PGOOD COMPARATORS FOR PP1V8_S0 AND PP12V_S0
(1.67V/1.22V; 132mV Hysteresis)
ASK INTEL: NEED 100K PULL-DOWN?
IBEX PEAK EDS
APPROXIMATE DELAY OF 10-15MS
SPARE
S0 RAILS PGOOD
FROM THIS SMC GENERATES PM_RSMRST_L
PULL-UP ON MXM PAGE
OPTION FOR PCH PWROK AND SYSPWROK
To SMC (2)
DELAY IS ABOUT 200MSWHICH GOES INTO RSMRST_L OF PCH
OPTION FOR SMC TO OUPUT
SMC
ALL_SYS_PWRGD CIRCUIT
DISABLE CPUVTT_REG_PGOOD WHEN SLP_S3_L = 0 (PER PIKETON PDG)
ME PGOOD SEQUENCE
TO BE DRIVEN BY SAME SIGNAL
(9.91V/9.58V; 330mV Hysteresis)
NEED TO VERIFY TIMINGS
70 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
SMC_DELAYED_PWRGD
PM_ME_PWRGD
ALL_SYS_PWRGD
PGOOD_SYSPWROK
ALL_SYS_PWRGD_R
PM_SYS_PWRGD
PM_PCH_PWRGD
PM_ME_PWRGD_R
PM_ME_PWRGD
PGOOD_1V05ME_G2
=PP3V3_S5_PWRCTL
12V_COMP_REF
1V80_COMP_REF
=PP12V_S0_PWRCTL
PGOOD_1V8_S0_G1
PM_SPARE_PGOOD
=PP3V3_S0_PWRCTL
=PP12V_S5_PWRCTL
=PP12V_S5_PWRCTL
=PP12V_S0_PWRCTL
1V60_COMP_REF
=PP3V3_S3_PWRCTL
=PP1V8_S0_CPU_PLL
PP12V_S0
=PP3V3_S0_PWRCTL
=PP3V3_S0_PWRCTL
PGOOD_P1V8_S0
=PP3V3_S0_PWRCTL
PGOOD_1V8_S0_G2
PGOOD_PCH_S0
=PP3V3_S0_PWRCTL
ALL_SYS_PWRGD_SMC
=PP3V3_S0_MXM =PM_MXM_PGOOD_PULLUP
PM_MXM_PGOOD
PM_PGOOD_PVCORE_CPU
PGOOD_CPU_GFX_DDR
=PP3V3_S0_PWRCTL
=PP3V3_S5_PWRCTL
PM_MXM_EN
RSMRST_PWRGD
=PP3V3_S5_PWRCTL
PGOOD_P1V8_S0
PGOOD_P3V3_S0
=PP3V3_S0_PWRCTL
PCHCORE_REG_PGOOD
PM_SLP_S3_L VTTS3PG_1
VTTS3PG_2
CPUVTT_REG_PGOOD
PGOOD_12V_S0_G1
PGOOD_P12V_S0
PGOOD_12V_S0_G2
PGOOD_SYSPWROK_R
PGOOD_PCH_AND_P1V8
PGOOD_1V05ME_G1
9V_91_COMP_REF
=PP1V05_SM_ME
=PP3V3_SM_PWRCTL
SYNC_DATE=07/01/2009SYNC_MASTER=K60_MIKE
POWER SEQUENCING PGOOD
5%
33
1/16WMF-LF402
R70711 2
NOSTUFF
402
5%
MF-LF1/16W
0R70701 2
2N7002DW-X-GSOT-363
Q7080
3
5
4SOT-3632N7002DW-X-GQ7080
6
2
1
CRITICAL
LM393SOI-HF
U7080
4
6
5
7
8
1/16W1%
MF-LF402
2.0KR70821 2
402
1%1/16WMF-LF
100KR70811
2
1/16WMF-LF
33.2K1%
402
R70801
2
SOI-HF
CRITICAL
LM393U7080
4
2
3
1
8
49.9K1%
1/16W
402MF-LF
R70831
2
10K
MF-LF1/16W5%
402
R70841
2
10K
MF-LF402
5%1/16W
R70861
2
603
0.1UF
16V20%
CERM
C70801
2
33
5%1/16WMF-LF402
R70321 2
1/16W5%
MF-LF
0
402
NOSTUFF
R70291 2
33
1/16WMF-LF
5%
402
R70271 2
74LVC08TSSOP-HF
U6900
7
13
12
11
14
1/16WMF-LF
5%
402
10KR70601 2
SOT-363-LFMMDT3904-X-GQ7060
2
6
1
MF-LF402
1/16W
10K5%
R70611
2
MMDT3904-X-GSOT-363-LF
Q70605
3
4
CRITICAL
SOI-HFLM393U7030
4
6
5
7
8
10K1/16W
402MF-LF
5%
R70251
2
100K5%
NOSTUFF
MF-LF402
1/16W
R70311
2
NOSTUFF
0.47UF
CERM-X5R6.3V10%
402
C70231
2
402
5%1/16WMF-LF
0R70301 2
1/16WMF-LF402
5%
33R70281 2
NOSTUFF
100PF
CERM402
5%50V
C70411
2 X5R402
0.1UF10%16V
NOSTUFF
C70421
2
NOSTUFF
6.3V10%
402
0.47UF
CERM-X5R
C70401
2
NOSTUFF
1/16WMF-LF402
1%301KR70421
2
NOSTUFF
MF-LF1/16W
402
1%30.1KR70411
2
MMDT3904-X-GSOT-363-LF
Q70402
6
1
NOSTUFF
MMDT3904-X-GSOT-363-LF
Q70405
3
4
NOSTUFF
5%
MF-LF1/16W
402
33KR70401
2
NOSTUFF
5.6K
MF-LF
5%1/16W
402
R70431
2
SOT-363-LFMMDT3904-X-GQ7011
2
6
1
MMDT3904-X-GSOT-363-LF
Q70115
3
4
402
NOSTUFF
5%1/16W
10K
MF-LF
R70241 2
TSSOP-HF74LVC08
U7000
7
1
2
3
14
TSSOP-HF74LVC08
U7000
7
13
12
11
14
74LVC08TSSOP-HF
U7000
7
10
9
8
14
TSSOP-HF74LVC08
U7000
7
4
5
6
14
10K5%1/16WMF-LF402
R70181
2
MF-LF402
5%1/16W
10KR70171
2
2.0K
1%1/16W
402MF-LF
R70021 2
1%
MF-LF402
1/16W
10KR70211
2
MF-LF
64.9K1%
402
1/16W
R70201
2
91 32 25 6
5%
33
1/16WMF-LF402
R70231 2
1/16W
402MF-LF
5%
33R70221 2
49.9K
402
1/16W1%
MF-LF
R70071
2
402X5R16V10%0.1UFC70501
2
1/16W
1K
402
MF-LF
5%
R70501
2
0.1UF
603CERM16V20%
C70101
2
0.1UF
402
CERM
20%10V
C70221
2
91 45
91 45
91 46
91 63 19
91
91 32 19
91 19
91 63 19
63 62 6 5
63 6
72 63 62 6 5
72 63 6
72 63 6
63 6
51
72 6
16 13 6
89 6
72 63 62 6 5
72 63 62 6 5
91 63
72 63 62 6 5
91
72 63 62 6 5
74 73 6 74
91 74
91 64 26 5
91
72 63 62 6 5
63 62 6 5
74
63 62 6 5
91 63
91 72 48
72 63 62 6 5
91 68 62 5
91 62 46 37 33 32 19 5
91 67 62 11
62
91
91
6
72 6
IN
OUT
OUT
OUT
IN
IN
IN
OUT
IN
IN
OUT
IN
IN
IN
ISEN4-
EN_VTT
THRM_PAD
VR_HOT
VR_FAN
ISEN4+
ISEN3-
ISEN3+
ISEN2-
ISEN2+
ISEN1+
PWM2
FB
PWM1
TCOMP
PSI*
IMON
OFS
VCC
VID0
VR_RDY
VID7
VID5
VID4
VID3
VID2
VID6
VID1
SS
FSPWM3
PWM4TM
REF
DAC
EN_PWR
RGND
VSEN
VDIFF
ISEN1-
COMP SYM_VER_2
IN
IN
IN
OUT
IN
OUT
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
LAYOUT: PLACE RT7101 NEAR HOT SPOT.
and LOW when VTM/VCC > 33%.VR_HOT goes HIGH when VTM/VCC < 28%
1.25 mOhm loadline
LOCAL 5V
CPU CORE REG 1.1V/110A O/P= PPVCORE_S0_CPU_REGCPU VCOREVOUT = VCORE
AVG = 90APEAK = 110A
IMAX = 10.5A
152-0104
CPU CORE INPUT Filtering
71 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
PM_EN_PVCORE_CPUVR_CPU_TM
AGND_CPU
NET_PHYSICAL_TYPE=SNS_DIFF
VR_CPU_VSNS_XW_NVOLTAGE=0V
CPU_VCC_PKG_SENSE_N
CPU_VCC_PKG_SENSE_P
VOLTAGE=1.1VNET_PHYSICAL_TYPE=SNS_DIFF
VR_CPU_VSNS_XW_P
VR_CPU_OFS
PP5V_S0_CPU_VCORE_VCC
VR_CPU_TCOMP
VR_CPU_FS
VR_CPU_SS
AGND_CPU
VR_CPU_VSNS_R_N
=PP5V_S0_VRD
VR_CPU_VSEN
VR_VDF_R1
VR_CPU_VDIFF
VR_CPU_IOUT_PD
VR_CPU_PSI_L
PP5V_S0_CPU_VCORE_VCC
VR_CPU_EN_VTT
VR_CPU_RGND
VR_CPU_PWM3_R
VR_CPU_PWM3
VR_CPU_DAC
VR_CPU_ISNS2_R_P
CPU_PSI_L
VR_CPU_PWM2_R
VR_CPU_ISNS3_R_N
VR_CPU_FB
MAX_NECK_LENGTH=3MM
VOLTAGE=5VMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.3MM
PP5V_S0_CPU_VCORE_VCC
VR_CPU_FAN
VR_CPU_COMP
VR_CPU_ISNS1_R_P
VR_CPU_ISNS1_RR_2
VR_CPU_ISNS2_RR_2
VR_CPU_ISNS3_RR_2
VR_CPU_ISNS4_RR_2
VR_CPU_COMP_R
VR_CPU_PWM4
VR_CPU_PWM1
VR_CPU_PWM2
VR_CPU_ISNS2_P
VR_CPU_COMP_RC
VR_CPU_ISNS3_P
VR_CPU_ISNS1_P
VR_CPU_ISNS4_P
MIN_NECK_WIDTH=0.3MM
VOLTAGE=0VMIN_LINE_WIDTH=0.6MM
AGND_CPUMAX_NECK_LENGTH=3MM
VR_CPU_ISNS1_N
VR_CPU_ISNS4_N
VR_CPU_ISNS3_N
VR_CPU_ISNS2_N
VR_CPU_VRDHOT
=PP12V_S0_VRD PP12V_S0_CPU_FLTRDNET_PHYSICAL_TYPE=POWERVOLTAGE=12V
AGND_CPU
VR_CPU_ISNS1_R_N
VR_CPU_REF
VR_CPU_VSNS_R_P
VR_CPU_FB_R
VR_VDF_R2
PPVCORE_S0_CPU_REG
VR_CPU_IMON
VR_CPU_EN_PWR
VR_CPU_ISNS4_R_N
VR_CPU_ISNS4_R_P
VR_CPU_PWM4_R
VR_CPU_ISNS3_R_P
VR_CPU_ISNS2_R_N
AGND_CPU
=PP3V3_S0_VRD=PPVTT_S0_CPU
PM_PGOOD_PVCORE_CPU
=PP3V3_S0_VRD
CPU_VID<7..0>
SYNC_DATE=07/16/2009SYNC_MASTER=K61_JERRY
VREG: PPVCORE_S0_CPU
402
1/16W
16.5K
MF-LF
1%
R71011 2
10%50V
402CERM
560PFC7105
1 2
10V
402X5R
1UF10%
C71071
2
22PF
402CERM50V5%
C71041 2
0
5%1/16WMF-LF402
R71791 2
470PF
10%
CERM50V
402
C7106
1 2
805
5%
MF-LF1/8W
2.2R7118
12
20.0K1/16W
402
1%
NOSTUFF
MF-LF
R71551
2
1%
806
402
1/16WMF-LF
R71031 2
201%1/16WMF-LF402
R71161
2
1%1/16WMF-LF402
10KR71171
2 10%0.0033UF
402CERM50V
C71121
2
1/16W
NOSTUFF
MF-LF402
200K5%
R71881
2
MF-LF1/16W
402
165
1%
R71611 2
MF-LF1/16W
402
165
1%
R71511 2
MF-LF1/16W
402
165
1%
R71411 2
MF-LF1/16W
402
165
1%
R71311 2
402MF-LF
1%
1K
1/16W
R71021 2
0.36UH-45A-0.76MOHM
MSQ1211R36LF-TH
CRITICALL7100
1 2
75K1/16WMF-LF
1%
402
R71081
2
0
MF-LF
5%
402
1/16W
R71111 2
402
5%
MF-LF1/16W
0R71711 2
50VCERM402
0.020UF10%
NOSTUFF
C71711
2
1/16W
1.02K
NOSTUFF
1%
MF-LF402
R71721
2
SOD-923-HF
NOSTUFF
NSR0140P2T5GD7171
12
MF-LF1/16W
402
1.02K
1%
R71631 2
5%220PF
402CERM25V
C71631
2
MF-LF1/16W
402
1.02K
1%
R71531 2
220PF
402CERM25V5%
C71531
2
MF-LF1/16W1%
1.02K
402
R71431 2
5%220PF
402CERM25V
C71431
2
MF-LF1/16W
402
1.02K
1%
R71331 2
5%220PF
402CERM25V
C71331
2
89 49
402
5%
MF-LF1/16W
10KR71361 2
NOSTUFF
15PF
402C0G50V1%
C7160 1
2
5%
0
MF-LF1/16W
402
R716012
5%50VCERM402
150PFC71611
2
0.1UF
402X5R16V10%
C71621
2
0
1/16WMF-LF
5%
402
R716212
89 66
89 66
89 66
6.8K0603
RT7101
1
2
SM
OMIT
XW7130
1 2
SM
OMITXW7120
1 2
89 13
1K
5%1/16WMF-LF402
R71381 2
1/16W5%
MF-LF
0
402
R71291 2
402
5%
MF-LF1/16W
0R71281 2
402
5%1/16W
1K
MF-LF
R71271 2
MF-LF1/16W5%
402
10R71371 2
10
5%
MF-LF402
1/16W
R71391 2
89 49 13
1M5%1/16WMF-LF402
NOSTUFF
R71461
2
1%
402MF-LF1/16W
47.5R7149
1 2
0
1/16WMF-LF
5%
402
R715212
MF-LF
5%1/16W
402
0R7142
12
0
1/16WMF-LF
5%
402
R713212
5%
0
MF-LF402
1/16W
R714012
0
1/16WMF-LF
5%
402
R715012
402C0G50V1%
NOSTUFF
15PFC7150 1
2
NOSTUFF
1%
402C0G50V
15PFC7140 1
2
NOSTUFF
402C0G50V1%
15PFC7130 1
2
5%
MF-LF1/16W
402
NOSTUFF
0
R71441
2
1/16WMF-LF
5%
NOSTUFF
402
0
R71481
2
NOSTUFF
402
5%1/16WMF-LF
0
R71471
2
402
0.1UF10VCERM
20%
C71801
2
NOSTUFF
402
5%
MF-LF
01/16W
R71771
2
1/16W
0
NOSTUFF
402MF-LF
5%
R71781
2
ISL6334
CRITICAL
QFNU7100
13
11
32
33
14
34
10
27
28
21
22
30
29
24
23
9
8
26
20
31
25
12
16
35
18
41
39
19
15
7
6
5
4
3
2
1
40
37
38
36
17
89 16 13
05%1/16WMF-LF402
R71041
2
5%
MF-LF1/16W
402
0R71451 2
89 16 13
5%50VCERM402
150PFC71411
2
0.1UF
402X5R16V10%
C71421
289 65
89 65
89 65
5%50VCERM402
150PFC71511
2
0.1UF
402X5R16V10%
C71521
2
89 65
89 65
89 65
5%50VCERM402
150PFC71311
2
0.1UF
402X5R16V10%
C71321
289 65
89 65
89 65
5%0
402MF-LF1/16W
R71061
2
402MF-LF
1%1.02K
1/16W
R71001
2MF-LF
NOSTUFF
1%
402
1/16W
20.0KR71051
2
1%
MF-LF402
1/16W
21KR71071
2
1%100K
402MF-LF1/16W
R71091
2
10%
402
25VX7R
1500PFC7110
1 2
402
1%
MF-LF1/16W
1KR71101 2
0.0022UF
402CERM50V10%
SIGNAL_MODEL=EMPTY
NOSTUFFC71011
2
402
50VCERM
10%0.0022UFC71021
2402
50VCERM
10%0.0022UFC71031
2
VR_CPU_IOUT88 13
91 63 26 5
62
16V10%
NOSTUFF
0.01UF
CERM402
C71091
25%
MF-LF
2.0K1/16W
402
R7112 1
2
402
1/16WMF-LF
1%49.9K
R71141
2
49.9K
MF-LF402
1%1/16W
R71151
2
0
1
2
3
4
5
6
7
0.001UF50V10%
402CERM
C7135
1
2
OMIT
SMXW7101
1 2
1K5%
1/16WMF-LF
402
R71351
2
89
64
89
89
89 64
89
89
89
64
6
89
89
89 64
89
89
89
89
89
89
89
89 64
89
89
89
89
89
64
6 89 66 65
64
89
89
89 66 65 6
89
89
89
89
89
64
64 6
46 16 13 11 6
64 6
OUT
IN
IN
S
G
D
D
G
S
S
G
D
D
G
S
S
G
D
D
G
S
OUT
OUT
OUT
OUT
BOOT
UGATE
PHASENC
NC
GND
LGATE
VCC PVCC
THRML
PWM
PAD
BOOT
UGATE
PHASENC
NC
GND
LGATE
VCC PVCC
THRML
PWM
PAD
IN
GDSEL
LGATE
VCC
PWM
BOOT
UGATE
GNDTHRML
PHASE
LVCCUVCC
PAD
OUT
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
376S0772
PHASE 1
PHASE 3
PHASE 2
OUTPUT BULK DECOUPLING:
THESE TWO CAPS ARE FOR EMC
376S0771
376S0772
128S0209
152-0114
152-0114
376S0772
110A MAX
376S0771
THESE TWO CAPS ARE FOR EMC
376S0771
THESE TWO CAPS ARE FOR EMC
152-0114
72 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
NET_PHYSICAL_TYPE=VR_CTL_PHYVR_CPU_BOOT1_RC
DIDT=TRUE
DIDT=TRUENET_PHYSICAL_TYPE=VR_CTL_PHYVR_CPU_DRV1_UGATE
DIDT=TRUENET_PHYSICAL_TYPE=POWERVR_CPU_PHASE1
VR_CPU_DRV2_VCCNET_PHYSICAL_TYPE=VR_CTL_PHY
NET_PHYSICAL_TYPE=VR_CTL_PHYVR_CPU_DRV1_VCC
VR_CPU_ISNS2_XW_PVR_CPU_ISNS2_XW_N
VR_CPU_ISNS3_XW_PVR_CPU_ISNS3_XW_N
PPVCORE_S0_CPU_REG3
VR_CPU_ISNS1_XW_PVR_CPU_ISNS1_XW_N
PPVCORE_S0_CPU_REG1
VR_CPU_DRV2_GDSEL
VR_CPU_DRV3_GDSEL
VR_CPU_PWM3VR_CPU_DRV3_BOOT
NET_PHYSICAL_TYPE=VR_CTL_PHY DIDT=TRUE
DIDT=TRUE
NET_PHYSICAL_TYPE=VR_CTL_PHY
VR_CPU_DRV3_UGATE
VR_CPU_DRV3_LGATEDIDT=TRUE
NET_PHYSICAL_TYPE=VR_CTL_PHY
PPVCORE_S0_CPU_REG
VR_CPU_ISNS3_N
VR_CPU_ISNS3_P
VR_CPU_ISNS2_N
VR_CPU_ISNS1_P
VR_CPU_ISNS1_N
NET_PHYSICAL_TYPE=VR_CTL_PHYDIDT=TRUE
VR_CPU_PH3_SNUB
DIDT=TRUE
NET_PHYSICAL_TYPE=VR_CTL_PHY
VR_CPU_BOOT2_RC
VR_CPU_BOOT3_RCNET_PHYSICAL_TYPE=VR_CTL_PHY
DIDT=TRUE
VR_CPU_DRV1_GDSEL
VR_CPU_PWM1
NET_PHYSICAL_TYPE=VR_CTL_PHYVR_CPU_DRV1_BOOT
DIDT=TRUE
VR_CPU_DRV3_UVCCNET_PHYSICAL_TYPE=VR_CTL_PHY
NET_PHYSICAL_TYPE=VR_CTL_PHY
VR_CPU_DRV2_PVCC
VR_CPU_DRV3_PVCCNET_PHYSICAL_TYPE=VR_CTL_PHY
VR_CPU_PHASE3
NET_PHYSICAL_TYPE=POWER
DIDT=TRUE
VR_CPU_DRV1_UVCCNET_PHYSICAL_TYPE=VR_CTL_PHY
VR_CPU_PH2_SNUB
DIDT=TRUENET_PHYSICAL_TYPE=VR_CTL_PHY
PPVCORE_S0_CPU_REG2
VR_CPU_DRV2_LGATENET_PHYSICAL_TYPE=VR_CTL_PHY DIDT=TRUE
NET_PHYSICAL_TYPE=VR_CTL_PHYVR_CPU_DRV3_VCC
VR_CPU_PWM2
NET_PHYSICAL_TYPE=VR_CTL_PHY
VR_CPU_DRV2_UVCC
NET_PHYSICAL_TYPE=VR_CTL_PHYVR_CPU_DRV2_BOOT
DIDT=TRUE
DIDT=TRUEVR_CPU_PHASE2
NET_PHYSICAL_TYPE=POWER
NET_PHYSICAL_TYPE=VR_CTL_PHYVR_CPU_DRV2_UGATE
DIDT=TRUE
PPVCORE_S0_CPU_REG
PPVCORE_S0_CPU_REG
VR_CPU_PH1_SNUB
DIDT=TRUENET_PHYSICAL_TYPE=VR_CTL_PHY
VR_CPU_ISNS2_P
PPVCORE_S0_CPU_REG
DIDT=TRUENET_PHYSICAL_TYPE=VR_CTL_PHYVR_CPU_DRV1_LGATE
NET_PHYSICAL_TYPE=VR_CTL_PHY
VR_CPU_DRV1_PVCC
PP12V_S0_CPU_FLTRD
SYNC_MASTER=K60_JERRY SYNC_DATE=07/01/2009
VREG: CPU CORE - PHASES 1-3
16V10%
X5R603
1UFC72001
2
MF-LF603
05%
1/10W
R7205 1
2
5%1/10WMF-LF603
0
NOSTUFF
R72071
2
1/10WMF-LF
603
105%
R72021
2
1/10W
10
MF-LF603
5%
NOSTUFFR7201
1
2
X5R
1UF10%
603
16V
C72011
2
89 64
16V
603X5R
10%1UF
C7202 1
2
CRITICAL
DFNISL6622U7201
23
5
6
7
10
4
11
1
8989 64
603
1/10W5%
MF-LF
0R72041
2
402
10%50VX7R
0.001UFC72511
2402
10%50VX7R
0.001UFC72501
2
10%
402
50VX7R
0.001UFC72311
210%
402
50VX7R
0.001UFC72301
2
402
10%50VX7R
0.001UFC72101
2
0.36UH-35A
MSQ1208-TH
CRITICALL7241
1 2
CRITICAL
MSQ1208-TH
0.36UH-35AL7221
1 2
CRITICAL
0.36UH-35A
MSQ1208-TH
L7201
1 2
CRITICAL
QFN1ISL6612U7241
2
5
6
3
8
10
9
4
11
1
7
QFN1
CRITICAL
ISL6612U7221
2
5
6
3
8
10
9
4
11
1
7
8X9-TH1
CRITICAL
16VELEC
20%270UFC72451
2
8X9-TH1
CRITICAL
16VELEC
270UF20%
C72251
2
8X9-TH1
CRITICAL
16VELEC
270UF20%
C72051
2
10%0.22UF
603
16VX7R
C72031
2
8X9-TH1
CRITICAL
ELEC16V
270UF20%
C72711
28X9-TH1
16V
CRITICAL
20%
ELEC
270UFC72701
2
SM
OMIT
SIGNAL_MODEL=EMPTY
XW7241
1
2
SM
SIGNAL_MODEL=EMPTY
OMITXW7242
1
2
MF1W
0.00051%
CRITICAL
0612
R7248
1 2
3 4
89 64
89 64
89 64
89 64
SIGNAL_MODEL=EMPTYSM
OMITXW7221
1
2
SIGNAL_MODEL=EMPTYSM
OMITXW7222
1
2
0612MF1W
0.00051%
CRITICALR7228
1 2
3 4
CRITICAL
MF1W
0.00051%
0612
R7208
1 2
3 4
IRF6795DIRECTFET-MX
CRITICAL
Q7242
1 2 6 7
5
3 4
CRITICAL
S1IRF6710Q7241
1
2
5
64
3
CRITICAL
DIRECTFET-MXIRF6795Q7222
1 2 6 7
5
3 4
S1IRF6710
CRITICAL
Q7221
1
2
5
64
3
IRF6795DIRECTFET-MX
CRITICAL
Q7202
1 2 6 7
5
3 4
IRF6710S1
CRITICAL
Q7201
1
2
5
64
3
20%
CASE-D2-SMPOLY2V
CRITICAL
330UF-0.006OHMC72601
2 2VPOLYCASE-D2-SM
20%
CRITICAL
330UF-0.006OHM
C72611
2 2VPOLYCASE-D2-SM
20%
CRITICAL
330UF-0.006OHMC72621
22VPOLY
20%
CRITICAL
330UF-0.006OHM
CASE-D2-SM
C72631
2
330UF-0.006OHM2VPOLYCASE-D2-SM
20%
CRITICAL
C72641
2
CRITICAL
CASE-D2-SM
2VPOLY
20%330UF-0.006OHMC72651
2
X5R-CERM
CRITICAL
0805
10%10UF16V
C72491
2
CRITICAL
X5R-CERM10%16V
0805
10UFC72291
2
X5R-CERM0805
16V10%10UF
CRITICALC72151
2
402
10%50VX7R
0.001UFC72111
2X5R603
16V10%1UFC72071
2
89 64
0
603MF-LF1/10W5%
NOSTUFF
R72471
2
16VX5R
1UF10%
603
C7242 1
2603X5R
1UF16V10%
NOSTUFFC72401
2
603
105%
1/10WMF-LF
R72421
2
05%
1/10WMF-LF
NOSTUFF
603
R72451
2
MF-LF603
1/10W5%10R72411
2
50VCERM
NOSTUFF402
10%0.001UFC72081
2
10%1UF16VX5R603
C72411
2 05%
MF-LF603
1/10W
R72441
2
0.22UF16V10%X7R603
C72431
2
NOSTUFF
50VCERM
0.001UF10%
402
C72481
2
NOSTUFF
1/8W5%
MF-LF
2.2
805
R72461
2
2.2
805MF-LF
NOSTUFF
1/8W5%
R72061
2
10UF16V10%
0805X5R-CERM
CRITICALC72461
2603X5R16V1UF10%
C72471
2
SIGNAL_MODEL=EMPTYSM
OMITXW7201
1
2
89 64
NOSTUFF
MF-LF603
1/10W5%0R72271
2
1UF10%16VX5R603
C7222 1
2
603X5R
1UF16V10%
NOSTUFFC72201
2
10
MF-LF603
5%1/10W
R72221
2MF-LF
5%0
603
1/10W
NOSTUFF
R72251
2
603MF-LF
101/10W5%
R72211
2
16V
603
1UF10%
X5R
C72211
2
MF-LF1/10W
5%0
603
R72241
2 603X7R16V
0.22UF10%
C72231
2
NOSTUFF
0.001UF
402
50V10%
CERM
C72281
2
16V
10UF10%
0805
CRITICAL
X5R-CERM
C72061
2
NOSTUFF
805MF-LF
2.21/8W
5%
R72261
2
10%16V
10UF
X5R-CERM0805
CRITICAL
C72261
210%1UF
X5R16V
603
C72271
2
SIGNAL_MODEL=EMPTYSM
OMITXW7202
1
2
89 64
89
89
89
89 89
89 89
89
89 89
89
89
89
89
89
89
66 65 64 6
89
89
89
89 89
89
89
89
89
89
89
89
66 65 64 6
66 65 64 6
89
66 65 64 6
89
89 66 64
IND
G
S
S
G
D
OUT
OUT
BOOT
UGATE
PHASENC
NC
GND
LGATE
VCC PVCC
THRML
PWM
PAD
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
376S0772
152-0114
THESE TWO CAPS ARE FOR EMC
376S0771
PHASE 4
73 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
NET_PHYSICAL_TYPE=VR_CTL_PHY
VR_CPU_DRV4_VCC
VR_CPU_PWM4
NET_PHYSICAL_TYPE=VR_CTL_PHY
VR_CPU_DRV4_UVCCVR_CPU_DRV4_PVCC
NET_PHYSICAL_TYPE=VR_CTL_PHY
NET_PHYSICAL_TYPE=VR_CTL_PHYDIDT=TRUE
VR_CPU_PH4_SNUB
DIDT=TRUE
VR_CPU_BOOT4_RCNET_PHYSICAL_TYPE=VR_CTL_PHY
VR_CPU_ISNS4_P
VR_CPU_DRV4_GDSEL
VR_CPU_ISNS4_N
PPVCORE_S0_CPU_REG4
VR_CPU_ISNS4_XW_N VR_CPU_ISNS4_XW_P
PPVCORE_S0_CPU_REG
DIDT=TRUENET_PHYSICAL_TYPE=VR_CTL_PHY
VR_CPU_DRV4_LGATE
PPVCORE_S0_CPU_REG
NET_PHYSICAL_TYPE=VR_CTL_PHY
DIDT=TRUEVR_CPU_DRV4_BOOT
NET_PHYSICAL_TYPE=VR_CTL_PHY
VR_CPU_DRV4_UGATEDIDT=TRUE
DIDT=TRUENET_PHYSICAL_TYPE=POWER
VR_CPU_PHASE4
PP12V_S0_CPU_FLTRD
VREG: CPU CORE - PHASE 4SYNC_DATE=07/16/2009SYNC_MASTER=K61_JERRY
0805X5R-CERM
CRITICAL
16V
10UF10%
C73061
2402
10%50VX7R
0.001UFC73091
210%
603
1UF16VX5R
C73071
210%
402
50VX7R
0.001UFC73081
2
X5R16V10%1UF
603
C73481
2 X5R16V10%1UF
603
C73491
216V10%1UF
603X5R
C73461
2 X5R16V10%1UF
603
C73471
2X5R16V10%1UF
603
C73441
2 X5R16V10%1UF
603
C73451
2X5R16V10%1UF
603
C73421
2 X5R16V10%1UF
603
C73431
2
402
0.1UF20%10VCERM
C73381
2 CERM10V20%0.1UF
402
C73391
2402
0.1UF20%10VCERM
C73361
2 CERM10V20%0.1UF
402
C73371
2
0.1UF20%
CERM402
10V
C73341
2 CERM10V20%0.1UF
402
C73351
2402
0.1UF20%10VCERM
C73321
2 CERM10V20%0.1UF
402
C73331
2
603
1UF10%16VX5R
C73411
2603
1UF10%16VX5R
C73401
2
402
0.1UF20%10VCERM
C73311
2CERM10V20%0.1UF
402
C73301
2
CRITICAL
MSQ1208-TH
0.36UH-35AL7301
1 2
QFN1
CRITICAL
ISL6612U7301
2
5
6
3
8
10
9
4
11
1
7
8X9-TH1ELEC
20%270UF16V
CRITICALC73041
2
89 64
89 64
OMIT
SMSIGNAL_MODEL=EMPTY
XW7302
1
2
SIGNAL_MODEL=EMPTYSM
OMITXW7301
1
2
MF1W
0.00051%
CRITICAL
0612
R7301
1 2
3 4
S1
CRITICAL
IRF6710Q7301
1
2
5
64
3
CRITICAL
DIRECTFET-MXIRF6795Q7302
1 2 6 7
5
3 4
89 64
1/10WMF-LF603
05%
NOSTUFFR73101
2
16V10%
X5R
1UF
603
C7312 1
2
NOSTUFF
10%16VX5R603
1UFC73101
2
1/10WMF-LF
5%10
603
R73111
2
NOSTUFF
603
5%
MF-LF
01/10W
R73121
2MF-LF603
1/10W5%10R73131
2
X5R16V
1UF10%
603
C7311 1
2
603
5%1/10WMF-LF
0R73031
2X7R603
16V10%0.22UFC73031
2
CERM402
50V
NOSTUFF
0.001UF10%
C73021
2
2.25%
805MF-LF1/8W
NOSTUFF
R73021
2
X5R-CERM0805
10%16V
10UF
CRITICALC7305
1
2
89
89
89
89 89
66 65 64 6
89
66 65 64 6
89
89
89
89 65 64
G
D
S
IN
OUT
PVCCVCC
OCSET
PGOOD
ENLLIREF
ICOMP
ISUM
RGND
VDIFF
VID4
VID3
VID2
VID1
VID0
VID12.5
REF
FB
VSEN
COMP
OFS
UGATE1
BOOT1
PHASE1
LGATE1
FS
BOOT2UGATE2
PHASE2LGATE2
ISEN1
ISEN2
THRM_PAD
G
D
S
TABLE_5_ITEM
REFERENCE DESIGNATOR(S) BOM OPTIONTABLE_5_HEAD
QTY DESCRIPTIONPART#
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
"PULL-UP" TO VTT RAIL ON CPU PAGE
VID0=0, VID[4-1]=1, VTT VR o/p= 1.10V
(SELECT MODE= VRM10)
VOUT = 1.1V OR 1.05VPEAK = 35AAVG = 30A
CPU VTT
Internal Pu on VID lines
OUTPUT BULK DECOUPLING
CPU VTT REG 1.1V/30A O/P= PPVTT_S0_CPU_REG
74 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
CPUVTT_REG_EN
PPVTT_S0_CPU_REG
VTT_REG_PHASE1
CPU_VTTSENSE_R_N
MIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
VTT_REG_BOOT1
NET_PHYSICAL_TYPE=POWER
PP5V_CPUVTT_VR
VTT_REG_RGND
VTT_REG_REF
CPU_VTTSENSE_R_P
DIDT=TRUE
VTT_REG_BOOT2_R
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.25MM
VTT_REG_PH2_SNUBDIDT=TRUE
CPU_VTTSENSE_P
CPU_VTTSENSE_N
MIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2 mm VTT_REG_UGATE2
DIDT=TRUE
PPVTT_S0_CPU_REGVTT_REG_VSEN_1
VTT_REG_COMP1
PP5V_CPUVTT_VR
VTT_VID3
VTT_VID1
VTT_REG_PH1_SNUB
DIDT=TRUE
VTT_VID4
VTT_REG_VIDFF
VTT_REG_RGND_1
VTT_REG_ISEN2
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2 mm
VTT_REG_LGATE2
DIDT=TRUE
MIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6MM
DIDT=TRUE
VTT_REG_UGATE1
VTT_REG_BOOT1_RDIDT=TRUEMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6MM
VTT_ICOMP2
VTT_REG_PHASE2
VTT_REG_VIDFF1
VTT_REG_VIDFF2
NET_PHYSICAL_TYPE=POWER
=PP5V_S0_CPU_VTT_VREG
VTT_ICOMP1
DIDT=TRUE
VTT_REG_LGATE1
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6MM
VTT_REG_FS
VTT_REG_FB
VTT_REG_ICOMP
VTT_REG_ISUM
VTT_REG_IREF
VTT_VID2
VTT_VID0
VTT_VID12P5
VTT_REG_COMP
VTT_OFST
VTT_REG_VSEN
SWITCHNODE
DIDT=TRUE
VTT_REG_PHASE2NET_PHYSICAL_TYPE=POWER
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6MM
=PP12V_S0_CPU_VTT_VREG
PPVTT_S0_CPU_REGNET_PHYSICAL_TYPE=POWER
VTT_REG_ISEN1
VTT_REG_BOOT2
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6MM
DIDT=TRUE
CPUVTT_REG_PGOOD
VTT_REG_OCSET
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6MM
DIDT=TRUE
VTT_REG_PHASE1 SWITCHNODE
DIDT=TRUE
=PP12V_S0_CPU_VTT_VREGNET_PHYSICAL_TYPE=POWER
1 TH7401RES,68k,0603,5%113S0127
CPU VTT REGULATORSYNC_DATE=07/16/2009SYNC_MASTER=K61_JERRY
5%
402NP0-C0G25V
1000PF
NOSTUFFC74551
2
CTLSH3-30M833
CRITICAL
TLM833
D7440
1 2 3 4
5
X7R-CERM10%16V
0.1UF
402
C7430
12
1.0UF
X7R
10%16V
805
C74011
2
RJK0365DPA
CRITICAL
MLP5X6-LFPAK-WPAK
Q7440
5
4
1 2 3
603
50V10%CERM
4700PFC7418
1 2
10KOHM
OMIT
0603-LFTH7401
1 2
MF-LF1/10W
603
5%
0R74301 2
CRITICAL
RJK0348DPAWPAK
Q74515
4
1 2 3
RJK0348DPAWPAK
CRITICALQ7441 5
4
1 2 3
CRITICAL
16V
402
10%1UF
X5R
C74511
2
16V
402
10%1UF
X5R
CRITICALC74431
2
NOSTUFF
1K
402
1/16WMF-LF
5%
R74091 2
1/16W5%
1K
402MF-LF
NOSTUFF
R74101 2
MF-LF
5%
1K
1/16W
402
R74131 2
1K
1/16W5%
402MF-LF
NOSTUFF
R74121 2
5%
1K
402
1/16W
NOSTUFF
MF-LF
R74111 2
5%
1K
402
1/16WMF-LF
R74141 2
16VELEC
CRITICAL
270UF20%
8X9-TH1
C74531
2
CRITICAL
16VELEC
270UF20%
8X9-TH1
C74451
2
28K1%1/10W
603MF-LF
R74611
2
1.1
NOSTUFF
1/10WMF-LF603
1%
R74401
2
CRITICAL
QFNISL6568U7400
24
18
5
20
6
29
11
13
26
16
12
27
14
10
3
28
23
19
15
2
8
33
25
17
4
7
32
31
1
30
21
22
9
1%1.11/10WMF-LF603
NOSTUFF
R74551
2
0.022UF
0402X5R
10%25V
C74161 2
1000PF
NP0-C0G25V5%
402
C74171 2
50VCERM
5%
402
100PFC7492 1
2
511
MF-LF
1%
402
1/16W
R74011 2
1%
100
402
1/16WMF-LF
R74201 2
100
402
1/16WMF-LF
1%
R74211 2
100
MF-LF1/16W
402
1%
R74181 2
1%
402
1/16WMF-LF
1.82KR74161 2
MF-LF402
1/16W1%
88.7KR74341 2
1K
402MF-LF1/16W1%
R74331 2
1K
1%1/16W
402MF-LF
R74321 2
CRITICAL
0.36UH-45A-0.76MOHM
MSQ1211R36LF-TH
L7454
1 2
0.36UH-45A-0.76MOHM
CRITICAL
MSQ1211R36LF-TH
L7441
1 2
MF-LF
1%
402
1/16W
35.7KR74061 2
MF-LF402
35.7K
1%1/16W
R74051 2
CRITICAL
330UF
POLY-TANTCASE-D3L-SM1
20%6.3V
C74631
2
CRITICAL
330UF20%6.3VPOLY-TANTCASE-D3L-SM1
C74621
2
CRITICAL
20%
CASE-D3L-SM1POLY-TANT
330UF
6.3V
C74611
2
20%330UF
CRITICAL
CASE-D3L-SM1POLY-TANT6.3V
C74601
2
603
1/10W
0
MF-LF
5%
R74311 2 0.1UF
10%402 16V
X7R-CERM
C7431
12
402
10
1/16WMF-LF
1%
R74241 2
10
1%1/16W
402MF-LF
R74251 2
PLACEMENT_NOTE=PLACE R7423 WITHIN 25.4MM OF CPU, NO STUBS.
0
1/16WMF-LF
5%
402
R74231 2
1/16W
402PLACEMENT_NOTE=PLACE R7422 WITHIN 25.4MM OF CPU, NO STUBS.MF-LF
5%
0R74221 2
1/10W
1.0K
MF-LF
1%
603
R74171 2
91 63 62 11
1000PF25VNP0-C0G
5%
402
NOSTUFFC74401
2
SM
OMIT
XW7422
12
OMIT
SM
XW7421
12
91 62
MF-LF1/10W
603
5%
4.7R74621 2
0
1/16WMF-LF
5%
402
R74191 2
NOSTUFF
75K
1/16WMF-LF
1%
402
R74601 2
16VX5R-CERM
10%10UF
1206
CRITICALC74441
2
MF-LF1/16W1%
402
4.99R74081 2
NOSTUFF
10
1%
402MF-LF1/16W
R74071 2
42.2K
1/16W1%
MF-LF402
R74031 2
402
1%
MF-LF1/16W
20.0KR74021 2
402
1%
MF-LF1/16W
19.1KR74041 2
1.0UF
805X7R
10%16V
C74021
2
5%NP0-C0G
25V402
1000PFC7404
12
40210% 50VX7R
0.01UFC7403
1225V
1000PF
402
5%
NP0-C0G
NOSTUFFC74051
225V
402
5%1000PF
NOSTUFF
NP0-C0G
C7406 1
2
NOSTUFF
5%50V
402
100PF
CERM
C74221
2
100PF
NOSTUFF
402CERM50V5%
C7426 1
2
5%25VNP0-C0G402
1000PFC74251
2
5%25V
NP0-C0G402
1000PF
NOSTUFF
C7423 1
2
CRITICAL
X5R-CERM
10%16V
10UF
1206
C74501
2
CRITICAL
16VX5R-CERM
10%10UF
1206
C74521
2
10%
CRITICAL
16VX5R-CERM
10UF
1206
C74421
2
RJK0365DPA
CRITICAL
MLP5X6-LFPAK-WPAK
Q7450
5
4
1 2 3
TLM833CTLSH3-30M833
CRITICAL
D7450
1 2 3 4
5
67 49 6
89 67
89
89
89 67
89
89
89
89
89 49 13
89 13
89
67 49 6
89 67
89
89
89
89 67
6
89
89
89
89
89
89
89
89
89
89 67
67 6
67 49 6
89
89
89 67
67 6
VBST
TON
LL
DRVH
DRVL
V5FILT V5DRV
PGNDGND
EN_PSV
VOUT
TRIP
VFB
THRM_PAD
PGOOD
SYM 2
OUT
IND1
G1
S2
G2
S1/D2
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
(PPCHCORE_REG_FB)
OUTPUT BULK DECOUPLING
376S0801
Vout= 0.75*( 1 + 8.45/21) = 1.05Vout= 0.75*( 1+R7615/R7616)
IBEX PEAK CORE REG 1.05V OUTPUT = PP1V05_S0_REG
AVG = 3APEAK = 7.5AVOUT = 1.05V
PP1V05_S0_REG
(PP1V05_S0_FB)
76 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
=PP12V_S0_PCH_CORE_VREG
NET_PHYSICAL_TYPE=POWERDIDT=TRUE
MIN_LINE_WIDTH=0.6MMDIDT=TRUEMIN_NECK_WIDTH=0.2MM
PCHCORE_REG_PHASE SWITCHNODE
OP_1V05_S0_FB
NET_PHYSICAL_TYPE=POWER
PP1V05_S0_REG
MIN_LINE_WIDTH=0.6MMPCHCORE_REG_LGATE
DIDT=TRUEMIN_NECK_WIDTH=0.2MM
PCHCORE_REG_TON
PCHCORE_REG_BOOT
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MM
DIDT=TRUE
PCHCORE_REG_UGATE DIDT=TRUE MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MM
PCHCORE_REG_5V_FLT
=PP3V3_S0_PCH
NET_PHYSICAL_TYPE=POWER=PP5V_S0_PCH_CORE_VREG
PCHCORE_REG_BOOT_R
MIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MM
DIDT=TRUE
PCHCORE_REG_PHASE_C
PCHCORE_REG_TRIP
PCHCORE_PGND_XW
PCHCORE_REG_EN
PCHCORE_REG_PGOOD
AGND_PCHCORE_REG
PCHCORE_REG_VFB
IBEX PEAK CORE
0805
10UF
CRITICAL
10%16VX5R-CERM
C76101
2
CRITICAL
10%50VX7R402
0.001UFC76211
216V10%
402X5R
0.1UFC76111
2
CRITICAL
10%50VX7R402
0.001UFC76201
2
WPAK
CRITICAL
RJK0384DPAQ7601
2
1
6
7
3 4 5
21K1%1/16WMF-LF402
R76161
2
10K1%
1/16WMF-LF
402
R76801
2
6.3V20%
603X5R
10UFC7601 1
2
0
1/10WMF-LF
5%
603
R765012
X5R
10%25V
402
0.1UFC7650
12
CRITICAL
10UF
X5R-CERM0805
10%16V
C76131
2
1%
200K
402
1/16WMF-LF
R76511 2
1/16W
6.98K1%
MF-LF402
R76601
2
SM
OMIT
XW76141 2
SM
OMIT
XW76011 2
91 62
91 63 62 5
10%
0805
10UF16V
CRITICAL
X5R-CERM
C76121
2
SM
OMIT
XW76001 2
10%16VX5R402
1UFC76701
2
3001/16W5%
MF-LF402
R76701
2
CRITICAL
0805X5R-CERM
10%16V
10UFC76081
2 X5R-CERM16V
10UF
0805
10%
CRITICALNOSTUFF
C76091
2
CRITICAL
330UF
CASE-D3L-SMPOLY-TANT6.3V20%
C76071
2
8.45K1%
402MF-LF1/16W
R76151
2
CRITICAL
SM-IHLP-1
1.0UH-13A-5.6M-OHML7614
1 2
0.499
603MF1/10W1%
NOSTUFFR76141
2
603
25V
NOSTUFF
CERM
5%1000PFC76141
2
TPS51117RGY_QFN14
CRITICAL
QFN
U7600
13
9
1
7
12
8
6
15
2
11
10
4
14
5
3
6
89
6
89
89
89
89
24 21 18 6
6
89
89
89
OUT
D1
G1
S2
G2
S1/D2
G
D
S
G
D
S
UGATE2
VCC2
VCC1
PGOOD1
LDO5
UGATE1
BOOT1
PHASE2PHASE1
LGATE2LGATE1
OCSET2OCSET1
ISEN1 ISEN2
VOUT1 VOUT2
FB2
EN1
PGNDTHRM
BOOT2
FSET2
EN2
FSET1
FB1
VIN
FCCM
PGOOD2
PAD
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
3V3 OUTPUT
3V3 S5 REGULATOR
Vout = 0.6V * (1 + Ra / Rb)
<Rb>
376S0631
(P3V3S5_UGATE)
PLACE CLOSE TO FETEMC CAPS
EMC: C7763,C7764PLACE AT L7750.2
Power Rating ?
5V OUTPUT
RB
<Ra>
PLACE AT Q7330
EMC CAPSPLACE CLOSETO L
RA
(P3V3S5_PHASE)
5V S3 REGULATOR
OUTPUT BULK DECOUPLING:
128S0237
376S0801
376S0631
EMC: C7754,C7755
OUTPUT BULK DECOUPLING:
(P3V3S5_LGATE)
77 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
DIDT=TRUE
NET_PHYSICAL_TYPE=POWER
=PP12V_S5_P3V3S5_VREG
P3V3S5_REG_OCSET
P3V3S5_REG_SNUB
DIDT=TRUE
MIN_NECK_WIDTH=0.2MMP3V3S5_REG_PHASE
DIDT=TRUE
MIN_LINE_WIDTH=0.6MM
SWITCHNODE
DIDT=TRUE
NET_PHYSICAL_TYPE=POWER
P3V3S5_REG_ISEN
P3V3S5_12VE_EN1
P3V3S5_REG_FSET1
P5VS3_REG_ISEN
DIDT=TRUE NET_PHYSICAL_TYPE=POWER
SWITCHNODE
P5VS3_REG_PHASEDIDT=TRUE
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6MM
P5VS3_REG_OCSET
P5VS3_REG_VOUT2
P5VS3_REG_FB
P5VS3_REG_FSET2
P3V3S5_REG_VOUT1
P3V3S5_REG_FB
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUEMIN_LINE_WIDTH=0.4MM
5V_SNUBBER
MIN_LINE_WIDTH=0.25MM
DIDT=TRUE
MIN_NECK_WIDTH=0.2 MM
P5VS3_REG_BOOT_R
TP_P3V3S5_REG_PGOOD
P3V3S5_REG_BOOT
MIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MM DIDT=TRUE
P3V3S5_REG_BOOT_RMIN_NECK_WIDTH=0.2MM
DIDT=TRUEMIN_LINE_WIDTH=0.6MM
P5VS3_EN
P5V_S5_VCC1
P3V3S5_REG_FB_R
P5VS5_REG_FB_R
DIDT=TRUE MIN_LINE_WIDTH=0.6MMP5VS3_REG_LGATE MIN_NECK_WIDTH=0.2 MM
PP3V3_S5_REG
P5V_S5_LDO_R
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6MM
DIDT=TRUE
P5VS3_REG_UGATE
DIDT=TRUE
P5VS3_REG_BOOT
MIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2 MM
TP_P5VS3_REG_FCCM
DIDT=TRUE
NET_PHYSICAL_TYPE=POWER
=PP12V_S5_P5VS3_VREG
P3V3S5_REG_LGATEDIDT=TRUE
MIN_LINE_WIDTH=0.6MMGATE_NODE=TRUE
MIN_NECK_WIDTH=0.2MM
P3V3S5_REG_UGATEDIDT=TRUE
GATE_NODE=TRUEMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MM
PP5V_S5_LDO
NET_PHYSICAL_TYPE=POWER
P5VS3_REG_PGOOD
PP5V_S3_REG
NET_PHYSICAL_TYPE=POWER
SYNC_DATE=07/01/2009SYNC_MASTER=K60_JERRY
5V_S3 / 3V3_S5 VREGS
16.5K1%1/16WMF-LF402
R77011
2402CERM
0.01UF16V10%
C77011
2
TLM833
CRITICALCTLSH3-30M833
D7700
1
2
3
4
5
20%
603
6.3VCERM
4.7UFC77421
2
2.2
1/8WMF-LF805
5%
R77401
2
X5R
1UF10%16V
603
C77411
2
603
16VX5R
1UF10%
C7740 1
2
CRITICAL
MMD06CZ-SM
2.2UH-14AL7710
1 2
1%1/16WMF-LF
402
16.5KR77711
2
40210%CERM16V
0.01UFC7770
1 2
MF-LF1/16W
4021%
16.5KR7770
12
10UF10%
X5R-CERM0805
16V
C7751 1
2
MF-LF1/16W1%
402
16.5KR77901 2
5%1/10W
0
MF-LF603
R77101 2
X7R10%
0.1UF
50V 603-1
C77141 2
0.4991%1/10W
NOSTUFF
MF603
R77301
2
1000PF
NOSTUFF
5%
NP0-C0G25V
402
C77301
2
402
1%1/16WMF-LF
16.5KR77911
2
10%
CERM
8200PF
603
50V
C7790
1 2
20%
603CERM16V
0.1UFC77231
2 CERM16V20%
603
0.1UFC77161
2
100UF20%16V
POLY6.3X9-TH
CRITICAL
C7713 1
2
QFNISL62383
CRITICAL
U7700
15 21
12 24
8 28
3
6 2
10 26
18
16 20
11 25
19
7 1
13 23
29
14 22
5 4
17
9 27
10%16V
0805X5R-CERM
10UFC7715 1
2
25V
402X5R
0.1UF10%
C7754 1
2
10%10UF
X5R-CERM16V
0805
C7717 1
2
X5R-CERM
10%
0805
16V
10UFC7712 1
2
MF1/16W
10.0K
402
0.5%
R77211
2
10%0.1UF
25VX5R402
C7755 1
2
MF-LF
1%
402
1/16W
45.3KR77201
2
1000PF
NP0-C0G25V5%
402
C7720 1
2
PLACEMENT_NOTE=PLACE NEXT TO C7716
OMIT
SM
XW7716
12
10UF
X5R-CERM16V10%
0805
C7710 1
2 16V10%
10UF
0805X5R-CERM
C7752 1
2X5R402
10%16V
0.1UFC77111
2
1/10W
0
5%
603MF-LF
R775012
NOSTUFFMF
1/10W1%603
0.499R7752
1
2
10UF
0805
16VX5R-CERM
10%
C7753 1
2
10%
0.1UF
25VX5R402
C7756
12
CTLSH3-30M833
TLM833
CRITICAL
D7750
1
2
3
4
5
10K1%1/16WMF-LF402
R77561
2
25VNP0-C0G
1000PF
402
5%
C7759 1
2
6.3V20%805-1CERM
10UFC77601
2 6.3VPOLY-TANT
20%330UF
CASE-D3L-SM
CRITICAL
C7761 1
2
OMITSM XW7751
1
2
10%
402
50VX7R
0.001UFC7763 1
2
X5R402
16V
0.1UF10%
C77221
2
CSD58851Q5A
CRITICAL
MLP5X6-LFPAK-Q5A
Q7751
5
4
1 2 3
10%
402
50VX7R
0.001UFC7764 1
2CSD58851Q5AMLP5X6-LFPAK-Q5A
CRITICAL
Q7750
5
4
1 2 3
WPAKRJK0384DPA
Q7710
2
1
6
7
345
270UF20%
ELEC16V
CRITICAL
8X9-TH1
C77501
2
402MF-LF1/16W
1%75K
R77551
2402
MF-LF1/16W
1%976
R77591
2
1/16WMF-LF
402
1%976
R77241
2
62
402MF-LF1/16W
68K5%
R77221
2
1/16WMF-LF402
33K5%
R77231
2
6.3V20%
CRITICAL
POLY-TANTCASE-D3L-SM
330UFC7721 1
2
CRITICAL
MMD06EZ-SM2.2UH-10A-13.6MOHM
L7750
1 2
NOSTUFF
0.001UF
CERM402
10%50V
C7757 1
2
NOSTUFF
CERM50V10%
402
0.001UFC77771
2
0.01UF
402CERM16V10%
C77471
2
16.5K1%1/16WMF-LF402
R77471
2
330UF
POLY-TANTCASE-D3L-SM
CRITICAL
20%6.3V
C77621
2
6
89
89
89
89 89
89
89
89 89
89
89
91 62
89
6
89
89
6
89
89
6
92 6
G
D
S
G
D
S
MODE
VDDQSNSCOMP
NC0
NC1
VTTSNS
VTT
VTTREF
PGOOD
S3
S5
VTTGND THRM_PAD GND CS_GNDPGND
CS
LL
DRVL
DRVH
VDDQSET
VBST
VLDOINV5FILTV5IN
SYM (2 OF 2)
NCNC
IN
IN
VIN
LX
VFB
RSI
EN
POR
SKIP
GND THRM_PAD
OUT
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
(DDRREG_LL)
FEEDBACK THROUGH SHORT
Vout = VTTREF
Vout = VDDQSNS/2
10mA max load
OFF
(DDRREG_DRVH)
(DDRREG_CSGND)
ONON
Vo=0.8*(1+ 59/47)=1.804V
Vo=0.8*(1+ Ra/Rb)
<Rb>
<Ra>
Vout = 0.75V * (1 + Ra / Rb)
<Rb>
<Ra>
1.8 V SUPPLY
(NOT USED)
VDDQ PGOOD
AVG = 6.7APEAK = 11AVOUT = 1.5V
PPDDR_S3_REG
S3S5
S0 HI
LOLO HI
S5HI
LOONOFF
ON
OFF
SHOULD NOT NEED TP
ONVTT
(DDRREG_DRVL)
EMC CAPSPLACE CLOSE TO FET
EMC CAPSPLACE CLOSE TO L7830
OUTPUT BULK DECOUPLING:
(DDRREG_VDDQSNS)
(DDRREG_FB)
VTT Enable
1.5 V DDR SUPPLY
OFF
VDDQS3STATE VTTREF
VDDQ/VTTREF Enable
78 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
PP1V5_S3_REG
NET_PHYSICAL_TYPE=POWER
NET_PHYSICAL_TYPE=POWER
MIN_LINE_WIDTH=0.6 mmDDR_REG_PHASE
DIDT=TRUEMIN_NECK_WIDTH=0.2 mm
SWITCHNODE
NET_PHYSICAL_TYPE=POWER
DDR_REG_CS
VOLTAGE=0VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm
AGND_DDR_REG
PPVTT_S3_DDR_BUF
PPVTT_S0_DDR_LDO
=PP5V_S3_DDR_VREG
NET_PHYSICAL_TYPE=POWER
DDR_REG_BOOT_R
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
=PP5V_S0_P1V8_VREG
P1V8_REG_SKIP
DIDT=TRUEMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmDDR_REG_BOOT
1V5_SNUBBER
MIN_NECK_WIDTH=0.4MMDIDT=TRUE
MIN_LINE_WIDTH=0.4MM
P1V8_REG_POR
MIN_NECK_WIDTH=0.2 mm
DDR_REG_PGND
MIN_LINE_WIDTH=0.2 mm
P1V8_REG_VFB
DDR_REG_FB
SWITCHNODEDIDT=TRUENET_PHYSICAL_TYPE=POWER
P1V8_REG_PHASE
PP1V8_S0_REG
NET_PHYSICAL_TYPE=POWER
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm
DIDT=TRUEDDR_REG_LGATE
DDR_REG_VTTSNSNO_TEST=TRUE
MIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mm
DDR_REG_VDDQSNS
DDR_REG_CSGNDMIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm
VOLTAGE=5V
PP5V_S3_DDR_REG_V5FILTNET_PHYSICAL_TYPE=POWER
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mmDIDT=TRUE
DDR_REG_UGATE
DDRVTT_EN=DDRREG_ENPM_PGOOD_DDRREG_S3
=PP12V_S5_DDR_VREGDIDT=TRUENET_PHYSICAL_TYPE=POWER
1.5V / 1.8V VREGSSYNC_MASTER=K60_JERRY SYNC_DATE=07/01/2009
10%0.001UF
402X7R50V
C78381
2
MF-LF
1%15.0K
402
1/16W
R78331
2
X5R
1UF10%
402
16V
C78511
2
16VELEC
20%270UF
CRITICAL
8X9-TH1
C7831 1
2
CRITICAL
20%270UF
16VELEC
8X9-TH1
C7830 1
2
NO STUFF
50V5%
CERM402
100PFC7820 1
2
CERM
20%22UF
805
6.3V
C78531
26.3V
805
22UF20%
CERM
C78521
2
91 62 5
CRITICAL
CTLSH3-30M833
TLM833
D7831
1234
5
6.3VX5R805
10UF10%
C7855
1
26.3VX5R805
10UF10%
C78541
2
402
1%1/16WMF-LF
15.0KR78321
2
402
50V
CERM
5%120PF
C7850
1
2 MF-LF1%
59.0K
4021/16W
R78501
2
4021%
MF-LF1/16W
47.0KR78511
2
CRITICAL
MMD04BZ-SM
2.2UH-3.25A-68M-OHML7850
1 2
1/16WMF-LF402
100K5%
R78521
2
SM
OMIT
PLACEMENT_NOTE=PLACE NEXT TO L7830
XW7830
1
2
100K5%1/16WMF-LF402
R78531
2
CRITICAL
DFNISL8009BU7850
2
7
8
3
54
9
6
1
62
91 62 32
CERM-X5R805-3
CRITICAL
22UF20%6.3V
C7804 1
220%22UF
CRITICAL
CERM-X5R805-3
6.3V
C78031
2
SM
OMITXW7803
1 2
603
6.3VCERM
20%4.7UFC7800 1
2
402
0.033UF
X5R16V10%
C7805 1
2
402MF-LF1/16W5%
4.7R7801
1 2
1UF
X5R402
10%10V
C7801 1
2
OMITSM
XW7800
1
2
SM OMITXW7801
1
2
QFN
CRITICAL
TPS51116U7800
6
16
17
21
19
3
20
4
7
12
18
13
10
11
25
14
15
22
9
8
23
24
1
5
2
1/16WMF-LF
402
1%6.04K
R7810 1
2
10%0.001UF
402X7R50V
C78391
2
10UF
6.3V
603X5R
20%
C78151
2
0
603
1/10W5%
MF-LF
R78401 2
CERM25V
603
20%
0.1UFC7840
1 2
SM
OMITPLACEMENT_NOTE=PLACE NEXT TO Q7831 XW7831
1 2
0.499
NOSTUFF
603MF1/10W1%
R78311
2
MLP5X6-LFPAK-Q5ACSD58850Q5A
CRITICAL
Q7831
5
4
1 2 3
0.1UF20%
603
16VCERM
C78331
216V
0805
10UF10%
X5R-CERM
C78321
2
MLP5X6-LFPAK-Q5A
CRITICAL
CSD58851Q5AQ7830
5
4
1 2 3
1000PF
NP0-C0G402
25V5%
NOSTUFFC7841 1
2
CRITICAL
20%
CASE-D2-HFPOLY2V
330UF-0.009OHMC78351
2
CRITICAL
MSQ12111R5LF-TH
1.5UH-22A-4MOHML7830
1 2
CRITICALNOSTUFF
POLY
20%2V
330UF-0.009OHM
CASE-D2-HF
C7836 1
2 603X5R6.3V20%10UFC78371
2
603
0.1UF
CERM16V20%
C78341
2
50 49 6
89
89
89
6
6
89
6
89
89
89
89
89
49 6
89
89
89
89
89
89
6
SW
BOOSTVIN
BIAS
SHDN*
GND
NC
FB
PADTHRM
NC
VIN
LX
VFB
RSI
EN
POR
SKIP
GND THRM_PAD
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
REMOVE for K60/K61
Supply needs to guarantee 3.31V delivered to SMC VRef generator
R7911 allow G3H current measuremnet
353S2171
3.425V "G3Hot" Supply
Remove R7911 after Proto-1
(Switcher limit)250mA max outputVout = 3.425
<Rb>
<Ra>
Vout = 1.25V * (1 + Ra / Rb)
1.05V S5 SUPPLY
79 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
MIN_NECK_WIDTH=0.4 mmVOLTAGE=12V
PP12V_G3HMIN_LINE_WIDTH=0.6 mm MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mmVOLTAGE=12V
PP12V_G3H_R
PP3V42_G3H_R
DIDT=TRUE
P3V42G3H_SW
SWITCH_NODE=TRUEMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm
P3V42G3H_BOOST
PP3V42_G3H_REG
P3V42G3H_FB
P1V05S5_REG_VFB
PP1V05_S5_REGNET_PHYSICAL_TYPE=POWER
SWITCHNODEDIDT=TRUE
NET_PHYSICAL_TYPE=POWER
P1V05_S5_REG_PHASE
P1V05S5_REG_POR
P1V05S5_REG_SKIP
P1V05S5_REG_EN_R
=PP3V3_S5_P1V05S5_VREG
NET_PHYSICAL_TYPE=POWER
SYNC_DATE=07/01/2009SYNC_MASTER=K60_JERRY
1.05 S5 SUPPLY
100K
402
5%1/16WMF-LF
NOSTUFF
R79851
2
DFNISL8009B
NOSTUFF
U7950
2
7
8
3
54
9
6
1
50VCERM402
5%120PF
NOSTUFFC7981
1
2
16V
402X5R
1UF10%
NOSTUFF
C79621
2
1K
402MF-LF1/16W5%
NOSTUFF
R79871
2
5%1/16WMF-LF402
100K
NOSTUFF
R79861
2
5%
0
MF-LF1/16W
402
R79111 2
X5R-CERM603
20%6.3V
22UFC79021
2
348K
402
1%1/16WMF-LF
R79001
2
22pF
CERM
5%50V
402
C7901 1
2
1/16W1%
402MF-LF
200KR79011
2
CRITICAL
33UH
CDPH4D19FHF-SM
L7900
1 2
0.22UF
X5R402
20%6.3V
C7900 1
2
DFNLT3470A
CRITICAL
U7900
2
3
1
5
7
8 4
9
6
1/16W5%
402MF-LF
0R79101 2
25V10%
X5R
10UF
805
C7910 1
2
10UF6.3VX5R805
10%
NOSTUFFC79611
2
10UF6.3VX5R805
10%
NOSTUFF
C79601
2
402
1/16W1%100K
MF-LF
NOSTUFF
R79821
2
31.6K1%
402MF-LF1/16W
NOSTUFFR79811
2
10UF6.3V20%
603X5R
NOSTUFF
C79401
26.3VX5R603
10UF20%
NOSTUFF
C79501
2
2.2UH-3.25A-68M-OHM
MMD04BZ-SM
NOSTUFF
L7950
1 2402MF-LF
100K5%1/16W
NOSTUFF
R79801
2
89 6
89
89 89
89
6
89
89
6
89
6
G
SD
G
SD
G
SD
G S
D
G
DS
G
PG
THRMGND
NC
D
VCC
S
ON
PAD
G
D
S
G
D
S
IN
G
PG
THRMGND
NC
D
VCC
S
ON
PAD
G
PG
THRMGND
NC
D
VCC
S
ON
PAD
IN
IN
G
PG
THRMGND
NC
D
VCC
S
ON
PAD
IN
G
SD
G
D
S
G
D
S
G
PG
THRMGND
NC
D
VCC
S
ON
PAD
IN
IN
G
SD
G
S D
G
SD
G
SD
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
1V05 ME FETS (S0: 2.2A MAX SM: 387MA)
5V S0 FET (7A PK/2.7A AVG)
12V S3 FET ( < 200MA )
REMOVE ALL OF THIS FOR PROTO2
R8063 ADD FOR PROTO1 TO KEEP Q8060 OFF
PP3V3_ME_FET
KEEP PADS IN CASE VCC ME IS REQUIRED
3.3VME FET (86MA MAX)
3.3V S3 FET (2.9A PK / 1.2A AVG)
NOTE:
ON PAGE 6
3.3V S0 FET (3.4APK / 1.9A AVG)
IN STATES OTHER THAN S0. DELETE AFTER PROTO1
BYPASS FET CIRCUIT FOR PROTO 1
IN STATES OTHER THAN S0. DELETE AFTER PROTO1
KEEP PADS IN CASE VCC_3V3 ME IS REQUIRED
1.5V S0 FET (6.2A PK / 3A AVG)BYPASS FET CIRCUIT FOR PROTO 1
ALIAS =PP3V3_ME_PWRCTL TO
80 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
PP3V3_S3_FET
=PP3V3_S5_S3FET
PGOOD_P3V3_S3
=PP12V_S5_PWRCTL
=PP12V_S5_PWRCTL
=PP1V05_S0_SM_FET
=PP3V3_S5_S0FET
PP5V_S0_FET
P1V5_S0_EN
=PP1V05_S5_SM_FET
PM_ME_S0_EN_R
P1V05_ME_SM_EN_G
PM_ME_S0_EN_G1
=PP3V3_S3_PWRCTL
P1V05_ME_SM_EN
P1V5_S0_EN_G
P3V3_S0_EN_G
P3V3_S3_EN_G
P5V_S0_EN_G
=PPDDR_S3_S0FET
P1V05_ME_S0_EN
=PP3V3_S0_PWRCTL
P3V3S3_EN
=PP12V_S5_PWRCTL
=PP3V3_S0_PWRCTL
PP3V3_S0_FET
P3V3S0_EN
=PP5V_S3_S0FET
PGOOD_P5V_S0
=PP3V3_S0_PWRCTL
PGOOD_P3V3_S0
PGOOD_P1V5_S0
P12V_S3_EN
P12V_S3_EN_D
=PP12V_S5_S3_FET
P12V_S3_EN_G
=PP12V_S5_PWRCTL
=PP12V_S5_PWRCTL
PP1V05_SM_SOURCE
VOLTAGE=12VMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=POWER
MAKE_BASE=TRUEPP12V_S3_FET
P5VS0_EN
=PP12V_S5_PWRCTL
NET_SPACING_TYPE=POWER
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.5 mm
MAKE_BASE=TRUEPP3V3_SM_FET
MAX_NECK_LENGTH=3 MM
=PP3V3_S0_ME
=PP3V3_SM_PWRCTL
P3V3ME_EN
PP1V05_SM_FETMAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 mmVOLTAGE=1.05V
MIN_NECK_WIDTH=0.2 mm
MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=POWER
VOLTAGE=1.5V
NET_SPACING_TYPE=POWER
PP1V5_S0_FETMAKE_BASE=TRUE
MAX_NECK_LENGTH=3 MM
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.4MM
P3V3_ME_EN_G
P1V05_ME_SM_EN_D P1V05_ME_SM_EN_G2
=PP12V_S5_PWRCTL
=PP3V3_S5_SM_FET
PM_ME_S0_EN_G
PGOOD_P3V3_ME
S3+S0 FETSSYNC_MASTER=K60_MIKE SYNC_DATE=07/01/2009
CRITICAL
POWER33FDMC8296Q8025
5
4
1
2
3
POWER33FDMC8296
NOSTUFF
Q8060
5
4
1
2
3
POWER33FDMC8296
NOSTUFF
Q8081
5
4
1
2
3
NOSTUFF
POWER33FDMC8296Q8080
5
4
1
2
3
91 62
NOSTUFF
5%1/16W
10K
MF-LF402
R80301
2
91 62
5%
0
MF-LF1/10W
603
R80711 2
1206
1/4W
0
5%
MF-LF
R80841 2
NOSTUFF
402MF-LF
10K1/16W5%
R80201
2
10K5%1/16WMF-LF402
NOSTUFF
R80701
2
10K
402
5%1/16WMF-LF
R80511
2
MF-LF1/16W5%
402
10KR80501
2
NOSTUFF
402MF-LF
10K1/16W5%
R80001
2
805
16V10%X7R
0.47UF
NOSTUFF
C80801
2
NOSTUFF
10K
1/16WMF-LF
5%
402
R80821 2
MF-LF1/16W5%
402
10K
NOSTUFF
R80811
2
SLG5AP001
CRITICAL
TDFN
U8050
5
7
4
3
2
8
6
9
1
NOSTUFF
1/16W5%
402
10K
MF-LF
R80801
2
SOT-3632N7002DW-X-G
NOSTUFFQ8082
3
5
4
2N7002DW-X-GSOT-363
Q8082
6
2
1
POWER33FDMC8296
CRITICALQ8053
5
4
1
2
3
91 62
TDFNSLG5AP001
CRITICAL
NOSTUFF
U8070
5
7
4
3
2
8
6
9
1
16VX5R
10%0.1UF
402
C80531
2
402
0.1UF16VX5R
10%
NOSTUFF
C80701
2
91 62
91 62
CRITICAL
TDFNSLG5AP001U8025
5
7
4
3
2
8
6
9
1
10%
X5R16V
402
0.1UFC80251
2
SLG5AP001TDFN
CRITICAL
U8000
5
7
4
3
2
8
6
9
1
402X5R16V10%0.1UFC80001
2
100K
402MF-LF1/16W5%
NOSTUFF
R80751
2
5%1/16WMF-LF
100K
402
NOSTUFF
R80891
2
402MF-LF1/16W5%10K
NOSTUFF
R80631
2
91 62
10UF
X5R603
20%6.3V
NOSTUFF
C80831
2603X5R
20%10UF6.3V
NOSTUFF
C80821
2
10K
5%
402
1/16WMF-LF
NOSTUFF
R80621 2
402MF-LF
10K5%
NOSTUFF
1/16W
R80611
2
10K
402
5%
MF-LF1/16W
NOSTUFFR80601
2
16VX7R805
10%0.47UF
NOSTUFF
C80601
2
SOT-3632N7002DW-X-GQ8063
3
5
4
2N7002DW-X-GSOT-363
NOSTUFFQ8063
6
2
1
TDFN
CRITICAL
SLG5AP001U8053
5
7
4
3
2
8
6
9
1
NOSTUFF
0.47UF
805
16V10%
X7R
C80301
2
NOSTUFF
402
5%
MF-LF1/16W
10KR80311 2
NOSTUFF
TP0610S0T23-3
Q8030
3
1
2
NOSTUFF
SOT23-HF12N7002Q8031
3
1
2
POWER33FDMC8296
NOSTUFF
Q8070
5
4
1
2
3
CRITICAL
POWER33FDMC8296Q8050
5
4
1
2
3
POWER33
CRITICAL
FDMC8296Q8000
5
4
1
2
3
16VX5R
10%0.1UF
402
C80501
2
6
6
91 34
72 63 6
72 63 6
6
6
6
6
91
91
63 6
91 62
6
62
72 63 62 6 5
72 63 6
72 63 62 6 5
6 6
91 62
72 63 62 6 5
91 63 48
6
72
63 6
72 63 6
6
72 63 6
6
6
63 6
6
49 6
72 63 6
6
91
3V3
5V
PWR_SRC
(4 OF 4)
PCI-E
DP
(2 OF 4)
PEX_TX15*
DP_A_AUX*
PEX_TX1*
PEX_TX13
PEX_TX11*
PEX_TX7*
PEX_TX8*
PEX_TX9
PEX_TX10
PEX_STD_SW*
PEX_TX15
PEX_TX14*
PEX_TX14
PEX_TX13*
PEX_TX12*
PEX_TX12
PEX_TX11
PEX_TX10*
PEX_TX9*
PEX_TX8
PEX_TX7
PEX_TX6*
PEX_TX6
PEX_TX5*
PEX_TX5
PEX_TX4*
PEX_TX4
PEX_TX3*
PEX_TX3
PEX_TX2*
PEX_TX2
PEX_TX1
PEX_TX0*
PEX_TX0
PEX_REFCLK*
PEX_REFCLK
PEX_RST*
DP_C_HPD
DP_D_HPD
DP_B_HPD
DP_A_HPD
PEX_RX15*
PEX_RX15
PEX_RX14*
PEX_RX14
PEX_RX13*
PEX_RX13
PEX_RX12*
PEX_RX12
PEX_RX11*
PEX_RX11
PEX_RX10*
PEX_RX10
PEX_RX9*
PEX_RX9
PEX_RX8*
PEX_RX8
PEX_RX7*
PEX_RX7
PEX_RX6*
PEX_RX6
PEX_RX5*
PEX_RX5
PEX_RX4*
PEX_RX4
PEX_RX3*
PEX_RX3
PEX_RX2*
PEX_RX2
PEX_RX1*
PEX_RX1
PEX_RX0*
PEX_RX0
CLK_REQ*
DP_C_L0*
DP_C_L0
DP_C_L1*
DP_D_L0*
DP_C_L1
DP_D_L0
DP_C_L2*
DP_D_L1*
DP_C_L2
DP_D_L1
DP_C_L3*
DP_D_L2*
DP_C_L3
DP_D_L2
DP_D_L3*
DP_D_L3
DP_B_L0*
DP_B_L0
DP_B_L1*
DP_A_L0*
DP_B_L1
DP_A_L0
DP_B_L2*
DP_A_L1*
DP_B_L2
DP_A_L1
DP_B_L3*
DP_A_L2*
DP_B_L3
DP_A_L2
DP_A_L3*
DP_A_L3
DP_C_AUX*
DP_C_AUX
DP_D_AUX*
DP_D_AUX
DP_B_AUX*
DP_B_AUX
DP_A_AUX
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
Page Notes
Signal aliases required by this page:
APPLE P/N: 516S0699
BOM options provided by this page:
- =PP3V3_S0_MXM
PLATFORM DEPENDENT
(NOT NECESSARILY THE SAME FOR EVERY MODULE)
MXM SPEC POWER REQUIREMENTS
VOLTAGE
PWR (7-20V)
- =PP5V_S0_MXM
(NONE)
12.5 W
3.3 W
POWERCURRENT
UP TO 10 A
2.5 A
1.0 A3V3
5V
Power aliases required by this page:
- =PPV_S0_MXM_PWRSRC
- MXM
84 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
MXM_PCIE_STD_SWING_L
MXM_RESET_L
MXM_PCIE_D2R_P<1>
MXM_PCIE_D2R_N<6>
MXM_PCIE_D2R_N<10>
MXM_PCIE_D2R_N<11>
MXM_DP_A_ML_P<0>
MXM_DP_A_ML_N<1>
MXM_DP_A_ML_P<1>
MXM_DP_A_ML_N<2>
MXM_DP_A_ML_P<2>
MXM_PCIE_D2R_N<2>
MXM_PCIE_D2R_N<9>
MXM_PCIE_D2R_P<7>
MXM_PCIE_D2R_P<5>
MXM_PCIE_D2R_N<5>
MXM_PCIE_D2R_P<6>
MXM_PCIE_D2R_P<12>
MXM_PCIE_D2R_N<12>
MXM_PCIE_D2R_N<13>
MXM_PCIE_D2R_P<15>
MXM_PCIE_D2R_P<10>
MXM_PCIE_D2R_P<9>
MXM_PCIE_D2R_N<8>
MXM_PCIE_D2R_P<4>
MXM_PCIE_D2R_N<7>
MXM_PCIE_D2R_P<11>
MXM_PCIE_D2R_P<13>
MXM_PCIE_D2R_N<14>
MXM_PCIE_D2R_P<14>
MXM_PCIE_D2R_N<15>
MXM_PCIE_D2R_P<8>
MXM_PCIE_D2R_P<3>
MXM_PCIE_D2R_N<3>
MXM_PCIE_D2R_N<4>
MXM_PCIE_D2R_P<2>
MXM_PCIE_D2R_N<1>
MXM_PCIE_D2R_P<0>
MXM_PCIE_D2R_N<0>
MXM_PCIE_R2D_N<2>
MXM_PCIE_R2D_P<2>
MXM_PCIE_R2D_P<3>
MXM_PCIE_R2D_N<3>
MXM_PCIE_R2D_N<4>
MXM_PCIE_R2D_N<5>
MXM_PCIE_R2D_P<5>
MXM_PCIE_R2D_N<6>
MXM_PCIE_R2D_P<8>
MXM_PCIE_R2D_N<1>
MXM_PCIE_R2D_P<10>
MXM_PCIE_R2D_N<10>
MXM_PCIE_R2D_N<9>
MXM_PCIE_R2D_N<8>
MXM_PCIE_R2D_P<6>
MXM_PCIE_R2D_P<0>
MXM_PCIE_R2D_N<11>
MXM_PCIE_R2D_P<12>
MXM_PCIE_R2D_P<13>
MXM_PCIE_R2D_P<14>
MXM_PCIE_R2D_N<14>
MXM_PCIE_R2D_P<15>
MXM_PCIE_R2D_N<15>
MXM_PCIE_R2D_P<7>
MXM_PCIE_R2D_P<11>
MXM_PCIE_R2D_N<13>
MXM_PCIE_R2D_N<12>
MXM_PCIE_R2D_P<9>
MXM_PCIE_R2D_P<1>
MXM_PCIE_R2D_P<4>
MXM_PCIE_R2D_N<7>
MXM_PCIE_R2D_N<0>
MXM_DP_C_AUX_P
MXM_DP_B_ML_N<0>
MXM_CLKREQ_L
MXM_DP_B_AUX_P
MXM_DP_B_HPD
MXM_DP_B_ML_P<0>
CLK_100M_MXM_N
CLK_100M_MXM_P
MXM_DP_C_HPD
MXM_DP_D_HPD
MXM_DP_A_HPD
MXM_DP_C_ML_N<0>
MXM_DP_C_ML_P<0>
MXM_DP_C_ML_N<1>
MXM_DP_D_ML_N<0>
MXM_DP_C_ML_P<1>
MXM_DP_D_ML_P<0>
MXM_DP_C_ML_N<2>
MXM_DP_D_ML_N<1>
MXM_DP_C_ML_P<2>
MXM_DP_D_ML_P<1>
MXM_DP_C_ML_N<3>
MXM_DP_D_ML_N<2>
MXM_DP_C_ML_P<3>
MXM_DP_D_ML_P<2>
MXM_DP_D_ML_N<3>
MXM_DP_D_ML_P<3>
MXM_DP_B_ML_N<1>
MXM_DP_A_ML_N<0>
MXM_DP_B_ML_P<1>
MXM_DP_B_ML_N<2>
MXM_DP_B_ML_P<2>
MXM_DP_B_ML_N<3>
MXM_DP_B_ML_P<3>
MXM_DP_A_ML_N<3>
MXM_DP_A_ML_P<3>
MXM_DP_C_AUX_N
MXM_DP_D_AUX_N
MXM_DP_D_AUX_P
MXM_DP_B_AUX_N
=PP3V3_S0_MXM
MXM_DP_A_AUX_N
MXM_DP_A_AUX_P
=PPV_S0_MXM_PWRSRC
=PP3V3_S0_MXM
=PP5V_S0_MXM
MXM PCIe, DP & PowerSYNC_DATE=07/16/2009SYNC_MASTER=K23_AARON
B35P101-0121
MXM
F-RT-SM
CRITICALJ8400
154
279
277
276
255
253
261
259
267
265
273
271
272
270
274
248
246
254
252
260
258
266
264
225
223
234
201
199
207
205
213
211
219
217
232
230
236
208
206
214
212
220
218
226
224
155
153
156
149
147
143
141
81
79
75
73
69
67
63
61
57
55
51
49
137
135
123
121
117
115
111
109
105
103
99
97
93
91
87
85
19
150
148
144
142
80
78
74
72
68
66
62
60
56
54
50
48
138
136
122
120
116
114
110
108
104
102
98
96
92
90
86
84
B35P101-0121
MXM
F-RT-SM
J8400
278
280
1
3
5
7
9
E1
E2
0.001UF50V
402X7R
10%
MXM
C84151
2
22UF20%6.3V
MXM
CERM-X5R805-3
C84161
2
MXM
MF-LF
5%1/16W
402
100KR84001
2
0.001UF50V
402
10%
X7R
MXM
C84141
2
0.001UF50V10%
X7R402
MXM
C84131
2
0.001UF50V
402
10%
X7R
MXM
C84121
2
50V
402X7R
10%
MXM
0.001UFC84101
2
22UF20%6.3V
MXM
CERM-X5R805-3
C84011
2
MXM
20%
6.3X5.5-SM1ELEC35V
22UFC84001
2
74
9
84 75
84 75
84 75
84 75
87 78
87 78
87 78
87 78
87 78
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
84 75
87 79
87 76
9
87 76
76
87 76
9
9
79
76
78
87 79
87 79
87 79
87 76
87 79
87 76
87 79
87 76
87 79
87 76
87 79
87 76
87 79
87 76
87 76
87 76
87 76
87 78
87 76
87 76
87 76
87 76
87 76
87 78
87 78
87 79
87 76
87 76
87 76
74 73 63 6
87 78
87 78
50
74 73 63 6
6
WC*
SDA
SCL
E2/NC2
E1/NC1
E0/NC0
VSS
VCC
GPIO0
VGA_DISABLE*
TH_OVERT*
TH_PWM
LVDS_DDC_CLK
LVDS_UTX1
LVDS_UTX2*
RSVD1
PNL_PWR_EN
LVDS_UTX1*
RSVD2
LVDS_UTX2
LVDS_UTX3*
LVDS_LCLK
PRSNT_R*
LVDS_LTX3
DVI_HPD
PWR_EN
SMB_CLK
LVDS_LTX0
LVDS_LTX0*
LVDS_LTX1
LVDS_LTX2
LVDS_LTX2*
LVDS_LTX3*
LVDS_UTX0
LVDS_UTX0*
LVDS_UTX3
PNL_BL_EN
PRSNT_L*
PWRGOOD
VGA_BLUE
VGA_GREEN
VGA_HSYNC
VGA_RED
VGA_VSYNC
VGA_DDC_DAT
GPIO1
GPIO2
HDMI_CEC
OEM0
OEM1
OEM2
OEM3
OEM4
OEM5
OEM7
VGA_DDC_CLK
RSVD3
RSVD4
RSVD5
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD21
SMB_DAT
TH_ALERT*
LVDS_UCLK*
LVDS_UCLK
RSVD20
LVDS_LCLK*
LVDS_LTX1*
RSVD6
RSVD0
RSVD22
RSVD23
PWR_LEVEL
LVDS_DDC_DAT
PNL_BL_PWM
OEM6
WAKE*
SYSTEM MANAGEMENT
(1 OF 4)
LVDS
ANALOG DISPLAY
POWER/THERMAL
MANAGEMENT
GNDGND
(3 OF 4)
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
FLOAT = LOW SWINGGND = HIGH SWING
Signal aliases required by this page:
- =PP3V3_S0_MXM
Page NotesPower aliases required by this page:
- =PM_MXM_PGOOD_PULLUP
STUFF FOR WRITE PROTECT
BOM options provided by this page:
PULLED TO GROUND ON MXMWE DON’T USE CARD DETECT
PLACE CLOSE TO J7800
MXM SYSTEM INFORMATION ROM
OR ANOTHER OPEN-DRAIN PGOOD SIGNAL DEPENDING ON DESIRED BEHAVIOR
SYSTEM INTEGRATOR MUST ALIAS THIS EITHER TO A VOLTAGE RAIL,
I2C ADDRESS: AC
- =SMB_MXM_THRM_CLK
- =SMB_MXM_THRM_DATA PULLUPS & PULLDOWNS AT MXM CONNECTOR
FLOAT = NORMAL VGA MODEGND = SECONDARY DISPLAY CARD
85 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
MXM_PNL_BL_PWM
MXM_PNL_PWR_EN
=PM_MXM_PGOOD_PULLUP
TP_MXM_HDMI_CEC
TP_MXM_GPIO2
TP_MXM_GPIO1
TP_MXM_GPIO0
MXM_LVDS_DDC_CLK
MXM_LVDS_DDC_DAT
TP_MXM_DVI_HPD
MXM_LVDS_A_CLK_N
MXM_LVDS_A_CLK_P
TP_MXM_TH_PWM
TP_MXM_VGA_DDC_CLK
TP_MXM_VGA_DDC_DAT
TP_MXM_VGA_RED
TP_MXM_VGA_VSYNC
TP_MXM_VGA_BLUE
MXM_LVDS_A_DATA_N<2>
PM_MXM_PGOOD
MXM_LVDS_B_DATA_P<2>
MXM_LVDS_B_DATA_N<0>
MXM_LVDS_B_DATA_P<0>
MXM_LVDS_B_DATA_N<1>
MXM_LVDS_B_DATA_P<1>
MXM_LVDS_B_DATA_N<2>
MXM_LVDS_B_DATA_N<3>
MXM_LVDS_B_DATA_P<3>
MXM_LVDS_B_CLK_N
MXM_LVDS_B_CLK_P
MXM_LVDS_A_DATA_P<3>
MXM_LVDS_A_DATA_N<3>
MXM_LVDS_A_DATA_P<2>
MXM_LVDS_A_DATA_P<1>
MXM_LVDS_A_DATA_N<1>
TP_MXM_WAKE_L
MXM_DETECT_R
MXM_DETECT_L
MXM_OVERT_L
MXM_ALERT_L
=SMB_MXM_THRM_SDA
=SMB_MXM_THRM_SCL
MXM_PWR_LEVEL
PM_MXM_PGOOD
PM_MXM_EN
MXM_DETECT_L
MXM_LVDS_DDC_DAT
MXM_ROM_WP
MXM_LVDS_DDC_CLK
MXM_VGA_DISABLE_L
MXM_LVDS_A_DATA_P<0>
MXM_LVDS_A_DATA_N<0>
=PP3V3_S0_MXM
MXM_DETECT_R
=PP3V3_S0_MXM
MXM_PNL_BL_EN
TP_MXM_VGA_HSYNC
TP_MXM_VGA_GREEN
MXM_PCIE_STD_SWING_L
MXM_VGA_DISABLE_L
MXM I/OSYNC_DATE=07/16/2009SYNC_MASTER=K23_AARON
NOSTUFF
0
5%
402
MF-LF 1/16W
R851012
MXM
0
402
5%MF-LF 1/16W
R850412
F-RT-SM
MXM
B35P101-0121J8400
11
13
58
59
64
65
70
71
76
77
82
83
15
88
89
94
95
100
101
106
107
112
113
17
118
119
124
125
133
134
139
140
145
146
36
151
152
157
166
173
174
179
180
185
186
37
191
192
197
198
203
204
209
210
215
216
46
221
222
228
244
E3
250
251
256
257
262
47
263
268
269
275
E4
282
283
52
53
B35P101-0121
MXM
F-RT-SM
J8400
31 26
28
30
29
35
33
178
176
202
200
196
194
190
188
184
182
171
169
195
193
189
187
183
181
177
175
38
39
40
41
42
43
44
45
25
27
23
281
2
8
18
6
10
159
233
235
237
238
239
240
241
242
243
245
12
247
249
14
16
161
163
165
167
227
229
231
34
32
22
20
24
172
160
158
21
170
164
168
162
4
402
MF-LF 5%
10K
1/16W
R850312
100K
5%MF-LF 1/16W402
R85011 2
M24C02-WMN6TPHFSO8
CRITICAL
MXM
U8570
1
2
3
6
5
8
4
7
100K
1/16W5%402
MF-LF
R85001 2
402CERM
20%10V
0.1UF
MXM
C85701
2NOSTUFF
0
402
5%1/16WMF-LF
R85701
2
81
81
63
74
74
87 76
87 76
87 76
91 74 63
87 76
87 76
87 76
87 76
87 76
87 76
87 76
87 76
87 76
87 76
87 76
87 76
87 76
87 76
87 76
74
74
46
46
48
48
46
91 74 63
63
74
74
74
74
87 76
87 76
74 73 63 6
74
74 73 63 6
81
73
74
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
IN
IN
OUT
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
MXM TX CAPS MXM RX CAPS
86 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
PEG_R2D_C_N<1>
PEG_R2D_C_N<2>
PEG_R2D_C_P<3>
MXM_PCIE_R2D_P<9>
MXM_PCIE_R2D_P<8>
MXM_PCIE_D2R_P<3>
MXM_PCIE_D2R_N<3>
MXM_PCIE_D2R_P<2>
MXM_PCIE_D2R_N<2>
PEG_D2R_P<14>
MXM_PCIE_D2R_N<5>
PEG_R2D_C_P<4>
MXM_PCIE_R2D_N<14>
PEG_R2D_C_P<11>
PEG_R2D_C_N<13>
PEG_R2D_C_N<15>
MXM_PCIE_R2D_P<11>
MXM_PCIE_R2D_N<11>
MXM_PCIE_D2R_N<15>
PEG_D2R_N<0>
PEG_D2R_N<3>
PEG_D2R_N<12>
PEG_D2R_N<10>
PEG_R2D_C_N<5>
MXM_PCIE_D2R_P<4>
MXM_PCIE_D2R_N<1>
MXM_PCIE_D2R_P<0>
MXM_PCIE_D2R_N<0>
MXM_PCIE_D2R_P<1>
MXM_PCIE_D2R_P<13>
MXM_PCIE_D2R_N<13>
MXM_PCIE_D2R_P<12>
MXM_PCIE_D2R_N<12>
MXM_PCIE_R2D_N<15>PEG_R2D_C_N<0>
MXM_PCIE_R2D_P<14>
MXM_PCIE_R2D_P<12>
MXM_PCIE_R2D_N<10>
PEG_R2D_C_P<13>
PEG_R2D_C_P<14>
PEG_R2D_C_N<14>
PEG_R2D_C_P<15>
MXM_PCIE_R2D_P<15>
MXM_PCIE_R2D_P<13>
MXM_PCIE_R2D_N<12>
MXM_PCIE_D2R_N<14>
MXM_PCIE_D2R_P<14>
MXM_PCIE_R2D_P<10>
PEG_R2D_C_P<10>
MXM_PCIE_R2D_P<5>
PEG_D2R_P<4>
PEG_R2D_C_N<12>
PEG_R2D_C_P<12>
PEG_R2D_C_N<10>
PEG_R2D_C_P<5>
PEG_R2D_C_P<6>
PEG_R2D_C_N<6>
PEG_R2D_C_P<7>
PEG_R2D_C_P<8>
PEG_R2D_C_N<8>
PEG_R2D_C_N<11>
PEG_R2D_C_N<9>
PEG_R2D_C_P<9>
PEG_R2D_C_N<7>
MXM_PCIE_R2D_N<5>
MXM_PCIE_R2D_P<4>
MXM_PCIE_R2D_N<4>
MXM_PCIE_R2D_N<3>
MXM_PCIE_R2D_P<3>
MXM_PCIE_R2D_P<2>
MXM_PCIE_R2D_N<2>
MXM_PCIE_R2D_N<1>
MXM_PCIE_R2D_P<1>
MXM_PCIE_R2D_N<0>
MXM_PCIE_R2D_N<9>
MXM_PCIE_R2D_N<8>
MXM_PCIE_R2D_P<7>
MXM_PCIE_R2D_N<7>
MXM_PCIE_R2D_P<6>
MXM_PCIE_R2D_N<6>
MXM_PCIE_R2D_P<0>
MXM_PCIE_D2R_P<8>
MXM_PCIE_D2R_P<7>
MXM_PCIE_D2R_P<5>
MXM_PCIE_D2R_N<8>
MXM_PCIE_D2R_N<9>
MXM_PCIE_D2R_P<9>
MXM_PCIE_D2R_N<10>
MXM_PCIE_D2R_P<10>
MXM_PCIE_D2R_N<11>
MXM_PCIE_D2R_P<11>
PEG_D2R_P<7>
PEG_D2R_P<12>
PEG_D2R_N<6>
PEG_D2R_N<7>
PEG_D2R_P<10>
PEG_D2R_N<14>
PEG_D2R_N<4>
PEG_D2R_N<9>
PEG_D2R_P<9>
PEG_D2R_N<11>
PEG_D2R_P<13>
PEG_D2R_N<13>
PEG_D2R_P<15>
PEG_D2R_N<15>
PEG_D2R_P<5>
PEG_D2R_N<5>
PEG_D2R_P<11>
PEG_D2R_P<6>
PEG_D2R_P<2>
PEG_D2R_N<2>
MXM_PCIE_R2D_N<13>
PEG_D2R_P<3>
MXM_PCIE_D2R_N<4>
MXM_PCIE_D2R_P<15>
PEG_D2R_P<1>
PEG_D2R_N<1>
PEG_D2R_P<0>
MXM_PCIE_D2R_N<7>
MXM_PCIE_D2R_N<6>
MXM_PCIE_D2R_P<6>
PEG_D2R_P<8>
PEG_D2R_N<8>
PEG_R2D_C_P<0>
PEG_R2D_C_N<4>
PEG_R2D_C_N<3>
PEG_R2D_C_P<2>
PEG_R2D_C_P<1>
MXM PCIE CAPSSYNC_MASTER=K60_AARON SYNC_DATE=07/01/2009
84 73
84 73
84 73
84 73
84 73
84 73
84 73
84 73
84 73
84 73
16V 40210%0.1UF X5RMXM C8634 1 2
84 73
84 73
84 73
16V10% X5R 4020.1UFMXM C8661 1 2
16V10% X5R 4020.1UFMXM C8659 1 2
16V X5R 40210%0.1UFMXM C8660 1 2
16V10% X5R 4020.1UFMXM C8663 1 2
16V X5R10% 4020.1UFMXM C8662 1 2
MXM 16V10% X5R 4020.1UFC8658 1 2
10% X5R 4020.1UF 16VMXM C8656 1 2
16V10% 4020.1UF X5RMXM C8635 1 2
16V X5R 4020.1UF 10%MXM C8657 1 2
16V10% X5R0.1UF 402MXM C8655 1 2
16V10% X5R0.1UF 402MXM C8654 1 2
84 73
84 73
84 73
84 73
84 73
84 73
84 73
0.1UF 40210% 16V X5RMXM C8633 1 2
84 73
84 73
84 73
84 73
84 73
84 73
84 73
84 73
84 73
84 73
0.1UF 40210% 16V X5RMXM C8632 1 2
0.1UF 16V10% X5R 402MXM C8650 1 2
0.1UF 16V10% X5R 402MXM C8651 1 2
16V10% X5R 4020.1UFMXM C8653 1 2
16V10% X5R 4020.1UFMXM C8652 1 2
40216V10% X5R0.1UFMXM C8649 1 2
0.1UF 16V10% X5R 402MXM C8648 1 2
0.1UF 10% 16V 402X5RMXM C8647 1 2
0.1UF 402X5R10% 16VMXM C8646 1 2
402X5R10% 16V0.1UFMXM C8645 1 2
0.1UF 402X5R10% 16VMXM C8644 1 2
84 9
402X5R10% 16V0.1UFMXM C8643 1 2
0.1UF 402X5R10% 16VMXM C8642 1 2
0.1UF 40210% X5R16VMXM C8640 1 2
0.1UF 16V 402X5R10%MXM C8641 1 2
0.1UF 402X5R10% 16VMXM C8639 1 2
0.1UF X5R10% 40216VMXM C8638 1 2
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
0.1UF 402X5R10% 16VMXM C8631 1 2
0.1UF 402X5R10% 16VMXM C8629 1 2
0.1UF 402X5R10% 16VMXM C8630 1 2
0.1UF 402X5R10% 16VMXM C8627 1 2
84 9
402X5R10% 16V0.1UFMXM C8628 1 2
0.1UF 402X5R10% 16VMXM C8626 1 2
16V10% X5R 4020.1UFMXM C8625 1 2
16V10% X5R 4020.1UFMXM C8624 1 2
0.1UF 402X5R10% 16VMXM C8623 1 2
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
84 9
10%0.1UF X5R 40216VMXM C8637 1 2
84 9
84 9
84 9
16V10% X5R 4020.1UFMXM C8621 1 2
0.1UF 402X5R10% 16VMXM C8622 1 2
16V10% X5R 4020.1UFMXM C8619 1 2
16V10% X5R 4020.1UFMXM C8620 1 2
16V10% X5R 4020.1UFMXM C8617 1 2
16V10% X5R 4020.1UFMXM C8618 1 2
0.1UF 16V10% X5R 402MXM C8616 1 2
84 73
16V10% X5R 4020.1UFMXM C8615 1 2
16V10% X5R 4020.1UFMXM C8614 1 2
10% 16V X5R 4020.1UFMXM C8613 1 2
10% X5R0.1UF 40216VMXM C8612 1 2
0.1UF 10% 16V X5R 402MXM C8611 1 2
0.1UF 16V10% X5R 402MXM C8610 1 2
10% 16V X5R 4020.1UFMXM C8609 1 2
MXM 16V X5R 4020.1UF 10%C8608 1 2
X5R10% 16V0.1UF 402MXM C8607 1 2
10% 16V 4020.1UF X5RMXM C8606 1 2
84 73
84 73
84 73
84 73
84 73
84 73
84 73
84 73
84 73
84 73
84 73
84 73
84 73
84 73
84 73
84 73
84 73
84 73
84 73
84 73
84 73
84 73
84 73
84 73
84 73
84 73
84 73
84 73
84 73
84 73 10% 4020.1UF X5R16VMXM C8605 1 2
84 9
84 9
84 73
84 9
84 9
84 9
0.1UF 402X5R10% 16VMXM C8603 1 2
10%0.1UF X5R 40216VMXM C8604 1 2
0.1UF 16V X5R10% 402MXM C8601 1 2
402X5R10% 16V0.1UFMXM C8602 1 2
40216V0.1UF X5R10%MXM C8600 1 2
84 73
84 73
10% X5R0.1UF 40216VMXM C8636 1 2
84 9
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
Unused MXM Interfaces
(NONE)
(NONE)
BOM options provided by this page:
Signal aliases required by this page:
Power aliases required by this page:
Page Notes- =PP3V3_S0_DP
Unused MXM DP Interfaces
MXM_LVDS_B_DATA_P<3>NO_TEST=TRUE
NC_MXM_LVDS_B_DATA_P<3>MAKE_BASE=TRUE
MXM_LVDS_B_DATA_P<2>MAKE_BASE=TRUE NO_TEST=TRUENC_MXM_LVDS_B_DATA_P<2>
MXM_LVDS_B_DATA_N<3>NO_TEST=TRUE
NC_MXM_LVDS_B_DATA_N<3>MAKE_BASE=TRUE
MXM_LVDS_B_DATA_N<2>NO_TEST=TRUE
NC_MXM_LVDS_B_DATA_N<2>MAKE_BASE=TRUE
MXM_LVDS_B_DATA_N<1>NO_TEST=TRUE
NC_MXM_LVDS_B_DATA_N<1>MAKE_BASE=TRUE
MXM_LVDS_B_DATA_P<1>NO_TEST=TRUE
NC_MXM_LVDS_B_DATA_P<1>MAKE_BASE=TRUE
MXM_LVDS_B_DATA_P<0>NO_TEST=TRUE
NC_MXM_LVDS_B_DATA_P<0>MAKE_BASE=TRUE
MXM_LVDS_B_DATA_N<0> NC_MXM_LVDS_B_DATA_N<0>NO_TEST=TRUEMAKE_BASE=TRUE
MXM_LVDS_B_CLK_PNO_TEST=TRUEMAKE_BASE=TRUE
NC_MXM_LVDS_B_CLK_P
MXM_LVDS_A_DATA_P<3>NO_TEST=TRUE
NC_MXM_LVDS_A_DATA_P<3>MAKE_BASE=TRUE
MXM_LVDS_B_CLK_NMAKE_BASE=TRUE NO_TEST=TRUENC_MXM_LVDS_B_CLK_N
MXM_LVDS_A_DATA_P<2>NO_TEST=TRUE
NC_MXM_LVDS_A_DATA_P<2>MAKE_BASE=TRUE
MXM_LVDS_A_DATA_N<3>NO_TEST=TRUE
NC_MXM_LVDS_A_DATA_N<3>MAKE_BASE=TRUE
MXM_LVDS_A_DATA_N<2>NO_TEST=TRUEMAKE_BASE=TRUE
NC_MXM_LVDS_A_DATA_N<2>
MXM_LVDS_A_DATA_N<1>MAKE_BASE=TRUE NO_TEST=TRUENC_MXM_LVDS_A_DATA_N<1>
MXM_LVDS_A_DATA_P<1>NO_TEST=TRUEMAKE_BASE=TRUE
NC_MXM_LVDS_A_DATA_P<1>
MXM_LVDS_A_DATA_N<0> NC_MXM_LVDS_A_DATA_N<0>MAKE_BASE=TRUE NO_TEST=TRUE
MXM_LVDS_A_DATA_P<0> NC_MXM_LVDS_A_DATA_P<0>MAKE_BASE=TRUE NO_TEST=TRUE
MXM_LVDS_A_CLK_PNO_TEST=TRUE
NC_MXM_LVDS_A_CLK_PMAKE_BASE=TRUE
MXM_LVDS_A_CLK_NNO_TEST=TRUE
NC_MXM_LVDS_A_CLK_NMAKE_BASE=TRUE NC_MXM_DP_B_ML_P<0..3>
MAKE_BASE=TRUE NO_TEST=TRUEMXM_DP_B_ML_P<0..3>
MAKE_BASE=TRUENC_MXM_DP_B_ML_N<0..3>
NO_TEST=TRUEMXM_DP_B_ML_N<0..3>
MAKE_BASE=TRUENC_MXM_DP_B_AUX_P
NO_TEST=TRUE
MAKE_BASE=TRUENC_MXM_DP_B_AUX_N
NO_TEST=TRUEMXM_DP_B_AUX_N
MAKE_BASE=TRUENC_MXM_DP_B_HPD
NO_TEST=TRUEMXM_DP_B_HPD
MAKE_BASE=TRUENC_MXM_DP_D_ML_P<0..3>
NO_TEST=TRUE
MAKE_BASE=TRUENC_MXM_DP_D_ML_N<0..3>
NO_TEST=TRUE
MAKE_BASE=TRUENC_MXM_DP_D_AUX_P
NO_TEST=TRUEMXM_DP_D_AUX_P
MAKE_BASE=TRUENC_MXM_DP_D_HPD
NO_TEST=TRUEMXM_DP_D_HPD
MAKE_BASE=TRUENC_MXM_DP_D_AUX_N
NO_TEST=TRUEMXM_DP_D_AUX_N
MXM_DP_D_ML_N<0..3>
MXM_DP_D_ML_P<0..3>
MXM_DP_B_AUX_P
SYNC_MASTER=K61_AARON
Display: Aliases
051-7997 3.0.0
9276
SYNC_DATE=07/01/2009
87 74
87 74
87 74
87 74
87 74
87 74
87 74
87 74
87 74
87 74
87 74
87 74
87 74
87 74
87 74
87 74
87 74
87 74
87 74
87 74 87 73
87 73
87 73
73
87 73
73
87 73
87 73
87 73
87 73
GND
GND
IN
IN
IN
IN
IN
IN
IN
IN
OUT
Y
B
A
14
OUT
G S
D
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PLACE NEAR J9002
used by diag LED
BACKLIGHT CONTROL SUPPORTonly on when Panel has valid video
Options for GPU or MLB HW controlled backlight enable are included
guarantee backlight is
PANEL POWER CONTROL
BOM options provided by this page:
Page NotesPower aliases required by this page:
I2C MASTER ON TCON
518S0685
INTERNAL DP INTERFACE
IG, MXM, MLB_PNL_PWR, LCD_PNL_PWR
- =PP12V_S0_LCD
- =PP3V3_S0_VIDEO
Signal aliases required by this page:
(NONE)
buffers are multiple parts, other parts are on csa 95
90 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
=PP3V3_S0_DP
VIDEO_ON_L_DLY
=PP3V3_S0_DP
LCD_PANEL_PWR_L
LCD_PANEL_PWR_L_RC
LCD_BKL_ON_DLY
=PP3V3_S0_DP
LCD_PANEL_PWR
VIDEO_ON
=PP12V_S0_LCD
VOLTAGE=12VMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm
PP12V_LCD
LCD_PANEL_PWR_G
LCD_BKL_MLB_EN
LCD_BKL_ON_MUX
VIDEO_ON
VIDEO_ON_L
DP_INT_LINK_P<0>
DP_INT_LINK_N<0>
DP_INT_LINK_P<1>
DP_INT_LINK_N<1>
LCD_PANEL_PWR_L_DIV
VIDEO_ON
DP_HPD_INT
SPDIF_DP_AUDIO_OUT
DP_INT_LINK_CONN_N<1> NO_TEST
LCD_PWM_FILTBACKLIGHT_PWM LCD_PWM
DP_INT_LINK_N<3>
DP_INT_LINK_N<2>
DP_INT_LINK_P<2>
I2C_TCON_SDA
DP_INT_AUXCH_P
DP_INT_AUXCH_N
=PP3V3_S0_VIDEO
DP_INT_LINK_CONN_P<2> NO_TEST
DP_INT_LINK_CONN_N<3> NO_TEST
I2C_TCON_SCL
DP_INT_LINK_CONN_N<2> NO_TEST
VIDEO_ON
MIN_LINE_WIDTH=0.5 mm
PP12V_LCD_CONNVOLTAGE=12V
MIN_NECK_WIDTH=0.25 mm
LCD_BKL_ON
=SMB_DP_TCON_SDA
=SMB_DP_TCON_SCL
DP_INT_LINK_CONN_P<1> NO_TEST
DP_INT_LINK_CONN_N<0> NO_TEST
DP_INT_LINK_CONN_P<0> NO_TEST
DP_INT_LINK_P<3>
DP_INT_LINK_CONN_P<3> NO_TEST
Display: Int DP ConnectorSYNC_DATE=07/16/2009SYNC_MASTER=K23_AARON
100K
1/16W5%
MF-LF402
R90701
2
2N7002SOT23-HF1
Q9001
3
1
2
MF-LF
5%1/16W
100K
402
R90001
2
402MF-LF
1%1/16W
29.4KR90011 2
50VX7R
10%
0.1UF
603-1
C9000
1 2SM
FERR-250-OHML9000
1 2
MF-LF
5%1/10W
603
0R9072
1 2
NOSTUFF
603
1/10W
0
5%
MF-LF
R90711 2
6
74LVC14
TSSOP-HF
U95003
7
414
402
10VCERM
20%0.1UF
NOSTUFF
C90111
2
SOT665
NOSTUFFTC7SZ08AFEAPE
U9050
2
1
3
5
4
402
1K
1/16W5%
MF-LF
NOSTUFFR90121 2
74AUP2G14GMSOT886
U9520
3
2
5
4
805
20%6.3V
22UF
CERM
C90051
2
6
1/16WMF-LF402
5%
1KR90111 2
19.1K
402
1%1/16WMF-LF
R90091 2
SOT23
BAT54XG
D90001 3
X5R-CERM0805
10%10UF
16V
C9020 1
2
87 79
87 79
87 79
87 79
87 79
87 79
87 79
CERM
0.001uF
402
20%50V
C9001 1
2
87 79
10% 16V 402X5R0.1uFC9047 1 2
10% X5R16V0.1uF
402C9046 1 2
16V X5R 4020.1uF
10%C9045 1 2
0.1uFX5R 40216V10%
C9043 1 2
16V 402X5R0.1uF
10%C9044 1 2
10% X5R 4020.1uF
16VC9041 1 2
0.1uF402X5R16V10%
C9042 1 2
16V X5R10%0.1uF
402C9040 1 2
NOSTUFF
1/16W5%
0
402MF-LF
R90511 2
402
0
5%1/16WMF-LF
NOSTUFF
R90501 2
402
0.001uF
50VCERM
20%
C9010 1
2
CRITICAL
20389-Y30E-01F-RT-SM
J9002
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25
26
27
28
29
3
30
31
32
33
34
4
5
6
7
8
9
CRITICAL
SMFDC638P_GQ9000
1
2
5
6
3
4
SM
FERR-250-OHM
CRITICAL
L9050
1 2
5%
402MF-LF1/16W
100KR9002
1
2
5%1/16WMF-LF
47
402
R90811 2
81 79 78 77 6
81 79 78 77 6
81 79 78 77 6
81
81 77
6
89
81
81 77
81 77
79
81
87
81 6
87 79
87 79
6
87
87
87
81 77
89
48
48
87
87
87
87
BI
BI
IN
XSD*
HPD_1
DIN1_0-
DIN1_1+
DIN1_2-
DAUX1+
DIN1_3+
DDC_DAT2
DAUX2-
DDC_CLK2
HPD_2
GPU_SEL
TST0
DIN1_2+
DIN1_1-
DOUT_0-
DOUT_1+
DDC_CLK1
DDC_DAT1
DOUT_2+
DOUT_2-
DOUT_3+
DOUT_3-DIN2_1+
DDC_AUX_SEL
DIN2_1-
AUX+
AUX-
HPDIN
DIN2_2+
DIN2_2-
DIN2_3+
DIN2_3-
DAUX2+
DIN2_0-
DIN2_0+
DIN1_0+
DAUX1-
DOUT_1-
DOUT_0+
DIN1_3-
VDD
GND
NCNC
IN
BI
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
VCC
NCCFGX
PC0/I2C_ADDR0
PC1/I2C_ADDR1
GND
REXT
AUX+
AUX-
CEXT
OUT4N
OUT4P
OUT3N
OUT3P
OUT2N
OUT2P
OUT1N
OUT1P
OE*
CA_DET
CFGY
SDA_CTL
SCL_CTL
MODE
IN1P
IN1N
IN2P
IN2N
IN3P
IN3N
IN4P
IN4N
THRM_PAD
I2C_CTL_EN*
HPD HPD_SINKIN
OUT
BI
IN
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
From external source
EQ & Re-Driver for DP source
Common mode bias for Tx EQ AUX interception
NC
NC
DisplayPort Mux 1Analog mux at External Connector
LO=AUX_CH
INT_PD
INT_PD
To External connector
NC
INT_PD
INT_PD
NC
HI=DDCHI=PORT2LO=PORT1
From iMac GPU
to internal display via EQ
91 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
MXM_DP_A_ML_EQ_N<1> NO_TESTMXM_DP_A_ML_N<1> NO_TEST
MXM_DP_A_ML_P<0> NO_TEST
=PP3V3_S0_DP
NO_TESTMXM_DP_A_ML_EQ_N<3>
DPMUX_VIDEO_IN_SEL
NO_TESTMXM_DP_A_ML_C_P<1>
MXM_DP_A_ML_C_P<3> NO_TEST
NO_TESTMXM_DP_A_ML_C_P<2>
NO_TESTMXM_DP_A_ML_P<3>
NO_TESTDP_EXT_LINK_C_N<3>
=I2C_DP_DRV_SDA
=I2C_DP_DRV_SCL
NO_TESTMXM_DP_A_AUX_P
=PP3V3_S0_DP
NO_TESTMXM_DP_A_AUX_C_P
MXM_DP_A_AUX_C_NNO_TEST
DP_TX_EQ_AUXCH_PNO_TEST
DP_TX_EQ_AUXCH_NNO_TEST
=PP3V3_S0_DP
NO_TESTMXM_DP_A_ML_EQ_N<0>
NO_TESTMXM_DP_A_AUX_C_P
NO_TESTDP_MUX_N<0>
DP_EXT_LINK_C_P<3>NO_TEST
NO_TESTDP_EXT_LINK_C_P<0>
DP_EXT_LINK_P<1>NO_TEST
DP_EXT_LINK_N<1>NO_TEST
MXM_DP_A_ML_EQ_P<3> NO_TEST
NO_TESTMXM_DP_A_ML_EQ_N<2>NO_TESTMXM_DP_A_ML_EQ_P<2>
DP_TX_EQ_AUXCH_P
DP_TX_EQ_AUXCH_N
NO_TESTMXM_DP_A_ML_EQ_P<1>
MXM_DP_A_ML_EQ_P<0> NO_TEST
NO_TESTMXM_DP_A_AUX_C_N
PS8121_PC0
NO_TESTMXM_DP_A_ML_C_N<0>
MXM_DP_A_HPD_EQ
PS8121_CEXT
PS8121_PC1
PS8121_I2C_EN_L
PS8121_REXT
NO_TESTMXM_DP_A_ML_C_N<3>
DP_EXT_LINK_C_N<0>NO_TEST
NO_TESTDP_MUX_N<1>
NO_TESTDP_MUX_P<3>
NO_TESTDP_MUX_AUXCH_P
NO_TESTDP_EXT_LINK_C_P<1>
DP_EXT_LINK_C_N<1>NO_TEST
NO_TESTDP_EXT_LINK_C_P<2>
DP_CA_DET
DPMUX1_ENABLE
NO_TESTMXM_DP_A_ML_P<2>
DP_HPD_EXT
NO_TEST DP_EXT_AUXCH_P
MXM_DP_A_ML_P<1> NO_TEST
NO_TESTDP_MUX_P<1>
=PP3V3_S0_DP
NO_TESTDP_EXT_LINK_N<3>
NO_TEST DP_EXT_AUXCH_N
NO_TESTDP_MUX_AUXCH_N
DP_EXT_LINK_C_N<2>NO_TEST
NO_TESTDP_EXT_LINK_P<2>
NO_TESTMXM_DP_A_ML_N<2> NO_TESTMXM_DP_A_ML_C_N<2>
NO_TESTMXM_DP_A_ML_C_N<1>
MXM_DP_A_ML_C_P<0> NO_TEST
NO_TESTDP_EXT_LINK_P<3>
DP_EXT_LINK_N<2>NO_TEST
NO_TESTDP_EXT_LINK_P<0>
NO_TESTDP_EXT_LINK_N<0>
DP_HPD_EXT_R
DP_MUX_P<0> NO_TEST
MXM_DP_A_ML_N<0> NO_TEST
=PP3V3_S0_DP
MXM_DP_A_ML_N<3> NO_TEST
DP_MUX_N<3> NO_TEST
DP_MUX_HPD
NO_TESTDP_MUX_P<2>NO_TESTDP_MUX_N<2>
NO_TESTMXM_DP_A_AUX_N
=PP3V3_S0_DP
MXM_DP_A_HPD
DP_CA_DET
SYNC_DATE=07/16/2009SYNC_MASTER=K23_AARON
Display: BiDiVi Mux1
MF-LF402
5%1/16W
100KR91511
2
100K
MF-LF402
5%1/16W
R91501
2
16V X5R0.1uF
10% 402C9150 1 2
0.1uF10% X5R 40216V
C9151 1 2
48
48
4.7UF6.3V
X5R-CERM402
20%
C91061 2
73
80 78
402
1/16W 1%
499
MF-LF
R9103 12
402
5% MF-LF
NOSTUFF 10K
1/16W
R9102 12
NOSTUFF40210K
5%1/16W MF-LF
R9101 12
10K 402
MF-LF
NOSTUFF
5%1/16W
R9100 12
10% X5R 40216V0.1uFC9123 1 2
10% 40216V X5R0.1uFC9124 1 2
40216V10% X5R0.1uFC9125 1 2
0.1uF16V 402X5R10%
C9126 1 2
0.1uFX5R10% 16V 402
C9127 1 2
X5R16V 4020.1uF
10%C9120 1 2
X5R0.1uF
40210% 16VC9121 1 2
X5R 40210%0.1uF
16VC9122 1 2
QFNPS8121EDU9100
9
8
27 10
2
32
5
12
18
24
31
37
43
7 30
26
39
38
42
41
45
44
48
47
36 1
28
29
25
22
23
19
20
16
17
13
14
3
4
6
35
34
49
11
15
21
33
40
4620%
10VCERM402
0.1UFC91001
2
20%10V
0.1UF
CERM402
C91011
2
0.1UF20%10VCERM402
C91021
2
20%10V
0.1UF
CERM402
C91031
2
20%10VCERM402
0.1UFC91041
2
0.1UF20%10VCERM402
C91051
2
87 73
87 73
87 73
87 73
87 73
87 73
87 73
87 73
87 80
87 80
87 80
87 80
87 80
87 80
87 80
87 80
10% X5R 40216V0.1uFC9136 1 2
0.1uF40216V10% X5R
C9137 1 2
0.1uFX5R16V 40210%
C9134 1 2
X5R10% 16V0.1uF
402C9135 1 2
0.1uFX5R 40216V10%
C9133 1 2
X5R0.1uF
40216V10%C9131 1 2
X5R 40216V0.1uF
10%C9132 1 2
402X5R10% 16V0.1uFC9130 1 2
81
87 73
87 73
87 79
87 79
87 79
87 79
87 79
87 79
87 79
87 79
87 79
87 79
80 78
81 80 1K
MF-LF1/16W
402
1%
R93091 2
1/16W5%
10K
402MF-LF
NOSTUFFR91301
2
0.1uFX5R16V 40210%
C9139 1 216V X5R
0.1uF10% 402
C9138 1 2
79
CBTL06141EE
CRITICAL
BGA
U9120
H1
H2
J9
H9
J6
H6
C2
H8
H5
J8
J5
A4
B4
A5
B5
A6
B6
A9
A8
B9
B8
D9
D8
E9
E8
F9
F8
B1
B2
D1
D2
E1
E2
F1
F2
B3
C8
G8
H4
H7
A1
J2
H3
J1
G2
A2
J4
B7
CERM
0.1UF10V20%
402
C93231
2
81 45
0.1UF
402CERM10V20%
C93221
2
87 81 80
87 81 80
87
81 79 78 77 6
87
87
87
87
87
81 79 78 77 6
87 78
87 78
87 78
87 78
81 79 78 77 6
87
87 78
87
87
87
87
87
87 78
87 78
87
87
87 78
87
87
87
87
87
87
81 79 78 77 6
87
87
87
87
81 79 78 77 6
81 79 78 77 6
IN
BI
BI
BI
BI
OUT
OUT
NCNC
OUT
NC
IN
IN
IN
OUT
IN
NC
OUT
NC
NCNC
NC
NCNC
NCNC
OUT
NC
NCNC
NC
IN2_D2N
IN2_D3P
IN2_D3N
IN2_PEQ/SCL_CTL
MODE0
CEXT
VDD
IN1_CADET
IN1_HPDX
IN2_CADET
IN2_D1N
IN2_HPDX
IN2_D2P
IN2_AUXP_SCL
IN2_AUXN_SDA
IN1_AUXP_SCL
IN1_AUXN_SDA
DP_AC_AUXP
DP_AC_AUXN
DP_AUXP_SCL
DP_AUXN_SDA
TMDS_SCL
TMDS_SDA
TMDS_PC0
TMDS_CLKN
TMDS_CLKP
TMDS_HPD
TMDS_CH0P
TMDS_PC1
TMDS_CH1N
TMDS_CH1P
TMDS_CH2N
TMDS_CH2P
DP_D3N
DP_D3P
DP_HPD
DP_D2N
DP_D2P
DP_D1N
DP_D1P
PD
DP_D0N
DP_D0P
MODE1
SW/I2C_ADDR
MODE2
REXT
PIO
THRM_PAD
IN1_D0P
IN1_D1P
IN1_D2P
IN1_D3P
IN1_D3N
IN1_D0N
IN1_D1N
IN2_D0P
IN2_D0N
IN2_D1P
DP_CADET
GND
TMDS_CH0N
IN1_PEQ/SDA_CTL
IN1_D2N
NC
OUT
IN
IN
IN
IN
IN
IN
IN
BI
OUT
BI
BI
BI
IN
IN
IN
IN
IN
OUT
IN
IN
BI
BI
OUT
BI
BI
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
MODE[2..0] = 111 SELECTS I2C CONTROL MODE
see below
To Internal display
TO EXTERNAL SOURCE VIA MUX1INT_PD
TO IMAC GPU
From iMac GPU
To Internal display
DisplayPort
on this pin of >=100 kOhms
Note: INT_PD = Internal Pulldown
Equalizer & MUX 2
INT_PD
From Internal display
From iMac GPU
via MUX 1
via MUX 1From external input
INT_PD
Pulls for AUX_CH
from DisplayPort Mux #2
INT_PD
From external input
AC caps for EQ AUX interception
INT_PD
INT_PD
INT_PD
92 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
DP_EQLZ_MODE1
DP_EQLZ_MODE0
=I2C_DP_EQLZ_SCL
DP_MUX_N<3>
DP_MUX_P<3>
DP_MUX_N<2>
NO_TESTMXM_DP_C_ML_C_P<0>
NO_TESTMXM_DP_C_ML_C_N<0>
NO_TESTMXM_DP_C_ML_C_N<1>
MXM_DP_C_ML_C_P<1> NO_TEST
NO_TESTMXM_DP_C_ML_C_P<2>
NO_TESTMXM_DP_C_ML_C_N<2>
DP_MUX_P<1>
DP_MUX_P<2>
DP_EQLZ_MODE2
NO_TEST DP_EQLZ_AUXCH_N
NO_TEST DP_INT_AUXCH_P
NO_TEST DP_INT_AUXCH_N
NO_TEST DP_INT_LINK_N<2>
DP_EQLZ_EXTC
NO_TESTDP_MUX_AUXCH_P
NO_TESTDP_MUX_AUXCH_N
NO_TEST DP_EQLZ_AUXCH_P
=PP3V3_S0_DP
MXM_DP_C_HPD
DP_MUX_N<1>
DP_MUX_HPD
MXM_DP_C_AUX_C_PNO_TESTMXM_DP_C_AUX_C_NNO_TEST
NO_TEST DP_INT_LINK_N<3>
DP_INT_LINK_P<3>NO_TEST
DP_HPD_INT
DP_INT_LINK_P<2>NO_TEST
DP_INT_LINK_N<1>NO_TEST
DP_INT_LINK_P<1>NO_TEST
DP_INT_LINK_N<0>NO_TEST
DP_INT_LINK_P<0>NO_TEST
DP_EQLZ_ADDR
DP_EQLZ_EXTR
NO_TESTMXM_DP_C_ML_C_P<3>
MXM_DP_C_ML_C_N<3> NO_TEST
DP_MUX_P<0>
DP_MUX_N<0>
DP_EQLZ_CADET
=I2C_DP_EQLZ_SDA
MXM_DP_C_ML_P<1>NO_TEST
MXM_DP_C_ML_P<0>NO_TEST
NO_TESTMXM_DP_C_ML_N<0>
NO_TESTMXM_DP_C_ML_N<1>
NO_TESTMXM_DP_C_ML_P<2>
NO_TESTMXM_DP_C_ML_N<2>
NO_TESTMXM_DP_C_ML_P<3>
NO_TESTMXM_DP_C_ML_N<3>
MXM_DP_C_AUX_C_N
=PP3V3_S0_DP
MXM_DP_C_AUX_C_P
=PP3V3_S0_DP
MXM_DP_C_AUX_N NO_TEST
MXM_DP_C_AUX_P NO_TEST
DP_EQLZ_AUXCH_N NO_TEST
NO_TESTDP_EQLZ_AUXCH_P
NO_TESTDP_INT_AUXCH_P
DP_INT_AUXCH_N NO_TEST
=PP3V3_S0_DP
SYNC_MASTER=K23_AARON
BIDIVI DP MUX2SYNC_DATE=07/16/200987 79
87 79 77
87 77
87 79 77
87 79
X5R 40210% 16V0.1uFC9291 1 2
0.1uFX5R16V 40210%
C9290 1 2
100K1%
402
1/16WMF-LF
R92131
2
1%100K1/16WMF-LF
402
R92121
2
MF-LF
5%1K
1/16W
402
R92211
2
87 73
87 73
87 77
87 73
87 73
87 73
87 73
87 73
5%
MF-LF1/16W
402
1KR92151
2
87 78
1/16WMF-LF
402
5%1K
R92201
2
87 73
87 78
87 77
87 73
87 78
87 78
87 78
87 78
87 78
77
48
X5R16V10% 4020.1uFC9249 1 2
87 77
0.1uFX5R16V10% 402
C9248 1 2
402MF-LF
1M5% 1/16WR92811 2
QFN
CRITICAL
PS8325U9200
1
31
30
33
32
56
60
61
57
58
54
55
51
52
53
13
27
36
50
63
72
29
28
7
3
2
6
5
9
8
12
11
10
68
26
25
16
15
14
18
17
21
20
24
23
19
67
64
65
69
59
71
70
66
73
42
43
45
46
48
49
39
40
41
37
44
34
35
4 22
38
47
62
MF-LF
01/16W5% 402
NOSTUFFR92801 2
87 77
1/16W
4.99K1% 402MF-LFR92221 2
87 77
16V 4020.1uF
10% X5RC9247 1 2
16V X5R10%0.1uF
402C9246 1 2
16V10% X5R 4020.1uFC9245 1 2
X5R 40210% 16V0.1uFC9244 1 2
0.1uFX5R10% 40216V
C9243 1 2
40210% 16V X5R0.1uFC9242 1 2
10% 16V X5R 4020.1uFC9241 1 2
10% 402X5R16V0.1uFC9240 1 2
87 78
87 77
87 78
87 78
48
20%10V
402CERM
0.1UFC92001
210V
0.1UF
402CERM
20%
C92011
2 CERM10V
0.1UF
402
20%
C92021
220%
402
10VCERM
0.1UFC92031
2402
20%
CERM10V
0.1UFC92041
2
87 77
78
73
87 79 77
87 79 77
87 79
87 79
6.3VX5R-CERM
402
20%
4.7UFC9212
1 2
87 73
87
87
87
87
87
87
81 79 78 77 6
87 79
87 79
87
87
87 79
81 79 78 77 6
87 79
81 79 78 77 6
81 79 78 77 6
IN
OC*
OUT
EN
GND
IN
IN
IN
IN
ML_LANE2P
ML_LANE2N
RETURN
GND
ML_LANE1N
ML_LANE0N
GND
ML_LANE1P
ML_LANE0P
GND
AUX_CHP
AUX_CHN
DP_PWR
GND
ML_LANE3N
ML_LANE3PGND
HPD
CONFIG1
CONFIG2
SHIELD PINS
IN
IO
NC NC
IO
GND
IO
NC NC
IO
GND
2E
1E
1Y 1Z
2Z
GND
VCC
2Y
IN
IN
OUT
IO
NC NC
IO
GND
IO
NC NC
IO
GND
IN
IN
IN
IN
SYM_VER-2
SYM_VER-2
SYM_VER-2
SYM_VER-2
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
APPLE PART NO 514-0686
94 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
VOLTAGE=3.3VMIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.38 MMPP3V3_S0_DPPWR
NO_TESTDP_ML_CONN_P<3>
DP_EXT_AUXCH_P
DP_EXT_LINK_N<3>
DP_HPD_EXTDP_CA_DET
DP_ML_CONN_P<2>NO_TEST
DP_EXT_LINK_N<0>
DP_EXT_LINK_P<2>
DP_EXT_LINK_N<2>
DP_EXT_LINK_N<1>
DP_EXT_LINK_P<1>
DP_EXT_LINK_P<0>
NO_TEST DP_ML_CONN_N<0>
DP_EXT_AUXCH_N
HDMI_CEC
MIN_LINE_WIDTH=0.38 MMPP3V3_S0_DPFUSE
MIN_NECK_WIDTH=0.20 MMVOLTAGE=3.3V
MIN_NECK_WIDTH=0.10 MMMIN_LINE_WIDTH=0.15 MM
VOLTAGE=0V
GND_DPAUX
PP3V3_S0_DPAUX
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.15 MMMIN_NECK_WIDTH=0.10 MM
=PP3V3_S0_DPCONN
DP_SRC_AUX_TERM_EN
PM_SLPS3_BUF1_L
=PP3V3_S0_DPCONN
TP_DP_OC
DP_ML_CONN_N<1>NO_TEST
NO_TEST DP_ML_CONN_P<1>
NO_TEST DP_ML_CONN_P<0>
NO_TEST DP_ML_CONN_N<2>
NO_TESTDP_ML_CONN_N<3>
DP_EXT_LINK_P<3>
SYNC_DATE=07/16/2009SYNC_MASTER=K23_AARON
Display: Ext DP Connector
TCM1210-4SM12-OHM-100MA
NOSTUFFFL9403
1
23
4
TCM1210-4SM12-OHM-100MA
NOSTUFFFL9402
1
23
4
TCM1210-4SM12-OHM-100MA
NOSTUFF
FL9401
1
23
4
TCM1210-4SM12-OHM-100MA
NOSTUFFFL9400
1
23
4
402
5%
MF-LF
1M
1/16W
R94221
2
87 78
87 78
400-OHM-EMI
SM-1
L9400
1 2
0.01UF20%50VCERM603
C94001
2
87 78
87 78
RCLAMP0524PSLP2510P8
CRITICALNOSTUFF
D9411
3
2 1
9 10
1M
MF-LF
5%
402
1/16W
R94251
2
CRITICAL
RCLAMP0524PSLP2510P8
NOSTUFF
D9411
3
5 4
6 7
SC70-6-1RCLAMP0504F
CRITICAL
D9400
1
34
6
2 5
100K
MF-LF402
1/16W1%
R94201
2
78
0R94071 2
0R94061 2
0R94051 2
0R94041 2
0R94031 2
0R94021 2
0R94011 2
0R94001 2
81
0.1UF10V
402
20%
CERM
C94501
2
87 78
100K
1/16WMF-LF402
1%
R94211
2
SOT996-2
NX3L2G66GD
CRITICAL
U9450
7
1 2
3
5 6
4
8
CRITICAL
RCLAMP0524PSLP2510P8
NOSTUFF
D9410
3
2 1
9 10
SLP2510P8
RCLAMP0524P
CRITICALNOSTUFF
D9410
3
5 4
6 7
81 78
F-ANG-TH1MDP-K22
CRITICAL
J9400
18
16
4
6
20
1
7 8
13 14
2
21
22
5
3
11
9
17
15
12
10
19
87 78
87 78
46
10UF
603
6.3VX5R
20%
CRITICAL
C94851
2
87 78
10V
402
20%
CERM
0.1UFC94811
2603
10UF20%
X5R6.3V
C94801
2
CRITICAL
SOT23TPS2051BU9400
4
2
5
3
1
89
87
87 81 78 87
87
87 81 78
89
89
80 6
80 6
87
87
87
87
87
IN
IN
OUT
IN
Y
B
A
OUT
IN
IN
IN
OUTIN
Y
A
B 08
OUT
OUT
OUT
14
Y
A
B 08IN
OUT
E
Z Y
VCC
GNDNC
Y
B
A
OUT
14IN
IN
OUT
OUT
OUT
OUT
OUT
1I1
1I0
2I1
2I0
3I0
4I0
GND
4Y
3Y
2Y
1Y
4I1
3I1
E*
S
VCC
PADTHM
IN
IN
IN
IN
IN
IN
OUT
S GND
OUTPUT
MUXSELECTOR
I1
I0Y
VCC
IN
IN
IN
14
14
IN
IN
14
IN
IN
Y
B
A
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
AUDIO MUX
PANEL/BACKLIGHT CONTROL MUX
P21*
PF6 X
0
enables 100k dp aux source termination
P26
Outputs
P27
P23*
P22*
PF7
PF3
PF4
SMC
0
X
0
X
0
0
0
X
0
S5/S3
Default Values
0
S0
PG0
Inputs
P25* so that one bi-directional system can find the other
enables weak sink-like aux termination
External AUX Channel and HPD Buffers & filters
DisplayPort
BiDiVi MUX Enable
SMC Signals for BiDiViOuptuts are OK as low by default
Series R should prevent any issues on the inputs
*Some inputs listed below come up as outputs driven low under the SMC flasher
AUX Bias Enable
PLACE NEAR U6201
95 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
DP_AUXP_L
=PP3V3_S0_DPBIDIVI_AUX_TERM_EN_L
MXM_PNL_PWR_EN
=PP3V3_S0_DP PP3V3_S0_DP_DVOLTAGE=3.3VMIN_LINE_WIDTH=0.15 MMMIN_NECK_WIDTH=0.10 MM
DPMUX_VIDEO_IN_SEL_L
AUX_TERM_OR_OUT
=PP3V3_S0_DP
DP_EXT_AUXCH_P
PP3V3_S0_DPAUXP_SINKVOLTAGE=3.3VMIN_LINE_WIDTH=0.15 MMMIN_NECK_WIDTH=0.10 MM
BIDIVI_AUX_TERM_EN
BIDIVI_BKL_MUX_SELDPMUX_VIDEO_IN_SEL
DP_SINK_AUX_TERM_EN
AUXCH_P_RDP_AUXP_DLY_L
AUXCH_N_R AUXCH_N_STATE
=PP3V3_S0_DP
SMC_DP_HPD
=PP3V3_S0_DP
BIDIVI_BKL_ON
SMC_VIDEO_ON
BIDIVI_PNL_PWR_EN
BIDIVI_AUX_TERM_EN
DPMUX_VIDEO_IN_SEL
=PP3V3_S0_DP
=PP3V3_S0_DP
DP_SRC_AUX_TERM_EN
=PP3V3_S0_DP
DPMUX_VIDEO_IN_SEL
HPD_FILT
MXM_PNL_BL_PWM
SMC_DP_HPD
SMC_PNL_BL_PWM
AUXCH_P_STATE
AUXCH_N_STATE
VIDEO_ON
BIDIVI_AUDIO_MUX_SEL
BIDIVI_BKL_PWM
DP_AUXN_L
DP_HPD_EXT
=PP3V3_S0_DP
DP_HPD_PULS_EAT_L
HPD_FILT
DPMUX_VIDEO_IN_SEL
DP_SINK_AUX_TERM_EN
DP_AUXN_DLY_L
BIDIVI_AUX_TERM_EN
DP_EXT_AUXCH_N
AUXCH_P_STATE
DP_HPD_EXT_L
=PP3V3_S0_DP
DPMUX1_ENABLEDPMUX1_OROUT_L
HPD_FILT
LCD_PANEL_PWRLCD_BKL_ON_MUXBACKLIGHT_PWM =PP3V3_S0_DP
BIDIVI_BKL_PWM
BIDIVI_PNL_PWR_EN
BIDIVI_BKL_ONMXM_PNL_BL_PWM
=PP3V3_S0_DP
=PP3V3_S0_DP
AUD_SPDIF_IN_CODEC
MXM_PNL_BL_EN
=PP3V3_S0_DP
BIDIVI_BKL_MUX_SEL
DPMUX_VIDEO_IN_SEL
SPDIF_DP_AUDIO_OUTAUD_SPDIF_IN
MUX_CNTRLAUD_MUX_CNTRL
BIDIVI_AUDIO_MUX_SEL
Display: BiDiVi SupportSYNC_DATE=07/16/2009SYNC_MASTER=K23_AARON
SOT90274LVC2G32U9501
7
6
4
8
1
81 45
MF-LF
5%
402
1/16W
3.3KR95091 2
10%
402
6.3VCERM
1UFC9504 1
2
SOT23
BAT54XG
D950213
4.7K
1/16W5%
402MF-LF
R95081 2
402
1/16W
1M5%
MF-LF
R95071
25%
MF-LF402
1/16W
0NOSTUFFR95411 255
TSSOP-HF
74LVC14U9500
9
7
814
MF-LF402
5%1/16W
3.3KR95401 281 74
77 3.3K
402
5%1/16WMF-LF
R95101 2
3.3K
1/16WMF-LF402
5%
R95061 2
402CERM
10%1UF6.3V
C9503 1
2
74LVC14
TSSOP-HF
U950011
7
1014
402
5%
MF-LF1/16W
1KR95051 2
SOT23
BAT54XG
D950113
3.3K
402
5%
MF-LF1/16W
R95031 2
6.3V
1UF
CERM
10%
402
C9501 1
2
CERM
0.1UF10V
402
20%
C95001
2
BAT54XG
SOT23D95001 3
TSSOP-HF
74LVC14U9500
13
7
12141K
1/16WMF-LF
5%
402
R95021 2
81 45
85 59
77
74LVC1G157SOT886
U9524
2
3
1
6
5
4 55
74
81 45
74
81 45
81 74
81 45
DHVQFN74LVC157AU9522
2
3
4
5
67
11
109
14
13
12
15
8
1
17
16
77
77
77
81 45
81 45
BAT54XG
SOT23D95031 3
81 78 45
81 45
74LVC14
TSSOP-HF
U95001
7
214
81 45
10V20%
0.1UF
CERM402
C9550 1
2
SOT665TC7SZ08AFEAPE
U9550
2
1
3
5
4
CRITICAL
NX3L1G66SOT886
U9540
4
35
6
12
499K
1%
MF-LF1/16W
402
R95431 2
81
81 78 45
SOT90274LVC2G08
U95027
6
4
8
1
74LVC14
TSSOP-HF
U95005
7
614
81 45
1/16W5%
0
MF-LF402
R95421 2
81
402CERM
20%10V
0.1UFC95621
2
74AUP2G14GMSOT886
U9520
1
2
5
6
0.1UF10V
402
20%
CERM
C95611
2
80
20%10V
0.1UF
CERM402
C95601
2
SOT90274LVC2G08
U95023
2
4
8
5
1/16W
402
1%
MF
4.75MR95211
2
1%4.75M
MF402
1/16W
R95201
2
SOT88674AUP2G14GMU9510
3
2
5
4
81 45
74AUP2G14GMSOT886
U9510
1
2
5
6
NOSTUFF
1/16W
402
5%
MF-LF
0R95231 2
81 45
81 45
81 45
81
81 78 45
74LVC2G32SOT902
U9501
3
2
4
8
5
81 78 45
78 0
1/16W5%
MF-LF402
R95111 2
81
81 78 45
81 79 78 77 6
81 79 78 77 6
81 79 78 77 6
87 80 78
81
81
81 45
81 79 78 77 6
81 45
81 79 78 77 6
45
81 79 78 77 6
81 79 78 77 6
81 79 78 77 6
46 45
80 78
81 79 78 77 6
87 80 78
81 45
81 79 78 77 6
81 79 78 77 6
81 79 78 77 6
81 79 78 77 6
81 79 78 77 6
81
60
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_BOARD_INFO
VERSIONALLEGRO
(MIL or MM)BOARD UNITSBOARD LAYERS BOARD AREAS
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
PHYSICAL CONSTRAINTS
K60/K61 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS
SPACING RULE SET
CONSTRAINTS FOR BGA AREA
* 1000SWITCHNODE 0.8 MM
* 10000.2 MMPWR_P2MM
*GND =STANDARD ?
* 0.2 MMGND_P2MM 1000
BGA_P2MM 0.2 MM ?*
BGA_P1MM* * BGA_P1MM
BGA_P1MMCLK_PCI * BGA_P1MM
TOP,BOTTOM =STANDARD0.085 MM 0.2 MM 0.1 MMY85_OHM_DIFF 0.125 MM
=STANDARD1:1_DIFFPAIR * 0.1 MM=STANDARD=STANDARD 0.085 MMY
0.15 MMTOP,BOTTOM110_OHM_DIFF Y 0.320 MM=STANDARD0.085 MM0.075 MM
=STANDARD=STANDARD* N90_OHM_DIFF =STANDARD=STANDARD =STANDARD
=STANDARD=STANDARD =STANDARDN =STANDARD =STANDARD*85_OHM_DIFF
=STANDARD45_OHM_SE Y =STANDARD* 0.12 MM 0.085 MM =STANDARD
VR_CTL_PHY * POWER_CTL
VR_CTL_PHY BGA_P1MM DEFAULT
POWER POWER_WIDTH*
POWER BGA_P1MM POWER_CTL
=STANDARD* N =STANDARD=STANDARD110_OHM_DIFF =STANDARD=STANDARD
35_OHM_SE 0.21 MMTOP,BOTTOM Y =STANDARD0.085 MM
=STANDARD =STANDARD35_OHM_SE 0.19 MM* =STANDARD0.085 MMY
39_OHM_SE 0.175 MM =STANDARDTOP,BOTTOM Y 0.085 MM
=STANDARD39_OHM_SE 0.16 MM 0.085 MM =STANDARD* Y =STANDARD
* ?0.380 MM5X_DIELECTRIC
DEFAULT * 100 MMY 0 MM=50_OHM_SE=50_OHM_SE 0 MM
GND ** STANDARD
POWER ** STANDARD
0.099 MMY 12 MM0.085 MMISL3,ISL690_OHM_DIFF 0.200 MM 0.1 MM
0.115 MM 0.1 MM0.2 MM=STANDARDISL3,ISL685_OHM_DIFF 0.085 MMY
?0.300 MM*4X_DIELECTRIC
=DEFAULTSTANDARD =DEFAULT* Y =DEFAULT=DEFAULT 12.7 MM
* Y 3.0 MM =STANDARD =STANDARD0.300 MMPOWER_CTL 0.200 MM
0.600 MM =STANDARD=STANDARD3.0 MM0.200 MMPOWER_WIDTH Y*
NO_TYPE,BGA_P1MMTOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,BOTTOM MM 15.5.1
=STANDARD45_OHM_SE 0.135 MM 0.085 MMTOP,BOTTOM Y
TOP,BOTTOM50_OHM_SE 0.085 MM 15 MMY 0.1 MM
?=DEFAULTSTANDARD *
DEFAULT * ?0.1 MM
0.150 MM ?*2X_DIELECTRIC
1.5:1_SPACING ?* 0.15 MM
2:1_SPACING ?* 0.2 MM
2.5:1_SPACING * 0.25 MM ?
0.4 MM ?*4:1_SPACING
*5:1_SPACING 0.5 MM ?
3X_DIELECTRIC TOP,BOTTOM ?0.240 MM
3X_DIELECTRIC * ?0.220 MM
?0.160 MM2X_DIELECTRIC TOP,BOTTOM
TOP,BOTTOM4X_DIELECTRIC ?0.320 MM
TOP,BOTTOM 0.400 MM ?5X_DIELECTRIC
CLK_PCIE * BGA_P1MMBGA_P1MM
50_OHM_SE =STANDARD* 0.085 MM =STANDARDY 0.1 MM =STANDARD
0.085 MMTOP,BOTTOM55_OHM_SE 0.085 MMY =STANDARD
*55_OHM_SE 0.076 MM =STANDARD=STANDARDY =STANDARD0.075 MM
9282
SYNC_MASTER=K60_DEREK SYNC_DATE=07/01/2009
3.0.0051-7997
K60/K61 RULE DEFINITIONS
=STANDARD=STANDARD=STANDARD*70_OHM_DIFF =STANDARDN =STANDARD
0.085 MM 0.1 MM0.25 MMISL3,ISL6 Y100_OHM_DIFF 0.081 MM =STANDARD
Y 0.25 MM 0.1 MM100_OHM_DIFF TOP,BOTTOM 0.085 MM =STANDARD0.091 MM
100_OHM_DIFF =STANDARD=STANDARDN* =STANDARD=STANDARD =STANDARD
0.1 MM0.200 MM0.110 MM 0.085 MMY90_OHM_DIFF =STANDARDTOP,BOTTOM
0.130 MM0.085 MMTOP,BOTTOM70_OHM_DIFF 0.1 MMY 0.165 MM =STANDARD
0.135 MM0.085 MM =STANDARDISL3,ISL670_OHM_DIFF 0.1 MMY 0.155 MM
BGA_P1MM =DEFAULT* ?
BGA_P1MM BGA_P2MM*MEM_CLK
CLK_LPC BGA_P1MM BGA_P1MM*
3:1_SPACING * ?0.3 MM
6:1_SPACING * ?0.6 MM
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TO CLEAR CHECK_PLUS ERRORS
ADD RULES TO NC_DQS<8>
NET_TYPE
ELECTRICAL_CONSTRAINT_SET PHYSICAL
PHYSICAL SPACINGELECTRICAL_CONSTRAINT_SET
Need to support MEM_*-style wildcards!
Memory Bus Spacing Group Assignments
Memory Net Properties
NET_TYPE
SPACING
Memory Bus Constraints
SPACINGPHYSICAL
NET_TYPE
MEMORY POWER PROPERTIES
VOLTAGE
Memory Net Properties
101 OF 110
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<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
MEM_B_DQ<39..32>MEM_DQ_EVENMEM_45S
MEM_B_DM<4>MEM_45S MEM_DQ_EVEN
MEM_B_DQ<47..40>MEM_45S MEM_DQ_ODD
MEM_B_DM<5>MEM_DQ_ODDMEM_45S
CPU_SM_RCOMP0MEM_RCOMP_PHY MEM_RCOMP
MEM_B_DQS_P<7>MEM_70D MEM_DQS
MEM_DQSMEM_70D MEM_B_DQS_N<6>
MEM_DQSMEM_70D MEM_B_DQS_N<5>MEM_70D MEM_DQS MEM_B_DQS_P<5>
MEM_B_CAS_LMEM_35S MEM_CMD
MEM_DQSMEM_70D MEM_B_DQS_P<6>
MEM_B_DQ<63..56>MEM_45S MEM_DQ_ODD
MEM_DQ_EVEN MEM_B_DM<0>MEM_45S
MEM_B_DM<1>MEM_45S MEM_DQ_ODD
MEM_DQ_EVEN MEM_B_DQ<7..0>MEM_45S
MEM_B_RAS_LMEM_35S MEM_CMD
MEM_35S MEM_CMD MEM_B_BA<2..0>
MEM_45S MEM_B_DQ<23..16>MEM_DQ_EVEN
MEM_B_DM<3>MEM_45S MEM_DQ_ODD
MEM_39S MEM_CTRL MEM_A_ODT<3..0>
MEM_35S MEM_CMD MEM_A_BA<2..0>
MEM_B_DQ<15..8>MEM_45S MEM_DQ_ODD
MEM_B_DQ<55..48>MEM_45S MEM_DQ_EVEN
MEM_DQ_EVEN MEM_B_DM<6>MEM_45S
MEM_A_A<15..0>MEM_35S MEM_CMD
MEM_DQSMEM_70D MEM_B_DQS_P<1>
MEM_DQSMEM_70D MEM_B_DQS_P<0>
MEM_DQSMEM_70D MEM_B_DQS_N<0>
MEM_35S MEM_CMD MEM_A_RAS_L
MEM_B_DQS_N<3>MEM_70D MEM_DQS
MEM_B_DQS_P<4>MEM_70D MEM_DQS
MEM_RCOMP_PHY MEM_RCOMP CPU_SM_RCOMP1
CPU_SM_RCOMP2MEM_RCOMPMEM_RCOMP_PHY
TP_MEM_B_DQS_P<8>MEM_DQSMEM_70D
TP_MEM_A_DQS_N<8>MEM_70D MEM_DQS
TP_MEM_A_DQS_P<8>MEM_DQSMEM_70D
TP_MEM_B_DQS_N<8>MEM_DQSMEM_70D
MEM_B_DQS_P<3>MEM_70D MEM_DQS
MEM_B_DQS_N<2>MEM_DQSMEM_70D
MEM_70D MEM_DQS MEM_B_DQS_N<4>
MEM_DQ_ODD MEM_B_DM<7>MEM_45S
MEM_CTRL MEM_A_CKE<3..0>MEM_39S
MEM_B_DM<2>MEM_45S MEM_DQ_EVEN
MEM_B_DQ<31..24>MEM_45S MEM_DQ_ODD
MEM_DQSMEM_70D MEM_B_DQS_P<2>
MEM_70D MEM_DQS MEM_A_DQS_N<6>
MEM_CLK MEM_A_CLK_N<3..0>MEM_70D
MEM_70D MEM_B_DQS_N<7>MEM_DQS
MEM_39S MEM_A_CS_L<3..0>MEM_CTRL
MEM_CLK MEM_A_CLK_P<3..0>MEM_70D
VREFMARGIN_DIMMA_DQMEM_POWER_PHY MEM_POWER
CPU_DIMM_VREF_B_SWMEM_POWER_PHY MEM_POWER
MEM_DQS MEM_A_DQS_N<1>MEM_70DCPU_DIMM_VREF_AMEM_POWER_PHY MEM_POWER
VREFMARGIN_DIMMB_DQMEM_POWER_PHY MEM_POWER
CPU_DIMM_VREF_A_SWMEM_POWER_PHY MEM_POWER
MEM_70D MEM_DQS MEM_A_DQS_N<5>
MEM_A_DQS_P<6>MEM_70D MEM_DQS
MEM_70D MEM_DQS MEM_A_DQS_P<5>
MEM_A_DQS_P<4>MEM_70D MEM_DQS
MEM_DQS MEM_A_DQS_N<3>MEM_70D
MEM_POWER_PHY MEM_POWER CPU_DIMM_VREF_B
MEM_B_WE_LMEM_35S MEM_CMD
MEM_DQ_ODDMEM_45S MEM_A_DM<5>
MEM_45S MEM_DQ_EVEN MEM_A_DM<6>
MEM_A_DQ<47..40>MEM_DQ_ODDMEM_45S
MEM_45S MEM_A_DM<4>MEM_DQ_EVEN
MEM_A_DQS_P<0>MEM_70D MEM_DQS
MEM_70D MEM_DQS MEM_A_DQS_N<0>
MEM_A_DQS_P<1>MEM_70D MEM_DQS
MEM_70D MEM_A_DQS_N<2>MEM_DQS
MEM_A_DQS_P<3>MEM_DQSMEM_70D
MEM_DQS MEM_A_DQS_N<7>MEM_70D
MEM_B_CLK_P<3..0>MEM_CLKMEM_70D
MEM_B_CLK_N<3..0>MEM_CLKMEM_70D
MEM_B_CKE<3..0>MEM_CTRLMEM_39S
MEM_39S MEM_B_CS_L<3..0>MEM_CTRL
MEM_39S MEM_B_ODT<3..0>MEM_CTRL
MEM_35S MEM_B_A<15..0>MEM_CMD
MEM_A_DQS_P<7>MEM_70D MEM_DQS
MEM_A_DQS_N<4>MEM_70D MEM_DQS
MEM_DQSMEM_70D MEM_A_DQS_P<2>
MEM_DQ_ODDMEM_45S MEM_A_DM<7>MEM_DQ_ODDMEM_45S MEM_A_DQ<63..56>
MEM_DQ_EVENMEM_45S MEM_A_DQ<55..48>
MEM_DQ_ODDMEM_45S MEM_A_DM<3>
MEM_DQ_EVENMEM_45S MEM_A_DQ<39..32>
MEM_A_DQ<23..16>MEM_DQ_EVENMEM_45S
MEM_A_DQ<15..8>MEM_45S MEM_DQ_ODD
MEM_A_DM<1>MEM_45S MEM_DQ_ODD
MEM_A_DM<2>MEM_DQ_EVENMEM_45S
MEM_A_DQ<31..24>MEM_45S MEM_DQ_ODD
MEM_CMDMEM_35S MEM_A_WE_L
MEM_A_CAS_LMEM_35S MEM_CMD
MEM_DQSMEM_70D MEM_B_DQS_N<1>
MEM_A_DM<0>MEM_DQ_EVENMEM_45S
MEM_DQ_EVEN MEM_A_DQ<7..0>MEM_45S
SYNC_DATE=07/01/2009SYNC_MASTER=K60_MIKE
Memory Constraints
MEM_CMD2MEM*MEM_DQSMEM_CMD
MEM_CMD2CMDMEM_CMD *MEM_CMD
MEM_CMD2MEM*MEM_CMD MEM_CTRL
MEM_CLK ** MEM_2OTHER
MEM_DQ_ODD2DQ_ODDMEM_DQ_ODD *MEM_DQ_ODD
MEM_DQS MEM_DQ_ODD2MEMMEM_DQ_ODD *
MEM_DQ_EVENMEM_CTRL * MEM_CTRL2MEM
MEM_DQ_EVEN2DQ_ODDMEM_DQ_ODD *MEM_DQ_EVEN
*MEM_CLK MEM_CLK2MEMMEM_DQ_ODD
* ?0.2 MMMEM_RCOMP
0.2 MM ?*MEM_POWER
0.175 MM =STANDARDMEM_RCOMP_PHY =STANDARD=STANDARDY* 0.175 MM
MEM_CTRL MEM_CLK * MEM_CTRL2MEM
MEM_CTRL *MEM_CTRL MEM_CTRL2CTRL
* MEM_CTRL2MEMMEM_CTRL MEM_CMD
*MEM_POWER_PHY MEM_POWER_WIDTH
MEM_CTRL2MEM*MEM_CTRL MEM_DQ_ODD
=STANDARD0.500 MM 0.175 MM =STANDARD=STANDARD*MEM_POWER_WIDTH Y
MEM_DQS2MEMMEM_DQ_EVENMEM_DQS *
MEM_DQ_EVEN2MEMMEM_DQ_EVEN MEM_DQS *
MEM_DQ_EVEN2DQ_EVENMEM_DQ_EVENMEM_DQ_EVEN *
MEM_DQ_EVEN2MEMMEM_DQ_EVEN MEM_CLK *
MEM_CLK2MEMMEM_CLK *MEM_DQ_EVEN
MEM_DQ_EVEN MEM_DQ_EVEN2MEMMEM_CTRL *
MEM_DQS2MEMMEM_DQS *MEM_DQ_ODD
MEM_CLK MEM_CLK2MEM*MEM_CMD
MEM_CLK2MEM*MEM_CLK MEM_CTRL
MEM_CLK2MEM*MEM_CLK MEM_DQS
MEM_DQ_ODD2MEMMEM_DQ_ODD *MEM_CLK
MEM_DQ_ODD2MEMMEM_DQ_ODD *MEM_CTRL
MEM_DQ_ODD2MEMMEM_DQ_ODD *MEM_CMD
MEM_DQSMEM_CTRL * MEM_CTRL2MEM
?=3:1_SPACINGMEM_DQ_EVEN2DQ_EVEN *
MEM_2OTHER =3:1_SPACING ?*
* ?=3:1_SPACINGMEM_DQS2MEM
=5:1_SPACINGMEM_DQ_EVEN2DQ_ODD * ?
MEM_CTRL2MEM * ?=2.5:1_SPACING
MEM_CLK *MEM_CLK MEM_CLK2MEM
=3:1_SPACING* ?MEM_DQ_EVEN2MEM
=3:1_SPACING ?MEM_DQ_ODD2MEM *
MEM_2OTHER*MEM_DQS *
* MEM_2OTHERMEM_DQ_EVEN *
MEM_2OTHERMEM_CMD **
MEM_DQ_ODD2DQ_ODD ?* =3:1_SPACING
* ?MEM_CMD2MEM =3:1_SPACING
=1.5:1_SPACINGMEM_CMD2CMD ?*
MEM_CTRL2CTRL * ?=2:1_SPACING
=4:1_SPACING ?MEM_CLK2MEM *
MEM_DQS * MEM_DQS2MEMMEM_DQS
MEM_DQ_EVEN2DQ_ODDMEM_DQ_EVEN *MEM_DQ_ODD
MEM_2OTHERMEM_DQ_ODD * *
MEM_2OTHERMEM_CTRL * *
=39_OHM_SE =STANDARD=STANDARD* =39_OHM_SE=39_OHM_SE=39_OHM_SEMEM_39S
=45_OHM_SE* =45_OHM_SE =STANDARDMEM_45S =45_OHM_SE=45_OHM_SE =STANDARD
=35_OHM_SE=35_OHM_SE* =STANDARD=35_OHM_SE =35_OHM_SEMEM_35S =STANDARD
=70_OHM_DIFF* =70_OHM_DIFF =70_OHM_DIFFMEM_70D =70_OHM_DIFF =70_OHM_DIFF=70_OHM_DIFF
MEM_DQS2MEM*MEM_DQS MEM_CMD
MEM_DQS2MEMMEM_DQS *MEM_CTRL
MEM_DQS2MEMMEM_DQS *MEM_CLK
MEM_DQ_EVEN2MEMMEM_DQ_EVEN MEM_CMD *
MEM_CMD2MEMMEM_CMD *MEM_CLK
*MEM_CMD MEM_DQ_ODD MEM_CMD2MEM
MEM_CMD2MEMMEM_CMD *MEM_DQ_EVEN
I169
I168
I167
I166
I165
I164
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I162
I161
I160
I159
I155
I154
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LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
NET_TYPE
SATA SSD
PCIE GRAPHICS
CLOCKS
CLOCKS
SPACINGPHYSICAL
SATA
ELECTRICAL_CONSTRAINT_SET
NET_TYPE
PHYSICAL SPACING
CPU ITP
CPU_MISC
CPU
SATA Interface Constraints
ELECTRICAL_CONSTRAINT_SET
FDI_MISC
ANY OTHER LYNNFIELD CONSTRAINTS NOT COVERED ON PAGES 101 AND 107 SHOULD GO ON THIS PAGE TOO
PCI-Express
PCIE REF CLOCKS
DMI
FDI
PCIE I/O
102 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
FDI_FSYNC<1..0>CPU_AGTLCPU_50S
CPU_50S CPU_ITP XDP_BPM_L<7..0>
CPU_50S CPU_RCOMP CPU_PEG_COMP
CPU_50S CPU_PEG_RBIASCPU_RCOMP
CPU_COMP3CPU_50S CPU_RCOMP
SATA_85D SATA SATA_SSD_R2D_C_P
SATA_85D SATA SATA_SSD_D2R_N
SATA_85D SATA_SSD_D2R_C_NSATA
SATA_85D SATA_SSD_D2R_PSATA
PCIE_85D PCIE_MINI_R2D_PPCIE
PCIE_85D PCIE_FW_D2R_PPCIE
PCIE_85D PCIE PCIE_FW_D2R_N
PCIE_85D PCIE_FW_D2R_C_PPCIE
PCIE_85D PCIE PCIE_FW_R2D_P
PCIE_85D PCIE PCIE_FW_R2D_C_P
PCIE_85D PCIE PEG_D2R_N<15..0>
PCIE_85D PCIE PEG_R2D_C_P<15..0>
PCIE_85D PCIE MXM_PCIE_R2D_N<15..0>
PCIE_85D PCIE MXM_PCIE_D2R_P<15..0>
PCIE_85D MXM_PCIE_D2R_N<15..0>PCIE
PCIE_CLK100M_ENET_NENET_100D ENET_MII
SATA_85D SATA_ODD_D2R_PSATA
PCIE_CLK100M_PCH_PCLK_PCIECLK_PCIE_100D
SATA_85D SATA SATA_HDD_R2D_C_P
SATA_85D SATA_HDD_R2D_NSATA
SATA_85D SATA_ODD_R2D_C_PSATA
SATA_85D SATA_ODD_D2R_C_NSATA
PCIE_85D PCIE PEG_R2D_C_N<15..0>
CLK_PCIE_100D CLK_PCIE DMI_MIDBUS_CLK100M_N
CPU_50S CPU_ITP CPU_CFG<17..0>
CPU_50S CPU_ITP XDP_OBSDATA_A<3..0>
PCIE_85D PCIE MXM_PCIE_R2D_P<15..0>
PCIE_85D PCIE PEG_D2R_P<15..0>
SATA_85D SATA SATA_HDD_R2D_C_NSATA_85D SATA SATA_SSD_R2D_PSATA_85D SATA SATA_SSD_R2D_C_N
SATA_85D SATA SATA_SSD_R2D_N
CPU_50S CPU_AGTL FDI_LSYNC<1..0>
CLK_PCIE_100D CLK_PCIE DMI_MIDBUS_CLK100M_P
FDI_INTCPU_AGTLCPU_50S
CPU_COMP0CPU_50S CPU_RCOMP
CPU_COMP2CPU_50S CPU_RCOMP
CPU_COMP1CPU_50S CPU_RCOMP
SATA_85D SATA SATA_SSD_D2R_C_P
CLK_PCIE_100D CLK_PCIE FSB_CLK133M_CPU_P
PCIE_CLK100M_PCH_NCLK_PCIECLK_PCIE_100D
PCIE_CLK100M_CPU_NCLK_PCIECLK_PCIE_100D
PCIE_CLK100M_CPU_PCLK_PCIECLK_PCIE_100D
FSB_CLK133M_ITP_NCLK_PCIECLK_PCIE_100D
FSB_CLK133M_ITP_PCLK_PCIECLK_PCIE_100D
GFX_CLK120M_DPLLSS_NCLK_PCIECLK_PCIE_100D
GFX_CLK120M_DPLLSS_PCLK_PCIECLK_PCIE_100D
CLK_PCIECLK_PCIE_100D FSB_CLK133M_CPU_N
SATA_85D SATA SATA_ODD_D2R_C_PSATA_85D SATA SATA_ODD_D2R_N
CLK_PCIECLK_PCIE_100D PCH_CLK96M_DOT_PCLK_PCIECLK_PCIE_100D FSB_CLK133M_PCH_N
CLK_PCIECLK_PCIE_100D PCH_CLK96M_DOT_N
CLK_PCIECLK_PCIE_100D PCH_CLK100M_SATA_NCLK_PCIECLK_PCIE_100D PCH_CLK100M_SATA_P
CLK_PCIECLK_PCIE_100D FSB_CLK133M_PCH_P
SATA_85D SATA SATA_ODD_R2D_NSATA_85D SATA SATA_ODD_R2D_PSATA_85D SATA SATA_ODD_R2D_C_N
SATA_HDD_D2R_C_NSATASATA_85D
SATA_85D SATA SATA_HDD_D2R_C_PSATA_85D SATA SATA_HDD_D2R_NSATA_85D SATA_HDD_D2R_PSATA
SATA_85D SATA_HDD_R2D_PSATA
CLK_PCIE GPU_CLK100M_PCIE_NCLK_PCIE_100D
ENET_MIIENET_100D PCIE_CLK100M_ENET_P
CLK_PCIE_100D PCIE_CLK100M_FW_PCLK_PCIE
CLK_PCIE_100D PCIE_CLK100M_FW_NCLK_PCIE
CLK_PCIECLK_PCIE_100D GPU_CLK100M_PCIE_P
CLK_PCIECLK_PCIE_100D PCIE_CLK100M_MINI_CON_P
CLK_PCIE_100D PCIE_CLK100M_MINI_PCLK_PCIE
CLK_PCIE_100D PCIE_CLK100M_MINI_NCLK_PCIE
CLK_PCIECLK_PCIE_100D PCIE_CLK100M_MINI_CON_N
PCIE DMI_S2N_P<3..0>PCIE_85D
PCIE DMI_S2N_N<3..0>PCIE_85D
DMI_N2S_P<3..0>PCIEPCIE_85D
PCIE DMI_N2S_N<3..0>PCIE_85D
PCIE FDI_DATA_N<7..0>PCIE_85D
FDI_DATA_P<15..0>PCIEPCIE_85D
PCIE_85D PCIE_FW_D2R_C_NPCIE
PCIE_85D PCIE_FW_R2D_C_NPCIE
PCIE_85D PCIE_FW_R2D_NPCIE
PCIE_85D PCIE_MINI_R2D_C_PPCIE
PCIE_85D PCIE_MINI_R2D_NPCIE
PCIEPCIE_85D PCIE_MINI_R2D_L_NPCIEPCIE_85D PCIE_MINI_R2D_L_P
PCIE_MINI_D2R_NPCIEPCIE_85D
PCIE_85D PCIE PCIE_MINI_D2R_PPCIE_85D PCIE_MINI_R2D_C_NPCIE
PCIE TOP,BOTTOM ?=4X_DIELECTRIC
?CLK_PCIE * 0.5 MM
=50_OHM_SE=50_OHM_SE =50_OHM_SE=50_OHM_SE* =STANDARD =STANDARDCPU_50S
?*CPU_RCOMP 0.2 MM
?*SATA =5X_DIELECTRIC
0.2 MMCPU_ITP * ?
?=STANDARD*CPU_AGTL
PCIE_85D =85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF* =85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF
PCIE/DMI/FDI/SATA CONSTRAINTSSYNC_MASTER=K60_SIJI SYNC_DATE=07/01/2009
=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF* =100_OHM_DIFF =100_OHM_DIFFCLK_PCIE_100D
=4X_DIELECTRICPCIE * ?
SATA_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF
TOP,BOTTOMSATA ?=5X_DIELECTRIC
25 11
10
10
11
42 18
42 18
42
42 18
33
39 18
39 18
39
39
39 18
75 9
75 9
75 73
75 73
75 73
36 18
42 18
26 18
42 18
92 42
42 18
92 42
75 9
18 10
25 15 10
25
75 73
75 9
42 18 42
42 18
42
18 10
11
11
11
42
21 11
26 18
18 11
18 11
25 11
25 11
18 11
18 11
21 11
92 42
42 18
26 18
26 18
26 18
26 18
26 18
92 42
92 42
42 18
92 42
92 42
42 18
42 18
92 42
9
36 18
39 18
39 18
9
33
33 18
33 18
33
19 10
19 10
19 10
19 10
39
39 18
39
33 18
33
33
33
33 18
33 18
33 18
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
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REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PCH CONSTRAINTS
LPC Bus Constraints
PCI Bus Constraints
PHYSICALSPACING
XTAL Constraints
PHYSICALNET_TYPE NET_TYPE
SPACING
SMBus Interface Constraints
HD Audio Interface Constraints
USB 2.0 Interface Constraints
SPI Interface Constraints
ELECTRICAL_CONSTRAINT_SETELECTRICAL_CONSTRAINT_SET
103 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
HDA AUD_SPKR_OUTLO2L_NOUTHDA_55S
HDA AUD_SPKR_OUTLO2R_NOUTHDA_55S
PCH_XCLK_RCOMPCOMP_PCHPCH_55S
PCH_55S COMP_PCH PCH_DMI_COMP
CLK_XTALUSB_HUB1_XTAL1
XTAL
CLK_XTAL XTALUSB_HUB1_XTAL2
HDA HDA_RST_R_LHDA_55S
HDA HDA_SDOUTHDA_55S
HDA_SDOUT_RHDA_55S HDA
HDA_55S HDA_SYNCHDA
SPI_55S SPI SPI_MOSI
SPI_55S SPI_MISOSPI
SPI_55S SPI SPI_MLB_CS_L
SPISPI_55S SPI_ALT_CS_L
USB_90D USBUSB_MINI_P
USBUSB_90DUSB_WM_L_N
USBUSB_90DUSB_MINI_N
USB_BRCRYPT_PUSB_90D USB
USB_BRCRYPT_NUSBUSB_90D
XTALCLK_XTAL PCH_CLK32K_RTCX2
CLK_XTAL XTAL CK505_XTAL_IN
CLK_XTAL XTAL CK505_XTAL_OUT
CLK_PCHCLK_PCH_55S PCH_CLK14P3M_REFCLK
USB_90D USBUSB_BRCRYPT_L_P
USBUSB_90D USB_BRCRYPT_L_NUSB_90D USB USB_HUB1_UP_PUSB_90D USB
USB_HUB1_UP_NUSBUSB_90D
USB_HUB2_UP_PUSB_90D USB
USB_HUB2_UP_N
USB_90DUSB_SDCARD_P
USB
USBUSB_IR_L_N
USB_90D
USBUSB_90D USB_IR_L_P
USB_CAMERA_L_PUSBUSB_90D
USBUSB_90D USB_D_MUXED_N
USBUSB_90DUSB_EXTB_N
LPC_CLK33M_LPCPLUS_RCLK_LPCCLK_LPC_55S
USB_90DUSB_EXTA_P
USB
USB_90DUSB_IR_P
USB
CLK_XTAL XTAL USB_HUB2_XTAL1CLK_XTAL XTAL
USB_HUB2_XTAL2
PCH_CLK25M_XTALINXTALCLK_XTAL
XTALCLK_XTAL PCH_CLK25M_XTALOUT
PCH_55S COMP_PCHPCH_USB_RBIAS
AUD_SPKR_OUTLO1R_POUTHDAHDA_55S
HDA AUD_SPKR_OUTLO1R_NOUTHDA_55S
AUD_SPKR_OUTLO2L_POUTHDAHDA_55S
USB_PORT3_PUSBUSB_90D
HDA AUD_SPKR_OUTLO2R_POUTHDA_55S
HDA_BIT_CLK_RHDA_55S HDA
AUD_SPDIF_OUTHDA
AUD_SPDIF_INHDA
HDA AUD_SPKR_OUTLO1L_NOUTHDA_55S
HDA AUD_SPKR_OUTLO1L_POUTHDA_55S
CLK_PCI_55S CLK_PCIPCH_CLK33M_PCIOUT
LPC_AD<3..0>LPC_55S LPC
LPCLPC_55S LPC_FRAME_L
LPC_CLK33M_SMC_RCLK_LPC_55S CLK_LPC
USB_PORT0_NUSBUSB_90D
USBUSB_EXTD_N
USB_90D
USB_90DUSB_CAMERA_L_N
USB
USB_90DUSB_SDCARD_L_N
USB
USBUSB_90DUSB_BT_N
USBUSB_90DUSB_BT_L_P
USB_90DUSB_BT_L_N
USB
XTALCLK_XTAL PCH_CLK32K_RTCX1
PMPM_CLK32K_SUSCLK
CLK_LPC_55S
SPISPI_55S SPI_CLK
SPISPI_55S SPI_MOSI_R
SPIROM_USE_MLBSPISPI_55S
USBUSB_90DUSB_PORT2_P
LPC_CLK33M_LPCPLUSCLK_LPCCLK_LPC_55S
USB_90D USB_SDCARD_L_PUSB
USBUSB_90DUSB_EXTB_P
USB_CAMERA_NUSB_90D USB
USB_90D USBUSB_WM_N
USBUSB_90DUSB_EXTD_P
USBUSB_90DUSB_PORT1_P
USB_90DUSB_WM_L_P
USB
USBUSB_90DUSB_WM_P
USBUSB_90DUSB_BT_P
USB_PORT3_NUSBUSB_90D
USB_CAMERA_PUSBUSB_90D
USB_90D USBUSB_SDCARD_N
USB_90DUSB_IR_N
USB
SPI_CS0_R_LSPI_55S SPI
LPC_CLK33M_SMCCLK_LPCCLK_LPC_55S
PCH_CLK33M_PCIINCLK_PCICLK_PCI_55S
HDA_BIT_CLKHDAHDA_55S
SPI_ALT_MISOSPISPI_55S
SPI_ALT_MOSISPI_55S SPI
HDA_55S HDA HDA_SYNC_R
HDAHDA_55S AUD_SDI_R
USBUSB_90D USB_PORT0_P
SPI_CLK_RSPISPI_55S
SPI SPI_MISO_RSPI_55S
SPI_CS0_LSPI_55S SPI
SPI_ALT_CLKSPISPI_55S
AUD_SPDIF_CHIPHDA
PCI_55S PCIPCI_REQ0_L
USBUSB_90DUSB_EXTC_N
USB_EXTA_NUSBUSB_90D
PMPM_CLK32K_SUSCLK_R
CLK_LPC_55S
USBUSB_90DUSB_PORT1_N
USBUSB_90DUSB_EXTC_P
PCI_REQ1_LPCI_55S PCI
HDA_SDIN0HDA_55S HDA
HDA HDA_RST_LHDA_55S
USBUSB_PORT2_N
USB_90D
USBUSB_90DUSB_D_MUXED_P
COMP_PCHPCH_55SPCH_SATAICOMP
COMP_PCHPCH_55SUSB_HUB1_RBIAS
COMP_PCHPCH_55SUSB_HUB2_RBIAS
* ?0.2 MMCLK_PCH
PCH_55S * =55_OHM_SE =55_OHM_SE =STANDARD=55_OHM_SE=55_OHM_SE =STANDARD
=55_OHM_SECLK_PCH_55S =STANDARD=55_OHM_SE =STANDARD* =55_OHM_SE =55_OHM_SE
=STANDARDPCI * ?
0.2 MMCLK_PCI * ?
XTAL =4X_DIELECTRIC ?*
SPI ?* 0.2 MM
=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF* =100_OHM_DIFFCLK_XTAL =100_OHM_DIFF
* 0.15 MM ?LPC
* ?USB =2x_DIELECTRIC
=55_OHM_SE =STANDARD=55_OHM_SE =55_OHM_SESMB_55S * =STANDARD=55_OHM_SE
=2x_DIELECTRICSMB * ?
=STANDARDCLK_PCI_55S =STANDARD* =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE
=4x_DIELECTRICTOP,BOTTOMUSB ?
0.2 MM*CLK_LPC ?
=90_OHM_DIFF=90_OHM_DIFF =90_OHM_DIFF=90_OHM_DIFF =90_OHM_DIFFUSB_90D * =90_OHM_DIFF
=STANDARD*LPC_55S =55_OHM_SE=55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD
=STANDARD=55_OHM_SECLK_LPC_55S * =55_OHM_SE =55_OHM_SE =STANDARD=55_OHM_SE
* =STANDARD=STANDARDHDA_55S =55_OHM_SE =55_OHM_SE=55_OHM_SE =55_OHM_SE
=55_OHM_SE* =STANDARD =STANDARDSPI_55S =55_OHM_SE =55_OHM_SE=55_OHM_SE
=2x_DIELECTRICHDA * ?
=STANDARD=55_OHM_SEPCI_55S =STANDARD=55_OHM_SE=55_OHM_SE =55_OHM_SE*
0.2 MM ?*COMP_PCH
SYNC_MASTER=K60_SIJI
IBEX PEAK CONSTRAINTSSYNC_DATE=07/01/2009
92 59 58
92 59 58
18
19
34
34
18
55 18
18
55 18
54
54 47 18
54 47
47
44
44 20
44 20
27 18
26
26
26 18
44
44
34 20
34 20
35 20
35 20
44 35
92 44
92 44
92 44
43
43 35
27 20
43 34
44 34
35
35
27 18
27 18
20
92 59 57
92 59 57
92 59 58
43 92 59 58
18
59 55
81 59
92 59 57
92 59 57
27 20
47 45 18
47 45 18
27 20
43
43 35
92 44
92 44
44 35
92 44
92 44
27 18
91 45 9
54
54 47 18
47 21
43
47 27
92 44
43 35
44 34
44 20
43 35
43
44
44 20
44 35
43
44 34
44 35
44 34
47 18
45 27
27 18
55 18
47
47
18
55
43
54 47 18
54
47
47
55
20
43 34
43 34
91 19 9
43
43 34
20
55 18
55 18
43
43
18
34
35
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
FireWire Net Properties
ELECTRICAL_CONSTRAINT_SET
UNUSED FW NETS PHYSICAL PROPERTIES
PORT 1 & 2 NOT USED
PHYSICAL
NET_TYPE
NET_TYPE
PHYSICAL SPACING
SOURCE: BROADCOM 5764-DS04-RDS. PAGE 38
CAESAR II (ETHERNET) CONSTRAINTS
ELECTRICAL_CONSTRAINT_SET
CAESAR II (ETHERNET) CONSTRAINTS
SOURCE:BROADCOM 5764M-DS04-RDS. PAGE 38
SPACING
FireWire Interface Constraints
FireWire Interface Constraints
AUDIO MIC PHYSICAL PROPERTIES
104 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
FW_TP FW_P0_TPA_L_PFW_110D
FW_110D FW_TP FW_P0_TPA_L_N
FW_P2_TPA_PFW_TPFW_110D
FW_TP FW_P0_TPB_L_NFW_110D
FW_110D FW_TP FW_PORT0_TPA_P
FW_P1_TPA_PFW_110D FW_TP
FW_P1_TPA_NFW_110D FW_TP
FW_PORT0_TPB_NFW_TPFW_110D
FW_TP FW_PORT0_TPB_PFW_110D
ENET_50S ENET_CLK25M_XTALBUF0_CLK
ENET_DIFFENET_100D ENET_MDI_T_N<3..0>
ENET_CLK25M_XTALIENET_50S BUF0_CLK
ENET_MDI_P<3..0>ENET_100D ENET_DIFF
ENET_DIFFENET_100D ENET_MDI_T_P<3..0>
ENET_MDI_N<3..0>ENET_100D ENET_DIFF
ENET_RDACENET_SEENET_50S
ENET_MII PCIE_ENET_R2D_NENET_100D
ENET_MII PCIE_ENET_R2D_PENET_100D
ENET_MII PCIE_ENET_D2R_NENET_100D
ENET_MIIENET_100D PCIE_ENET_R2D_C_P
ENET_MIIENET_100D PCIE_ENET_R2D_C_N
ENET_MII PCIE_ENET_D2R_C_PENET_100D
ENET_MII PCIE_ENET_D2R_C_NENET_100D
ENET_MII PCIE_ENET_D2R_PENET_100D
ENET_CLK25M_XTALOENET_50S BUF0_CLK
FW_PORT0_TPA_NFW_110D FW_TP
FW_P0_TPB_L_PFW_110D FW_TP
AUD_MIC1_IN_NAUDIOAUDIO_PHY
FW_P2_TPA_NFW_TPFW_110D
AUD_MIC1_IN_PAUDIOAUDIO_PHY
FIT;
SYNC_DATE=07/01/2009SYNC_MASTER=K60_AARON
ENET/FIREWIRE CONSTRAINTS
* =3:1_SPACING ?FW_TP
ENET_DIFF 0.6 MM ?*
=3:1_SPACING* ?BUF0_CLK
ENET_100D =100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF* =100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF
* 0.3 MM ?ENET_MII
=STANDARD* ?ENET_SE
=STANDARD* ?AUDIO
=50_OHM_SE=50_OHM_SE =50_OHM_SEENET_50S =50_OHM_SE =STANDARD=STANDARD*
FW_110D =110_OHM_DIFF* =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF=110_OHM_DIFF
* =STANDARD =STANDARD=50_OHM_SE=50_OHM_SE =50_OHM_SEAUDIO_PHY =50_OHM_SE
40
40
40 39
40
41 40
40 39
40 39
41 40
41 40
36
38
36
38 36
38
38 36
36
36
36
36 18
36 18
36 18
36
36
36 18
36
41 40
40
60 59
40 39
60 59
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PAIRS SHOULD BE WITHIN 100 MILS OF CLOCK LENGTH.
ELECTRICAL_CONSTRAINT_SET
Max length of LVDS/DisplayPort/TMDS traces: 12 inches.
NET_TYPE
SPACING
ASSINGED IN CONT. MGR.
DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.
DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.
PHYSICAL
UNUSED VIDEO NET PHYSICAL CONSTRAINTS
105 OF 110
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B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
DISPLAYPORT MXM_DP_B_AUX_PDP_85D
DISPLAYPORT MXM_DP_D_AUX_PDP_85D
DISPLAYPORT MXM_LVDS_A_CLK_PDP_85D
DISPLAYPORT MXM_LVDS_B_CLK_NDP_85D
MXM_DP_B_ML_N<3..0>DISPLAYPORTDP_85D
DISPLAYPORT MXM_LVDS_B_DATA_P<3..0>DP_85D
DISPLAYPORT MXM_DP_B_AUX_NDP_85D
MXM_DP_B_ML_P<3..0>DISPLAYPORTDP_85D
DISPLAYPORT MXM_DP_D_AUX_NDP_85D
DISPLAYPORT MXM_LVDS_A_CLK_NDP_85D
DISPLAYPORT MXM_DP_D_ML_N<3..0>DP_85D
MXM_LVDS_A_DATA_P<3..0>DP_85D DISPLAYPORT
DISPLAYPORT MXM_LVDS_A_DATA_N<3..0>DP_85D
DISPLAYPORT DP_INT_AUXCH_PDP_85D
DISPLAYPORT MXM_LVDS_B_DATA_N<3..0>DP_85D
DISPLAYPORT MXM_DP_D_ML_P<3..0>DP_85D
DISPLAYPORT DP_INT_LINK_CONN_N<3..0>DP_85D
DP_ML_CONN_P<3..0>DISPLAYPORTDP_85D
DP_ML_CONN_N<3..0>DISPLAYPORTDP_85D
DP_85D DISPLAYPORT DP_EXT_AUXCH_N
DISPLAYPORT DP_INT_LINK_CONN_P<3..0>DP_85D
DISPLAYPORT MXM_DP_A_ML_P<3..0>DP_85D
MXM_DP_A_ML_N<3..0>DP_85D DISPLAYPORT
DP_MUX_P<3..0>DP_85D DISPLAYPORT
MXM_DP_A_ML_C_P<3..0>DP_85D DISPLAYPORT
DP_85D DISPLAYPORT DP_EXT_LINK_P<3..0>
DISPLAYPORT DP_EXT_LINK_N<3..0>DP_85D
DISPLAYPORTDP_85D DP_EXT_LINK_C_P<3..0>
DP_85D DISPLAYPORT DP_INT_AUXCH_N
DP_85D MXM_DP_A_AUX_C_NDISPLAYPORT
DP_85D MXM_DP_A_AUX_PDISPLAYPORT
DP_85D MXM_DP_A_AUX_C_PDISPLAYPORT
DP_85D DISPLAYPORT DP_EXT_LINK_C_N<3..0>
DP_85D DISPLAYPORT DP_EXT_AUXCH_P
DISPLAYPORTDP_85D DP_INT_LINK_N<3..0>DISPLAYPORT DP_INT_LINK_P<3..0>DP_85D
DP_85D DISPLAYPORT MXM_DP_C_ML_C_P<3..0>
DP_85D DISPLAYPORT MXM_DP_C_ML_C_N<3..0>
DISPLAYPORT MXM_LVDS_B_CLK_PDP_85D
MXM_DP_A_ML_C_N<3..0>DP_85D DISPLAYPORT
DP_85D DISPLAYPORT DP_EQLZ_AUXCH_N
DISPLAYPORTDP_85D MXM_DP_C_AUX_C_N
MXM_DP_C_ML_N<3..0>DP_85D DISPLAYPORT
MXM_DP_A_AUX_NDP_85D DISPLAYPORT
DP_85D DP_MUX_AUXCH_NDISPLAYPORT
DP_85D DP_MUX_AUXCH_PDISPLAYPORT
DP_85D DISPLAYPORT DP_MUX_N<3..0>
DISPLAYPORTDP_85D MXM_DP_C_AUX_C_PDP_85D MXM_DP_C_AUX_NDISPLAYPORT
DP_85D MXM_DP_C_AUX_PDISPLAYPORT
DISPLAYPORT MXM_DP_C_ML_P<3..0>DP_85D
DP_85D DISPLAYPORT DP_TX_EQ_AUXCH_N
DISPLAYPORTDP_85D MXM_DP_A_ML_EQ_N<3..0>DISPLAYPORTDP_85D MXM_DP_A_ML_EQ_P<3..0>
DP_85D DISPLAYPORT DP_TX_EQ_AUXCH_P
DP_85D DISPLAYPORT DP_EQLZ_AUXCH_P
=3:1_SPACING ?*DISPLAYPORT
=85_OHM_DIFF* 0.08MM=85_OHM_DIFF =85_OHM_DIFFDP_85D =85_OHM_DIFF=85_OHM_DIFF
SYNC_DATE=07/01/2009SYNC_MASTER=K60_AARON
GRAPHICS CONSTRAINTS
76 73
76 73
76 74
76 74
76 73
76 74
76 73
76 73
76 73
76 74
76 73
76 74
76 74
79 77
76 74
76 73
77
80
80
81 80 78
77
78 73
78 73
79 78
78
80 78
80 78
78
79 77
78
78 73
78
78
81 80 78
79 77
79 77
79
79
76 74
78
79
79
79 73
78 73
79 78
79 78
79 78
79
79 73
79 73
79 73
78
78
78
78
79
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
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2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
SMC THERMAL NET PROPERTIES
SPACINGELECTRICAL_CONSTRAINT_SET
NET_TYPE
PHYSICAL
SMBus Interface Constraints
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
SMC VOLTAGE/CURRENT NET PROPERTIESNET_TYPE
ELECTRICAL_CONSTRAINT_SET PHYSICAL
NET_TYPE
SPACING
SMC SMBus Net Properties
106 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
THERMAL MXM_ISENSE_NTHERM_DIFF
SENSE_CPU_VTT2_PTHERMALTHERM_DIFF
THERM_DIFF SENSE_CPU_VTT2_NTHERMAL
THERMAL SMC_CPU_1V5_VSENSE
THERMAL SMC_CPU_VTT_ISENSE_R
SMC_CPU_VSENSETHERMAL
VR_ISNS_CPU_PTHERMALTHERM_DIFF
THERMAL SMC_CPU_1V5_ISENSE_R
SMC_CPU_VTT_ISENSETHERMAL
THERMAL SMC_CPU_VTT_VSENSE
THERMAL SMC_CPU_1V8_ISENSE
SMC_1V5_S3_ISENSE_RTHERMAL
SMC_GPU_ISENSETHERMAL
SMC_MXM_ISENSE_RTHERMAL
SNS_CPU_THERMD_PTHERMALTHERM_DIFF
SNS_CPU_THERMD_NTHERM_DIFF THERMAL
THERM_DIFF SNS_ODD_NTHERMAL
SNS_CPU_H_PTHERMALTHERM_DIFF
THERM_DIFF SNS_ODD_PTHERMAL
THERM_DIFF THERMAL SNS_LCD_N
THERMALTHERM_DIFF SNS_T_DP4_DN5
THERM_DIFF THERMAL SNS_T_DP1_DN6THERM_DIFF THERMAL SNS_T_DN1_DP6THERM_DIFF THERMAL SNS_T_DN2_DP3
SMC_XTALXTALCLK_XTAL
SMC_EXTALXTALCLK_XTAL
SML_PCH_1_DATASMB_55S SMB
SMBSMB_55S SML_PCH_0_CLK
SMBUS_PCH_CLKSMBSMB_55S
SMBSMB_55S SMBUS_SMC_MGMT_SDASMB_55S SMB SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDASMB_55S SMB
SMBUS_SMC_MGMT_SCLSMB_55S SMB
SMBUS_SMC_BSA_SDASMBSMB_55S
SMB SMBUS_SMC_BSA_SCLSMB_55S
SMBUS_SMC_B_S0_SDASMBSMB_55S
THERMAL SNS_MXM_NTHERM_DIFF
SMBUS_PCH_DATASMB_55S SMB
SMB_55S SMBUS_SMC_A_S3_SDASMB
THERMAL SMC_CPU_INPUT_ISENSE
THERMAL SMC_GPU_VSENSE
SMC_CPU_1V8_VSENSETHERMAL
VR_CTL VR_CPU_IOUTVID_PHY
SMC_CPU_INPUT_VSENSETHERMAL
SENSE_CPU_VTT_NTHERM_DIFF THERMAL
THERMALTHERM_DIFF SENSE_CPU_1V5_S0_N
SENSE_CPU_1V5_S0_PTHERMALTHERM_DIFF
THERM_DIFF THERMAL MXM_ISENSE_P
SMBUS_PCH_S0_DATASMB_55S SMB
SMBUS_SMC_0_S0_SDASMBSMB_55S
SMBSMB_55S SMBUS_SMC_0_S0_SCL
SMB_55S SMB SMBUS_SMC_B_S0_SCL
SMBUS_SMC_A_S3_SCLSMBSMB_55S
SMC_DIMM_1V5_ISENSETHERMAL
SMC_DIMM_1V5_VSENSETHERMAL
THERMAL SMC_CPU_ISENSETHERMAL SNS_PS_CPU_ISNS
THERMAL SMC_CPU_1V5_ISENSE
THERMAL SENSE_CPU_VTT_PTHERM_DIFF
SENSE_CPU_1V5_PTHERMALTHERM_DIFF
THERMALTHERM_DIFF SENSE_CPU_1V5_N
THERM_DIFF THERMAL SENSE_CPU_1V5_S3_NTHERM_DIFF THERMAL SENSE_CPU_1V5_S3_P
SENSE_CPU_VTT1_PTHERMALTHERM_DIFF
SENSE_CPU_VTT1_NTHERMALTHERM_DIFF
SMC_CPU_1V8_ISENSE_RTHERMAL
THERMAL GND_SMC_AVSS
THERM_DIFF VR_ISNS_CPU_NTHERMAL
SMB SMBUS_PCH_S0_CLKSMB_55S
SMBSMB_55S SML_PCH_0_DATA
SMB_55S SML_PCH_1_CLKSMB
THERMALTHERM_DIFF SNS_T_DP2_DN3
THERMALTHERM_DIFF SNS_T_DN4_DP5
THERM_DIFF THERMAL SNS_LCD_P
THERM_DIFF THERMAL SNS_SKIN_P
SNS_CPU_H_NTHERM_DIFF THERMAL
THERM_DIFF THERMAL SNS_SKIN_N
SNS_AMB_PTHERMALTHERM_DIFF
THERMALTHERM_DIFF SNS_AMB_N
THERM_DIFF THERMAL SNS_MXM_P
THERMAL HDD_OOB_TEMP_FILT
HDD_OOB_TEMPTHERMAL
HDD_OOB_TEMP_RTHERMAL
SMC_HDD_OOB_TEMPTHERMAL
THERMALTHERM_DIFF SNS_T_DN1_DP6
SNS_T_DP1_DN6THERMALTHERM_DIFF
SYNC_DATE=07/01/2009SYNC_MASTER=K60_JERRY
SMC Constraints
POWER PWR_P2MMTHERMAL *
THERMAL *GND GND_P2MM
THERMAL * 4:1_SPACING*
?=2x_DIELECTRIC*SMB
=STANDARD=55_OHM_SE =55_OHM_SESMB_55S * =STANDARD=55_OHM_SE =55_OHM_SE
SNS_DIFF 1:1_DIFFPAIR*
THERM_DIFF * 1:1_DIFFPAIR
I99
I98
I97
I94
I93
I90
I89
I88
I87
I201
I200
I199
I198
I197
I196
I195
I194
I184
I183
I182
I181
I180
I179
I178
I174
I173
I172
I171
I169
I168
I167
I166
I165
I164
I163
I162
I161
I160
I153
I152
I151
I150
I149
I148
I140
I139
I138
I137
I136
I135
I134
I133
I132
I131
I130
I129
I128
I124
I123
I122
I115
I114
I113
I112
I111
I110
I109
I106
I105
I104
I103
I102
I101
I100
50
49 46
49
49 45
49
49
49 46
49 46
49 46
50 45
50
51 10
51 10
92 51
51
92 51
92 51
51
88 51
88 51
51
46 45
46 45
48 18
48 18
48 18
88 48
88 48
88 48
88 48
48
48
48
51
48 18
48
46
50 45
49 46
64 13
46
49
49
49
50
48
48
48
48
48
50 46
50 46
49 45
49
49 46
49
49
49
49
49
50 49 46 45
49
48
48 18
48 18
51
51
92 51
92 51
51
92 51
92 51
92 51
51
92 51
51
51
51
88 51
88 51
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
POWER NET PROPERTIESVR CTRL NET PROPERTIES
PHYSICAL
VR VID NET PROPERTIES
VOLTAGE
VID LENGTH RANGE< 1 TO 15-INCH
PULL-UP STUB < 1-INCHVID LENGTH SKEW < 1-INCH
PHYSICAL SPACING SPACINGNET_TYPE
PHYSICAL
SPACING
NET_TYPE
VR CTRL NET PROPERTIESNET_TYPE
SPACING
SENSING NET PROPERTIES
PHYSICAL
NET_TYPE
SPACING
SPACING
NET_TYPE
NET_TYPE
VOLTAGE
PHYSICAL
POWER NET PROPERTIES
PHYSICAL
107 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
1.05VPOWERPOWER PP1V05_SM_PCH_LAN
PP3V42_G3HPOWER POWER 3.42V
POWER 12VPOWER P12V_S0_FW
PP12V_S512VPOWERPOWER
POWER PP12V_S0_FAN0_LPOWER 12V
12VPOWER POWER P12V_S0_FW_D
POWERPOWER 12V FW_PORT0_VP_F
POWER 3.3VPOWER PP3V3_ENETVR_CPU_PHASE4POWER 1.5VSWITCHNODE
VR_CPU_PHASE1SWITCHNODE 1.5VPOWER
POWER PP3V3_S0M3.3VPOWER
3.3VPOWER POWER PPVOUT_SO_PCH_VCCRTC_NCTFPOWERPOWER FW_PORT0_VP12V
POWER POWER 12V P12V_S0_FW_R
POWER POWER 3.3V PPVOUT_S5_PCH_DCPSUSPOWER POWER 3.3V PPVOUT_S5_PCH_DCPSUSBYP
PPVOUT_G3_PCH_DCPRTC3.3VPOWER POWER
POWER POWER 3.3V PPVOUT_S0_PCH_DCPSST
PPVTT_S3_DDR_BUFPOWER POWER 3.3V
POWER POWER PP3V3_G3H_AVREF_SMC3.3V
PP_ENET_CTRL123.3VPOWER POWER
POWER PP3V3_G3_RTC3.3VPOWER
3.3V PP3V3_FW_VDDAPOWERPOWERPP3V3_FW_PLLVDD3.3VPOWERPOWER
3.3VPOWER PP3V3_FW_ESDPOWER
POWER 3.3V PP3V3_FW_AVDDPOWERPP3V3_AUDIO_SPDIF_JACKPOWER POWER 3.3V
POWER 3.3VPOWER PPVBATT_G3_RTCPOWER POWER 3.3V PPVBATT_G3_RTC_R
PP3V3_S0_CK505_F3.3VPOWERPOWER
VR_CPU_VSENSNS_DIFF
SNS_DIFF VR_CPU_VSNS_XW_P
3.3VPOWERPOWER PP3V3_S3_BT_FLT
POWERPOWER 3.3V PP3V3_S5
3.3VPOWER POWER PP3V3_S0_DPAUX
VR_CTL_PHY VR_CTL VR_CPU_COMP_RCVR_CTL_PHY VR_CTL VR_CPU_DAC
VR_CTL_PHY DDR_REG_CSVR_CTL
VR_CTL P1V8_REG_PORVR_CTL_PHY
VR_CTLVR_CTL_PHY P3V3S5_REG_BOOT_R
VR_CTL P3V3S5_REG_ISENVR_CTL_PHY
VR_CTL_PHY VR_CTL P3V3S5_REG_OCSET
5VPOWERPOWER VREFMARGIN_DIMMB_P5V
5VPOWERPOWER PP5V_S5
PP1V96_FW_PLLVDD1.96VPOWER POWER
5VPOWER PP5V_S3_CAMERA_FLTPOWER
CPU_VCC_PKG_SENSE_PSNS_DIFF
VR_CTL_PHY P3V3S5_REG_BOOTVR_CTL
VR_CTLVR_CTL_PHY DDR_REG_BOOTDDR_REG_UGATEVR_CTL_PHY SWITCHNODE
VR_CTLVR_CTL_PHY DDR_REG_VDDQSNS
VR_CTL_PHY VR_CTL VR_CPU_BOOT3_RC
P3V3S5_REG_UGATESWITCHNODEVR_CTL_PHY
VR_CTL_PHY VR_CTL P3V3S5_REG_SNUB
VTT_REG_FSVR_CTL_PHY VR_CTLVTT_REG_FBVR_CTLVR_CTL_PHYVTT_REG_COMPVR_CTL_PHY VR_CTLVTT_REG_BOOT2VR_CTL_PHY VR_CTL
PCHCORE_REG_BOOTVR_CTL_PHY VR_CTL
VR_CTL_PHY VR_CPU_DRV3_GDSELVR_CTL
VR_CTL PCHCORE_REG_TONVR_CTL_PHY
VTT_REG_ISUMVR_CTLVR_CTL_PHY
VTT_REG_LGATE1VR_CTL_PHY SWITCHNODE
VR_CTL_PHY VTT_REG_LGATE2SWITCHNODE
VR_CTLVR_CTL_PHY VTT_REG_REF
VR_CPU_ISNS1_XW_NTHERMALSNS_DIFF
VR_CTL VR_CPU_TCOMPVR_CTL_PHY
VR_CTL_PHY VR_CTL VR_CPU_SS
VR_CTL_PHY P5VS3_REG_LGATESWITCHNODE
DDR_REG_LGATEVR_CTL_PHY SWITCHNODE
VR_CTL_PHY VR_CTL DDR_REG_BOOT_R
VR_CTL_PHY P5VS3_REG_UGATESWITCHNODE
PCHCORE_REG_BOOT_RVR_CTLVR_CTL_PHY
VR_CTL PCHCORE_REG_TRIPVR_CTL_PHY
PCHCORE_REG_UGATEVR_CTL_PHY SWITCHNODE
VR_CPU_FSVR_CTLVR_CTL_PHYVR_CPU_FB_RVR_CTL_PHY VR_CTL
VR_CTL_PHY VR_CTL VR_CPU_FB
VTT_REG_PH2_SNUBVR_CTLVR_CTL_PHY
VR_CTL_PHY VTT_REG_UGATE2VR_CTL
SNS_DIFF THERMAL VR_CPU_ISNS3_P
THERMALSNS_DIFF VR_CPU_ISNS2_R_N
SWITCHNODEPOWER VTT_REG_PHASE21.1VPOWER 3.3VPOWER PP3V3_S0_PCH_VCCA_DAC_F
VID_PHY VR_CTL CPU_VID<0>VR_CTLVID_PHY CPU_VID<1>VR_CTLVID_PHY CPU_VID<2>
VR_CTLVR_CTL_PHY P5VS3_REG_OCSET
CPU_VID<7>VR_CTLVID_PHY
VR_CTLVID_PHY CPU_VID<4>VR_CTL CPU_VID<5>VID_PHY
VR_CTL CPU_PSI_LVID_PHY
VR_CPU_ISNS4_XW_PSNS_DIFF THERMAL
VR_CPU_ISNS4_XW_NTHERMALSNS_DIFF
SNS_DIFF VR_CPU_VSNS_R_P
POWER 5V PP5V_USB2_PORT0_FPOWER
SWITCHNODEPOWER 3.4V P3V42G3H_SW
POWER 5V PP5V_USB2_PORT1POWER
POWER 5V PP5V_USB2_PORT2POWER
5V PP5V_USB2_PORT3POWER POWER
SNS_DIFF THERMAL VR_CPU_ISNS1_N
VR_CTL VTT_REG_IREFVR_CTL_PHYVTT_REG_ICOMPVR_CTLVR_CTL_PHY
VR_CTL VTT_REG_BOOT1VR_CTL_PHY
VR_CTL VTT_REG_UGATE1VR_CTL_PHY
VR_CTL_PHY VTT_OFSTVR_CTL
VR_CTL_PHY VR_CTL VTT_REG_OCSET
VR_CTL_PHY VR_CTL VR_CPU_BOOT2_RC
VR_CTL_PHY VR_CTL VR_CPU_PH2_SNUBVR_CTL_PHY VR_CTL VR_CPU_PH3_SNUBVR_CTL_PHY VR_CTL VR_CPU_PH4_SNUBVR_CTL_PHY VR_CTL VR_CPU_PWM1
VR_CTL_PHY VR_CTL VR_CPU_PWM2_RVR_CTL_PHY VR_CTL VR_CPU_PWM3VR_CTL_PHY VR_CTL VR_CPU_PWM3_RVR_CTL_PHY VR_CTL VR_CPU_PWM4
VR_CTL_PHY VR_CTL VR_CPU_REF
VR_CTL CPU_VID<6>VID_PHY
VR_CTL DDR_REG_VTTSNSVR_CTL_PHY
SNS_DIFF THERMAL VR_CPU_ISNS2_R_P
SNS_DIFF VR_CPU_ISNS1_R_PTHERMAL
SNS_DIFF THERMAL VR_CPU_ISNS3_R_P
POWER 5V PP5V_USB2_PORT1_FPOWER
POWER 5V PP5V_USB2_PORT2_FPOWER
POWER DDR_REG_PGNDPOWER
POWER DDR_REG_CSGNDPOWER
VID_PHY VR_CTL CPU_VID<3>
SNS_DIFF THERMAL VR_CPU_ISNS4_R_P
VR_CTL VTT_REG_PH1_SNUBVR_CTL_PHY
VTT_REG_RGNDVR_CTLVR_CTL_PHY
VR_CPU_ISNS3_XW_NSNS_DIFF THERMAL
3.3VSWITCHNODEPOWER P3V3S5_REG_PHASEVR_CTL_PHY VR_CTL VR_CPU_PWM4_R
SNS_DIFF THERMAL VR_CPU_ISNS1_P
VR_CTL_PHY VR_CTL VR_CPU_DRV1_GDSEL
3.3V PP3V3_S0POWER POWER
SNS_DIFF THERMAL VR_CPU_ISNS3_N
SNS_DIFF VR_CPU_ISNS4_NTHERMAL
P5VS3_REG_FBVR_CTLVR_CTL_PHY
VR_CTLVR_CTL_PHY P3V3S5_REG_FB
POWERPOWER 1.5V PP0V75_S3_MEM_VREFCA_A
SWITCHNODE 1.5VPOWER DDR_REG_PHASE
5VPOWER POWER PP5V_S5_PCH_V5REFSUSPOWER 5VPOWER PP5V_CPUVTT_VR
POWER 5V PP5V_USB2_PORT3_FPOWER
SNS_DIFF CPU_VTTSENSE_R_P
CPU_VTTSENSE_PSNS_DIFF
CPU_VTTSENSE_R_NSNS_DIFF
VR_CPU_RGNDSNS_DIFF
DDR_REG_FBVR_CTLVR_CTL_PHY
5VPOWERPOWER VREFMARGIN_DIMMA_P5VPOWER POWER PP5V_S3_IR_FLT5V
5VPOWER PP5V_S0_CPU_VCORE_VCCPOWER
SNS_DIFF THERMAL VR_CPU_ISNS1_R_N
POWER 3.3VPOWER PP3V3_S0_DPFUSEPOWER 3.3VPOWER PP3V3_S0_DPPWR
VR_CPU_VSNS_R_NSNS_DIFF
THERMALSNS_DIFF VR_CPU_ISNS4_R_N
VR_CPU_ISNS2_XW_PSNS_DIFF THERMAL
SNS_DIFF THERMAL VR_CPU_ISNS3_XW_P
SWITCHNODE VR_CPU_DRV3_LGATEVR_CTL_PHY
VR_CTL_PHY VR_CTL VR_CPU_DRV4_BOOTVR_CTL_PHY VR_CTL VR_CPU_DRV4_GDSEL
PCHCORE_REG_VFBVR_CTL_PHY VR_CTLPCHCORE_REG_LGATEVR_CTL_PHY SWITCHNODE
VR_CTL VR_CPU_IOUT_PDVR_CTL_PHY
VR_CTL_PHY VR_CTL VR_CPU_IMON
CPU_VTTSENSE_NSNS_DIFF
SNS_DIFF CPU_VCC_PKG_SENSE_N
SNS_DIFF THERMAL VR_CPU_ISNS2_N
SNS_DIFF THERMAL VR_CPU_ISNS4_P
POWERPOWER 5V PP5V_S0_SATA_FET
5V PP5V_S0_PCH_V5REFPOWER POWER
5V PP5V_USB2_PORT0POWERPOWER
POWER POWER 3.3V PP3V3_S3_WM_FLT
3.3VPOWERPOWER PP3V3_S3_SDCARD_FLT
POWER 1.5VSWITCHNODE VR_CPU_PHASE2
1.05VPOWER SWITCHNODE P1V05_S5_REG_PHASE
POWER 1.5V PP0V75_S3_MEM_VREFDQ_BPOWER
12VPOWER POWER PP12V_LCD_CONN12VPOWER POWER PP12V_S0
POWER 12V PP12V_S0_CPU_FLTRDPOWER
POWER 1.05VSWITCHNODE PCHCORE_REG_PHASE
POWER 1.1V VTT_REG_PHASE1SWITCHNODE
POWER SWITCHNODE P5VS3_REG_PHASE5V
POWERPOWER 1.5V PP0V75_S3_MEM_VREFCA_B
1.8VPOWER SWITCHNODE P1V8_REG_PHASE
POWERPOWER 12V PP12V_AUD_SPKRAMP_PLANEPOWER POWER 12V PP12V_LCD
POWER 12VPOWER PP12V_S0_CPUVTT_FLTD
POWER 1.5VPOWER PP0V75_S3_MEM_VREFDQ_A
POWERPOWER 1.1V PPVCORE_S0_CPU
POWER 1.1VPOWER PPVCORE_S0_CPU_REG21.1VPOWERPOWER PPVCORE_S0_CPU_REG3
PPVCORE_S0_CPU_REG4POWER 1.1VPOWER
POWER POWER PP1V05_S0_CK505_F1.05V
PP1V05_SM_SOURCE1.05VPOWERPOWER
PP1V05_S0_PCH_VCCADPLLBPOWER 1.05VPOWERPP1V05_S0_PCH_VCCADPLLA_FPOWER POWER 1.05V
POWER POWER PP1V05_S01.05V
P1V05S5_REG_VFBVR_CTLVR_CTL_PHY
VTT_REG_VSENVR_CTLVR_CTL_PHY
VR_CTL_PHY VR_CTL VTT_SEL
P3V42G3H_BOOSTVR_CTLVR_CTL_PHY
VR_CTLVR_CTL_PHY P3V42G3H_FB
VR_CPU_VSNS_XW_NSNS_DIFF
VR_CPU_ISNS2_XW_NSNS_DIFF THERMAL
VR_CPU_ISNS1_XW_PTHERMALSNS_DIFF
PP4V5_AUDIO_ANALOGPOWER 4.5VPOWER
PP5V_S0POWERPOWER 5V
PP3V42_G3H_RPOWERPOWER 3.42V
POWERPOWER PP3V3_G3H_SMC_AVCC3.4V
POWER PP12V_S0_FAN1_L12VPOWER
PP12V_S0_FAN2_LPOWER 12VPOWER
12V PP12V_G3HPOWERPOWER
12VPOWERPOWER P12V_S0_FW_CL
POWER POWER 1.1V PPVCORE_S0_CPU_REG1
12VPOWER PP12V_S3_WM_FLTPOWER
12VPOWERPOWER PPVP_FW_PHY_CPS
POWER POWER PP1V05_S0_PCH_VCCADPLLA1.05V
POWERPOWER 0.75V PP0V75_S0
POWER PP1V05_S0_PCH_VCCAPLL_FDIPOWER 1.05VPP1V05_S0_PCH_VCCAPLL_EXPPOWER 1.05VPOWERPP1V05_S0_PCH_VCCADPLLB_FPOWER 1.05VPOWER
1.05VPOWERPOWER PP1V05_S5
PP1V95_FW_FWPHYPOWER POWER 1.96V
4V5_REG_INPOWER POWER 4.5V
P3V3S5_REG_LGATEVR_CTL_PHY SWITCHNODE
PP5V_S3_DDR_REG_V5FILTPOWERPOWER 5VPP5V_S3POWER POWER 5V
PPV_S0_MXM_PWRSRCPOWER POWER 3.3V
P5VS3_REG_BOOTVR_CTLVR_CTL_PHY
PP12V_G3H_R12VPOWER POWER
PP12V_S3POWER 12VPOWER
PP1V8_S0_CPUPOWERPOWER 1.8VPP1V8_S0POWER POWER 1.5V
POWERPOWER 1.5V PP1V5_FW_VDDA1.5VPOWERPOWER PP1V8R1V5_S0_PCH_VCCVRM
PP1V5_CPU_MEMPOWER 1.5VPOWER
1.5VPOWERPOWER PP1V5_S3
POWER POWER 1.5V PP1V5_S0_CK505_R1.5VPOWERPOWER PP1V5_S0_CK505_F1.5VPOWER POWER PP1V5_S0
POWER 1.2VPOWER PP1V2_S5_ENET
POWERPOWER 0.75V PPVTT_S0_DDR
1.1VPOWER POWER PPVTT_S0_CPU
POWERPOWER 1.1V PPVTT_S0
POWERPOWER 1.05V PP1V05_SM
POWER PP1V05_S0_CIO_VDD1P0_DP_PLL1.05VPOWER
POWERPOWER 1.05V PP1V05_S0_CIO_VDD1P0_DPPOWER PP1V05_S0_PCH_VCCA_CLK_FPOWER 1.05V
POWER POWER PP1V05_S0_PCH_VCCA_CLK1.05VPP1V05_S0_PCH_VCCAPLL_SATAPOWER POWER 1.05V
POWER SWITCHNODE 1.5V VR_CPU_PHASE3
VR_CPU_ISNS2_PTHERMALSNS_DIFF
VR_CTL_PHY VR_CTL VR_CPU_PWM2
VR_CTL_PHY VR_CTL VR_CPU_PH1_SNUB
VR_CTL P5VS3_REG_ISENVR_CTL_PHY
VR_CTL_PHY VR_CTL VR_CPU_FAN
VR_CTL_PHY VR_CTL VR_CPU_DRV1_BOOT
SWITCHNODEVR_CTL_PHY VR_CPU_DRV1_UGATE
VR_CTL_PHY VR_CTL VR_CPU_DRV2_BOOT
VR_CTLVR_CTL_PHY VR_CPU_DRV2_GDSEL
VR_CTL_PHY VR_CPU_DRV4_UGATESWITCHNODE
VR_CPU_DRV4_LGATESWITCHNODEVR_CTL_PHY
VR_CTL_PHY VR_CPU_DRV3_UGATESWITCHNODE
VR_CTL_PHY VR_CPU_DRV3_BOOTVR_CTL
VR_CTL_PHY SWITCHNODE VR_CPU_DRV2_UGATE
SWITCHNODEVR_CTL_PHY VR_CPU_DRV2_LGATE
VR_CTL_PHY SWITCHNODE VR_CPU_DRV1_LGATE
VR_CTL VR_CPU_COMP_RVR_CTL_PHY
VR_CTL_PHY VR_CTL VR_CPU_COMP
VR_CPU_BOOT1_RCVR_CTLVR_CTL_PHYVR_CPU_TMVR_CTL_PHY VR_CTL
VR_CPU_ISNS3_R_NTHERMALSNS_DIFF
POWER PP3V3_S3POWER 3.3V
POWER 3.3VPOWER PP3V3_S0_TSENS_R
POWER 3.3V PP3V3_S0_PCH_VCCA_DACPOWER
POWER 3.3VPOWER PP3V3_MINI
POWERPOWER 3.3V PP3V3_S0_HS_F
39_OHM_SEVID_PHY *
?*VR_CTL 0.2MM
BGA_P2MMSWITCHNODESWITCHNODE BGA_P1MM
6:1_SPACINGGND *SWITCHNODE
SWITCHNODE SWITCHNODE**
POWER BGA_P1MMSWITCHNODE BGA_P2MM
BGA_P1MM BGA_P2MMSWITCHNODE GND
* BGA_P1MMSWITCHNODE BGA_P2MM
6:1_SPACINGSWITCHNODE *POWER
POWER CONSTRAINTSSYNC_DATE=07/01/2009SYNC_MASTER=K60_JERRY
I614
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I588I587
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I57
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I568
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I466
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I341
I340
I339
I338
I278
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I274
I273
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I255
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I234
I231
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I226
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I223
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I221
I219
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I217
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I212
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I198
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I129
I128
6
6
6
92 52
41
37 36 66
65
6
41
22
22
22
22
70
46 45
37
27 24 22 18
39
39
41
39
59
27
27
26
64
64
44
6
80
64
64
70
70
69
69
69
28
6
39
44
64 49 13
69
70
70
70
65
69
69
67
67
67
67
68
65
68
67
67
67
67
65
64
64
69
70
70
69
68
68
68
64
64
64
67
67
65 64
64
67
64 16 13
64 16 13
64 16 13
69
64 16 13
64 16 13
64 16 13
64 16 13
66
66
64
43
71
43
43
43
65 64
67
67
67
67
67
67
65
65
65
66
65 64
64
65 64
64
66 64
64
64 16 13
70
64
64
64
43
43
70
70
64 16 13
64
67
67
65
69
64
65 64
65
6
65 64
66 64
69
69
30 28
70
24 22
67
43
67
67 49 13
67
64
70
28
44
64
64
80
80
64
64
65
65
65
66
66
68
68
64
64 49
67 13
64 13
65 64
66 64
42
24 22
43
44
44
65
71
31 28
77
63 6
66 65 64
68
67
69
31 28
70
60 58 57
77
30 28
6
65
65
66
26
72
22 17
6
71
67
71
71
64
65
65
55
92 6
71
45
92 52
92 53
71 6
65
44
41 40
22 17
6
24 22
24 22
6
40 39
55
69
70
6
50
69
71
6
49 6
6
39
24 22
49 6
6
26
26
6
37
6
49 6
6
6
24
24 22
24 22
65
65 64
65 64
65
69
64
65
65
65
65
66
66
65
65
65
65
65
64
64
65
64 64
92 6
51
22 17
33
61
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
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D
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108 OF 110
051-8233
B.0.0
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
BLANK PAGESYNC_MASTER=K60_SIJI SYNC_DATE=07/01/2009
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
DR
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
ELECTRICAL_CONSTRAINT_SET
NET_TYPE
PHYSICALPHYSICAL
PHYSICAL
NET_TYPE
SPACING
NET PHYSICAL FOR NC NETS
REMOVE WHEN CHECKPLUS IS FIXED
(PM, RESET, EN, PGOOD)PM NET PROPERTIES
PCIE GRAPHICS
SPACING
NET_TYPESPACING
109 OF 110
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<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
SDCARD_PLT_RST_LPM
PM PM_SYS_PWRGD
PM_SYNCPM_VTT
PM PM_SUS_PWR_ACK
PM_SLP_S5_LPM
PM_SLP_S4_LPM
PM PM_SLP_S4_3_L
PM PM_SLP_S4_2_L
PM_SLP_M_RPM
PM_RSMRST_LPM
PM PM_ME_S0_EN_R
PM_VTT PM_MEM_PWRGD
PM PCHCORE_REG_EN
PM PGOOD_PCH_S0
PGOOD_SYSPWROKPM
PM PGOOD_SYSPWROK_R
RTC_RESET_LPM
NO_TEST=TRUE NC_USB_EXCARD_P USB_90D USB
NO_TEST=TRUE NC_USB_EXTE_N USB_90D USB
GFX_VR_ENPM
LAN_RESET_LPM
MINI_RESET_LPM
SMC_LRESET_LPM
PM RTC_RESET_L
PM PGOOD_1V05ME_G2
PM PGOOD_P12V_S3PM PGOOD_P1V05_ME_S5
PM PGOOD_P3V3_S0
PGOOD_PCH_AND_P1V8PM
PM P12V_S3_EN
PM P3V3S0_ENPM P3V3S3_ENPM P5VS0_EN
P5VS3_ENPM
PCHCORE_REG_PGOODPM
PEG_RESET_LPM
PM SDCARD_RESET
PM_VTT PM_THRMTRIP_L
GFX_VR_PGOODPM
PM FW_RESET_L
FWXIO_SNOOP_ENPM
PM_VTT XDP_CPUPWRGD
SMC_DELAYED_PWRGDPM
MEM_RESET_LPM
PM P1V05_ME_SM_EN
PM PGOOD_P1V5_S0
PM PGOOD_1V05ME_G1
PM PGOOD_1V8_S0_G1
PGOOD_1V8_S0_G2PM
PM PGOOD_CPU_GFX_DDR
PM PGOOD_P3V3_S3PM PGOOD_P5V_S0
PM P1V5_S0_EN
PM PGOOD_P1V8_S0
PCIE NC_PCIE_CLK100M_EXCARD_N PCIE_85D
NC_PCIE_EXCARD_D2R_P PCIEPCIE_85D
CPUVTT_REG_PGOODPM_VTT
PM ALL_SYS_PWRGD_SMC
PGOOD_P3V3_MEPM
PM P3V3ME_EN
SMC_RESET_LPM
PCIEPCIE_85D NC_PCIE_EXCARD_R2D_C_P
NO_TEST=TRUEUSB_90D USB
NC_USB_TPAD_P
PM_VTT CPU_PWRGD
PM RSMRST_PWRGD
PM_SYSRST_LPM
PM_VTT XDP_DBRESET_L
PM PM_BATLOW_L
PM_CLK32K_SUSCLKPM
PM PM_CLK32K_SUSCLK_R
PM PM_ACDC_PS_ON
PM CPU_RESET_L
PM_RSMRST_PCH_LPM
PM_SLP_S3_LPM
PM PM_SLP_S4_1_L
PM PM_SLP_S3_L_AND_S0_RDY
PM_SLP_M_LPM
FWPHY_RESET_LPM
DEBUG_RESET_LPM
DDRVTT_ENPM
CPU_MEM_RESET_LPM
PCIEPCIE_85D NC_PCIE_EXCARD_D2R_N
NC_PCIE_CLK100M_EXCARD_P PCIE_85D PCIE
PCIEPCIE_85D NC_PCIE_EXCARD_R2D_C_N
NO_TEST=TRUE NC_USB_EXCARD_N USB_90D USB
NO_TEST=TRUEUSB
NC_USB_EXTE_P USB_90D
NO_TEST=TRUEUSB_90D USB
NC_USB_TPAD_N
XDP_PWRGDPM_VTT
PM T28_RESET_L
CPUVTT_REG_ENPM
PM CK505_27MHZ_EN
PM ALL_SYS_PWRGD_R
PM 4V5_REG_ENPLT_RESET_LS1V1_LPM_VTT
PM PM_EXT_TS_L<0>
FSB_CPURSTOUT_LPM_VTT
PM_ME_PWRGDPM
PM_ME_S0_EN_GPM
PM_ME_S0_EN_G1PM
PM PM_MXM_PGOODPM PM_PCH_PWRGDPM PM_PGOOD_DDRREG_S3PM PM_PGOOD_PVCORE_CPUPM PM_PWRBTN_L
PM PM_EXT_TS_L<1>
PLT_RESET_LPM
PM PM_CLKRUN_L
PM USB_HUB_RESET_L
PM_LAN_PWRGDPM
PM_VTTPM_VTT 2:1_SPACING*
*PM 2:1_SPACING*
DEFAULTGNDPM *
DEFAULTGNDPM_VTT *
PM_VTT 3:1_SPACING* *
SYNC_DATE=07/01/2009SYNC_MASTER=K60_MIKE
PM RESETS ENABLES PGOOD CONST
I99
I98
I97
I96
I95
I94
I93
I92
I91
I90I9
I89
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I87
I86
I85
I84
I83
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I81
I80
I79
I78
I77
I76
I75
I74
I73
I72
I71
I70
I7
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I68
I67
I66
I65
I64
I63
I62
I61
I60
I6
I59
I58
I57
I56
I55
I54
I53
I52
I51
I50
I5
I49
I48
I47
I46
I45
I44
I43
I42
I41
I40
I4
I39
I38
I37
I36
I35
I34
I33
I32
I31
I30
I3
I29
I28
I27
I26
I25
I24
I2
I123
I122
I120
I12
I119
I118
I117
I116
I115
I114
I113
I112
I111
I110
I109
I108
I107
I106
I105
I104
I103
I102
I101
I100
I10
I1
44 27
63 32 19
19 11
19
45 19
32 19
19 5
46 45 19
62 45
72
19 11
68 62
63
63
63
91 18
36 27
33 27
45 27
91 18
63
72 63 48
63
72 62
72 62
72 62
72 62
69 62
68 63 62 5
27 9
92 44 25 21
46 21 11
39 27
39
25 11
63 46
32 31 30
72 62
72
63
63
63
63
72 34
72 62
72 62
63
67 63 62 11
63 45
72
72 62
47 46 45
25 21 11
63 45
45 27 19
27 25 11
45 19 15
85 45 9
85 19 9
6
27 11
62 19
63 62 46 37 33 32 19 5
62 19
62 19 5
39
47 27
70 62 32
32 11
25
67 62
26
63 32 25 6
55 11
46 11
25 11
63 19
72
72
74 63
63 19
70 62 5
64 63 26 5
45 25 19
46 11
27 20
47 45 19 15
35 34
19 15
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
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PAGE TITLE
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
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8 7 5 4 2 1
J5550 HDD TEMP SENSOR
J5560 SKIN TEMP SENSOR
J5551 ODD TEMP SENSOR
J5521 AMBIENT TEMP SENSOR
1 PP5V_S0 Testpoint near J4520
5 Ground Testpoints near J4520
J5520 ANALOG LCD TEMP SENSOR
J6603 AUDIO LEFT SPEAKER
2 Ground Testpoints near J4780
1 PP3V3_S3 Testpoint near J4720
J5700 CPU FAN
J5601 HD FAN
1 PP5V_S3_REG Testpoint near J4780
J4780 IR BOARD
J4520 SATA ODD (HIGH SPEED)
J4510 SATA HDD (HIGH SPEED)
3 Ground Testpoints near J4510
16 TP’S
2 TP’S
J5600 ODD FAN
2 Ground Testpoints near J4720
J4720 USB BLUETOOTH
J4700 USB CAMERA
2 Ground Testpoints near J4700
J4750 USB CARD READER
FUNCTIONAL TESTPOINTS FOR MAC-1 & ICT
1 PP5V_S3_REG Testpoint near J4700
2 TP’S
J6601 AUDIO MICROPHONE
1 Ground Testpoint near J6601
J6602 AUDIO RIGHT SPEAKER
2 Ground Testpoints near J4750
1 PP3V3_S3 Testpoint near J4750
110 OF 110
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<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
FUNC_TEST=TRUEMIN_ALLOWED_TPS=16
GND
FAN_1_GND FUNC_TEST=TRUE
SNS_SKIN_P FUNC_TEST=TRUE
FUNC_TEST=TRUESNS_SKIN_N
FUNC_TEST=TRUESNS_ODD_NFUNC_TEST=TRUESNS_ODD_P
SNS_AMB_P FUNC_TEST=TRUE
SMC_ODD_DETECT FUNC_TEST=TRUE
HDD_OOB_TEMP_FILT FUNC_TEST=TRUE
FUNC_TEST=TRUESNS_LCD_P
USB_SDCARD_L_N FUNC_TEST=TRUE
SDCARD_RESET FUNC_TEST=TRUEMIN_ALLOWED_TPS=1
FUNC_TEST=TRUEPP5V_S0
USB_BT_L_P FUNC_TEST=TRUE
FUNC_TEST=TRUESATA_ODD_D2R_C_N
SATA_ODD_R2D_P FUNC_TEST=TRUE
USB_BT_L_N FUNC_TEST=TRUE
SNS_LCD_N FUNC_TEST=TRUE
FUNC_TEST=TRUESNS_AMB_N
FAN_2_PWR_L FUNC_TEST=TRUE
FUNC_TEST=TRUEPP12V_S0_FAN2_L
FUNC_TEST=TRUEFAN_2_GND
FUNC_TEST=TRUEFAN_TACH1_L
FAN_1_PWR_L FUNC_TEST=TRUE
FUNC_TEST=TRUEPP12V_S0_FAN1_L
FUNC_TEST=TRUEUSB_IR_L_P
FUNC_TEST=TRUEUSB_IR_L_N
SATA_ODD_R2D_N FUNC_TEST=TRUE
SATA_ODD_D2R_C_P FUNC_TEST=TRUE
FUNC_TEST=TRUESATA_HDD_R2D_P
SATA_HDD_R2D_N FUNC_TEST=TRUE
FUNC_TEST=TRUESATA_HDD_D2R_C_N
SATA_HDD_D2R_C_P FUNC_TEST=TRUE
GND_AUDIO_MIC1_CONN FUNC_TEST=TRUE
FUNC_TEST=TRUEAUD_SPKR_OUTLO2L_POUT
AUD_SPKR_OUTLO1R_POUTFUNC_TEST=TRUE
AUD_SPKR_OUTLO2R_POUTFUNC_TEST=TRUEAUD_SPKR_OUTLO2R_NOUTFUNC_TEST=TRUE
FUNC_TEST=TRUEAUD_SPKR_OUTLO2L_NOUT
AUD_SPKR_OUTLO1R_NOUTFUNC_TEST=TRUE
FUNC_TEST=TRUEAUD_SPKR_OUTLO1L_POUT
FUNC_TEST=TRUEAUD_SPKR_OUTLO1L_NOUT
FUNC_TEST=TRUEFAN_TACH0_L
FAN_TACH2_L FUNC_TEST=TRUE
FUNC_TEST=TRUEFAN_0_GNDFUNC_TEST=TRUEPP12V_S0_FAN0_L
FUNC_TEST=TRUEUSB_CAMERA_L_P
FUNC_TEST=TRUEFAN_0_PWR_L
USB_CAMERA_L_N FUNC_TEST=TRUE
USB_SDCARD_L_P FUNC_TEST=TRUE
MIN_ALLOWED_TPS=2FUNC_TEST=TRUEPP3V3_S3
FUNC_TEST=TRUE
MIN_ALLOWED_TPS=1PP5V_S3_CAMERA
FUNC_TEST=TRUEMIN_ALLOWED_TPS=1
PP5V_S3_REG
AUD_MIC_IN1_P_CONN FUNC_TEST=TRUE
AUD_MIC_IN1_N_CONN FUNC_TEST=TRUE
K22/K23 ICT/FCTSYNC_MASTER=K60_DEREK SYNC_DATE=07/01/2009
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