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Seminar Architectureand Design Methods of
Embedded System
Topic : Objective VHDL
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OutlineWhat is VHDLWhat is OOPOO-VHDLObjective VHDLThe implementationThe toolsSummary
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What is VHDLUsed to describe behaviour of FPGA and ASIC in electronic design automation of digital circuitModel can be verified before translating the design into real hardwareOther HDL: Verilog
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What is OOPTo implement the functions and instruction in objects or individual unitsGreater flexibility, maintainability, and easy to learn
{...add()...multiply()...openFile()...closeFile()......}
Math {..add()...multiply().....}
File {...open()...close()......}
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The Concept of OOPClassMethodObjectAbstractionInheritanceEncapsulationPolymorphism
+accelerate()+brake()
Vehicle
+changeGear()-engineType
Car
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OO-VHDLTo manage design complexity and increase software reuseThe former : VHDL_OBJ, VHDL++, and VistaThe latter : SUAVE, Schumacher’s OO-VHDL, and Objective VHDL
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Objective VHDLExtension of VHDLDesigned to ease synthesis with some hardware-related restriction and hardware specific semantics
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The Points of Objective VHDLObject stateState transitionsObject lifetimeCommunicationbetween objectsRequest arbitration
SerialParalel
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Implementation of OOP in Objective VHDL (2)
Class
type FIFO is class
end class FIFO;type FIFO is class body
class attribute item: Buffer_array := (others =>0);class attribute first: Natural range 0 to size -1 := 0;class attribute nxt: Natural range 0 to size -1 := 0;class attribute empty: Boolean := true;
class attribute index: Natural range 0 to size := 0;end class body FIFO;
+is_full()+is_empty()-next_index()+put()+get()
#item#first#nxt#empty+size+bits+type-index
FIFO
Protected attributes
Private attributes
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Implementation of OOP in Objective VHDL (3)
Method
+is_full()+is_empty()-next_index()+put()+get()
#item#first#nxt#empty+size+bits+type-index
FIFO
type FIFO is class
end class FIFO;type FIFO is class body
end class body FIFO;
function is_full return Boolean;function is_empty return Boolean;for variable,signal
procedure put (val: in Integer);procedure get (val: out Integer);
end for;
…function next_index (index: in Integer)
return Integer is…function is_full return Boolean is…function is_empty return Boolean is…for variable
procedure put(val: in Integer) is…procedure get(val: out Integer) is…
end forfor signal
procedure put(val: in Integer) is…procedure get(val: out Integer) is…
end for
Public methods
Private methods
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Implementation of OOP in Objective VHDL (4)
Method
+is_full()+is_empty()-next_index()+put()+get()
#item#first#nxt#empty+size+bits+type-index
FIFO
…function is_full return Boolean is
beginreturn nxt = first and not empty;
end…for variable
procedure put(val: in Integer) isempty := false;…
end forfor signalprocedure put(val: in Integer) is
empty <= false;…
end for…
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Implementation of OOP in Objective VHDL (5)
Objectvariable fifo_object: FIFO generic map(size=>8, bits =>3);Orsubtype FIFO_8_3 is FIFO generic map(size=>8, bits=>3);signal fifo_object: FIFO_8_3;
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Implementation of OOP in Objective VHDL (6)
Abstractiontype Buffer_t is abstract class
generic(size : Positive; bits : Positive
);subtype Item_t is Integer range 0 to 2**bits – 1;type Buffer_array is array ( 0 to size -1 ) of Item_t;class attribute item : Buffer_array := (others => 0);for variable, signal
procedure put ( val : in Integer );procedure get (val : out Integer );
end for;end class Buffer_t;
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Implementation of OOP in Objective VHDL (7)
Inheritance
+put()+get()
#item+size+bits
Buffer_t
+is_full()+is_empty()-next_index()
#first#nxt#empty+type-index
FIFO
type FIFO is new class Buffer_t with
end class FIFO;type FIFO is class body
class attribute first: Natural range 0 to size -1 := 0;class attribute nxt: Natural range 0 to size -1 := 0;class attribute empty: Boolean := true;function is_full return Boolean;function is_empty return Boolean;for variable,signal
procedure put (val: in Integer);procedure get (val: out Integer);
end for;
class attribute index: Natural range 0 to size := 0;…
end class body FIFO;
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Implementation of OOP in Objective VHDL (8)
Exampletype Producer is class
port(link: inout FIFO);class attribute token : Integer := 0;for variable
procedure produce;end for;
end class Producer;type Producer is class body
for variableprocedure produce isbegin
server.put(token);end;
end for;end class body Producer;
type Consumer is classclass attribute token : Integer := 0;for variableprocedure consume(signal link: inout FIFO);end for;
end class Consumer;type Consumer is class bodyfor variable
procedure consume(signal link: inout FIFO) isbegin
server.get(token);end;
end for;end class body Consumer;
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Implementation of OOP in Objective VHDL (9)
Examplesignal fifo_obj: FIFO;process
variable producer_obj1: Producer port map(link => fifo _obj);variable producer_obj2: Producer port map(link => fifo _obj);variable consumer_obj: Consumer;begin…
producer_obj1.produce;producer_obj2.produce;consumer_obj.consumer(fifo_obj);
…end
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Implementation of OOP in Objective VHDL (10)
PolymorphismObject
type Producer is classport(link: inout Buffer_t’CLASS);…
end class Producer;type Producer is class body
…end class body Producer;
type Consumer is class…procedure consume(signal link: Buffer_t’CLASS);…
end class Consumer;type Consumer is class body
…procedure consume(signal link: Buffer_t’CLASS) is…
end class body Consumer;
signal buffer_obj: Buffer_t’CLASS;
CLASS WIDE TYPE
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Implementation of OOP in Objective VHDL (11)
Concurrency Solution1. Modelling of guard expression
procedure guard(expression: Boolean)
for signalprocedure get(val: out Integer) is
variable object_copy: FIFO;begin
guard(not is_empty);object_copy:=this;object_copy.get(val);this <= object_copy;
end;end for;
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Implementation of OOP in Objective VHDL (12)
Concurrency Solution2. Scheduling policy
static priority schedulinground robin schedulingenhanced round robin schedulingequal priority schedulingfirst come first serve scheduling
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Implementation of OOP in Objective VHDL (13)
Examplesignal fifo_obj: FIFO;use SCHEDULERS.DECLARATIONS.SCHEDULING;attribute SCHEDULING of fifo_obj : signal is “Round_Robin”;signal producer_obj1: Producer port map(link => fifo _obj);signal producer_obj2: Producer port map(link => fifo _obj);signal consumer_obj: Consumer;…
-- in process 1producer_obj1.produce;-- in process 2producer_obj2.produce;-- in process 3consumer_obj.consumer(buffer_obj);
…
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SummaryObjective VHDL provides object oriented paradigm such as class, object, method, inheritance, encapsulation, and abstractionThe main advantage and disadvantage of Objective VHDL are the supporting toolsBetter synthesis tools
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