several topics on tdc and the wave union tdc implemented in fpga
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Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 1
Several Topics on TDC and the Wave Union TDC implemented in FPGA
Wu, Jinyuan
Fermilab
LBNL, Mar. 2009
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 2
Features of FPGA TDC
• Fast Turn Around: – 10 - 20 min recompile time.
• Sufficiently Good Resolution: – Delay line based: as good as 10ps.
• Low Cost at Small Volume: – 8ch are implemented in EP2C8T144C6 ($31.68).
• Flexibility of DAQ Integration: – Trigger, event packing, serialization etc. can be
integrated in the same device.
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 3
FPGA TDC: a Single Chip Solution
TDC FPGA
TDC
FPGA
TDCTDCTDC
DAQ
VTH
VTH
PMTIn
PMTIn • The differential input of the
FPGA is a comparator.
• It is possible to directly interface analog signals.
VB
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 4
Actual Board and Circuit
TDC
FPGA
TDC
TDC
DAQ
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 5
TDC Using FPGA Logic Chain Delay• In Cyclone II chips, carry
chain in a (ripple) adder is used as the delay line.
• The registers recodes each bit of the adder result.
• A priority encoder follows the array.
IN
CLK
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 6
Two Major Issues Due ToDifferential Non-Linearity
0
20
40
60
80
100
120
140
160
180
0 16 32 48 64
bin
wid
th (
ps)
1. Widths of bins are different and varies with supply voltage and temperature.
2. Some bins are ultra-wide due to LAB boundary crossing
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 7
Digital Calibration Using Twice-Recoding Method
IN
CLK
• Use longer delay line.• Some signals may be
registered twice at two consecutive clock edges.
N2-N1=(1/f)/t
The two measurements can be used:– to calibrate the delay.– to reduce digitization
errors.
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 8
TDC Output at Different PS Voltage
0
5
10
15
20
25
1.5 2 2.5
VCCINT (V)
TD
C O
utp
uts
N1
n2
TDC Output at Different PS Voltage
0
5
10
15
20
25
1.5 2 2.5
VCCINT (V)
TD
C O
utp
uts
N1
n2
Tc
Digital Calibration Result• Power supply voltage
changes from 2.5 V to 1.8 V, (about the same as 100 oC to 0 oC).
• Delay speed changes by 30%.
• The difference of the two TDC numbers reflects delay speed.
2nd TDC
1st TDCCorrected Time
)()(
0112
01 NNL
T
NN
NNTTc
• Warning: This is only an average bin width calibration, not bin-by-bin.
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 9
0
500
1000
1500
2000
2500
0 16 32 48 64
bin
tim
e (p
s)
Histogram Based Auto Calibration
0
20
40
60
80
100
120
140
160
180
0 16 32 48 64
bin
wid
th (
ps)
DNLHistogram
In (bin)LUT
Out (ps)
16KEvents
• It provides a bin-by-bin calibration at certain temperature.
• It is a turn-key solution (bin in, ps out)
• It is semi-continuous (auto update LUT every 16K events)
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 10
Good, However
• Auto calibration solved some problems • However, it won’t eliminate the ultra-wide
bins
0
20
40
60
80
100
120
140
160
180
0 16 32 48 64
bin
wid
th (
ps)
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 11
Cell Delay-Based TDC + Wave Union Launcher
Wave UnionLauncher
In
CLK
The wave union launcher creates multiple logic transitions after receiving a input logic step.
The wave union launchers can be classified into two types:
• Finite Step Response (FSR)
• Infinite Step Response (ISR)
This is similar as filter or other linear system classifications:
• Finite Impulse Response (FIR)
• Infinite Impulse Response (IIR)
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 12
Wave Union Launcher A (FSR Type)
In
CLK
1: Unleash0: HoldWave UnionLauncher A
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 13
Wave Union Launcher A:Two Measurements in One Array
1: Unleash
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 14
Sub-dividing Ultra-wide BinsImproving Sensitivity
1: Unleash
1
2
1
2
• Plain TDC:– Max. bin width: 160 ps.
– Average bin width: 60 ps.
• Wave Union TDC A:– Max. bin width: 65 ps.
– Average bin width: 30 ps.0
20
40
60
80
100
120
140
160
180
0 16 32 48 64 80 96 112 128bin
wid
th (p
s)
Plain TDC
Wave Union TDC A
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 15
Auto Calibration for Wave Union TDC A
DNLHistogram
In (bin)LUT
Out (ps)
0
• It is not possible and not necessary to control the relative timing of two edges precisely.
• Use TN1+TN2 as input for calibration.
0
20
40
60
80
100
120
140
160
180
0 16 32 48 64 80 96 112 128bin
wid
th (p
s)
Plain TDC
Wave Union TDC A
0
500
1000
1500
2000
2500
0 16 32 48 64 80 96 112 128
bin
t(p
s)
Plain TDC
Wave Union TDC A
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 16
Measurement Result forWave Union TDC A
Histogram
Raw
TDC+
LUT53 MHzSeparate Crystal
-
-WaveUnion Histogram
• Plain TDC:– delta t RMS width: 40 ps.
– 25 ps single hit.
• Wave Union TDC A:– delta t RMS width: 25 ps.
– 17 ps single hit.0
500
1000
1500
2000
2500
3000
3500
1000 1100 1200 1300 1400 1500
dt (ps)
Un-calibrated
Plain TDC
Wave Union TDC A
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 17
More Measurements
• Two measurements are better than one.
• Let’s try 16 measurements?
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 18
Wave Union Launcher B (ISR Type)
Wave UnionLauncher B
In
CLK
1: Oscillate0: Hold
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 19
Wave Union Launcher B: Screen Dump
1 Hit16 Measurements@ 400 MHz
VCCINT=1.20V
VCCINT=1.18V
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 20
Delay Correction
0
500
1000
1500
2000
2500
3000
0 4 8 12 16
m
T0
(ps)
16
32
48
64
0 2 4 6 8 10 12 14 16
m
TD
C (
bin
)
Delay Correction Process:• Raw hits TN(m) in bins are first calibrated
into TM(m) in picoseconds.
• Jumps are compensated for in FPGA so that TM(m) become T0(m) which have a same value for each hit.
• Take average of T0(m) to get better resolution.
The raw data contains:
• U-Type Jumps: [48-63][16-31]
• V-Type Jumps: other small jumps.
• W-Type Jumps: [16-31][48-63]
15
000 )(
16
1
mav mtt
The processes are all done in FPGA.
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 21
The Test Module
Two NIM inputs
FPGA with 8ch TDC
Data Output via Ethernet
BNC Adapter to add delay @
150ps step.
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 22
Test ResultOn Board Signal
RMS 9ps
-Wave Union TDC BWave Union TDC BWave Union TDC BWave Union TDC B
Wave Union TDC BWave Union TDC BWave Union TDC BWave Union TDC B
+
+
Two independent crystals for:• Driving TDC• Creating test hits
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 23
Test ResultNIM Inputs
0 1 2
RMS 10ps
LeCroy 429ANIM Fan-out
NIM/LVDS
NIM/LVDS
-
140ps
Wave Union TDC BWave Union TDC BWave Union TDC BWave Union TDC B
Wave Union TDC BWave Union TDC BWave Union TDC BWave Union TDC B
+
+BNC adapters to add delays @ 140ps step.
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 24
PerformanceDevice: EP2C8T144C6, Price: $28 (April 2008),
Operating Frequency: 400MHz, Total Logic Elements: 8256
Max bin width
Av bin width
DT RMS error
Dead Time
Delay Chain Length
Logic Element Usage
Un-calibrated TDC
165ps 60ps 58ps 2.5ns 64 1621
(21%)Plain TDC 165ps 60ps 40ps 2.5ns
Wave Union TDC A
65ps 30ps 25ps 5ns
Wave Union TDC B
10ps 45ns 6581
(83%)
8CH
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 25
Some Deleted Slides
• Resource usage in TDC depends on the measurement resolution strongly.
• To improve resolution by a factor of 2 may increase resource usage by a factor of 4 with the same base design.
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 26
Test Result (1)
01 2
RMS 20ps
LeCroy 429ANIM Fan-out
NIM/LVDS
NIM/LVDS
-
150ps
Wave Union TDC B
Wave Union TDC B
BNC adapters to add delays @ 150ps step.
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 27
Test Result (2)
0 12
RMS 14ps
LeCroy 429ANIM Fan-out
NIM/LVDS
NIM/LVDS
-
150ps
Wave Union TDC BWave Union TDC B
Wave Union TDC BWave Union TDC B
+
+
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 28
Test Result (3)
0 1 2
RMS 10ps
LeCroy 429ANIM Fan-out
NIM/LVDS
NIM/LVDS
-
140ps
Wave Union TDC BWave Union TDC BWave Union TDC BWave Union TDC B
Wave Union TDC BWave Union TDC BWave Union TDC BWave Union TDC B
+
+
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 29
Slower But Cheaper
• Multi-sampling TDC uses significantly less resources.
• Typical resolution is 500ps-1ns (LSB) or 144-288ps (RMS).
• This scheme is suitable for drift chamber applications.
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 30
Multi-Sampling TDC FPGA c0
c90
c180
c270
c0
MultipleSampling
ClockDomain
Changing
Trans. Detection& Encode
Q0
Q1
Q2
Q3QF
QE
QD
c90
Coarse TimeCounter
DV
T0T1
TS
• Ultra low-cost: 48 channels in $18.27 EP2C5Q208C7.
• Sampling rate: 360 MHz x4 phases = 1.44 GHz.
• LSB = 0.69 ns.
4Ch
Logic elements with non-critical timing are freely placed by the fitter of the compiler.
This picture represents a placement in Cyclone FPGA
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 31
A 96 Channel TDC Module
Data Concentration FPGA
48CH TDC FPGA
48CH TDC FPGA
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 32
The 96 CH TDC Module Specifications
TABLE I MIPP TDC CARD PARAMETERS
Main Input Clock: RF 53.102MHz, 18.8ns
Internal Clock: CK212 212.4MHz, 4.708ns
TDC Resolution: LSB 1.18ns
Hit Rate Limiter Setting 4hits/256CK212
Double Hit Min. Separation 4xCK106, 37.7ns
Event Window 2 x 1.2s
Absolute Maximum Hits/event/48ch 123hits+5header/trailers
Event Maximum Size/96ch 256 x 2Bytes
SDRAM port data rate 53MHz x 2Bytes
Number of events/spill <32K
Absolute Maximum data/spill/FE card 8M words
Absolute Maximum data/spill/8 FE 128MB, 1280Mbits
Readout Chain Data Rate 26.5Mbits/s
Absolute Maximum Spill Readout Time 48.3sec
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 33
Some Important Details on Coarse Time Counters
• Connecting coarse time with the fine time is normally considered a “challenge”.
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 34
Issues of Coarse Time Counter
• There are some common misunderstandings on coarse time counters in a TDC:– Tow coarse time counters are needed, driven by clocks with 180
degree phase difference.
– The coarse time counter should be a Gray code counter.
• Actually, dual counters and/or Gray code counters are only needed in one ASIC TDC architecture.
• In the architectures used by FPGA TDC and some ASIC TDC, only one plain binary counter is needed as coarse time counter.
CoarseTime
Counter
CoarseTime
Counter
CoarseTime
Counter
GrayCode
Counter
000001011010110111101100
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 35
Delay Line Based TDC Architectures
HIT
CLK
HIT
CLK
HIT
CLK
HIT
CLK
Delay Hit Delay CLK Delay Both
CLK is used as clock
HIT is used as clock
Only this architecture needs dual coarse time counters.
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 36
Implementation of Coarse Time CounterCoarseTime
Counter
FineTime
Encoder
In
CLK
ENA
Fine Time
Coarse Time
Data Ready
Hit Detect Logic
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 37
Differential Inputs and Multiple Thresholds
• An FPGA can handle many differential inputs and each input can feed a TDC functional block.
• Multi-threshold approach is commonly used to compensate time-walk due to amplitude variation.
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 38
Differential Dual Threshold for PMT
T0 = (T1+T2)/2 – ((T3+T4)/2-(T1+T2)/2)/4
• Four comparators: two for +- signals, two for signals vs. fix thresholds.
• Insensitive to amplitude, threshold voltage, common mode noise.
• High resolution TDC is needed only for T1 and T2, not T3 and T4.
T3
T0
T4
T1
T2
2Vth 8Vth
T1
T2
T3
T4
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 39
Insensitivity to Common Mode Level
T3
T0
T4
T1
T2
2Vth8Vth
T0 = (T1+T2)/2 – ((T3+T4)/2-(T1+T2)/2)/4
• Typically, differential noise << common mode noise.
• The common mode level variation is canceled in (T3+T4).
• Large common mode noise is tolerated.
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 40
Another Differential Dual Threshold Input Circuit
T3T0 T1
T2
8Vth
T1
T2
T3
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 41
Summary
• FPGA TDC covers wide range of applications:– TOF, Delta T RMS resolution: 20-25ps: Delay Line.– Drift Chamber, LSB 0.5-1ns: Multi-sampling.
• After-fact digital calibration instead of analog compensation is more convenient for FPGA TDC.
• Multiple-measurement method is used in the Wave Union TDC to improve performance.
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 42
The End
Thanks
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 43
TDC Back End
MDRDY
MD[15..0]
POP
CK200
DQRDY
DQ[7..0]
DQV
Keq0Q
Meq0Q
Buff16x8a
inst13
MDRDY
MD[15..0]
POP
CK200
DQRDY
DQ[7..0]
DQV
Keq0Q
Meq0Q
Buff16x8a
inst22
TNRDY
TN[7..0]
TNV
Keq0Q
Meq0Q
CK200
TMRDY
TM[15..0]
TNQQ[15..8]
DKUVW[3..1]
DKUQ
DKVQ
DKWQ
TMOK
MISC[7..0]
DNL_LUTb
inst8
TNRDY
TN[7..0]
TNV
Keq0Q
Meq0Q
CK200
TMRDY
TM[15..0]
TNQQ[15..8]
DKUVW[3..1]
DKUQ
DKVQ
DKWQ
TMOK
MISC[7..0]
DNL_LUTb
inst16
IN
ENINP
CK200
CK400
QxB[63..0]
TDC64carry1ChH
TCH1
IN
ENINP
CK200
CK400
QxB[63..0]
TDC64carry1ChH
TCH2
LCELL
TBC1
LCELL
TBC2
QxB[63..0]
CK200
CK400
DVQQ
DKQQ[1..0]
TBQQ[5..0]
TBRDY
TB[15..0]
PUSHTB
PUSH1TB
DecodeTDC48bitC
DCH1
QxB[63..0]
CK200
CK400
DVQQ
DKQQ[1..0]
TBQQ[5..0]
TBRDY
TB[15..0]
PUSHTB
PUSH1TB
DecodeTDC48bitC
DCH2
ENINP
CK200
CK400
CK200
ENINP
CK200
CK400
CK200
CK200
CK400
POP
CK200
CK400
POP
CK200
CK200
ETB
ETC
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 44
Calibration Resource
256
Wor
d(s)
RA
M
Block Ty pe: M4K
data_a[15..0]
address_a[7..0]
w ren_a
data_b[15..0]
address_b[7..0]
w ren_b
clock
q_a[15..0]
q_b[15..0]
lpm_ram_dp3
inst13
A
B
A+B
dataa[15..0]
datab[15..0]
cin
result[15..0]
lpm_add_subH4
inst7
PRN
CLRN
D
ENA
Q
DFFE
inst11
AND2
inst37
NOT
inst31
CK200
PGN,AA[6..0]
WEA
DA[15..0]
zzz[15..0]
zzz[0]
MHQAD[15..0] CK200
DA[15..0]MHQAD[15..0]
DA[15..0]
ENADA
ZERODA
AccumDNL
PG,zzz[6],TN[5..0]
TMB[15..0]
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 45
Timing Diagram
0 1 2 3 4 5 6 7SEQ[2..0]
ST[1..0]
ZERODA
ENADA
WEA
0
AA[6..0] 0 1
HCNT[14..0] 1
WT
0 1 2 3 4 5 6 7SEQ[2..0]
ST[1..0]
ZERODA
ENADA
WEA
1
AA[6..0] 127
1 2 3 4 5 6 7
0
0
BK
HCNT[14..0]
BK
ZERODA
ENADA
WEA
1 2 3
CntHCNT CntHCNT
TN1 TN2
7 1 2 3 4 5 6 7
BK
ZERODA
ENADA
WEA
CntHCNT
TN16382 TN16383
16383 0
ST[1..0]
0 1 2 3 4 5 6 7
0
1 2
ZERODA
ENADA
WEA
0 1 2 3 4 5 6 7
ZERODA
ENADA
WEA
1
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 46
“Wavelet TDC” --> “Wave Union TDC”
• This design was named “Wavelet TDC”.
• Criticism was received for confusion that may be caused by using “Wavelet”.
• It is now renamed as “wave union” TDC.
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 47
Wave Union Launcher B: Delta T
0
500
1000
1500
2000
2500
3000
0 4 8 12 16
m
T0
(ps)
0
1000
2000
3000
4000
5000
6000
-100 -80 -60 -40 -20 0 20 40 60 80 100
bin (ps)
(Tsum16-2Tsum8) (T02-T01)
• Plain TDC:– delta t RMS width: 40 ps.
– 25 ps single hit.
• Wave Union TDC B:– delta t RMS width: 12 ps.
– 8 ps single hit.
Wave UnionTDC B
(+)RandomInput
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 48
FPGA and ASIC
• FPGA is not the best vehicle to pursue the resolution frontier. (Double-digit ps).
• However, some tricks can be cross-transplanted between FPGA & ASIC:– Multi-measurement method.– Auto calibration to eliminate PLL and to
tolerate DNL as silicon process goes finer.
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 49
Delay Line in ASIC TDC
Encoder
Auto Calibration
Mar. 12, 2009 Wu, Jinyuan (jywu168@fnal.gov) Fermilab 50
The End
Thanks
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