streamlining ip and ip to soc prototyping
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©Synopsys 2012 1
Streamlining IP and IP to SoC
Prototyping
Mick Posner
©Synopsys 2012 2
Agenda
Understanding IP Prototyping Use Mode Example
Streamlining IP to SoC Prototyping
©Synopsys 2012 3
IP and SoC Validation Require Different
Prototyping Solutions
• Problem:
– IP and SoC level prototypes require different capacity solutions
– IP and SoC level prototypes require similar capabilities
– IP prototypes need to be rapidly integrated into SoC level
prototypes
• Goals:
– Minimize effort for both IP and SoC teams
– Minimize cost to both teams
Graphics
Display
Video
Memory
Controller
©Synopsys 2012 4
Use Modes for RTL Block, IP Developers
and Validation/SW Engineers
Common
Use Modes
Emerging Hybrid
PCI E Connected
Prototype
Standalone Validation
©Synopsys 2012 5
Use Case: Standalone Self Contained Validation Environment
Subsystem
with or w/o
CPU
Real
World
I/O
Prototyping board
Real
World
I/O
Memory • Software
development
• Software
debugger
linked via JTAG
• Configuration
RTL Validated As Part of a Standalone Subsystem
High Performance “real world” interfaces, HW validation, HW/SW Integration, SW
Development
RW I/O = Real World IO
Example: MIPI http://www.synopsys.com/dw/ipdir.php?ds=mipi_csi2
Standalone validation platform with encapsulation of MIPI CSI/DSI
©Synopsys 2012 6
Use Case: PCI E Connected Prototype RTL Memory Mapped, HW/SW Integration, SW Development
Glue
Logic
PCI E
Core
• Custom software
development
• Standard SW Driver
validation
• Streaming data
video/image tests
Real
World
I/O
Prototyping board
RTL is Memory Mapped Across Transparent PCI E for Direct Interface Access
High Performance data streaming, enables custom software development and
standard software drivers to be validated against IP.
Example: USB 3.0 IP http://www.youtube.com/watch?v=MTGBz--4tVY
Prototyping platforms connect to host via PCI E and run software on host
©Synopsys 2012 7
Use Case: Hybrid Immerse RTL in Subsystem
Transactors RW
I/O
Prototyping board
Synopsys Virtual
Prototype
Software
Virtual Prototype
Hybrid Prototyping
RTL validated in-context of a system/subsystem. Virtual system enables SW
development within context of target system without implementation
Example: Hybrid http://www.synopsys.com/Systems/FPGABasedPrototyping/Pages/hybrid-prototyping.aspx
Combination of Virtual Prototype and FPGA-Based Prototype
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Streamlining IP to SoC Prototyping
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Streamlining IP to SoC
• Problem:
– IP prototypes need to be rapidly integrated into SoC level
prototypes
• Goals:
– Minimize effort for both IP and SoC teams
– Minimize cost to both teams
• Solutions
– IP teams have three options of delivery to SoC teams
– IP as RTL
– IP encapsulated as a physical “hardware” deliverable
– IP and FPGA Binary
©Synopsys 2012 10
RTL IP Deliverables
Advantages
• Portable “soft” delivery
• Flexible, can be tailored to suit
any SoC platform
Disadvantages
• Duplicated prototyping effort;
both IP and SoC teams
• Potential model mismatches
between IP and SoC versions
if prototyping platforms and
software tool flow differ
• Lack of IP protection
In-house or 3rd party prototyping boards
IP
SoC
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RTL IP Deliverables
• Ensure a consistent software tool flow
– Use the same implementation tools between IP and SoC teams
– Maintains consistency and enables greater chance of script reuse between teams
which in-turn reduces
– Example: Synopsys Synplify Premier/Certify
• Use consistent hardware
– While capacity requirements are different ensure consistent hardware is utilized
with similar capabilities
– Minimizes design, debug and pin out changes
– Example: Synopsys HAPS Modular and Scalable systems with unified pin
mapping
Recommendation
IP
SoC
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“Physical” IP Deliverables
Advantages
• Validated IP delivery
• Tuned for required
configuration
• Single prototyping effort
Disadvantages
• Duplicate hardware cost
• Effort to create hardware
adapter and debug
• Effort to create custom
software interface and debug
• Increased risk introduced by
custom interface
• No Clock synchronization
• Unknown performance
In-house or 3rd party IP prototyping boards
IP SoC
©Synopsys 2012 13
“Physical” IP Deliverables
• Use consistent hardware with support for “chaining”
– Ensure hardware supports multiple units being chained easing integration to units
– Requirements
– Clock & reset synchronization across units
– High performance interfacing
– Secure bit file to IP can be locked & encrypted
– Optional
– Remote usage modes eases deployment and debug
– High speed configuration
Recommendation
SoC
HAPS HAPS
IP Hapstrak to Hapstrak
Clock
Example
©Synopsys 2012 14
IP
The Loop Concept IP Validation Mode
UMRBus or
PCI E Core
To Host
I/O
Native PCI E Prototyping
Host running IP Validation
software or standard Driver
IP Prototyping Tasks
• Controller + PHY Interoperability
• System Compliance testing
• Early firmware/software
development
The Loop Concept
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The Loop Concept Easing SoC Integration SoC Validation Mode
IP
UMRBus or PCI
E Core Unused
I/O
Advantages:
• No change to IP FPGA bit file image
• Accelerates SoC integration
• Start SoC validation and HW/SW integration earlier
©Synopsys 2012 16
FPGA Binary IP Deliverables
IP team delivers FPGA “bit file” to SoC Validation team for
incorporation into SoC level prototype
Advantages
• Reduced hardware cost
• Validated IP delivery
• Tuned for required configuration
• Single prototyping effort
• Difficult to do even with unified hardware
In-house or 3rd party prototyping boards
©Synopsys 2012 17
FPGA Binary IP Deliverables
• IP FPGA bit file directly reused in SoC system
• Daughter board placement and connectors need to be identical
• The loop concept needs to be implemented
Requirements
SoC
IP
Possible with HAPS but careful planning
between IP and SoC teams needed.
System available for next project
©Synopsys 2012 18
Summary
• Plan for SoC Prototyping at the IP prototyping stage
• Utilize unified software tool flow enabling reuse between
IP and SoC teams
• Standardize on hardware between IP and SoC teams
minimizing prototyping effort between teams
©Synopsys 2012 19
Backup
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Validate IP Blocks
(IP Team Effort)
HAPS Streamlining IP to SoC Integration
System Validation
(SoC Team Effort)
Individual IP quickly
integrates into larger systems
Identical pinout, Script
Reuse
Reduced Effort!
MIPI
Display
HDMI
Video
USB 3.0
Interface
HAPS-70 S12
HAPS-70 S48
SoC
©Synopsys 2012 21
Streamlining Multi-IP Integration MIPI
Display
HDMI Video
USB 3.0
Interface
USB 3.0
HDMI
MIPI
Individual IP modules quickly
integrated into single system
before integration into SoC
Prototype
Script reuse, identical pin out
SoC/System
Prototype
©Synopsys 2012 22
Prototyping with Xilinx V7 Devices
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Xilinx Virtex-7 2000T
• Xilinx Virtex-7 2000T
– 12 Million ASIC Gates
– Multiple Super Logic Regions
– Like four FPGA’s in one package connected by thousands of wires
• Enables large IP’s such as cores and controllers
©Synopsys 2012 24
V7 Enables Multi-IP Consolidation Virtex-7 2000T SLR (Super Logic Region)
IP #1
IP #2
IP #3
~3.1M
ASIC
Gates
~3.1M
ASIC
Gates
~3.1M
ASIC
Gates
~3.1M
ASIC
Gates
©Synopsys 2012 25
SLR Crossing Caution
Virtex-7 2000T SLR (Super Logic Region)
Example PCB: IO Banks and SLRs not matched
• Board architecture forces
SLR crossing
• HW architecture limits the
prototype performance
Common Logic
2x SLR
Crossing
Delay
Don’t do this!
©Synopsys 2012 26
The HAPS-70 Systems
Virtex-7 2000T SLR (Super Logic Region)
• Hardware design ensures
minimal SLR crossing
• Hardware architecture
maximizes the prototype
performance
Common Logic
Example HAPS: IO Bank and SLR matched
No SLR
Crossing
Delay
Recommended
for Performance
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