synchronization pres
Post on 07-Apr-2015
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Synchronization in DigitalLogic Circuits
Ryan DonohueRdonohue@yahoo.com
Synchronization: Why care?
Digital Abstraction depends on allsignals in a system having a valid logicstateTherefore, Digital Abstraction dependson reliable synchronization of externalevents
The Real World
Real World does not respect the DigitalAbstraction!
$ Inputs from the Real World are usuallyasynchronous to your system clock
8 PORTGigabit
Ethernet Switch
$ Inputs that come from othersynchronous systems are basedon a different system clock, whichis typically asynchronous to yoursystem clock
MetastabilityWhen asynchronous events enter yoursynchronous system, they can cause bistablesto go into metastable statesEvery real life bistable (such as a D-latch) hasa metastable state
Vin
Vout
VTC offeedback
VTC ofseries inverters
'0' state
'1' state
metastablestate
Vin VoutD Q
CLK
0
1Vin VoutD Q
CLK
2
Quick Metastability Review
Once a FF goes metastable (due to a setuptime violation, say) we can_t say when it willassume a valid logic level or what level itmight eventually assumeThe only thing we know is that the probabilityof a FF coming out of a metastable stateincreases exponentially with time
FF in 'normal' states FF in metastable state
'1' state'0' state '0' state '1' state
Mean Time Between Failures
For a FF we can compute its MTBF,which is a figure of merit related tometastability.
e(tr/t)
TofaMTBF(tr) =
tr resolution time (time since clock edge)
t and To FF parameters
f sampling clock frequencya asynchronous event frequency
For a typical .25umASIC library FF
t = 0.31nsTo = 9.6as
tr = 2.3nsFor f = 100MHz,
a = 1MHzMTBF = 20.1 days
Synchronizer Requirements
Synchronizers must be designed toreduce the chances system failure dueto metastabilitySynchronizer requirements$ Reliable [high MTBF]$ Low latency [works as quickly as possible]$ Low power/area impact
Single signal SynchronizerTraditional synchronizer
$ SIG is asynchronous, and META might gometastable from time to time
$ However, as long as META resolves before thenext clock period SIG1 should have valid logiclevels
$ Place FFs close together to allow maximum timefor META to reslove
D Q D QSIG META
CLK
SIG1SIG
META
SIG1
CLK
3
Single Synchronizer analysis
MTBF of this system is roughly:
e(tr/t)
Tof
e(tr/t)
TofaMTBF(tr) = x
Can increase MTBF by adding more seriesstages
For a typical .25umASIC library FF
t = 0.31nsTo = 9.6as
tr = 2.3ns For f = 100MHz,a = 1MHz
MTBF = 9.57x1010 years
Age of Earth = 5x109 years
D Q D QSIG META SIG1
D QSIG2
CLK
Flip Flop design is important?
Dynamic FFs not suitable for synchronizerssince they have no regeneration
Special _SYNC_ FFs should be used for theprimary synchronizer if available
D Q
CLK CLKD Q
f
f
f
f
CMOS Dynamic FF TSFF (Svenson)
SYNC Flip FlopSYNC Flip Flops are available in some ASIClibraries
$ Better MTBF characteristics due to high gain in thefeedback path
$ Very large (5x regular FF) and very high power
D Q D QSIG META
CLK
SIG1
SYNC
Vin
Vout
VTC ofregular FF
series inverters
VTC ofSYNC FF
series inverters
'0' state
'1' state
Synchronization Pitfall
Never synchronize the same signal in multipleplaces! Inconsistency will result!
D Q D QSIG1
SYNC
D Q D QSIG2
SYNC
SIGCLK
CLK
4
Bus Synchronization
Obvious approach is to use single signalsynchronizers on each bitWRONG!
D Q D QSIG1[0]
SYNC
D Q D QSIG1[1]
SYNC
SIG[0]
CLK
CLK
SIG[1]
SIG[0]
SIG1[0]
CLK
SIG[1]
SIG1[1]
Handshaking is the AnswerNeed a single point of synchronization for theentire busCLK
SIG[1:0]
ACK
REQ
Handshaking
FSM
Handshaking
FSM
D QD Q
DQDQ
2SIG
REQ
ACK
CLK1 CLK2
CLK1
CLK2
Handshaking Rules
Sender outputs data and THEN asserts REQReceiver latches data and THEN asserts ACKSender deasserts REQ, will not reassert ituntil ACK deassertsReceiver sees REQ deasserted, deasserts ACKwhen ready to continue
CLK
SIG[1:0]
ACK
REQ
Alternate Handshaking SchemePrevious example is known as 4-phasehandshaking2-phase (or edge based) handshaking is alsosuitable
$ Sender outputs data and THEN changes state ofREQ, will not change state of REQ again until afterACK changes state.
$ Receiver latches data. Once receiver is ready formore it changes state of ACK.
2-phase requires one bit of state be kept oneach side of transaction. Used when FFs areinexpensive and reliable reset is available.
5
High Bandwidth solutions
Handshaking works great, but reducesbandwidth at the clock crossinginterface because each piece of datahas many cycles of series handshaking.Correctly designed FIFOs can increasebandwidth across the interface and stillmaintain reliable communication
Abstract FIFO design
Ideal dual port FIFO writes with oneclock, reads with anotherFIFO storage provides buffering to helprate match load/unload frequencyFlow control needed in case FIFO getstotally full or totally empty
DATA_IN DATA_OUT
FULL EMPTY
CLK1 CLK2
FIFO in detailFIFO of any significantsize is implemented usingan on-chip SRAMSRAM must be dual-ported for our design[have two independentports]We will use a writepointer to determine thewrite address, and a readpointer to determine theread address
Dual PortSRAM
FIFOWRITELOGIC
FIFOREADLOGIC
RD_PTRWR_PTR
WR_DATA RD_DATA
CLK1 CLK2
FULL EMPTY
DATA_IN DATA_OUT
PORT1 PORT 2
FIFO pointer control
FIFO is managed as acircular buffer usingpointers.First write will occur ataddress 00h. Next writewill occur at 01h.
After writing at FFh, nextwrite will wrap to 00h.Reads work the same way.First read will occur ataddress 00h.
FEhFFh
WRITEPNTR
READPNTR
00h01h
n bits of datan bits of data
n bits of datan bits of datan bits of datan bits of data
6
FIFO pointers and flow controlGeneration of FULL and EMPTY signals.
$ FIFO is FULL when write pointer catches readpointer
$ FIFO is empty when read pointer catches writepointer
Write pointer and read pointer must neverpass each other.
$ Write passing read overwrites unread data$ Read passing write re-reads invalid data
always @(posedge clk1)FULL <= (WR_PNTR == RD_PNTR) && ((OLD_WR_PNTR + 1 == RD_PNTR) || FULL)
always @(posedge clk2)EMPTY <= (WR_PNTR == RD_PNTR) && ((OLD_RD_PNTR + 1 == WR_PNTR) || EMPTY)
FIFO in detailWe have a problem!
To generate FULL/EMPTY conditions the writelogic needs to see the read pointer and the readlogic needs to see the write pointer!
Dual PortSRAM
FIFOWRITELOGIC
FIFOREADLOGIC
RD_PTRWR_PTR
WR_DATA RD_DATA
CLK1 CLK2
FULL EMPTY
DATA_IN DATA_OUT
PORT1 PORT 2
Pointer Synchronization
Our pointers change in a very specific way(when they change, they increment by 1)
$ Applying a traditional two stage FF synchronizer oneach bit of a binary pointer could cause a wildlyinvalid pointer value to be produced
$ Gray coding the pointer value means at most onebit will change per cycle _ we can only be _off byone_000001010011100101110111
000001011010110111101100
Binary Gray CLK
BIN[2:0]
GRAY[2:0]
011
010 110
100
BIN_S[2:0] 011
GRAY_S[2:0] 010 110 or 010
100
110
XXX
Pointer SynchronizerPointer is stored in gray code.A standard single bitsynchronizer is used on eachbit of PTR_OUT. At most onebit changes per cycle!We can still do binary math toincrement the pointer.
D Q
CLK
PTR_OUT
1
bin2gray
gray2bin
module bin2gray (bin,gray);
parameter SIZE = 4;
input [SIZE-1:0] bin;output [SIZE-1:0] gray;reg [SIZE-1:0] gray;
always @(bin) gray = (bin >> 1) ^ bin;
endmodule
module gray2bin (gray,bin);
parameter SIZE = 4;
input [SIZE-1:0] gray;output [SIZE-1:0] bin;reg [SIZE-1:0] bin;
integer i;
always @(gray)for (i=0; i<SIZE; i=i+1) bin[i] = ^(gray >> i);
endmodule
7
Pointer Synchronizer pitfall
Write and read pointers need to be registeredin gray code as shown on previous slide.Don_t be tempted to cheat and registerpointers in binary. What_s wrong with thesynchronizer shown below?
D Q D QPTR_IN
CLK
PTR_OUT
SYNCbin2gray gray2bin
Answer to pitfall
Combinational logic frequently containshazards at the output (non fully coveredKarnaugh map)Avoid this problem by using a registeredvalue of PTR_IN
D Q D QPTR_IN
CLK
PTR_OUT
SYNCbin2gray gray2bin
PTR_IN[2:0] 011 100
CLK
PTR_IN_G[2:0] 010 110
LOGIC HAZARD (unknown value)
Pointer math pitfall
When our pointer synchronizer goesmetastable our new pointer value may not beupdated until one cycle later.We need to be conservative when generatingFULL and EMPTY signals to reflect this.
$ Typically FULL = 1 when WRITE catches READ.We need FULL = 1 when WRITE catches READ-1.
$ Typically EMPTY = 1 when READ catches WRITE.We need EMPTY = 1 when READ catches WRITE-1.
Final Synchronizer FIFO
Works for any phase/frequency relationshipbetween CLK1 and CLK2
Dual PortSRAM
FIFOWRITELOGIC
FIFOREADLOGIC
RD_PTRWR_PTR
WR_DATA RD_DATA
CLK1 CLK2
FULL EMPTY
DATA_IN DATA_OUT
PORT1 PORT2
SYNC
SYNC
CLK1
CLK2
8
Mesosynchronous Designs
When two systems of bounded frequencyneed communicate, open loopsynchronization circuits can be used (no ACK)
CLK
SIG[1:0]
REQ
Handshaking
FSM
Handshaking
FSM
D QD Q
2SIG
REQ
CLK1 CLK2
CLK2 Assume:
CLK2 = CLK1 +- 5%
Mesosynchronous Tradeoffs
Benefits to mesosynchronous designs$ Less synchronization circuitry$ Synchronizer might have lower latency vs. full 4-
phase handshaking
Costs of mesosynchronous designs$ Synchronizer only works at certain frequency
ratios (may hamper bringup/debug)$ Intolerant of spec mistakes (maybe that unload
frequency was supposed to be +- 50%!)
Words to the wise
Be wary of synchronizer schemes designed byothers
$ Synopsys Designware DW04_sync multi-bitsynchronizer DOES NOT WORK as a synchronizer
$ Synthesizers might use dynamic FFs assynchronizers _ they don_t know the difference.
$ Auto-placement tools must be told to placesynchronizer FF pairs close together
BE PARANOID
Conclusions
Synchronizers are important. Synchronizationfailure is deadly and difficult to debugSynchronization requires careful design. MostCAD and logic tools CANNOT catch badsynchronizer designs.Design of synchronizer depends onperformance level needed. Basicsynchronizer of back-to-back FFs is the coredesign all others are based on.
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