synthesizing sram timing and periphery using synopsis
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Rob
ust
Low
Power
VLSI
Robust
LowPower
VLSI
Synthesizing SRAM timing and Periphery using SynopsisBy: Jim Boley
Rob
ust
Low
Power
VLSI
Background and Motivation Most SoC designs require on chip
memory Design time on the order of
months SRAMs consume a majority of
the area and power on a digital design
To reduce this area, the bitcell array is made as dense as DRC will allow
Bitcell array consumes a majority of the total area, therefore optimizing the periphery doesn’t result in significant area savings
Rob
ust
Low
Power
VLSI
Outline Motivation SRAM bitcell layout Synthesis of periphery Future work
Rob
ust
Low
Power
VLSI
Outline Motivation SRAM bitcell layout Synthesis of periphery Future work
Rob
ust
Low
Power
VLSI 5
SRAM Bitcell Layout
NL NR
XL XR
PRPL
Q QB
VDD
WLBL BLB
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Step 1- Place PMOS Devices
PL PR
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Step 2- Place NMOS Pull Down devices
NL NR
PRPL
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Step 3- Place NMOS Passgate Device
XL XR
NL NR
PRPL
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Step 4- Create Gate to Diffusion Contacts
XL XR
NL NR
PRPL
Q QB
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Step 5- Create Diffusion-M1 Contacts
XL XR
NL NR
PRPL
Q QB
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Step 6- Place M2 Strips
NL NR
XL XR
PRPL
Q QB
VDD
BL BLB
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Step 6- Place M3 Strips
NL NR
XL XR
PRPL
Q QB
VDD
BL BLBWL
VSS
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Shared Contacts Minimize Area
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Shared Contacts Minimize Area
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Final Array- 16x16
53.84μm x 15.12μm = 814.1μm2
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Outline Motivation SRAM bitcell layout Synthesis of periphery Future work
Rob
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Decoder Synthesismodule decoder(binary_in , // 4 bit binary inputdecoder_out , // 16-bit out enable // Enable for the decoder);input [3:0] binary_in ;input enable ; output [15:0] decoder_out ; wire [15:0] decoder_out ;
assign decoder_out = (enable) ? (1 << binary_in) : 16'b0 ;
endmodule
Rob
ust
Low
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VLSI
Timing/Periphery Synthesis
}
}
BL Drivers
BLB Drivers
<- Decoder output
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ust
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VLSI
Timing/Periphery Synthesis
Inactive Read Write
Rob
ust
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VLSI
Outline Motivation SRAM bitcell layout Synthesis of periphery Future work
Rob
ust
Low
Power
VLSI
Future Work Bitcell array- finish power grid, add body
contacts, add pins ICC- integration of synthesized periphery with
custom array (Milkyway) Simulation of final design
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ust
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VLSI 22
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