system-on-chip design, embedded system design challenges
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System-on-Chip DesignEmbedded System Design Challenges
Pierre Boulet – DaRT project-team
Master recherche informatique 2009–2010
Embedded System Design ChallengesDefinition and SignificanceSystem-on-Chip TodayMain Challenges on DesignSome AnswersOverview of the Course
Embedded System Design ChallengesDefinition and SignificanceSystem-on-Chip TodayMain Challenges on DesignSome AnswersOverview of the Course
DefinitionWhat is an embedded system?
É systemÉ set of components needed to perform a
functionÉ hardware + software + ...
É embeddedÉ main function not computingÉ usually not autonomous
É usuallyÉ computer inside a systemÉ specific purposeÉ submitted to constraints
ExamplesÉ very small
É electronic tagsÉ smartcards
É microcontrollersÉ washing machine, microwave oven, ...É computer peripherals
É keyboardÉ hard drive controller
É more complex controllersÉ digital cameraÉ automotive
É air bags, ABS, ...É ESB, engine control, ...
Examples – continuedÉ communications
É mobile phonesÉ network routers, modemsÉ software radio
É multimediaÉ set-top boxes
É cable, satellite TVÉ HDTV, DVD players
É video gamesÉ radar, sonar
Market SignificanceÉ huge market
É global embedded systems market (2009):88,144 M$
É average annual growth rate (2009): 14 %É embedded software
É global embedded systems market (2009):3,448 M$
É average annual growth rate (2009): 16 %
Technology Trends
Overall Roadmap Technology Characteristics 39
THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2003
The ORTC metrics are often used by semiconductor companies as a set of targets that need to be achieved ahead of schedule to secure industry leadership. Thus, the highly competiti ve environment of the semiconductor industry quickly tends to make obsolete many portions of the ORTC metrics and, consequently, the Roadmap. Hopefull y, the gathering and analysis of actual data, combined with the ITRS annual update process will provide suff iciently close tracking of the evolving international consensus on technology directions to maintain the usefulness of the ITRS to the industry.
For example, the actual data and conference papers, along with company survey data and public announcements will be re-evaluated during the year 2004 ITRS update process, and the possibilit y of a continued two-year node cycle. In addition, logic and Flash product half-pitch acceleration will be monitored for future header leadership candidates.
As mentioned above, to reflect the variety of cycles and to allow for closer monitoring of future roadmap shifts, it was agreed to continue the practice of publishing annual technology requirements from 2003 through 2009, called the “Near-term Years,” and at three-year (node) intervals thereafter, called the “L ong-term years” (2012, 2015, 2018), while retaining the previous 2001 ITRS long-term columns for ease of comparison and to retain the tracking of the three-year cycle nodes.
Figure 7 2003 ITRS—Half Pitch Trends
2003 ITRS Technology Trends - 1/2 Pitch
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MPU M1 1/2 Pitch
2003 ITRS Period: Near-term: 2003-2009; Long-term: 2010-2018
hp90
hp65
hp45
hp32
hp22
2-year Node Cycle
3-year Node Cycle
Generations46 Overall Roadmap Technology Characteristics
THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2003
Table 1i High-Performance MPU and ASIC Product Generations and Chip Size Model—Near-term Years
Year of Production 2003 2004 2005 2006 2007 2008 2009
Technology Node hp90 hp65
DRAM ½ Pitch (nm) 100 90 80 70 65 57 50
MPU/ASIC Metal 1 (M1) ½ Pitch (nm) 120 107 95 85 76 67 60
MPU/ASIC ½ Pitch (nm) (Un-contacted Poly) 107 90 80 70 65 57 50
MPU Printed Gate Length (nm) †† 65 53 45 40 35 32 28
MPU Physical Gate Length (nm) 45 37 32 28 25 22 20
Logic (Low-volume Microprocessor) High-performance ‡
Generation at production ** p03h -- p05h -- p07h -- p09h
Functions per chip (milli on transistors) 439 553 697 878 1,106 1,393 1,756
Chip size at production (mm2) §§ 310 310 310 310 310 310 310
High-performance MPU Mtransistors/cm2 at production
(including on-chip SRAM) ‡ 142 178 225 283 357 449 566
ASIC
ASIC usable Mtransistors/cm2
(auto layout) 142 178 225 283 357 449 566
ASIC max chip size at production (mm2) (maximum
lithographic field size) 572 572 572 572 572 572 572
ASIC maximum functions per chip at production (Mtransistors/chip) (fit in maximum lithographic field size)
810 1,020 1,286 1,620 2,041 2,571 3,239
Design Productivity Gap
Today, we have the opportunity to define a
reuse strategy that can not only co-exist for
FPGAs and ASICs but can also work seam-
lessly between the two technologies. The
decision to include FPGAs in a Design
Reuse strategy must be made up-front
because it affects almost all phases of the
Design Reuse process, from design specifica-
tion to verification planning.
Sharing RTL Design Methods
One of the most exciting outcomes of the
dramatic improvements in FPGA architec-
tures, pricing, and design tools is that this
technology advancement has made it possi-
ble for ASIC and FPGA designers to share a
common RTL design methodology. A com-
mon RTL design methodology is the basis
for a common design reuse methodology.
Though ASICs will continue to provide
higher levels of design integration, higher
speeds, and new EDA environments,
FPGAs are never far behind. The major
FPGA and EDA companies have made a
conscious decision to keep their design envi-
ronments the same, from the end users
point of view, to make it easy for users to
move from one technology to the another.
This was illustrated by the wide adoption of
RTL synthesis tools and verification tools in
the mid-1990s. In the case of RTL synthesis,
existing ASIC methodology was kept the
same and the synthesis algorithms where
changed to target specific FPGA devices.
Today we are seeing higher-level EDA tools
such as Floorplanners and team-based
design tools using the Internet.
Conclusion
In 1999, the number of ASIC design starts
peaked at only 1000 designs, and despite all
the publicity over the multimillion gates
designs, most of these design starts were
under 200K transistors. The average FPGA
design start in 1999 was between 10K and
50K gates, with the fastest growing size range
between 50K and 100K gates. Considering
that FPGAs are more widely used than ASICs
in digital designs today, it makes sense to
include FPGAs in a design reuse strategy.
There are many benefits of sharing a common
design reuse strategy; one of the most com-
pelling is the flexibility it gives the designer to
choose the IC technology late in the design
cycle. It provides the flexibility to choose the
best method to implement an SLI design
without the overhead of retraining the design
teams. In this fast pace market it is difficult to
predict what features your product will need
and what technology you should use.
A Design Reuse strategy is more than RTL code
and synthesis. Many companies reusing designs
have found more value in the design and test
specifications than the actual RTL design. If
you are currently an ASIC user, the good news
is that many of the elements of a good design
reuse methodology can easily incorporate
FPGAs with minimal modifications.
Xilinx has joined efforts with Qualis DesignCorporation to create the first Reuse DesignGuide for FPGA users. This new FPGA ReuseField Guide will walk you through the elementsof building a design reuse strategy and is avail-able, free of charge, from the Xilinx website at:www.xiliinx.com/ipcenter.
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SchematicCapture
LogicSynthesis
DesignReuse
ProductivityGap
Moore’sLaw
EngineeringProductivity
SystemVerification
BehavioralCompilers
Gates / designer / day
Figure 2 - The productivity gap
Perspective Design Reuse
42
Embedded System Design ChallengesDefinition and SignificanceSystem-on-Chip TodayMain Challenges on DesignSome AnswersOverview of the Course
System-on-ChipÉ definition
É (nearly) complete embedded systemÉ on a single chip
É usualy includesÉ programmable processorsÉ memoryÉ accelerating function unitsÉ I/OÉ software
Technology Integration4 System Drivers
THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2003
Figure 9 First Integration of Technologies in SOC with Standard CMOS Process
SOC MULTI-TECHNOLOGY The need to build heterogeneous systems on a single chip is driven by such considerations as cost, form-factor, connection speed/overhead, and reliabilit y. Thus, process technologists seek to meld CMOS with MEMS, and other sensors. Process complexity is a major factor in the cost of SOC-MT applications, since more technologies assembled on a single chip requires more complex processing. The total cost of processing is diff icult to predict for future new materials and combinations of processing steps. However, at present cost considerations limit the number of technologies on a given SOC: processes are increasingly modular (e.g., enabling a flash add-on to a standard low-power logic process), but the modules are not generall y “stackable”. Figure 9 shows how first integrations of each technology within standard CMOS processes—not necessaril y together with other technologies, and not necessaril y in volume production—might evolve. CMOS integration of the latter technologies (electro-optical, electro-biological) is less certain, since this depends not only on basic technical advances but also on SOC-MT being more cost-effective than multi -die SIP alternatives. Today, a number of technologies (MEMS, GaAs) are more cost-effectively flipped onto or integrated side-by-side with silicon in the same module depending also on the area and pin-count restrictions of the respective product (e.g. Flash, DRAM). Physical scale in system applications (e.g., ear-mouth = speaker-microphone separation, or distances within a car) also affect the need for single-die integration, particularly of sensors.
SOC HIGH-PERFORMANCE Examples of SOC-HP include network processors and high-end gaming applications. Since it reflects MPU-SOC convergence, SOC-HP follows a similar trend as MPU and is not separately modeled here. However, one aspect of SOC-HP merits discussion, namely, that instances in the high-speed networking domain drive requirements for off-chip I/O signaling (which in turn create significant technology challenges to Test, Assembly and Packaging, and Design). Historicall y, chip I/O speed (per-pin bandwidth) has been scaling much more slowly than internal clock frequency. This is partly due to compatibilit y with existing slow I/O standards, but the primary limitation has been that unterminated CMOS signals on printed circuit boards are diff icult to run at significantly greater than 100MHz due to slow settling times. During the past decade, high-speed links in technology initially developed for long-haul communication networks have found increasing use in other applications. The high-speed I/O eliminates the slow board settling problems by using point-to-point connections and treating the wire as a transmission line. Today the fastest of these serial links can run at 10Gbit/s per pin.
A high-speed link has four main parts: a transmitter to convert bits to an electrical signal that is injected into the board-level wire, the wire itself , a receiver that converts the signal at the end of the wire back to bits, and a timing recovery circuit that compensates for the delay of the wire and samples the signal on the wire at the right place to get the correct data. Such links are intrinsically mixed-signal designs since receivers, transmitters, and timing recovery all require analog blocks (e.g., the VCO discussed as part of the Mixed-Signal driver is a key component of a timing recovery circuit). Broadly speaking, high-speed links are used in optical systems, chip-to-chip connections, and backplane connections. We now discuss each of these applications in slightly more detail.
SoC ExamplesÉ Canon Digic processor family
É image processorÉ improved quality, power consumption, speed,
costÉ STI Cell
É Sony+Toshiba+IBMÉ aim at several TFlops at 65nm integrationÉ one PowerPC + 8 SIMD units
É TI OMAPÉ platformÉ dedicated to 2.5G and 3G mobile phones / PDA
STI Cell
http://www.blachford.info/computer/Cell/Cell0_v2.html
OMAP 9
Frame Buffer/Internal SRAM (2 MBit)
Timers, Interrupt Controller , RTC
Security: SHA-1/MD5 DES/3DES RNG
GPS
EmulatorPod
JTAG/Emulation
I/F
McBSP
MCSI
UART
UART/IrDA
LED
Voice
Data
Control
OMAP1612
TMS320C55x™
DSP ARM926
LCDController PWLUSB OTG
LiquidCrystal Display
LCDLight
Controller
TCS4105TCS2100TCS2010ModemChipset
Buzzer
GPIO
Keypad
LPG
PWT
Memory StickMMC-SD
LEDLPG
Keypad
GPIO
HDQ/1Wire Battery
Memory Stick Card,MMC-SD Card
Memory StickMMC-SD
Memory Stick Card,MMC-SD Card
ARM Peripherals Baseband Peripherals Shared ARM and DSP Peripherals Dedicated Ports
I2C
Debug Messaging
UARTData
Voice
BRF6100 Bluetooth ™
MCSI
Serial
FastIrDA
12 MHz
32 kHzReset
Clock and
Reset Mgt.
TNETw1130 NANDFLASH
CompactFLASH
EMIF/CFHigh Speed WLAN a/b/g
FLASH
MobileDDR
Client Host
Shared Memory Controller/DMA
2D Graphic Accelerator
I2C Peripheral
In/OutAudio
TLC320AIC23AudioCodec
TSC2301Audio Codec
Touch Screen ControllerAudio Amplifier
McBSPµWire
Camera I/F CMOSSensor
EMT9Debugger
Typical application using the OMAP1612 device
OMAP1612application processor
For high-performance, space-constrained product platforms, the OMAP1612
application processor includes all the capabilities of the OMAP1611 device
plus the added benefit of stacked mobile double data rate (DDR) memory.
The significance of DDR memory to system designers is it allows for a 100-MHz
interface clock to memory while providing memory access speeds up to
200 MHz. With stacked memory, mobile device manufacturers can design a sys-
tem with a very small footprint but expanded memory storage. The stacked
memory options include up to 256 Mb of storage. In addition, the OMAP1612
processor’s stacked memory consumes less power than traditional external
memory because of reduced load capacitance on the IOs.
Requirements for PDA SOC-LP
6 System Drivers
THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2003
• Die size increases on average by 10% per node through 2018 to accommodate increased functionality; this matches historical trends for the application domain.
• Layout densities for memory and logic fabrics are the same as for the MPU driver, with eDRAM density assumed to be 3× SRAM density.
• Maximum on-chip clock frequency is approximately 5–10% of the MPU clock frequency at each node.
Peak power dissipation is limited to 0.1 W at 1000C, and standby power to 2.1 mW, due to battery life.
Table 9 System Functional Requirements for the PDA SOC-LP Driver
YEAR OF PRODUCTION 2003 2006 2009 2012 2015 2018
Process Technology (nm) 101 90 65 45 32 22
Supply Voltage (V) 1.2 1 0.8 0.6 0.5 0.4
Clock Frequency (MHz) 300 450 600 900 1200 1500
Application (maximum required performance)
Still Image Processing
Real Time Video Codec (MPEG4/CIF) Real Time Interpretation
Application (other) Web Browser TV Telephone (1:1) TV Telephone (>3:1)
Electric Mailer Voice Recognition (Input) Voice Recognition (Operation)
Scheduler Authentication (Crypto Engine)
Processing Performance (GOPS) 0.3 2 14 77 461 2458
Required Average Power (W) 0.1 0.1 0.1 0.1 0.1 0.1
Required Standby Power (mW) 2 2 2 2 2 2
Battery Capacity (Wh/Kg) 120 200 200 400 400 400
SOC TRENDS SOC presents Design, Test, PIDS and other areas with a number of technology challenges, such as development of reusable analog IP. The most daunting SOC challenges are:
• design productivity improvement of > 100% per node, with needs including platform-based design7 and integration of programmable logic fabrics (Design),8
• management of power especially for low-power, wireless, multimedia applications (Design, PIDS),
• system-level integration of heterogeneous technologies including MEMS and optoelectronics (PIDS, FEP, Design), and
• development of SOC test methodology, with needs including test reusabili ty and analog/digital BIST.
Since SOC is aimed at low-cost and rapid system implementation, and since power is one of the grand challenges in recent ITRS editions, it is appropriate to consider implications of power management on the achievable space of SOC designs. The following discussion develops trend analyses for the SOC-LP driver with respect to this issue.
Two approaches can be used to derive the power dissipation for the SOC-LP model. The first approach is to accept the system specifications (0.1 W peak power, and 2 mW standby power) in a “ top-down” fashion. The second approach is to derive the power requirements “bottom-up” f rom the implied logic and memory content, as well as process and circuit
7 Platform-based design is focused on a specific application domain. The platform embodies the hardware architecture, embedded software architecture, design methodologies for IP authoring and integration, design guidelines and modeling standards, IP characterization and support, and hardware/software verification and prototyping. Derivative designs may be rapidly implemented from a single platform that has a fixed portion and a variable portion that permits proprietary or differentiated designs. (See: H. Chang et al., Surviving the SOC Revolution: A Guide to Platform-based Design, Boston:Kluwer Academic, 1999.) 8 A programmable logic core is a flexible logic fabric that can be customized to implement any digital logic function after fabrication. The structure of a programmable logic fabric may be similar to an FPGA capability within specific blocks of the SOC. They allow reprogrammability, adaptability and reconfigurability, which greatly improve chip productivity. Applications include blocks that implement standards and protocols that continue to evolve, changing design specifications, and customization of logic for different, but related, applications and customers.
Embedded System Design ChallengesDefinition and SignificanceSystem-on-Chip TodayMain Challenges on DesignSome AnswersOverview of the Course
Technology Challenges for SoCDesign
É design productivity increaseÉ main challengeÉ need >100% increase per technology node
É management of powerÉ especially for low-power, wireless, multimedia
applicationsÉ system-level integration of heterogeneous
technologiesÉ development of SoC test methodology
Target Design Freedom100% of Design Productivity Improvement
22 System Drivers
THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2001
Figure 13 New and Reused Logic Content versus Memory Content with Constant Die Size and
Insufficient (42% Per Node) Design Productivity Growth
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Figure 14a Evolution of Maximum Logic
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Figure 14b 100% Productivity Improvement
per Node Will Preserve Designer Freedom at
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Logic vs Memorywith Different Rates of Productivity Improvement
22 System Drivers
THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2001
Figure 13 New and Reused Logic Content versus Memory Content with Constant Die Size and
Insufficient (42% Per Node) Design Productivity Growth
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Figure 14a Evolution of Maximum Logic
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Figure 14b 100% Productivity Improvement
per Node Will Preserve Designer Freedom at
the End of the ITRS Forecast Period
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SoC Design Cost Model2 Design
THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2003
Figure 13 Impact of Design Technology on SOC LP-PDA Implementation Cost
This chapter first presents silicon complexity and system complexity challenges, followed by five crosscutting challenges (productivity, power, manufacturing integration, interference, and error tolerance) that permeate all DT areas. The bulk of the chapter then sets out detailed challenges according to a traditional landscape of DT areas (see Figure 14): design process; system-level design; logical, circuit and physical design; design verification; and design test.1 These challenges are discussed at a level of detail that is actionable by management, R&D, and academia in the target supplier community, i.e., the electronic design automation (EDA) industry. As appropriate, the detailed challenges are mapped to the MPU, SOC, AMS, and memory system drivers; most challenges map to MPU and SOC, reflecting today’s EDA technology and market segmentation. A brief unified overview of AMS-specific DT is given to reflect the rise of application- and driver-specific DT, and the likely organization of future ITRS Design Chapter editions according to system drivers, rather than traditional areas of DT.
1 Additional discussion of analog/mixed-signal circuits issues is contained in the System Drivers Chapter (AMS Driver). Test equipment and the test of manufactured chips are discussed in the Test Chapter, while this chapter addresses design for testability, including built-in self test (BIST).
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Design Cost ProblemÉ economy will limit the semiconductor industry
É before the end of Moore’s lawÉ today design time
É 30% designÉ 70% verification/test
Complexity ChallengeÉ silicon complexity
É impact of process scaling and new materialsand architectures
É previously ignorable phenomena now haveimpact
É system complexityÉ reuseÉ verification and testÉ cost-driven design optimizationÉ embedded software designÉ reliable implementation platformsÉ design process management
É together: superexponentially increasingcomplexity of the design process
Methodology PreceptsITRS
É exploit reuseÉ evolve rapidlyÉ avoid iterationÉ replace verification by preventionÉ improve predictabilityÉ orthogonalize concernsÉ expand scopeÉ unify
Embedded System Design ChallengesDefinition and SignificanceSystem-on-Chip TodayMain Challenges on DesignSome AnswersOverview of the Course
ReuseÉ IP
É IP = Intellectual PropertyÉ HW or SW blockÉ designed for reuseÉ need of standards (VSIA)
É platform based SoC designÉ organized methodÉ to reduce cost and riskÉ by heavy reuse of HW and SW IPs
É steps in reuseÉ block → IP → integration architecture
Raising the Abstraction LevelÉ ESL (Electronic System Level)
É from RTL to TLM or higherÉ from VHDL to SystemC to UML
É HW/SW co-designÉ need new toolsÉ consider the whole systemÉ large optimization potentialÉ combination of formal, semi-formal and non
formal techniques
Other Problem: PowerConsumptionLower Bound for Fixed Chip Size
System Drivers 7
THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2003
parameters. Logic power consumption is estimated based on αCVdd2f + IoffVdd model for dynamic plus static power,
using area-based calculations similar to those in the MPU power analysis. The memory power consumption model also uses αCVdd
2f + IoffVdd with a different factor for α.9 For these calculations, we refer to the low-power device roadmap described in the PIDS Chapter. It is almost certain that future low-power SOCs will integrate multiple (LOP, LSTP, HP) technologies simultaneously within the same core, to afford greater control of dynamic power, standby power, and performance.
Figure 10 shows the “bottom-up” lower bound for total chip power at an operating temperature of 100°C, assuming that all logic is implemented with LOP or LSTP devices and operates as described in Footnote 25. We say that this is a lower bound since in practice some logic would need to be implemented with faster, higher-current devices. The figure suggests that SOC-LP power levels will exceed the low-power requirements of the PDA application, and further provides a breakdown of power contributions for each case. As expected, LOP power is primarily due to standby power dissipation while LSTP power is primaril y due to dynamic power dissipation10. Total chip power using only LOP devices reaches 1.39 W in 2018, mostly due to a sharp rise in static power after 2012. Total chip power using only LSTP devices reaches 1.27 W in 2018; almost all of this is dynamic power.
Figure 10 Total Chip Power Trend for SOC-LP PDA Application
9 Ioff denotes the NMOSFET drain current at room temperature, and is the sum of the NMOS sub-threshold, gate, and junction leakage current components, as described in the PIDS chapter. Details of active capacitance density calculations, dependences on temperature and threshold, etc. may be found in the PIDS Chapter documentation and in the following supplemental file. The activity of logic blocks is fixed at 10%. The activity of memory blocks is estimated to be 0.4% based on the following analysis of large memory designs. We first assume that a memory cell contributes 2 gate capacitances of minimum size transistors for switching purposes, accounting for source/drain capacitances, contact capacitances and wiring capacitance along the bit li nes. A write access requires power in the row/column decoders, word line and M bit lines, sense amplifiers and output buffers. We consider memory to be addressed with 2N bits and assume that memory power is due primarily to the column capacitances, and that Mx2N bits are accessed simultaneously out of 2Nx2N possible bits. Then α=M/2N which is the ratio of accessed bit to total bits in the memory. For example, for a 16 Mbit memory, M=16 and N=12; hence α=0.4%. 10 At 25°C, dynamic power dissipation dominates the total power in both the LOP and LSTP cases.
Power Trend
0.00
0.20
0.40
0.60
0.80
1.00
1.20
1.40
1.60
2003 2006 2009 2012 2015 2018
Year
Po
we
r (W
)
- Dynamic Power LOP (W)
- Dynamic Power LSTP (W)
- Static Power LOP (W )
- Static Power LSTP (W)
- Memory Power LOP (W)
- Memory Power LSTP (W)
- Power for LOP Bottom-Up (W)
- Power for LSTP Bottom-Up (W )
Power Consumption
É power consumption model
αCVdd2f + IoffVdd
É necessary improvement of powermanagement (in 2016)É reduction by 20 for dynamic powerÉ reduction by 800 for standby power
É one possible direction: exploit parallelismÉ allows to decrease fÉ and thus decrease Vdd
SummaryÉ challenge of SoC design
É more complexÉ fasterÉ cheaperÉ more reliableÉ with lower power consumption
É how to handle the complexity?
ReferencesÉ International Technology Roadmap for
SemiconductorsÉ http://public.itrs.net/
É HiPEAC (European Network of Excellence onHigh Performance and Embedded Architectureand Compilation) RoadmapÉ http://wwww.hipeac.net/roadmap
É Winning the SoC RevolutionÉ Experiences in Real DesignÉ Edited by Grant Martin & Henry ChangÉ Kluwer Academic Publishers
Embedded System Design ChallengesDefinition and SignificanceSystem-on-Chip TodayMain Challenges on DesignSome AnswersOverview of the Course
Course Outline
É Embedded System Design Challenges (PierreBoulet), 21 sept
É Codesign (Jean-Luc Dekeyser), 5 octÉ DaRT (Jean-Luc Dekeyser), 12 octÉ Models of Computation (Pierre Boulet), 19 octÉ MARTE UML profile (Pierre Boulet), 26 octÉ SystemC Simulation (Jean-Luc Dekeyser et
Rabïe ben Atitallah), 2 novÉ Validation (Abdoulaye Gamatié), 9 novÉ Model Driven Engineering (Anne Étien), 16 novÉ Applications (Jean-Luc Dekeyser et Frédéric
Guyomarc’h), 23 novÉ VHDL Synthezis (Philippe Marquet), 30 nov
Course EvaluationÉ study of the research trends of some research
teamsÉ choice of the teamÉ first reportÉ refereeingÉ final report
É exam
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