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An Introduction to An Introduction to Programmable LogicProgrammable Logic
30 November 200430 November 2004
OutlineOutline
TransistorsTransistorsLogic GatesLogic GatesCPLD ArchitecturesCPLD ArchitecturesFPGA ArchitecturesFPGA ArchitecturesDevice ConsiderationsDevice ConsiderationsSoft Core ProcessorsSoft Core ProcessorsDesign ExampleDesign ExampleQuizQuiz
SemiconductorsSemiconductorsSemiconductors:Can be conductor OR insulator,located at boundary of the two
Insulators:Do not conduct electricity
Metals: Conduct electricity
Semiconductor PhysicsSemiconductor Physics
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Transistor Analog CharacteristicsTransistor Analog Characteristics Transistor SwitchTransistor Switch
Apply current here
And the switchis on!
ON
Fundamental Logic GatesFundamental Logic Gates Transistor Logic ImplementationTransistor Logic Implementation
NOT NAND
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Logic CombinationsLogic Combinations Basic Logic ExampleBasic Logic Example
ON
ON
OFF
ON
ON
ON
0 1
1
11
1
0
1
AND Gate AND Gate
Input
Output
All inputs must be a “1” or “On” in order to have an output of “1” or “On”
The FlipThe Flip--FlopFlop
DATA
CLOCK
OUTPUT
time
0
1
0
1
0
1
go! go!
transition A transition B
Logic Integrated CircuitsLogic Integrated CircuitsIntroduced in the late 60Introduced in the late 60’’ssMultiple gates in a single package!Multiple gates in a single package!Aliases: DTL, RTL, TTL, SSI, MSI, LSIAliases: DTL, RTL, TTL, SSI, MSI, LSIMajor players today: Philips, TI, NationalMajor players today: Philips, TI, NationalGives design flexibility to connect individual Gives design flexibility to connect individual ““chipschips”” off the off the shelf saving lots of timeshelf saving lots of time
4 - 50 gates
The black outlineis the IC package,this one 16 pin DualInline Package (DIP)
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Programmable Array Logic (PAL)Programmable Array Logic (PAL)
Developed in the late Developed in the late 7070’’ssMajor player today: Major player today: Lattice Lattice First device that First device that needs softwareneeds software
50 - 200 gates
interconnect gates flip flops
D Q
>
D Q
>
D Q
>
D Q
>
Programmable Logic DeviceProgrammable Logic Device
32-1024 macrocells
interconnect macrocellsDefinition:Definition:PAL*PAL*--derived derived programmable logic programmable logic devices that implement devices that implement logic as sumlogic as sum--ofof--products driving products driving macrocells. macrocells.
*Programmable Array Logic. Oldest practical form of programmable logic, implemented a sum-of-products plus optional output flip-flops.
AlteraAltera MAX MAX MacrocellMacrocell AlteraAltera MAX CPLD ArchitectureMAX CPLD Architecture
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AlteraAltera CPLDCPLD
I/O Elements (IOEs)
Macrocells
Internal Routing
LookLook--Up Table LogicUp Table Logic
Field Programmable Logic ArrayField Programmable Logic Array
2 types of FPGAs2 types of FPGAsReprogrammable (SRAMReprogrammable (SRAM--based)based)
Xilinx, Altera, Lattice, AtmelXilinx, Altera, Lattice, Atmel
OneOne--time Programmable time Programmable (OTP)(OTP)
Actel, QuicklogicActel, Quicklogic
gates flip flop
OTP logic cell
LUT flip flop
SRAM logic cell
0 1 1 0 01 0 1 1 01 1 0 0 10 0 0 1 11 0 1 0 01 1 1 1 1
AlteraAltera FPGA Logic Element (LE)FPGA Logic Element (LE)
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AlteraAltera FPGA InterconnectFPGA Interconnect AlteraAltera FPGA Memory BlockFPGA Memory Block
AlteraAltera FPGA Multiplier BlockFPGA Multiplier Block AlteraAltera FPGAFPGA
Logic ArrayBlocks (LABs)
M512 RAM Blocks
Phase-LockedLoops (PLLs)
DSP Blocks
M4K RAM Blocks
M-RAM Blocks
I/O Elements (IOEs)
Internal Routing
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Issues Issues -- InterconnectInterconnect
Method to hookMethod to hook--up gates inside a single deviceup gates inside a single deviceNeed to have enough to connect most gatesNeed to have enough to connect most gatesLarger gate counts result in bigger die size & Larger gate counts result in bigger die size & higher costhigher cost
gates
vertical interconnect
horizontalinterconnect
usedinterconnectpath
A
B
Issues Issues –– Input / OutputInput / Output
All signals on & All signals on & off chip must off chip must go through I/O go through I/O bufferbufferUser can User can choose many choose many I/O buffer I/O buffer optionsoptions silicon die
package pin
I/O bufferO
I
Issues Issues –– Propagation DelayPropagation Delay
Propagation Delay:Propagation Delay: The time required for a signal to travel The time required for a signal to travel from A to B, measured in nanoseconds (ns).from A to B, measured in nanoseconds (ns).
tPD = 3ns tPD = 1ns
Gate Delay Interconnect Delay
“A”“A” “B”
“B”
Issues Issues –– Path DelayPath Delay
Path Delay:Path Delay: The sum of all the gate and net delays The sum of all the gate and net delays from starting to ending point.from starting to ending point.
Path Delay “A” to “B” = sum of all gate + net delays3ns + 1.2ns + 3ns + 1.8ns + 3ns = 12ns
tPD = 1.8nstPD = 1.2ns tPD = 3nstPD = 3nstPD = 3ns
fanout=2
“A” “B”
“C”
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Issues Issues –– Maximum FrequencyMaximum FrequencyMaximum Frequency: Maximum Frequency: The fastest speed a circuit The fastest speed a circuit containing flipcontaining flip--flops can operate.flops can operate.
tPD = 0.5ns tPD = 2nstPD = 1.5ns
D Q
>
D Q
>
tPD = 1nstCQ = 2.5ns
D Q
>
D Q
>
tPD = 0.5ns
fMAX = 1/(flip-flop delay + gate delays + net delays)= 1/(2.5 + 1 + 1.5 + 0.5 + 2 + 0.5)ns= 125 MHz
Issues Issues –– Power ConsumptionPower ConsumptionPower = VCCINT x ICCINT + PEXT
CPLD versus FPGACPLD versus FPGA
CPLDCPLDLower PowerLower PowerLower DensityLower DensityLower SpeedLower Speed
FPGAFPGAHigher PowerHigher PowerHigher DensityHigher DensityHigher SpeedHigher Speed
System Partitioning YesterdaySystem Partitioning Yesterday
Backplane
Optical/Analog
ProcessorProcessor
ASSPO/E
O/EPLD
Logic
Processors
Memory
Analog
Serial BackplaneCommunication
Line-SideCommunication
Serial Chip-to-ChipCommunication
SRA
MSR
AM
Flas
h
DR
AM
DR
AMDSP
PLD
ASSP
ASSP
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FPGA Vendor Desired System FPGA Vendor Desired System TodayToday
Flas
h
DR
AM
DR
AM
O/E
O/E
Stratix
Backplane
Optical/Analog
Altera Logic Devices Now Perform Majority of System’s Digital Functions
NIOS II Processor CoreNIOS II Processor Core
NIOS II Processor ExampleNIOS II Processor Example FPGA DesignFPGA Design
Synthesis & Synthesis & Functional SimulationFunctional Simulation
Define Design Define Design FunctionalityFunctionality
SchematicSchematicHDLHDL
Optimize Design Optimize Design FunctionalityFunctionality
Functional Functional SimulationSimulation
Design Design VerificationVerification
Verify Design Verify Design FunctionalityFunctionalityVerify Verify PerformancePerformance
Timing Timing SimulationSimulation
Design EntryDesign EntryDesign EntryFunctional &
TimingVerification
Functional &Timing
Verification
Compilation− Convert to FPGA
resources− Place & Route
DesignImplementation
DesignImplementation
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Traffic Light DesignTraffic Light Design Traffic Light State DiagramTraffic Light State Diagram
EW Car Present /
Set 10 Second Timer
3 Se
cond
Tim
er E
xpire
d /
Set 1
0 Se
cond
Tim
er
3 Second Timer Expired
Design ExamplesDesign Examples
Hardware Based DesignHardware Based DesignImplemented Completely in Discrete LogicImplemented Completely in Discrete Logic
Soft Core Processor Based DesignSoft Core Processor Based DesignImplemented in SoftwareImplemented in SoftwareWith With MicroCMicroC/OS/OS--II RTOSII RTOS
Design ComparisonsDesign Comparisons
EasyEasyModerateModerateModification Modification EffortEffort
EasyEasyModerateModerateDesign EffortDesign Effort571,136571,13600MemoryMemory8800DSP BlocksDSP Blocks1111PLLsPLLs351635164848Logic ElementsLogic Elements
Processor Processor DesignDesign
Hardware Hardware DesignDesign
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Resource UsageResource Usage
Res
ourc
e U
sage
Quiz QuestionsQuiz QuestionsDoes a transistor functions as an insulator, a conductor or a swDoes a transistor functions as an insulator, a conductor or a switch?itch?
A switchA switchAre logic gates built with paper, plastic or transistors?Are logic gates built with paper, plastic or transistors?
TransistorsTransistorsName three fundamental logic gates?Name three fundamental logic gates?
And, Or and NotAnd, Or and NotWhat does FPGA stand for?What does FPGA stand for?
FField ield PProgrammable rogrammable GGate ate AArrayrrayWhat is a lookWhat is a look--up table?up table?
A memory block that is used to implement logic functionsA memory block that is used to implement logic functionsDefine the maximum frequency of an FPGA.Define the maximum frequency of an FPGA.
The highest clock frequency at which the FPGA can operate correcThe highest clock frequency at which the FPGA can operate correctlytlyWhat is a What is a ““Soft CoreSoft Core”” processor?processor?
A processor built using FPGA resources (e.g. gates, memory)A processor built using FPGA resources (e.g. gates, memory)How are VHDL and / or How are VHDL and / or VerilogVerilog used in FPGA design?used in FPGA design?
Simulation and Synthesis Simulation and Synthesis -- A subset of each language is synthesizable A subset of each language is synthesizable into logicinto logic
Quiz QuestionsQuiz QuestionsHow long does it take a lobster to grow to be 1lb?How long does it take a lobster to grow to be 1lb?
7 Years7 YearsHow much does a pelican consume in one meal?How much does a pelican consume in one meal?
About 1/3 of its body weightAbout 1/3 of its body weightHow fast can a grizzly bear run?How fast can a grizzly bear run?
About as fast as the average horseAbout as fast as the average horseWhen was the first million share trading day on the When was the first million share trading day on the NYSE?NYSE?
18861886What does a selenologist study?What does a selenologist study?
The MoonThe MoonWhat is the largest island in the world?What is the largest island in the world?
Greenland, at 840,000 square milesGreenland, at 840,000 square miles
Presentation Questions?Presentation Questions?
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