versatile link fpga-based bit-error-ratio tester for seu-hardened optical links csaba soos,...
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Versatile Link
FPGA-based Bit-Error-Ratio Testerfor SEU-hardened Optical Links
Csaba SOOS, Stéphane DETRAZ, Sérgio SILVA, Paulo MOREIRA, Spyridon PAPADOPOULOS, Ioannis PAPAKONSTANTINOU,
Christophe SIGAUD, Pavel STEJSKAL, Jan TROSKA
CERN, PH-ESE
Versatile LinkIntroduction
● Stringent requirements● High speed, low power, high reliability, long lifetime etc.
● Harsh environment● Noise, radiation etc.
● The answer: Versatile Link and GBT projects
Csaba Soos et al. 2TWEPP '09, 21-25 September, 2009
Versatile LinkChallenges (1/2)
● Amplitude noise● Low-swing signals => reduced SNR
● Phase noise, i.e. Jitter● Reduced bit period => less tolerance
Csaba Soos et al. 3TWEPP '09, 21-25 September, 2009
Receiver electrical signal Receiver electrical signal, when the opticalsignal is attenuated
Versatile LinkChallenges (2/2)
● Radiation effects● Single-Event Upsets in the photodiode and in the receiver
subassembly
● In the SEU dominated region, the BER is almost independent from the SNR
Csaba Soos et al. 4TWEPP '09, 21-25 September, 2009
Jan Troska et al., “Single-Event Upsets in Photodiodes for Multi-Gb/s Data Transmission”, TWEPP 2008, Naxos, Greece
Versatile LinkTest methods
● Eye diagram● Good qualitative measurement
● Difficult to predict the bit error rate
● Used for mask tests (standards)
● Bathtub curve● Links the jitter performance to
the bit error rate
● Ignores the amplitude noise
● Not precise at low bit error rate (extrapolation)
Csaba Soos et al. TWEPP '09, 21-25 September, 2009 5
Versatile LinkBit Error Rate testing
● Simple method for evaluating the performance of the entire transmission channel
● The measurement time depends on the required confidence level and the number of errors observed
TN
NBER
bits
err when ,
RBERkBERn
RBER
CLT
N
k
k
)!
)(ln(
)1ln( 0
Csaba Soos et al. 6TWEPP '09, 21-25 September, 2009
T – measurement timeBER – target bit error rateR – data rateCL – confidence leveln – number of transmitted bitsN – number of error bits
Versatile LinkMotivations to build a custom BERT
● Limitations of the oscilloscope● Sampling rate, memory, extrapolation, long measurement time
● We would like to use custom physical layer protocol (GBT)● It will allow us to study the performance of the protocol
● Standard BERT uses pseudo-random bit pattern
● We would like to carry out tests on multiple channels● It will reduce the overall test time
● Standard BERT can typically handle one channel at a time
● Error logging● Required for off-line analysis
● Limited in standard BERT equipments
Csaba Soos et al. TWEPP '09, 21-25 September, 2009 7
Versatile LinkBERT system architecture
PPC440
On-chipmemory
On-chipmemory
UART
BERTcore
PLB0
DUTGBT
RS232
Csaba Soos et al. 8TWEPP '09, 21-25 September, 2009
Crossbar
Externalmemory
PLB1
SoC implemented on the ML523 Virtex 5 transceiver evaluation platform
Versatile Link
Hig
h-s
pee
d S
eria
l4.
8 G
bit
/s
Bit Error Tester – Single Channel
GBT Encoder MGT TX
GBT Decoder MGT RX
Error inject
Compare
Compare
Generator
System errors
Line errors
GBT core Hard IP
Control
Csaba Soos et al. 9TWEPP '09, 21-25 September, 2009
DUT
Versatile LinkDevelopment platform
ML523 Virtex 5 transceiver evaluation platform featuring:
XC5VFX100T device- 8 GTX dual tiles- 16,000 slices- 256 DSP48E blocks- 8,208,000 bits internal memory
+128 MB DDR2 external memory
Csaba Soos et al. 10TWEPP '09, 21-25 September, 2009
Versatile LinkTest system
electrical opticalBERT
Clock source
Labview
J-BERTN4903A
Agilent8156A
Attenuator
Power meterAgilent8163B + 81635A
Csaba Soos et al. 11TWEPP '09, 21-25 September, 2009
Versatile LinkGraphical user interface - Labview
Csaba Soos et al. 12TWEPP '09, 21-25 September, 2009
Stop criteriaMeasurement settings Result plots
Log file path
Versatile LinkMeasurement flowchart
● To improve speed, measurements are started from the highest attenuation value
● If a channel cannot acquire lock, it will be masked
● Stop criteria: target BER, confidence factor, time
● Record values: BER bounds, confidence factor, time, average optical power
● The loop is finished, when we reach the target BER on all channels
Initialize
Set attenuation
Read counters
Stop criteria ?
Locked ?
Write log
End loop ?
Csaba Soos et al. 13TWEPP '09, 21-25 September, 2009
N
N
Y
Y
N
Y
start
end
Versatile LinkResults – System and Line BER
Csaba Soos et al. 14TWEPP '09, 21-25 September, 2009
Hig
h-s
pee
d
Ser
ial
4.8
Gb
it/s
GBT Encoder MGT TX
GBT Decoder MGT RX
Error inject
Compare
Compare
Generator
System errors
Line errors
GBT core Hard IP
Control
DUT
Versatile LinkFuture work
● Optimize the system for multi-channel readout● FPGA resource usage (clock network and PLLs)
● Labview script
● Implement advanced logging● Record erroneous words with timestamp
● Add support for multiple line rates● Dynamic reconfiguration of the multi-gigabit transceivers
● Prepare the system for the SEU tests
● Test components in radiation
Csaba Soos et al. 16TWEPP '09, 21-25 September, 2009
Versatile LinkConclusion
● Future, radiation-hard optical links will have to meet strict requirements
● The physical layer protocol will have to deal with the radiation induced errors (GBT)
● Bit-Error-Rate testing can be used to characterize the link components quantitatively
● Advanced testing (error logging) can provide insights into how error propagates in the system
● FPGA-based BERT system supporting the above mentioned features has been developed
● Link components are being tested in the lab, and will be tested soon (November 2009) in radiation
Csaba Soos et al. 17TWEPP '09, 21-25 September, 2009
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