vls i design

One Day National Conference on VLSI Design Architectures and

Applications

School of Electronics Engineeering (SENSE) VIT Chennai, India.

One day Pre Conference Workshop on Analog IC Design using Cadence

School of Electronics Engineeering (SENSE) VIT Chennai, India

ConvenersDr. T. Vigneswaran

Prof. P. Reenamonica

VIT - A place to learn; A chance to grow

REGISTRATION FEEConference :Industry/Faculty Participants : Rs. 1500/-Academicians/Research scholars &PG students : Rs.1000/-

Workshop :Industry/Faculty Participants : Rs. 1000/- Academicians/Research scholars &PG students : Rs.750/-

Registration Fee includes Proceedings, Courseware, Working Lunch and Tea.

Conference and workshop will have separate registration.

Interested Participants from Colleges, Industry and Research Institutes are requested to fill the registration form and send the same to Dr. T. Vigneswaran, Convener, NCVDAA 2014. Registration fee will be accepted by Demand Draft drawn in favour of VIT Chennai, payable at Chennai along with the completed registration form. Registration fee does not include accommodation charges.

DATES TO REMEMBERConference:Last date for receipt of papers : 25th March, 2014Acceptance intimation : 31st March, 2014Camera ready papers : 10th April, 2014

Workshop:

ORGANIZING SECRETARIESDr. V.S. Kanchana Bhaskaran, SENSE. VITCC.Dr. A.Ravisankar, SENSE. VITCC.Dr. Anith Nelleri, SENSE. VITCC.Dr. S.R.S. Prabaharan, SENSE. VITCC.Dr. R.Manojkumar, SENSE. VITCC.

VIT Chennai

VIT University for the past 25 years has made a mark in the field of higher education in India imparting quality education in a cross cultural ambience, intertwined with extensive application oriented research. Established by well-known educationalist and former parliamentarian, Dr. G Viswanathan, Founder and Chancellor is a visionary who transformed VIT into a center of excellence in higher technical education. His dream has taken the shape of VIT Chennai. Dr. V. Raju, Former Professor of State University of New York, USA, currently the Vice Chancellor, strives to internalize the world class educational standards. Dr. Anand A. Samuel, Pro-Vice Chancellor leads the team in Chennai with the following objectives:

To maximize the Industrial Connectivity To Create Centers of Excellence in niche areas of

research

To enrich technological and Managerial Human Capital nurtured in a multicultural ambience

To provide a common platform for the agglomeration of ideas of personnel from various walks of life for learning enrichment

To create opportunities and exploit the available resources to benefit industry/society

To encourage participation in the National Agenda of knowledge building

To foster International collaborations for mutual benefits in areas of research.

WORKSHOP

One day Pre Conference Workshop on Analog IC Design using Cadence

Organized

Prof. P. Manikandan Prof. S. Umadevi

and

Interested delegates can attend the workshop with prior registaration. The participants of the workshop will be given certificates.(limited to 50 seats as First come First Serve Basis)

18th April 2014Organized ByVLSI Division,

17th April 2014Organized by

One day Pre- workshop will be conducted by School of Electronics Engineering (SENSE) on 17-4-2014.

Last date of Registration : 10th April, 2014Acceptance intimation : 11th April, 2014

manikandan.p@vit.ac.in umadevi.s@vit.ac.in 8870702353 8939916003

ADDRESS FOR COMMUNICATIONDr. T.Vigneswaran Professor, VLSI Division,School of Electronics Engineering (SENSE) VIT Chennai, Vandalur - Kelambakkam Road Chennai - 600 127.Phone : 9884222629 / 9840837624Email id: vigneswaran.t@vit.ac.in

About SENSE

The School of Electronics Engineering was established for imparting state-of-the-art education, training and research in the field Electronics & Communication Engineering and allied areas. It offers B.Tech, M.Tech, MS (By Research) & Ph.D in the domains of ECE, VLSI Design & Embedded Systems .The expertise of faculty members includes VLSI, Communication, Embedded Systems & Signal Processing.

Conference Theme

The VLSI Design Architectures and Applications Conference serving as a forum for researchers and designers to present and discuss current topics in VLSI design, electronic design automation, embedded systems, and enabling technologies. It covers the entire spectrum of activities in the two vital areas of very large scale integration (VLSI) and embedded systems, which underpin the semiconductor industry

Workshop Theme

The objective of the program is to make the participants understand the key principles, concepts and techniques involved in analog IC design. The hands on training using CADENCE, an industry standard CAD tool, will help the participants to design analog IC components to meet the given specification.

Workshop Content

Design of CMOS OTA and its Applications

Basic & Differential OTA

Realization of resistors & Inductors using OTA

Realization of active R-C filters using OTA

Topics of interest include, but not limited to

Low Power VLSI.

Image/Signal Processing

Cryptography

Networking

Analog/Digital-Communication

Embedded Systems

MEMS/NEMS

NanoTechnology

NanoElectronics

Satellite Communication

Microwave Engineering

Robotics

Neural Networks

VLSI/DSP Architectures

Analog VLSI

Cellular/Mobile Communication

Design, Simulation and Test of Digital, Analog, Mixed Mode and RF Circuits and Systems

VLSI, ASIC, FPGA, MPSoC and SoC

Computer Aided Design and Electronic Design Automation

Circuits and Systems for Low Power Applications

Circuits and Systems for Cryptography

Route Map

One Day National Conference on VLSI Design Architectures and

Applications&

One day Pre Conference Workshop on Analog IC Design using Cadence

REGISTRATION FORMName : .............................................................................Designation : .............................................................................Organization : .............................................................................Address for Correspondence :...........................................................................................................

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PIN Code : .................................. Phone: ...........................E-mail : ............................................................................Registration For

a) Conference :

b) Workshop :

c) For Both :

PAYMENT DETAILS :Amount : .............................................................................DD No. : .................................. Date : ..............................(In favour of VIT Chennai payable at Chennai)Name of Bank & Branch :...........................................................................................................

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Date : Signature