zynq ultrascale+ rfsoc zcu208 and zcu216 rf data converter ...€¦ · the evaluation tool enables...
Post on 09-Oct-2020
12 Views
Preview:
TRANSCRIPT
Zynq UltraScale+ RFSoCZCU208 and ZCU216 RFData Converter EvaluationTool
User Guide
UG1433 (v1.1) June 23, 2020
Revision HistoryThe following table shows the revision history for this document.
Section Revision Summary06/23/2020 Version 1.1
General updates. Added ZCU208 board information throughout.
RF-ADC DDR Added information on dual RF-ADC tiles.
User Space Components Added note to refer to appendix.
Software Build Revised the steps for making the SD card images andcopying files to the SD card.
Appendix A: Software Design Notes — Multimaster Accessof CLK104 on TCA9548 Multiplexer Added appendix.
Appendix B: Command ListRemoved SetSignalDetector and GetSignalDetectorcommands. Revised description for RfclkWriteReg. AddedGetExtParentClkList, GetExtParentClkConfig, SetMMCMFin,GetMMCMFin, and GetMTS_Setup commands.
03/23/2020 Version 1.0
Initial release. N/A
Revision History
UG1433 (v1.1) June 23, 2020 www.xilinx.comRF Data Converter Evaluation Tool User Guide 2Send Feedback
Table of ContentsRevision History...............................................................................................................2
Chapter 1: Introduction.............................................................................................. 5
Chapter 2: Overview......................................................................................................6Installation................................................................................................................................... 7
Chapter 3: Hardware Design.................................................................................... 8Block RAM Generation and Capture......................................................................................... 9RF-DAC DDR............................................................................................................................... 10RF-ADC DDR............................................................................................................................... 10Clocking Scheme....................................................................................................................... 12
Chapter 4: Software Design and Build.............................................................. 14Software Architecture............................................................................................................... 14User Space Components.......................................................................................................... 15Kernel Space Components.......................................................................................................16Software Build............................................................................................................................17
Chapter 5: Protocol Specifications...................................................................... 19Protocol Overview..................................................................................................................... 19Protocol Rules............................................................................................................................ 20Socket Interface.........................................................................................................................21
Appendix A: Software Design Notes — Multimaster Access ofCLK104 on TCA9548 Multiplexer....................................................................... 22
Appendix B: Command List..................................................................................... 23
Appendix C: Additional Resources and Legal Notices............................. 30Xilinx Resources.........................................................................................................................30Documentation Navigator and Design Hubs.........................................................................30References..................................................................................................................................30
UG1433 (v1.1) June 23, 2020 www.xilinx.comRF Data Converter Evaluation Tool User Guide 3Send Feedback
Please Read: Important Legal Notices................................................................................... 31
UG1433 (v1.1) June 23, 2020 www.xilinx.comRF Data Converter Evaluation Tool User Guide 4Send Feedback
Chapter 1
IntroductionThe Zynq® UltraScale+™ RFSoC RF Data Converter (DC) Evaluation Tool and the ZCU208 andZCU216 Evaluation Kits are the ideal combination of evaluation software and test platform tofacilitate cutting edge application development. The evaluation tool can be used to jump startRF-class analog designs and to demonstrate the capabilities and excellent performance of theGen 3 RF data converters. Advantages of using this tool include acceleration of the productdesign cycle, reduction of product go-to-market expense, and quicker revenue realization.
Chapter 1: Introduction
UG1433 (v1.1) June 23, 2020 www.xilinx.comRF Data Converter Evaluation Tool User Guide 5Send Feedback
Chapter 2
OverviewThe evaluation tool enables control of the ZCU208 and ZCU216 RF DC IPs (see Zynq UltraScale+RFSoC RF Data Converter LogiCORE IP Product Guide (PG269)) and associated designs from a hostcomputer. The tool allows the exploration of RF configurations, generation and capture of RFdata, and observation of key RF metrics.
The following figure shows the evaluation tool and test platform overview.
Figure 1: Evaluation Tool and Test Platform Overview
X24062-062220
The tool is built from these components:
• ZCU208 Evaluation Board User Guide (UG1410)
• ZCU216 Evaluation Board User Guide (UG1390)
• FPGA hardware design (see Chapter 3: Hardware Design)
• FPGA embedded software design (see Chapter 4: Software Design and Build)
• GUI (see RF Data Converter Interface User Guide (UG1309))
Chapter 2: Overview
UG1433 (v1.1) June 23, 2020 www.xilinx.comRF Data Converter Evaluation Tool User Guide 6Send Feedback
• Protocol used to communicate between the host computer (GUI) and the software design (see Chapter 5: Protocol Specifications)
InstallationSee the RF DC Evaluation Tool for ZCU208 Board Quick Start or the RF DC Evaluation Tool forZCU216 Board Quick Start website for installation and folder structure information.
Chapter 2: Overview
UG1433 (v1.1) June 23, 2020 www.xilinx.comRF Data Converter Evaluation Tool User Guide 7Send Feedback
Chapter 3
Hardware DesignThe Vivado® Design Suite project used to build this programmable logic (PL) design is located inthe install directory in the pl folder. The hardware design architecture is based on the RFanalyzer architecture (see Zynq UltraScale+ RFSoC RF Data Converter LogiCORE IP Product Guide(PG269)). Notable additions to this architecture include:
• MicroBlaze™ is replaced by the Cortex™-A53
• PL DDR4 support, including DMA, AXI4-Stream broadcaster and switch, and GPIO control
• Clocking scheme to support DDR4 and multi-tile synchronization
• I2C connection to control external clocks (CLK104, see ZCU208 Evaluation Board User Guide(UG1410) and ZCU216 Evaluation Board User Guide (UG1390))
The following figure shows the high-level hardware architecture.
Chapter 3: Hardware Design
UG1433 (v1.1) June 23, 2020 www.xilinx.comRF Data Converter Evaluation Tool User Guide 8Send Feedback
Figure 2: High-level Hardware Architecture
M_AXIS_03M_AXIS_10M_AXIS_11M_AXIS_12M_AXIS_00M_AXIS_01M_AXIS_02M_AXIS_13
s00_0s01_0s02_0s03_0s10_0s11_0s12_0s13_0
user_select_00_0user_select_01_0user_select_02_0user_select_03_0user_select_10_0user_select_11_0user_select_12_0user_select_13_0
m00_0m01_0m02_0m03_0m10_0m11_0m12_0m13_0m20_0m21_0m22_0m23_0m30_0m31_0m32_0m33_0
S10_AXISS11_AXISS12_AXISS13_AXISS20_AXISS21_AXISS22_AXISS23_AXISS30_AXISS31_AXISS32_AXISS33_AXISS00_AXISS01_AXISS02_AXISS03_AXIS
DAC_DMA_DDR RF_Analyzer
ADC_DDR_DMA
Dout[0:0]Dout1[0:0]Dout2[0:0]Dout3[0:0]Dout4[0:0]Dout5[0:0]Dout6[0:0]Dout7[0:0]
GPIO_DDR_SWITCH
X23663-012320
Block RAM Generation and CaptureThe block RAM generation and capture are described in the "RF Analyzer" section in the ZynqUltraScale+ RFSoC RF Data Converter LogiCORE IP Product Guide (PG269).
Chapter 3: Hardware Design
UG1433 (v1.1) June 23, 2020 www.xilinx.comRF Data Converter Evaluation Tool User Guide 9Send Feedback
RF-DAC DDRA DDR4 memory controller (see UltraScale Architecture-Based FPGAs Memory IP LogiCORE IPProduct Guide (PG150)) is instantiated to control the external DDR4 memory. It connects to anAXI DMA controller (see AXI DMA LogiCORE IP Product Guide (PG021)). The waveform loadedinto the DDR4 memory is then broadcast to the RF-DAC tiles selected by the AXI GPIO (see AXIGPIO LogiCORE IP Product Guide (PG144)). The GPIO connects to the user_select input of theblock RAM generation and effectively bypasses this block when user_select is High.
For crossing clock domains, the broadcasting is done in two steps. The first step is part of theDDR clock domain and the second step is part of the RF-DAC tile clock domain. The RF-DACDDR block architecture is illustrated in the following figure.
Figure 3: RF-DAC DDR Block Architecture
S_AXIS
S_AXIS1
S_AXIS2
S_AXIS3
M00_AXIS
M01_AXIS
M02_AXIS
M03_AXIS
M00_AXIS1
M01_AXIS1
M02_AXIS1
M03_AXIS1
M00_AXIS2
M01_AXIS2
M02_AXIS2
M03_AXIS2
M00_AXIS3
M01_AXIS3
M02_AXIS3
M03_AXIS3
Broadcast_stg2
M_AXIS0
M_AXIS1
M_AXIS2
M_AXIS3
M_AXIS4
M_AXIS5
M_AXIS6
M_AXIS7
M_AXIS8
M_AXIS9
M_AXIS10
M_AXIS11
M_AXIS12
M_AXIS13
M_AXIS14
M_AXIS15
S_AXIS
S_AXIS1
S_AXIS2
S_AXIS3
M_AXIS
M_AXIS1
M_AXIS2
M_AXIS3
Clock_CrossingS_AXIS
M00_AXIS
M01_AXIS
M02_AXIS
M03_AXIS
axis_inter_dac_stg1
S01_AXI
S00_AXIM00_AXI
broadcast_interconnect
C0_DDR4_S_AXI
dbg_clk
dbg_bus[511:0]
c0_ddr4_ul_clk_sync_rst
ddr4_0
S_AX
I_LI
TE
M_A
XI_S
G
M_A
XI_M
M2S
M_A
XIS_
MM
2S
axi_
dma_
0
S_AXI_PS_DDR
S_AXI_DMA_CTRL
AXI SmartConect (Pre-Production) DDR4 SDRAM (MIG) (Pre-Production)
AXI4-Stream Broadcaster (Pre-Production)
AXI D
irect
Mem
ory
Acce
ss
(Pre
-Pro
duct
ion)
S_AXI_SG_DAC
X23664-012320
RF-ADC DDRA DDR4 memory controller (see UltraScale Architecture-Based FPGAs Memory IP LogiCORE IPProduct Guide (PG150)) is instantiated to control the external DDR4 memory. The RF-ADCoutput is duplicated on the output of the RF analyzer block RAM capture block. An AXI4-Streaminterconnect is then used as a switch to select which RF-ADC waveform is fed into the DMA andcaptured into the DDR memory. To allow the software to control the DMA accurately, a TLAST
Chapter 3: Hardware Design
UG1433 (v1.1) June 23, 2020 www.xilinx.comRF Data Converter Evaluation Tool User Guide 10Send Feedback
block is created. This block generates a TLAST pulse so that the DMA generates an interruptafter the correct number of samples. Because the dual RF-ADC tiles have two AXI4-Streamoutputs in I/Q mode, an AXI4-Stream combiner is used to write both streams in the DDRmemory. Consequently, the real mode cannot be used to capture the dual RF-ADC tiles in theDDR. The RF-ADC DDR block architecture is shown in the following figures.
Figure 4: RF-ADC DDR Block Architecture for Quad RF-ADC Tiles
S00_AXIS
S01_AXIS
S02_AXIS
S03_AXIS
S04_AXIS
S05_AXIS
S06_AXIS
S07_AXIS1
S08_AXIS2
S09_AXIS2
S10_AXIS2
S11_AXIS2
S12_AXIS3
S13_AXIS3
S14_AXIS3
S15_AXIS3
S_AXI_CTRL
axis_inter_adc
S_AXIS0
S_AXIS1
S_AXIS2
S_AXIS3
S_AXIS4
S_AXIS5
S_AXIS6
S_AXIS7
S_AXIS8
S_AXIS9
S_AXIS10
S_AXIS11
S_AXIS12
S_AXIS13
S_AXIS14
S_AXIS15
S_AXI_CTRL s_axis
s00_AXIm_axis
tlast_gen_v1_0_0
S_AXI_LITE
S_AXIS_S2MM
M_AXI_SG
M_AXI_S2MM
axi_dma_0
tlast_gen_v1_0(Pre-Production)
AXI Direct Memory Access) (Pre-Production)
S00_AXI
S01_AXIM00_AXI
smartconnect_0
C0_DDR4_S_AXI
dbg_clk
dbg_bus[511:0]
c0_ddr4_ul_clk_sync_rst
ddr4_adc
AXI SmartConect (Pre-Production) DDR4 SDRAM (MIG) (Pre-Production)
S00_ARB_REQ_SUPPRESS
S01_ARB_REQ_SUPPRESS
S02_ARB_REQ_SUPPRESS
S03_ARB_REQ_SUPPRESS
S04_ARB_REQ_SUPPRESS
S05_ARB_REQ_SUPPRESS
S06_ARB_REQ_SUPPRESS
S07_ARB_REQ_SUPPRESS
S08_ARB_REQ_SUPPRESS
S09_ARB_REQ_SUPPRESS
S10_ARB_REQ_SUPPRESS
S11_ARB_REQ_SUPPRESS
S12_ARB_REQ_SUPPRESS
S13_ARB_REQ_SUPPRESS
S14_ARB_REQ_SUPPRESS
S15_ARB_REQ_SUPPRESS
M00_AXIS S_AXI_SG_ADC
s_axi_dma_adc
s00_axi
s_axi_ps_adc_ddr
AXI4-Stream Interconnect (Pre-Production)
X23665-012320
Chapter 3: Hardware Design
UG1433 (v1.1) June 23, 2020 www.xilinx.comRF Data Converter Evaluation Tool User Guide 11Send Feedback
Figure 5: RF-ADC DDR Block Architecture for Dual RF-ADC Tiles
X23874-042220
Clocking SchemeThe clocking scheme is built to support both individual tile clocks and independent RF-ADC orRF-DAC multi-tile synchronization (MTS). Consequently, two of the typical clocking schemesfrom the Zynq UltraScale+ RFSoC RF Data Converter LogiCORE IP Product Guide (PG269) aremerged. The first clocking scheme uses the output of each tile to connect to a mixed-mode clockmanager (MMCM) or phase-locked loop (PLL), which gives an independent clock per tile. Thesecond clocking scheme supports MTS, takes its input from a fabric pin, and generates an outputfor the tiles selected by the MTS functions. BUFGMUX and MMCM dual input allows mergingthese two clocking schemes. For the RF-ADC, a mixture of MMCM and PLL are used. The RF-ADC clocking scheme figure shows a representation for two tiles. The RF-DAC clocking schemefigure shows a representation for two tiles. For the RF-DAC, only the MMCM is used. The pathused in the MTS case is shown in red.
Chapter 3: Hardware Design
UG1433 (v1.1) June 23, 2020 www.xilinx.comRF Data Converter Evaluation Tool User Guide 12Send Feedback
Figure 6: RF-ADC Clocking Scheme
PLL
Clk from Tile 1
BUFGM
UX
MMCM
Clk from Tile 0
BUFGM
UXClk from Pin
RF-ADC Tile 2
RF-ADC Tile 0
X23666-052820
Figure 7: RF-DAC Clocking Scheme
MMCM
Clk from Tile 1
MMCM
Clk from Tile 0
Clk from Pin
RF-DAC Tile 2
RF-DAC Tile 0
X23667-052820
Chapter 3: Hardware Design
UG1433 (v1.1) June 23, 2020 www.xilinx.comRF Data Converter Evaluation Tool User Guide 13Send Feedback
Chapter 4
Software Design and BuildThis chapter describes the software platform running on the application processing unit (APU),which is logically further subdivided into user and kernel space components (see Figure 8: APULinux Software Platform). The Linux application rftool in the user space receives the commandover the Ethernet and performs the appropriate action. This application is the main interface tothe GUI and uses a string-based communication protocol described in Chapter 5: ProtocolSpecifications. Device drivers expose a systematic interface to control hardware. Theseinterfaces are used by the user space application to control hardware.
All configurations of the RF-ADCs and RF-DACs are done by the Linux application rftool runningon the processing system (PS). The application supports all the configuration options supportedby the GUI. The GUI sends configuration details via the Ethernet interface to the Linuxapplication, which are implemented by their respective software APIs.
Software ArchitectureThe following figure shows the APU Linux software platform, which includes two logical softwareflows: the control path and the datapath. The control path and datapath are implemented usingtwo different TCP sockets. The components in the software flows are implemented in the userspace and the kernel space.
Chapter 4: Software Design and Build
UG1433 (v1.1) June 23, 2020 www.xilinx.comRF Data Converter Evaluation Tool User Guide 14Send Feedback
Figure 8: APU Linux Software Platform
RFDC GUIRemote machine
Rftool (Application)User space
Device Directory (/dev)
plmem
sysfs Directory (/sys)
gpio voltage mem_type
select_mem power_input1
Rfclk user space driver (Lmx2594/lmk04828)
driver
RFDC user
space driver
MMCM Control
Kernel space DMA client driver
DMAEngine
TCP/IPstack
AXI DMADriverGEM driver
lic driver UIO
Hardware
GEM I2C CLK104 GPIO Controller Memory RFDC IP
AXI Infrastructure AXI DMAs MMCM
Libmetal
X23668-031920
User Space ComponentsThe Linux user space components used are:
• The rftool is the Linux application that receives commands over the Ethernet from the PC GUIand performs appropriate actions.
Chapter 4: Software Design and Build
UG1433 (v1.1) June 23, 2020 www.xilinx.comRF Data Converter Evaluation Tool User Guide 15Send Feedback
• RFDC user space drivers provide APIs for communication with the RFDC hardware.
• RFCLK user space drivers provide APIs for communications with external CLK104 daughterboards.
Note: See Appendix A: Software Design Notes — Multimaster Access of CLK104 on TCA9548Multiplexer.
• DMA client driver interface /dev/pl_mem is used to allocate a buffer from the PL DDR, andis also used to trigger a DMA transaction from the user space.
Kernel Space ComponentsThe Linux kernel space components used are:
• The GEM driver provides the interface to send and receive packets over the GEM Ethernetcontroller.
• The TCP/IP stack provides the interface to create a transmission control protocol (TCP)socket. It also provides the interface to send and receive data over the TCP socket. The stackuses the GEM driver to send and receive packets from a network interface card (NIC).
• The DMA client driver provides the interface for a user application to trigger DMAtransactions.
• The AXI DMA driver and DMA engine provide a driver interface to the AXI DMA. The DMAclient driver uses APIs for this DMA engine. The DMA engine uses the AXI DMA driver tocontrol hardware.
• The libmetal driver is a kernel space driver that allows the execution of user space drivers.
• Userspace I/O (UIO) is a Linux framework used to export a hardware space to a user space. Itis used by the RFDC user space driver libmetal to configure RFDC hardware.
• MMCM control is reconfiguring the MMCM/PLL depending on tile clock requirement.
The following figure shows the application execution flow.
Chapter 4: Software Design and Build
UG1433 (v1.1) June 23, 2020 www.xilinx.comRF Data Converter Evaluation Tool User Guide 16Send Feedback
Figure 9: Application Execution Flow
GUI
TCP Socket(Command/Data)
Protocol Layer
Command Handler
DMA Client Driver I2C/Clock Driver RFDC User Space Driver MMCM Control
X23669-012820
Software BuildTo build the software, the board support package (BSP) and build tools are needed. For the tools,see the 2019.2 version of the PetaLinux Tools Documentation: PetaLinux Command Line Reference(UG1157)
1. Ensure the PetaLinux tools are available in the PATH environment variable.
2. To create the project, enter:
petalinux-create -t project -s <bsp> -n <project_name>
3. To build the project, enter:
cd <project_name>
petalinux-build -v
4. To make the images for the SD card, enter:
Chapter 4: Software Design and Build
UG1433 (v1.1) June 23, 2020 www.xilinx.comRF Data Converter Evaluation Tool User Guide 17Send Feedback
petalinux-package --force --boot --fsbl ./pre-built/linux/images/zynqmp_fsbl.elf --fpga ./images/linux/system.bit --pmufw ./pre-built/linux/images/pmufw.elf --u-boot ./images/linux/u-boot.elf
5. Copy these files to the SD card:
<project_name>/images/linux/BOOT.BIN
<project_name>/images/linux/image.ub
<project_name>/images/linux/boot.scr
autostart.sh (copy from the Externals\image\216 folder)
Chapter 4: Software Design and Build
UG1433 (v1.1) June 23, 2020 www.xilinx.comRF Data Converter Evaluation Tool User Guide 18Send Feedback
Chapter 5
Protocol Specifications
Protocol OverviewTo communicate between the host and the design, a simple but robust protocol is used. Thisprotocol is a string-based, space-separated command and response protocol. The state machineis represented in the following figure.
Figure 10: Finite State Machine Representing the Protocol
Get Command
Error
Execute
Parse Command Return
X23670-012320
Each command is sent in text (ASCII) format, parsed to check that the command is known andthe number of arguments is correct, and then executed. The design returns the command nameplus some parameters or the error type without any parameter if an error condition occurs. Thehost can get information on the error by using the getlog command, which reads the metal logbuffer (see Zynq UltraScale+ RFSoC RF Data Converter LogiCORE IP Product Guide (PG269)).
The command can be split into these categories.
Chapter 5: Protocol Specifications
UG1433 (v1.1) June 23, 2020 www.xilinx.comRF Data Converter Evaluation Tool User Guide 19Send Feedback
• RFDC commands are usually a direct translation of the RFDC driver with an addition of errorchecking when necessary
• PL design commands control the PL side of the design (MMCM, GPIO, capture and generationmemories, etc.)
• Board control commands control some of the board components such as external clocks
Protocol RulesThe full list of commands is provided in Appendix B: Command List.
The command syntax for input is:
• CMD PARAM1 PARAM2 PARAM3 (with any number of parameters)
• Commands and parameters are separated by an ASCII space
• Commands and parameters are human readable, i.e., sent in ASCII format
• Receive end of line is \n
The output return format is:
• If an input command is not recognized, the parser errors out and sends ERROR: CMD:Invalid Command\n
• If an input command is recognized, the parser checks the number of arguments, and sendsERROR: CMD: Invalid Number of Arguments\n
• If execution succeeds, the result is returned CMD param1 param2 ... paramX value1value2 ... valueY\n
• Commands that are not expected to return values return their name if execution succeeds:[CMD]
• CMD and values are separated by a space
• Receive end of line is \n
• Any log or messages from metal-log can be returned via the getlog command; the \r\ncharacters are replaced from any log messages with "|" and a single \n appended at the end
Chapter 5: Protocol Specifications
UG1433 (v1.1) June 23, 2020 www.xilinx.comRF Data Converter Evaluation Tool User Guide 20Send Feedback
Socket InterfaceThe TCP/IP socket protocol is used for the datapath and control path. The GUI running on thehost machine has TCP clients, and the TCP servers are running under the Linux application onthe Zynq UltraScale+ RFSoC PS. The control path works on TCP port 8081 and the datapathworks on TCP port 8082. The TCP socket uses a Linux TCP/IP stack, which uses the GEMEthernet controller and driver for sending packets. Because the TCP socket is used, it is possibleto run the GUI on any networked machines.
Chapter 5: Protocol Specifications
UG1433 (v1.1) June 23, 2020 www.xilinx.comRF Data Converter Evaluation Tool User Guide 21Send Feedback
Appendix A
Software Design Notes —Multimaster Access of CLK104 onTCA9548 Multiplexer
The TCA9548 multiplexer is shared between the I2C masters MSP430 and APU on the Gen 3RFSoC. The operation to select the CLK104 device on the multiplexer and read/write operationis completed in three steps in the I2C driver. When one master is accessing the device, the othermaster should not access it.
Appendix A: Software Design Notes — Multimaster Access of CLK104 on TCA9548Multiplexer
UG1433 (v1.1) June 23, 2020 www.xilinx.comRF Data Converter Evaluation Tool User Guide 22Send Feedback
Appendix B
Command ListThe commands supported by the evaluation tool are classified as basic commands, RFDC IPcommands, board control commands, and PL data and control commands. The following tablelists the supported commands.
Table 1: Command List
Command Input Parameters Output Parameters Description
Basic Commands
GUI_Title None Rftool VersionRftool version, forexample, “(RFEvalToolv1.8)”.
RfdcVersion None Version Number(s) RFdc API version.
Version None Rftool Version Rftool version.
TermMode Mode None
Switch between UImode (mode=0) andInteractive mode(mode=1). Interactivemode prints morestatus information tothe terminal andshould not be usedwith the evaluationtool GUI.
GetLog None Logged Strings
Uses metal_log toreturn any error,warning, orinformationalmessages returnedfrom the API orcommand interface.
JtagIdcode None Idcode Return the deviceJTAG IDCODE.
Help None None Print help oncommand interface.
Disconnect None None
RFDC IP Commands
GetBlockStatus Type, Tile, Block
Type, Tile, Block,BlockStatus.SamplingFreq,BlockStatus.AnalogDataPathStatus,BlockStatus.DigitalDataPathStatus,BlockStatus.DataPathClocksStatus,BlockStatus.IsFIFOFlagsAsserted,BlockStatus.IsFIFOFlagsEnabled
Cf. PG269
GetCalFreeze Tile, BlockTile, Block, CalFreezePtr.CalFrozen,CalFreezePtr.FreezeCalibration,CalFreezePtr.DisableFreezePin
Cf. PG269
GetCalibrationMode Tile, Block Tile, Block, CalibrationMode Cf. PG269
Appendix B: Command List
UG1433 (v1.1) June 23, 2020 www.xilinx.comRF Data Converter Evaluation Tool User Guide 23Send Feedback
Table 1: Command List (cont'd)
Command Input Parameters Output Parameters Description
GetClkDistribution Type, Tile
Type, Tile, SettingsPtr.PLLEnable,SettingsPtr.DivisionFactor,SettingsPtr.DistributedClock,DistStatusPtr.Enabled,DistStatusPtr.DistributionSource,DistStatusPtr.UpperBound,DistStatusPtr.LowerBound,DistStatusPtr.MaxDelay,DistStatusPtr.MinDelay,DistStatusPtr.IsDelayBalanced
Cf. PG269
GetClockSource Type, Tile Type, Tile, ClockSource Cf. PG269
GetCoarseDelaySettings Type, Tile, Block Type, Tile, Block, Settings.CoarseDelay,Settings.EventSource Cf. PG269
GetConnectedData Type, Tile, Block Type, Tile, Block, ConnectedIData,ConnectedQData Cf. PG269
GetDACCompMode Tile, Block Tile, Block, EnablePtr Cf. PG269
GetDataPathMode Tile, Block Tile, Block, Mode Cf. PG269
GetDecimationFactor Tile, Block Tile, Block, DecimationFactor Cf. PG269
GetDecoderMode Tile, Block Tile, Block, DecoderMode Cf. PG269
GetDither Tile, Block Tile, Block, Mode Cf. PG269
GetDSA Tile, Block Tile, Block, SettingsPtr.DisableRTS,SettingsPtr.Attenuation Cf. PG269
GetFabClkOutDiv Type, Tile Type, Tile, FabClkDiv Cf. PG269
GetFabRdVldWords Type, Tile, Block Type, Tile, Block, FabricDataRate Cf. PG269
GetFabWrVldWords Type, Tile, Block Type, Tile, Block, FabricDataRate Cf. PG269
GetFIFOStatus Type, Tile Type, Tile, enable Cf. PG269
GetIMRPassMode Tile, Block Tile, Block, Mode Cf. PG269
GetInterpolationFactor Tile, Block Tile, Block, InterpolationFactor Cf. PG269
GetIntrStatus Type, Tile, Block Type, Tile, Block, IntrStatus Cf. PG269
GetInvSincFIR Tile, Block Tile, Block, enable Cf. PG269
GetIPStatus None
IpStatus.DACTileStatus[Tile].IsEnabled,IpStatus.DACTileStatus[Tile].BlockStatusMask, IpStatus.DACTileStatus[Tile].TileState,IpStatus.DACTileStatus[Tile].PowerUpState,IpStatus.DACTileStatus[Tile].PLLState,IpStatus.ADCTileStatus[Tile].IsEnabled,IpStatus.ADCTileStatus[Tile].BlockStatusMask, IpStatus.ADCTileStatus[Tile].TileState,IpStatus.ADCTileStatus[Tile].PowerUpState, IpStatus.ADCTileStatus[Tile].PLLState,IpStatus.State
Cf. PG269
GetLinkCoupling Tile, Block Tile, Block, Mode Cf. PG269
GetMixerSettings Type, Tile, Block
Type, Tile, Block, Mixer_Settings.Freq,Mixer_Settings.PhaseOffset,Mixer_Settings.EventSource,Mixer_Settings.MixerType,Mixer_Settings.CoarseMixFreq,Mixer_Settings.MixerMode,Mixer_Settings.FineMixerScale
Cf. PG269
GetMTSEnable Type, Tile Type, Tile, enable Cf. PG269
GetNyquistZone Type, Tile, Block Type, Tile, Block, NyquistZone Cf. PG269
GetOutputCurr Tile, Block Tile, Block, OutputCurr Cf. PG269
Appendix B: Command List
UG1433 (v1.1) June 23, 2020 www.xilinx.comRF Data Converter Evaluation Tool User Guide 24Send Feedback
Table 1: Command List (cont'd)
Command Input Parameters Output Parameters Description
GetPLLConfig Type, Tile
Type, Tile, PLLSettings.Enabled,PLLSettings.RefClkFreq,PLLSettings.SampleRate,PLLSettings.RefClkDivider,PLLSettings.FeedbackDivider,PLLSettings.OutputDivider
Cf. PG269
GetPLLLockStatus Type, Tile Type, Tile, LockStatus Cf. PG269
GetQMCSettings Type, Tile, Block
Type, Tile, Block,QMC_Settings.GainCorrectionFactor,QMC_Settings.PhaseCorrectionFactor,QMC_Settings.EnablePhase,QMC_Settings.EnableGain,QMC_Settings.OffsetCorrectionFactor,QMC_Settings.EventSource
Cf. PG269
GetThresholdSettings Tile, Block
Tile, Block,ThresholdSettings.UpdateThreshold,ThresholdSettings.ThresholdMode[0],ThresholdSettings.ThresholdMode[1],ThresholdSettings.ThresholdAvgVal[0],ThresholdSettings.ThresholdAvgVal[1],ThresholdSettings.ThresholdUnderVal[0],ThresholdSettings.ThresholdUnderVal[1],ThresholdSettings.ThresholdOverVal[0],ThresholdSettings.ThresholdOverVal[1]
Cf. PG269
GetDACPower Board_id, Tile Board_id, Tile, value_1, value_2, value_3,value_4, value_5 Cf. PG269
IntrClr Type, Tile, Block, IntrMask None Cf. PG269
IntrDisable Type, Tile, Block, IntrMask None Cf. PG269
IntrEnable Type, Tile, Block, IntrMask None Cf. PG269
MTS_Sysref_Config Enable, dac_tiles, adc_tiles
DAC_Sync_Config.Target_Latency,DAC_Sync_Config.Offset[Tile],DAC_Sync_Config.Latency[Tile],DAC_Sync_Config.Marker_Delay,DAC_Sync_Config.SysRef_Enable,ADC_Sync_Config.Target_Latency,ADC_Sync_Config.Offset[Tile],ADC_Sync_Config.Latency[Tile],ADC_Sync_Config.Marker_Delay,ADC_Sync_Config.SysRef_Enable
Cf. PG269
MultiConverter_Init Type None Cf. PG269
MultiConverter_Sync Type, ADC_Sync_Config.Target_Latency/DAC_Sync_Config.Target_Latency, Tile
Sync_config.Target_Latency,Sync_config.Offset[Tile],Sync_config.Latency[Tile],Sync_config.Marker_Delay,Sync_config.SysRef_Enable
Cf. PG269
Reset Type, Tile None Cf. PG269
ResetNCOPhase Type, Tile, Block None Cf. PG269
RF_ReadReg16 Offset Value Cf. PG269
RF_ReadReg32 Offset Value Cf. PG269
RF_WriteReg16 Offset, Value None Cf. PG269
RF_WriteReg32 Offset, Value None Cf. PG269
SetCalFreeze Tile, Block, CalFreezePtr.FreezeCalibration,CalFreezePtr.DisableFreezePin None Cf. PG269
SetCalibrationMode Tile, Block, Calibration Mode None Cf. PG269
Appendix B: Command List
UG1433 (v1.1) June 23, 2020 www.xilinx.comRF Data Converter Evaluation Tool User Guide 25Send Feedback
Table 1: Command List (cont'd)
Command Input Parameters Output Parameters Description
SetClkDistribution
Distribution_Settings.DAC[Tile].SourceTileDistribution_Settings.DAC[Tile].PLLEnableDistribution_Settings.DAC[Tile].PLLSettings.RefClkFreqDistribution_Settings.DAC[Tile].PLLSettings.SampleRateDistribution_Settings.DAC[Tile].DivisionFactorDistribution_Settings.DAC[Tile].DistributedClockDistribution_Settings.ADC[Tile].SourceTileDistribution_Settings.ADC[Tile].PLLEnableDistribution_Settings.ADC[Tile].PLLSettings.RefClkFreqDistribution_Settings.ADC[Tile].PLLSettings.SampleRateDistribution_Settings.ADC[Tile].DivisionFactorDistribution_Settings.ADC[Tile].DistributedClock
None Cf. PG269
SetCoarseDelaySettings Type, Tile, Block, Settings.CoarseDelay,Settings.EventSource None Cf. PG269
SetDACPowerMode Board_id, Tile, Block, op_current Board_id, Tile, Block, op_current Cf. PG269
SetDACVOP Tile, Block, uACurrent None Cf. PG269
SetDataPathMode Tile, Block, Mode Tile, Block, Mode Cf. PG269
SetDecimationFactor Tile, Block, DecimationFactor None Cf. PG269
SetDecoderMode Tile, Block, DecoderMode None Cf. PG269
SetDither Tile, Block, Mode Tile, Block, Mode Cf. PG269
SetDSA Tile, Block, DisableRTS, Attenuation Tile, Block, Attenuation Cf. PG269
SetFabClkOutDiv Type, Tile, FabClkDiv None Cf. PG269
SetFabRdVldWords Tile, Block, FabricDataRate None Cf. PG269
SetFabWrVldWords Tile, Block, FabricDataRate None Cf. PG269
SetIMRPassMode Tile, Block, Mode Tile, Block, Mode Cf. PG269
SetInterpolationFactor Tile, Block, InterpolationFactor None Cf. PG269
SetInvSincFIR Tile, Block, enable None Cf. PG269
SetMixerSettings
Type, Tile, Block, Mixer_Settings.Freq,Mixer_Settings.PhaseOffset,Mixer_Settings.EventSource,Mixer_Settings.MixerType,Mixer_Settings.CoarseMixFreq,Mixer_Settings.MixerMode,Mixer_Settings.FineMixerScale
None Cf. PG269
SetMMCMReg Type, Tile, Mult, Mult_frac, Div, clkout0_div,clkout0_frac None Cf. PG269
SetNyquistZone Type, Tile, Block, NyquistZone None Cf. PG269
SetQMCSettings
Type, Tile, Block,QMC_Settings.EnablePhase,QMC_Settings.EnableGain,QMC_Settings.GainCorrectionFactor,QMC_Settings.PhaseCorrectionFactor,QMC_Settings.OffsetCorrectionFactor,QMC_Settings.EventSource
None Cf. PG269
Appendix B: Command List
UG1433 (v1.1) June 23, 2020 www.xilinx.comRF Data Converter Evaluation Tool User Guide 26Send Feedback
Table 1: Command List (cont'd)
Command Input Parameters Output Parameters Description
SetThresholdSettings
Tile, Block,ThresholdSettings.UpdateThreshold,ThresholdSettings.ThresholdMode[0],ThresholdSettings.ThresholdMode[1],ThresholdSettings.ThresholdAvgVal[0],ThresholdSettings.ThresholdAvgVal[1],ThresholdSettings.ThresholdUnderVal[0],ThresholdSettings.ThresholdUnderVal[1],ThresholdSettings.ThresholdOverVal[0],ThresholdSettings.ThresholdOverVal[1]
None Cf. PG269
SetupFIFO Type, Tile, Enable None Cf. PG269
Shutdown Type, Tile None Cf. PG269
StartUp Type, Tile None Cf. PG269
UpdateEvent Type, Tile, Block, Event None Cf. PG269
DynamicPLLConfig Type, Tile, Source, RefClkFreq,SamplingRate
RefClkDivider, FeedbackDivider,OutputDivider Cf. PG269
MultiBand Type, Tile, DigitalDataPathMask, DataType,DataConverterMask
Type, Tile, DigitalDataPathMask, DataType,DataConverterMask Cf. PG269
SetCalCoefficientsTile, Block, CalBlock, Coeffs.Coeff0,Coeffs.Coeff1, Coeffs.Coeff2, Coeffs.Coeff3,Coeffs.Coeff4, Coeffs.Coeff5, Coeffs.Coeff6,Coeffs.Coeff7
None Cf. PG269
GetCalCoefficients Tile, Block, CalBlockTile, Block, CalBlock, Coeffs.Coeff0,Coeffs.Coeff1, Coeffs.Coeff2, Coeffs.Coeff3,Coeffs.Coeff4, Coeffs.Coeff5, Coeffs.Coeff6,Coeffs.Coeff7
Cf. PG269
DisableCoefficientsOverride Tile, Block, CalBlock None Cf. PG269
SetDACCompMode Tile, Block, Enable Tile, Block, Enable Cf. PG269
GetEnabledInterrupts Type, Tile, Block Type, Tile, Block, IntrMask Cf. PG269
Board Control Commands
GetExtPllConfig Board_id, Pll_src Freq Return the currentfrequency of the LMX.
GetExtParentClkList Board_id LMK_FREQ_LIST[LMK_FREQ_NUM]Return a list offrequencies availablefor the LMK.
GetExtParentClkConfig Board_id LMKCurrentFreq Return the currentLMK frequency.
GetExtPllFreqList Board_id, Pll_srcADC_FREQ_LIST[LMX_ADC_NUM] orDAC_FREQ_LIST[LMX_DAC_NUM]depending on Pll_Src
Return a list ofallowed values for theLMX.
RfclkReadReg Board_id, chip_id, reg_addr Board_id, chip_id, reg_addr, data Read a register fromthe LMK/LMX.
RfclkWriteReg Board_id, chip_id, reg_addr, data Board_id, chip_id, reg_addr, data
Write a register fromthe LMK/LMX with thefollowing parameters:Board_id (always 0)chip_id ( 0 :PLL ADC, 1PLL DAC, 2: LMK)reg_addr (registeraddress from the TCSfile)data (data from theTCS file)
SetExtParentclk Board_id, freq Board_id, freqConfigure LMK clockwith requestedfrequency.
Appendix B: Command List
UG1433 (v1.1) June 23, 2020 www.xilinx.comRF Data Converter Evaluation Tool User Guide 27Send Feedback
Table 1: Command List (cont'd)
Command Input Parameters Output Parameters Description
SetExtPllClkRate Board_id, Pll_src, freq Board_id, Pll_Src, freqConfigure PLL (LMX)with requestedfrequency.
PL Data and Control Commands
GetMemtype Type, Tile MemtypeGet selected memorytype (block RAM orDDR).
SetLocalMemSample Type, Tile, Block, numsamples NoneSet the number ofsamples to begenerated orcaptured.
SetMemtype Type, Tile, mem_type Error code on failureSet memory type toDDR (0) or block RAM(1).
SetMMCM Type, Tile MMCM_Lock, Mult, Div, clkout0_div,Clk0DivFrac
Reconfigure theMMCM according tothe tile settings, block0 of this tile, and Fs.
MTS_Setup Type, Enable NoneSetup the clockingscheme for multi-tilesynchronizationfeature.
SetMMCMFin Type, Tile, Fplin MMCM_Lock, Mult, Div, clkout0_div,Clk0DivFrac
Reconfigure theMMCM based on tilesettings, block 0 ofthis tile, and Fplin(user fabric clockinput).
GetMMCMFin Type, Tile MMCMFinReturns the currentMMCM frequencyinput.
GetMTS_Setup Type Type Tile_MaskGet the currentclocking scheme forall tiles (standard orMTS).
GetMMCMReg Type, Tile Lock, Mult, MultFrac, Div, Clk0Div,Clk0DivFrac, Clk1Div
Get the MMCMsettings.
MMCM_Rst Type, Tile None Reset the MMCM.
LocalMemInfo TypeType, memBaseAddr, numTiles, numMem,memSize, numWords, mem_enable,mem_clksel
Get information onthe memory.
LocalMemTrigger Type, clksel, numsamples, rfdc_ch NoneTrigger the memorychannel according tothe mask rfdc_ch.
LocalMemAddr Type, Tile, Block Type, Tile, Block, Addr_I, Addr_QGet the memoryaddresses associatedwith the tile andblock.
WriteDataToMemory Tile, Block, number of bytes, interleavedpair None
In this case, thebuffer address isallocated by Linux(CMA pool) from PSDDR and firmwarewrites the data to thebuffer by readingdata from a socket.
Appendix B: Command List
UG1433 (v1.1) June 23, 2020 www.xilinx.comRF Data Converter Evaluation Tool User Guide 28Send Feedback
Table 1: Command List (cont'd)
Command Input Parameters Output Parameters Description
ReadDataFromMemory Tile, Block, number of bytes, interleavedpair None
In this case, thebuffer address isallocated by Linux(CMA pool) from PLDDR and firmwarereads the data fromthe buffer and sendsit to a socket. In thiscommand, thenumber of bytesshould be aligned to32.
Appendix B: Command List
UG1433 (v1.1) June 23, 2020 www.xilinx.comRF Data Converter Evaluation Tool User Guide 29Send Feedback
Appendix C
Additional Resources and LegalNotices
Xilinx ResourcesFor support resources such as Answers, Documentation, Downloads, and Forums, see XilinxSupport.
Documentation Navigator and Design HubsXilinx® Documentation Navigator (DocNav) provides access to Xilinx documents, videos, andsupport resources, which you can filter and search to find information. To open DocNav:
• From the Vivado® IDE, select Help → Documentation and Tutorials.
• On Windows, select Start → All Programs → Xilinx Design Tools → DocNav.
• At the Linux command prompt, enter docnav.
Xilinx Design Hubs provide links to documentation organized by design tasks and other topics,which you can use to learn key concepts and address frequently asked questions. To access theDesign Hubs:
• In DocNav, click the Design Hubs View tab.
• On the Xilinx website, see the Design Hubs page.
Note: For more information on DocNav, see the Documentation Navigator page on the Xilinx website.
ReferencesThese documents provide supplemental material useful with this guide:
Appendix C: Additional Resources and Legal Notices
UG1433 (v1.1) June 23, 2020 www.xilinx.comRF Data Converter Evaluation Tool User Guide 30Send Feedback
1. Zynq UltraScale+ RFSoC RF Data Converter LogiCORE IP Product Guide (PG269)
2. ZCU208 Evaluation Board User Guide (UG1410)
3. ZCU216 Evaluation Board User Guide (UG1390)
4. RF Data Converter Interface User Guide (UG1309)
5. UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150)
6. AXI DMA LogiCORE IP Product Guide (PG021)
7. AXI GPIO LogiCORE IP Product Guide (PG144)
Please Read: Important Legal NoticesThe information disclosed to you hereunder (the "Materials") is provided solely for the selectionand use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials aremade available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES ANDCONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TOWARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANYPARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, includingnegligence, or under any other theory of liability) for any loss or damage of any kind or naturerelated to, arising under, or in connection with, the Materials (including your use of theMaterials), including for any direct, indirect, special, incidental, or consequential loss or damage(including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of anyaction brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinxhad been advised of the possibility of the same. Xilinx assumes no obligation to correct anyerrors contained in the Materials or to notify you of updates to the Materials or to productspecifications. You may not reproduce, modify, distribute, or publicly display the Materialswithout prior written consent. Certain products are subject to the terms and conditions ofXilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms containedin a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe orfor use in any application requiring fail-safe performance; you assume sole risk and liability foruse of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which canbe viewed at https://www.xilinx.com/legal.htm#tos.
Copyright
© Copyright 2020 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, Kintex, Spartan, Versal, Virtex,Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the UnitedStates and other countries. AMBA, AMBA Designer, Arm, ARM1176JZ-S, CoreSight, Cortex,PrimeCell, Mali, and MPCore are trademarks of Arm Limited in the EU and other countries. Allother trademarks are the property of their respective owners.
Appendix C: Additional Resources and Legal Notices
UG1433 (v1.1) June 23, 2020 www.xilinx.comRF Data Converter Evaluation Tool User Guide 31Send Feedback
top related