an 577: recommended protocol configurations for stratix iv ... · recommended configuration to...

March 2011 Altera Corporation

AN-577-3.0 Application Note

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Recommended Protocol Configurationsfor Stratix IV GX FPGAs

The architecture of the Altera® Stratix® IV GX FPGA is designed to accommodate the widest range of protocol standards spread over multiple data rates and data rate ranges. This application note helps you implement the protocols shown in Table 1 using specific configurations of Stratix IV GX FPGAs with transceivers that are not shown in the ALTGX MegaWizard™ Plug-In Manager of Quartus® II software version 8.0 and later.

1 The protocol implementations shown in this application note are the recommended implementations. You have the freedom to implement these protocols in any other configurations appropriate to your specific custom implementations according to your system design constraints, requirements, or both.

1 The recommended configurations described in this application note are used by Altera to characterize the respective protocols.

f Detailed functional descriptions of all the blocks shown in the flow charts that follow are available in the Transceiver Architecture for Stratix IV Devices chapter in volume 2 of the Stratix IV Device Handbook.

Table 1. Protocol Configurations for Stratix IV GX FPGAs

Protocols Refer to

Fibre Channel “Recommended Configuration to Achieve Fibre Channel Protocol Implementation” on page 2

Interlaken “Recommended Configuration to Achieve Interlaken Protocol Implementation” on page 4

SF1-5.1 “Recommended Configuration to Achieve SFI-5.1 Protocol Implementation” on page 7

Gigabit-capable passive optical network (GPON) “Recommended Configuration to Achieve GPON Protocol Implementation” on page 9

Advanced switching interconnect (ASI) “Recommended Configuration to Achieve ASI Protocol Implementation” on page 11

Serial data converter (SDC) (JESD204) “Recommended Configuration to Achieve SDC (JESD204) Protocol Implementation” on page 13

SerialLite II “Recommended Configuration to Achieve SerialLite II Protocol Implementation” on page 15

Serial ATA (SATA) and Serial attached SCSI (SAS)

“Recommended Configuration to Achieve SATA and SAS Protocols Implementation” on page 16

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Recommended Configuration to Achieve Fibre Channel Protocol Implementation

Recommended Protocol Configurations for Stratix IV GX FPGAs March 2011 Altera Corporation


The Fibre Channel protocol manages the transfer of information between different entities within a storage area network (SAN) using a point-to-point link. Table 2 shows the four supported Fibre Channel specifications and their data rates.

Although dependent on the system requirements and data rate of the application, any one of the recommended configurations shown in Figure 1 can implement the Fibre Channel protocol in Stratix IV GX transceivers. To use the Fibre Channel protocol, you must add the 8B/10B encoder/decoder to the FPGA fabric.

Table 2. Fibre Channel Data Rates for Stratix IV GX Devices

Fibre Channel Specification Data Rate (Gbps)

FC-1 1.0625

FC-2 2.125

FC-4 4.25

FC-8 8.5


March 2011 Altera Corporation Recommended Protocol Configurations for Stratix IV GX FPGAs

Figure 1. Recommended Configurations to Implement the Fibre Channel Protocol in a Stratix IV GX FPGA

Note for Figure 1:

(1) FC-1 = 1.0625 Gbps, FC-2 = 2.125 Gbps, FC-4 = 4.25 Gbps, and FC-8=8.5 Gbps.

Word Aligner(Pattern Length)

Basic Double-Width20-bit PMA-PCSInterface Width

Disabled

8B/10BEncoder/Decoder

Rate Match FIFO

Byte SERDES

Byte Ordering

Stratix IV GX Configurations

Basic

SingleWidth

DoubleWidth

FunctionalModes

-

Low-Latency PCS

Disabled

Disabled

Disabled Enabled

Data Rate (Gbps)

Channel Bonding

Disabled Enabled

FPGA Fabric-Transceiver

Interface Width

--FPGA FabricTransceiver

Interface Frequency

FPGA FabricTransceiver

Interface Frequency(MHz)

53.125 for FC-1,106.25 for FC-2,212.5 for FC-4

26.5625 for FC-1,53.125 for FC-2,106.25 for FC-4

Configuration optionsfor Fibre Channel data rates

FC-1, FC-2, and FC-4

Basic Single-Width10-bit PMA-PCSInterface Width

Disabled

Enabled (Manual,7-bit, 10-bit)

Disabled

Disabled

Disabled Enabled

x1

Disabled Enabled

106.25 for FC-1,212.5 for FC-2

53.125 for FC-1,106.25 for FC-2

Configuration optionsfor Fibre Channel data rates

FC-1 and FC-2

Reference Clock(MHz)

53.125 - 531.25 @ FC-142.5 - 531.25 @ FC-285.0 - 680.0 @ FC-4

Disabled

20-bit

Disabled

Enabled

Enabled

FC-8 (1)

Enabled

40-bit

212.5 for FC-8

Configuration optionsfor Fibre Channel data rate

FC-8

425.0

DoubleWidth

20-bit10-bit8-bit 16-bit 16-bit

FC-1, FC-2, FC-4 (1)FC-1, FC-2 (1)

Functional Modes


53.125 - 531.25 @ FC-142.5 - 531.25 @ FC-2

x1 x1

Enabled (Manual,7-bit, 10-bit, 20-bit)

Enabled (Manual,7-bit, 10-bit, 20-bit)

40-bit20-bit20-bit10-bit

PMA-PCSInterface Width

Recommended Configuration to Achieve Interlaken Protocol Implementation



The Interlaken protocol is a serial protocol capable of achieving 10 Gbps to 100 Gbps throughput. Stratix IV GX FPGAs support an Interlaken data rate range of 3.125 Gbps to 6.5 Gbps.

This application note describes the recommended configuration for 24 Interlaken channels on one side of the device. In this configuration, all 24 transmitter channels are configured in Basic (PMA-Direct) double-width mode (Figure 2). All 24 receiver channels are also configured in Basic (PMA-Direct) double-width mode (Figure 3 on page 6).

This configuration requires two ALTGX instantiations:

1. Twenty-four Transmitter-only channels in Basic (PMA-Direct) double-width mode

2. Twenty-four Receiver-only channels in Basic (PMA-Direct) double-width mode



Figure 2. Recommended Configuration to Implement 24 Transmitter Channels in PMA-Direct Mode for the Interlaken Protocol in a Stratix IV GX FPGA


Basic (PMA-Direct)Double-Width

20-bit PMA-FPGA FabricInterface Width

Disabled


Rate Match FIFO

Byte SERDES

Byte Ordering


Basic

SingleWidth

FunctionalModes

8-bitPMA-PCS

Interface Width

Low-Latency PCS

Disabled

Disabled

Disabled

Disabled

Data Rate (Gbps) 3.125 - 6.5

Channel Bonding Up to x24

Disabled


Interface Width20-bit

FPGA Fabric -Transceiver

Interface Frequency



156.25 -325

PMADirect


62.5 - 625.0 @ 3.125 Gbps130.0 - 650.0 @ 6.5 Gbps

DoubleWidth

10-bit 16-bit 20-bit

FunctionalMode



Figure 3. Recommended Configuration to Implement 24 Receiver Channels in PMA-Direct Mode for the Interlaken Protocol in a Stratix IV GX FPGA


Basic (PMA-Direct)Double Width

20-bit PMA-FPGA Fabric Interface Width

Disabled


Rate Match FIFO

Byte SERDES

Byte Ordering


Basic

SingleWidth

FunctionalModes

20-bitPMA-PCS

Interface Width

Low-Latency PCS

Disabled

Disabled

Disabled

Disabled


Channel Bonding Disabled

Disabled




Interface Frequency



156.25 -325

PMADirect


62.5 - 625.0 @ 3.125 Gbps130.0 - 650.0 @ 6.5 Gbps

DoubleWidth

16-bit10-bit8-bit

FunctionalMode

Recommended Configuration to Achieve SFI-5.1 Protocol Implementation



The serializer/deserializer (SERDES) Framer Interface Level 5.1 (SFI-5.1) protocol is a serial protocol intended for 40-Gbps applications. The 40G solution comprises 16 data channels and one de-skew control channel, for a total of 17 channels. Stratix IV GX FPGAs support SFI-5.1 data rates from 2.488 Gbps to 3.125 Gbps. Figure 4 shows the recommended configuration to implement the SFI-5.1 protocol with 17 transceiver channels configured in Basic (PMA-Direct) double-width mode.



Figure 4. Recommended Configuration to Implement 17 Transceiver Channels for the SFI-5.1 Protocol in a Stratix IV GX FPGA

)

Basic (PMA-Direct)Double Width

16-bit PMA-FPGA Fabric Interface Width

Disabled

Rate Match FIFO

Byte SERDES

Byte Ordering

Basic

SingleWidth

20-bit

FunctionalModes


Disabled

Disabled

Disabled

Disabled

) 2.488 - 3.125



Low-Latency PCS

Channel Bonding x17

Disabled

-16-bit

--


Interface Width

FPGA FabricTransceiver

Interface Frequency



155.52 -195.3125

PMADirect

Data Rate (Gbps)


49.76 - 622.0 @ 2.488 Gbps62.50 - 625.0 @ 3.125 Gbps


DoubleWidth

16-bit10-bit8-bit

FunctionalMode

Recommended Configuration to Achieve GPON Protocol Implementation


Recommended Configuration to Achieve GPON Protocol ImplementationThe GPON protocol network provides optical fiber cabling and signals to the home and office using a point-to-multipoint scheme. Stratix IV GX FPGAs support GPON data rates of 155.52 Mbps, 622.08 Mbps, 1.24416 Gbps, and 2.48832 Gbps, with a reference clock of 155.52 MHz. The minimum supported data rate of Stratix IV GX FPGAs is 600 Mbps, so a 5x over-sampling factor is used for the GPON data rate of 155.52 Mbps, resulting in a data rate of 777.6 Mbps. Figure 5 shows the recommended configurations for implementing the GPON protocol in Stratix IV GX FPGAs.

Recommended Configuration to Achieve GPON Protocol Implementation


Figure 5. Recommended Configurations to Implement the GPON Protocol in a Stratix IV GX FPGA

Disabled


Basic

SingleWidth

16-bit 20-bit

Disabled

Disabled

Disabled

Disabled

1.24416- 2.48832

x1

DisabledByte Ordering


Interface Width


Interface Frequency



77.76,155.52

PMADirect

FunctionalModes


Data Rate Gbps)(

-Low-Latency PCS

Channel Bonding



Disabled

Disabled

Disabled

Disabled

Disabled

0.7776 - 1.24416

Disabled

8-bit

97.2,77.76,155.52

38.88 - 622.08 @ 777.6 Mbps31.104 - 622.08 @ 1.24416 Gbps

Configurationoptions for GPON

data rates 1.24416 Gbpsand 2.48832 Gbps

Configurationoptions for GPON

data rates 155.52 Mbps,622.08 Mbps, and 1.24416 Gbps


Rate Match FIFO


Byte SERDES

DoubleWidth

10-bit8-bit


31.104 - 622.08 @ 1.24416 Gbps49.76 - 622.08 @ 2.48832 Gbps

x1

16-bit

FunctionalModes

Recommended Configuration to Achieve ASI Protocol Implementation


Recommended Configuration to Achieve ASI Protocol ImplementationThe ASI protocol is a serial data-transmission protocol that carries an MPEG-2 video stream. Stratix IV GX FPGAs support an ASI data rate of 270 Mbps. The minimum supported data rate of Stratix IV GX FPGAs is 600 Mbps, so a 5x over-sampling factor is used for the ASI data rate of 270 Mbps, resulting in a data rate of 1.35 Gbps. Figure 6 shows the recommended configuration for implementing the ASI protocol in Stratix IV GX FPGAs.

Recommended Configuration to Achieve ASI Protocol Implementation


Figure 6. Recommended Configuration to Implement the ASI Protocol in a Stratix IV GX FPGA



Disabled


Rate Match FIFO

Byte SERDES

Byte Ordering


Basic

SingleWidth

20-bit

FunctionalModes


Low-Latency PCS

Enabled (Bit-slip,10-bit)

Disabled

Disabled

Disabled

Data Rate (Gbps) 1.35

Channel Bonding x1

Disabled




Interface Frequency



135

PMADirect


27.0 - 675.0

DoubleWidth

16-bit10-bit8-bit

FunctionalMode

Recommended Configuration to Achieve SDC (JESD204) Protocol Implementation



The SDC (JESD204) protocol follows JESD204, a JEDEC standard that enables a high-speed serial connection between analog-to-digital converters and logic devices using only a two-wire high-speed serial interface. Stratix IV GX FPGAs support an SDC (JESD204) data rate range of 312.5 Mbps to 3.125 Gbps. The minimum supported data rate of Stratix IV GX FPGAs is 600 Mbps, so a 5x over-sampling factor is used for the SDC (JESD204) data rate of 312.5 Mbps, resulting in a data rate of 1.5625 Gbps. Figure 7 shows the recommended configurations for implementing the SDC protocol in Stratix IV GX FPGAs.



Figure 7. Recommended Configurations to Implement the SDC (JESD204) Protocol in a Stratix IV GX FPGA



Rate Match FIFO

Byte SERDES

Byte Ordering


Basic

SingleWidth

DoubleWidth

20-bit

FunctionalModes


Low-Latency PCS

Data Rate (Gbps)

Channel Bonding


Interface Width


Interface Frequency



Configurationoption for SDC

data rate range of2.0 Gbps - 3.125 Gbps

Disabled

Enabled

Disabled

Enabled

2.0 - 3.125

Enabled

16-bit

100 -156.25

Configuration option for SDC

data rate range of312.5 Mbps- 2.0 Gbps


40.0 - 500.0 @ 2.0 gbps62.50 - 625.0 @ 3.125 gbps


Disabled

Enabled (Manual)

Enabled

Disabled

Disabled

1.5625 - 2.0

x1

Disabled

8-bit

156.25 -200

16-bit10-bit8-bit


31.25 - 625.0 @ 1.5625 Gbps40.0 - 500.0 @ 2.0 Gbps

x1

Enabled (Manual)

FunctionalModes

Recommended Configuration to Achieve SerialLite II Protocol Implementation


Recommended Configuration to Achieve SerialLite II Protocol Implementation

The SerialLite II protocol is a point-to-point communication protocol for data transmission over one or more lanes. The data rate of each lane can be between 622 Mbps and 6.375 Gbps. Figure 8 shows the recommended configurations for implementing the SerialLite II protocol in Stratix IV GX FPGAs.

Figure 8. Recommended Configurations to Implement the SerialLite II Protocol in a Stratix IV GX FPGA


Disabled

8B/10B Encoder /Decoder

Rate Match FIFO

Byte SerDes

Byte Ordering


Basic

SingleWidth

Double Width

FunctionalModes

8-bitPMA-PCSInterface Width

Low-Latency PCS

Enabled (Manual,10-bit and 20-bit)

Enabled

Enabled

Disabled


Channel Bonding

Disabled




Interface Frequency



50 - 187.5

Configurationoption for

SerialLite IIdata rate range of

2.0 Gbps - 3.75 Gbps

Disabled

Enabled

Disabled

Enabled

2.0 - 3.75

Disabled

16-bit

100 -187.5



622 Mbps - 2.0 Gbps


50.0 - 500.0 @ 1.0 Gbps75.0 - 600.0 @ 3.75 Gbps

40.0 - 500.0 @ 2.0 Gbps75.0 - 600.0 @ 3.75 Gbps

Disabled

Enabled(Manual, 10-bit)

Enabled

Disabled

Disabled

0.622 - 2.0

Disabled

8-bit

62.208 -200

31.1 - 622.08 @ 622 Mbps40.0 - 500.00 @ 2.0 Gbps



1.0 Gbps - 3.75 Gbps


Disabled

Enabled

Disabled

Enabled

3.75 - 6.375

x1

Disabled

32-bit

93.75 -159.375

75.0 - 600.0 @ 3.75 Gbps127.5 - 637.5 @ 6.375 Gbps



3.75 Gbps - 6.375 Gbps 10-bit 16-bit 20-bit




x1x1x1


Enabled (Manual,10-bit and 20-bit)

FunctionalModes

Recommended Configuration to Achieve SATA and SAS Protocols Implementation



SATA is a serial interface between the host bus adaptors and the mass storage devices, such as desktop class disk drives used in consumer PCs, workstations, and laptop computing applications. SAS is a serial interface between the host bus adaptors and the mass storage devices, such as enterprise class disk drives used in servers, disk arrays, and datacenter applications.

Table 3 lists the serial data rates supported by Altera’s Stratix IV GX devices.

Figure 9 shows the recommended configurations for implementing the SATA and SAS protocols in Stratix IV GX devices.

The two main requirements of SATA and SAS protocols, out-of-band signaling (OOB) and speed negotiation, are easily implemented in Stratix IV GX devices.

The OOB signaling required by SATA and SAS protocol’s COMINIT, COMWAKE, COMRESET, and COMSAS sequences require the transmitter to be in the electrical idle power save state and the receiver to detect these valid sequence signals on the link. These requirements are easily implemented in Stratix IV GX devices by using the tx_forceelecidle port on the transmitter-to-transmit electrical idles and the rx_signaldetect port on the receiver-to-detect sequence signal levels above a certain threshold level at the input of the Stratix IV GX receiver. You can set the rx_signaldetect threshold using the Quartus II software version 9.1 or later.

The speed negotiation of SATA and SAS protocols requires both the host and device to exchange aligns at the fastest data rate they can both support. This requirement is implemented by using the Stratix IV GX device’s capability to dynamically reconfigure data rates.

Table 3. Serial Data Rates for SATA and SAS Protocols in Stratix IV GX Devices

Protocol SATA (Gbps) SAS (Gbps)

Gen1 1.5 1.5

Gen1.1 — 3.0

Gen2 3.0 6.0

Gen3 6.0 —



Figure 9. Recommended Configurations to Implement the SATA and SAS Protocol in a Stratix IV GX FPGA



Rate Match FIFO

Byte SERDES

Byte Ordering


Basic

SingleWidth

FunctionalModes

20-bitPMA-PCSInterface Width

Low-Latency PCS

Data Rate (Gbps) 1.5

Channel Bonding


Interface Width


Interface Frequency

FPGA Fabric-Trasnceiver


150

Configuration option for

SATA/SASdata rate of3.0 Gbps



Disabled


Enabled

Disabled

Enabled

Disabled



Configuration option for


Disabled

Enabled

Disabled

Enabled

3.03.0

Disabled

75

60.0 - 600.0



Disabled

Disabled

75

Disabled

Enabled

Disabled

Enabled

Disabled

37.5

30.0 - 600.060.0 - 600.0

Disabled

Disabled

150150

Disabled

Enabled

Disabled

Enabled

1.5

Disabled

75

30.0 - 600.0

Disabled

Disabled

Disabled

Enabled

Disabled

Enabled

6.0

×1

Disabled

150

120.0 - 600.0



32-bit

DoubleWidth

16-bit10-bit8-bit





×1×1×1 ×1





32-bit16-bit16-bit 32-bit16-bit16-bit8-bit

FunctionalModes

Document Revision History


Document Revision HistoryTable 4 lists the revision history for this application note.

Table 4. Document Revision History

Date Version Changes

March 2011 3.0

■ Updated the “Recommended Configuration to Achieve Interlaken Protocol Implementation”, “Recommended Configuration to Achieve GPON Protocol Implementation”, and “Recommended Configuration to Achieve SATA and SAS Protocols Implementation” sections.

■ Updated Figure 1, Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Figure 7, Figure 8, and Figure 9.

■ Updated Table 2.

■ Added Table 3.

■ Removed Figure 4.

■ Converted to the new template.

■ Minor text edits.

December 2009 2.0 Added “Recommended Configuration to Achieve SATA and SAS Protocols Implementation” on page 17.

May 2009 1.0 Initial release.

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