an algorithmic analog to ditital converter for cmos … · · 2016-06-07an algorithmic analog to...

An algorithmic Analog to Ditital Converter forCMOS image sensors

Master’s Thesis Presentation

Deyan Dimitrov

Linkoping University

June 12, 2013

Deyan Dimitrov Linkoping University

An algorithmic Analog to Ditital Converter for CMOS image sensors

Outline

Analog readout schemes in CMOS Image Sensors (CIS)

General performance requirements from a column-parallel CISADC

The Algorithmic/Cyclic ADC architecture

A few explored MDAC configurations

The Cyclic ADC implementation

Designed ADC characterization and results

Some improvement ideas

Conclusion and possible future tasks



Introduction to image sensor readout

RO

WD

EC

OD

ER

ADC

Column Amplifiers/Sample and Hold

Column Multiplexers

Basic serial readout

0101 0101 0101 0101 0101 0101 0101 0101 0101 0101

RO

WD

EC

OD

ER

Local Memory and Drivers

to on-chip

processing

Basic parallel readout



A pixel (the device under read)

Main pixel parameters coupled toADC requirements:

Output range

Integration (exposure) time

Reset time

Dark Noise

PSRR

A photogate-based active pixel

VDD

p+

TXPG

Vreset

Vword

nn

out



Requirements over column-parallel CIS ADCs

Integral Non-Linearity - random uniform (8-bit image)

±1 LSB ±8 LSB

For visible spectrum, human eye starts recognizing distortionbeyond 6-7% INL



Requirements over column-parallel CIS ADCs cont’d

Differential Non-Linearity - random single missing codes overthe whole range (up-to 1 code from stair-to-stair)

Reference Image Random missing codes

Even if ±1 LSB, artifacts become visible to the eye.




Column ADC mismatch fixed-pattern noise effect (8-bitimage), pattern used ∆rand1 , ∆rand2 , ∆rand3 ...

±2 LSB ±16 LSB




Full-scale step-response

Out of range recovery

Random noise

Conversion speed:

τconv <≈1

Hfs

Nmencds− Nme

τpixres + τpixsig

2(1)

Power consumption, typically: 100 ÷ 500 µW

Resolution: 8 (very high speed imagers) ÷ 14 bits



The Algorithmic/Cyclic ADC architecture

Why cyclic?

Sub-AD

φin

MDAC

RSD [1 :0]

WORDOUT [12 :0]

vAnalogIn

φcycle

x2

analog input

digitized analog signal

residual signal

Sub-DA

partial result

iteration loop

RSD to BIN Logic

A functional block diagram of a RSD Cyclic ADC



The Algorithmic/Cyclic ADC architecture cont’d

The RSD error correction scheme

”10””01””00”

VinVin

VoutVout

offset

clipped output

Vref

1

4Vref

3

4Vref

offset

”1””0”

only offsets over 7

8and below

1

8will not be corrected

A comparative example between RSD and conventional ADC stages

Allows for Sub-AD comparator online offset error correctionduring each consecutive iteration (cycle)



A few explored MDAC configurations

Advantages/Disadvantages:

⊕ Offset cancellation

⊕ Parasitic insensitive

Amplifier BW limited

Matching dependent

The ”flip-around” MDACarchitecture

Cf

Cs

φ1

φ2

φ1

φ1

Vr(0,±Vref )

Vin

Vout

φ2

virtual ground



A few explored MDAC configurations cont’d

Advantages/Disadvantages:

⊕ Non-OP-BW limited (φ1)

⊕ Allows OP re-use at φ1

No offset cancellation

Matching dependent

The ”modified flip-around”MDAC architecture

Cf

Cs

φ1

φ2

φ1

Vr(0,±Vref )

Vin

φ2

Vout

φ1 φ1

More popular than the previous due to OP BW independence




The cap-stacking concept

2Vin

q = CVin

VinVin

q = CVin

Vin

Cparasitic

An SC integrator - multiply by nstructure

Vout

Cf

Cs

φ1

φ1

φ2

φ2

Vin

Opamp high gain requirement

Accumulates offset

Parasitic sensitive




A MDAC with integrated analog CDS

C2

C5

C1

C3

C6

C4

Vref+

Vsig

Signal sampling

C2

C3

C6

Vref− C5

C1

C4

Vreset

Reset sampling

C1

C3

C6

C4

C2

C5

Vref+

Vref−

φ3 φ4

within range

to comparators

to comparators

over-range

under-range

Feedback andamplification

High complexity, non-trivial to design

”Bulky” design, multiple switches, phases, capacitors



Preliminary followed ADC design specifications

Parameter Value Unit

Resolution 12 bitsSampling rate > 130 kSpsIntegral Non-Linearity < 10 LSBDifferential Non-Linearity < 0.5 LSBPower consumption < 300 µWSupply voltage 3.3 ±10% VProcess node 0.18 µmArea - µm

Main ADC specifications followed during the design study



The implemented Cyclic ADC

C1a

Vcom

C2

C1b

VRH

VRL

VcomφM

φN

φP

φSD φ1D

φINIT

φ0

φS

φ2

φ1

VIN

to comparators

Principal schematic diagram of the cyclic core-architecture, as proposedby Jong-Ho Park et. al.



The implemented Cyclic ADC cont’d

OTA requirements

DC Gain: > 84 dB

ωug : > 10 MHz

PSRR: > 40 dB

Offset: ALAP

Noise: < 200 µV 2 at BWrange

Power: 30 ÷ 50 µW

Input and output ranges >pixel range

Possible candidates

Telescopic OTA

Current mirror OTA

Folded cascode OTA

Two stage OTA




VDD VDD VDD VDD

M8M7

M12

M10

M1 M2

M3 M4

VINnVoutVINp

CL

Ibias

1 : BB : 1

M11

M5 M6

M9

Vbias

Vbias Vbias

Vbias

The implemented current mirror OTA architecture




Comparator requirements

Input offset:±1

8 (VRH − VRL)

Response time: < 500 ns

Resolution: > 400 µV

Noise variance: < Inputoffset

Kickback noise: < left OTArecover time

Power: < 10 µW

Explored candidates

Static latched comparator

A Class AB latchedcomparator

A fully dynamic latchedcomparator




VDDVDD VDDVDD VDD VDD

Vlat

M′

7

Vlat

M′′

7

M′

1M

′

2M

′′

1M

′′

2

VPHVINp

VPLVNL

VOPH

M′

3

Vlat Vlat

M′′

4

M′′

6M

′′

8

Vlat Vlat

VONL

M′′′

3

M′′′

5M

′′′

6M

′′′

8M

′′′

11M

′′′

10

Vlat Vlat

M′′′

4M

′

4

M′

10M

′

8M

′

5M

′

6M

′

9M

′

11

M′′

3

M′′

10M

′′

5M

′′

9M

′′

11M

′′′

9

VONHVOPL

VOPMVONM

A principal schematic diagram of the implemented Sub-AD comparators




Switch requirements

Input range: VRL ÷ VRH +margin

Ron: to achieve a reasonablesettling-time

Charge injection: at MSBcycle < VLSB distortion

Explored candidates

Clock-boosted techniques

A Bootstrapped switchtechnique

A transmission-gate basedswitch




∆

C1a

Vcom

C2

C1b

VRH

VRL

VcomφM

φN

φP

φSD φ1D

φINIT

φ0

φS

φ2

φ1

VIN

to comparators

LA

LA

LA

∆

φ1

φ1D

φ2

Vgp

Vgn

Vin

holes

electrons

Vout

A clarification of the considered accuracy-critical switch nodes



Some improvement ideas

Two capacitor mismatch effect reduction techniques:

Even-odd fashion cap flipping

σmm =C1

C2

− 1 (2)

σgainp,n = G ± Gσmm (3)

Sflipping =∑

i=1≤k≤i,odd

12k σgainp + (4)

∑i=1≤k≤i,even

12k σgainn (5)

Snon−flipping =k∑1

12k σgainp (6)

Capacitor flipping switch networkchanges for the current MDAC

C1a

C1b

Vcom

Vcom

φ2

φ1

C2a

C2b

φf φf

φs φs

φs φs

φf φf

φf φf

φs φs

φs φs

φf φf

DAC

Cap flipping MDAC modifications



Some improvement ideas cont’d

Pseudo cap-flipping

Flip caps once after MSBhas been resolved (cycle 1)

Spc =1

2σgainx +

∑i=2≤k≤i

1

2kσgainy (7)

σredpc =

(Spc

Snon−pc

− 1

).100 (8)

Capacitor flipping switch networkchanges for the current MDAC

Err

orre

du

ctio

n,

[%]

Converter resolution/cycles, bits

5.5

5.0

4.5

4.0

3.5

3.0

2.50 2 4 6 8 10 12 14 16

with pseudo-calibration

even-odd basis cap flipping

A comparative error reduction progress between theeven-odd capacitor flipping technique and the proposedpseudo-calibration flipping method. C1=500 fF, C2=487fF



Designed ADC characterization and results

Static linearity tests (no capacitor mismatch)

INL

Dev

inL

SB

1.5

1

0.5

0

−0.5

−1

−1.5

−2

−2.5

−3

−3.5

Code0 500 1000 1500 2000 2500 3000 3500 4000 4500

Simulated Integral Non-Linearity, worst case processcorner, 3V3, 70 ℃, transient noise included

DNL

Dev

inL

SB

Code

1

0.8

0.6

0.4

0.2

0

−0.2

−0.4

−0.6

−0.8

−10 500 1000 1500 2000 2500 3000 3500 4000 4500

Simulated Differential Non-Linearity, worst case processcorner, 3V3, 70 ℃, transient noise included



Designed ADC characterization and results cont’d

Summarized results

Parameter Value Unit

Technology UMC 0.18µm G-02-MIXEDMODE/RFCMOS18-1.8V/3.3V-1P6M

-

Resolution 12 bits

Sampling Rate < 150 kSps

Input Voltage Range 1.35 (1 ÷ 2.35) V

Integral Non-Linearity 1 +1.5/-3.5 LSB

Differential Non-Linearity 2 ±0.8 LSB

Random Noise 3 367 µV

Power Supply, TYP 3.3 V

Power Consumption core @ 3V3, 70 ℃, TYP 72 µW

Power Consumption core+logic @ 3V3, 70 ℃, TYP 193 µW

Energy per Conversion Cycle @ 3V3, 70 ℃, TYP 15.4 µJ

Reference Voltage H 2.35 V

Reference Voltage L 1.00 V

1Integral Non-Linearity measured without capacitor mismatch at worst case corner

2Differential Non-Linearity measured without capacitor mismatch at worst case corner

3Based on a 1500 sample transient noise (5 Hz - 200 MHz) runs, measured in the middle of the input range



Conclusion and possible future tasks

An analysis on the architectural choice was performed, allbasic ADC core component requirements were identified.

A few MDAC architectures have been explored and a choice,transistor-level design and verification was conducted.

Three comparator architectures were explored, a comparativeanalysis between the latter was performed. A transistor-levelSub-ADC was designed.

Two capacitor mismatch error improvement schemes wereexplored.



Conclusion and possible future tasks cont’d

More component optimization and verification has to be done- design is by far not tape-out ready.

No parasitic estimations have been made. Layout andpost-layout verification is necessary after settling.

An RTZ coding signal feedback may be a relevant feature toimplement, with this SE MDAC design.

It may be wiser to change the Sub-ADC interpolativearchitecture.

Capacitor flipping schemes appear very relevant to investigatefor this application.

Simplified digital background calibration schemes are worthchecking-out.



an algorithmic analog to ditital converter for cmos … · · 2016-06-07an algorithmic analog to...

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