1

Abstract— This paper presents a chipset including an asymmetrical QPSK/OOK transceiver

SoC and a JPEG image encoder for wireless capsule endoscopy. The transceiver SoC

supports bi-directional telemetry for high data-rate image transmission with QPSK

modulation and low data-rate command link with OOK modulation. A low power JPEG

encoder is designed to compress raw image data with compression ratio as high as 15:1 using

sub-sampling technique in YUV color plane. Implemented in 0.18 µm CMOS, the QPSK TX

consumes 5 mW at –6 dBm of output power with 3 Mb/s data rate while the OOK RX

achieves –65 dBm of sensitivity at 500 kb/s data rate with 4.5 mW power consumption. A

prototype capsule has been implemented with the chipset and the performance has been

verified with in vivo animal experiment. With duty cycling, the average power consumption

of TX is 2.5 mW when transmitting at 3 fps frame rate.

Index Terms— Wireless capsule endoscopy (WCE), transceiver, quadrature phase-shift

keying (QPSK), OOK, JPEG

An Asymmetrical QPSK/OOK Transceiver SoC and 15:1 JPEG Encoder IC for Multifunction Wireless

Capsule Endoscopy

Yuan Gao, Member, IEEE, San-Jeow Cheng, Member, IEEE, Wei-Da Toh, Yuen-Sam Kwok, Kay-Chuan Benny Tan, Xi Chen, Wai-Meng Mok, Htun-Htun Win, Bin Zhao, Shengxi Diao,

Cabuk Alper, Member, IEEE, Yuanjin Zheng, Member, IEEE, Sumei Sun, Member, IEEE, Minkyu Je, Senior Member, IEEE and Chun-Huat Heng, Senior Member, IEEE

2

Correspondence: Yuan Gao Integrated Circuits & Sys. Lab Institute of Microelectronics A*STAR, Singapore 11 Science Park Road, Singapore Science Park II Singapore 117685. Tel: +65-67705462 gaoy@ime.a-star.edu.sg

Minkyu Je Integrated Circuits & Sys. Lab Institute of Microelectronics A*STAR, Singapore 11 Science Park Road, Singapore Science Park II Singapore 117685. Tel: +65-67705507 jemk@ime.a-star.edu.sg

Chun-Huat Heng Department of ECE, National University of Singapore 4 Engineering Drive 3, Singapore 117576. Tel: +65-6516-1628 Fax: +65-6516-8890 elehch@nus.edu.sg

3

I. INTRODUCTION

Wireless capsule endoscopy (WCE) is an emerging diagnostic tool to provide patient-friendly

inspection of gastrointestinal (GI) tract [1]. A typical WCE consists of a camera with an

illumination source, a wireless telemetry module and a battery pack which are miniaturized to fit

into a pill-size capsule made of biocompatible materials. As shown in Fig. 1, after a patient

swallows the WCE, the camera captures the images of the GI tract as the capsule passes through

with normal peristalsis. These images are transmitted to an external receiver (RX) worn by the

patient through wireless telemetry and then uploaded to a data server where a doctor can then

review and analyze the images. Since the disposable WCE is easy to swallow and can be expelled

out naturally, sedation or anesthesia requirement can be avoided. This minimizes patients’

discomfort associated with conventional endoscopy procedures and improves their experiences.

The primary application of WCE is to examine areas of small intestine which are difficult to access

with conventional endoscopy. It has been proven that the WCE is able to provide useful

information about small intestinal bleeding and tumors [2–4]. Since the first WCE approved by the

U.S. Food and Drug Administration (FDA) in 2001, more than 1 million patients worldwide have

benefited from such devices.

The major performance specifications of a WCE include image resolution, image frame rate and

system power consumption. Since battery capacity is limited by the capsule size and the system is

required to work 8–10 hours to allow the capsule pass through small intestine [5], current

commercial WCEs usually adopt QVGA (256×256) image resolution with 2 frames per second

(fps) refresh rate and one-way wireless telemetry from the capsule to the base station (BS) [6, 7].

However, high-resolution images are always preferred by doctors to obtain more accurate

4

diagnosis. Higher frame rate is also required in certain portion of GI tract to avoid the missed

detection of lesion location. These requirements pose significant design challenges to RF

transmitter (TX) design. As an example, given image color depth of 8 bits per pixel, standard VGA

resolution of 640×480 and frame rate of 10 fps, the raw image data transmission without any

image compression will exceed 25 Mb/s considering minimal baseband coding overhead. Such a

large amount of image data transmission demands energy-efficient on-chip image compression as

well as energy-efficient high data-rate RF transmission. From a system-level perspective, the

image compression helps reducing the transmitted data bandwidth requirement. Coupled with an

energy-efficient high data-rate TX, burst-mode transmission with heavy duty cycling can be

employed to reduce the system power significantly. Potentially, the combined techniques also

allow energy-efficient transmission of images with even higher resolution (SVGA, SXGA or HD)

and higher frame rate. Several image compression modules for WCE have been reported [8–11]. It

often involves trade-off among power consumption, compression ratio and image quality. Our

earlier works in [12, 13] also showed the feasibility of the energy-efficient high data rate TX.

However, it was tested without integrated reference frequency generation, and hence its

performance with a practical on-chip crystal oscillator in terms of energy efficiency and phase

noise performance needs further evaluation. Besides the high data-rate uplink mentioned above,

the recent advancement of microelectromechanical systems (MEMS) and actuator technologies

has enabled novel diagnostic and therapeutic functions within WCE. Novel integrated actuators

have been developed for locomotion, lesion localization or drug delivery [14–16]. Such functions

would require a reliable low data-rate downlink from the BS to the capsule. Hence, an

energy-efficient bi-directional wireless communication system together with an image

compression module is critical for the next-generation multifunction WCE.

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In this paper, a chipset including an asymmetrical quadrature phase-shift keying/on-off keying

(QPSK/OOK) RF transceiver system on chip (SoC) and a low power JPEG encoder for the next

generation multifunctional WCE is presented. An energy-efficient high data-rate QPSK TX with

an integrated on-chip crystal oscillator is employed for the uplink whereas an energy-efficient low

data-rate OOK RX is incorporated for the downlink. A low-power JPEG encoder IC using

sub-sampling technique in YUV color plane and pipelining is also designed to achieve

high-quality image transmission with high compression ratio. A part of this work has been

presented in [17]. In this paper, the system considerations and circuit block design are discussed in

detail. More measurement results including animal experiment are also presented. This paper is

organized as follows. Important system considerations and architecture are addressed in Section II.

The implementation details of the individual circuit blocks, such as the RF TX/RX, digital

baseband (DBB) and JPEG encoder are presented in Section III. Section IV reports the

measurement results and demonstration of the prototype capsule. Section V concludes the paper.

II. SYSTEM CONSIDERATIONS AND ARCHITECTURE

A. Frequency Selection

The selection of wireless telemetry frequency is constrained by several factors including tissue

loss, antenna size, data rate and spectrum regulations. It has been reported in [18–20] that sub-GHz

band provides minimal tissue loss and is thus a good choice for wireless telemetry for implantable

devices. Among various sub-GHz bands, medical implant communication service (MICS) [21]

frequency band (402–405 MHz) has been approved by Federal Communications Commission

(FCC) for implantable devices. However, its 300-kHz narrow channel bandwidth and adjacent

channel interference requirement limit its usefulness for wideband communications. On the other

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hand, 915-MHz industrial, scientific and medical (ISM) band has much larger channel bandwidth

(902–928 MHz) suitable for high data-rate wideband in-body communication. For example,

920–925 MHz ISM band has been allocated for short-range devices in Singapore to cater for such

applications. In addition, higher channel frequency also has the added benefits of smaller antenna

size and smaller on-chip spiral inductor with higher quality factor. In this project, 3 Mb/s uplink

data rate and 500 kb/s downlink data rate are chosen for the allocated 920–925 MHz ISM band.

However, we can easily scale up the TX data rate to 20 Mb/s with only minor power penalty when

full ISM band of 902–928 MHz is available.

B. Modulation Scheme

Spectrum efficiency is another major consideration when selecting a modulation scheme for the

high data-rate uplink. Frequency-shift keying (FSK) with its constant amplitude characteristic is a

popular choice as the efficient nonlinear power amplifier (PA) can be used. However, the

conventional FSK without pulse shaping has inferior spectrum efficiency. On the other hand, the

FSK with pulse shaping tends to complicate the TX architecture and results in poor energy

efficiency. Hence, QPSK with double bandwidth efficiency compared to OOK and FSK is adopted

in this design. This choice will not lead to significant disadvantage in PA efficiency due to the

relatively small output power and voltage level for such implantable devices. For example, even

though FSK is adopted in [22], only about 30% PA drain efficiency is achieved due to the small

TX output amplitude. Although a coherent QPSK RX is needed, it is not implemented on the

capsule but rather on the BS due to the asymmetrical data link. Therefore, it would not impact the

overall energy efficiency of WCE. On the other hand, the downlink from the BS to the capsule for

control signal only requires low data-rate. A non-coherent OOK RX with better energy efficiency

is therefore adopted here.

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C. Link Budget

For the high data-rate uplink, the received power at the BS RX input (PRX,BS) is given by

, , , ,RX BS TX WCE T WCE R BS pathP P G G L , (1)

where PTX,WCE is the TX output power, GT,WCE and GR,BS are the TX and RX antenna gain

respectively, and Lpath is the overall path loss including free space and tissue loss. Due to the space

constraint within the capsule, a small size coil antenna with –10-dBi antenna gain is commonly

adopted. Given that the TX has –16 dBm effective isotropic radiated power (EIRP) as stipulated

by FCC regulation and an overall path loss is about 60 dB, the PRX,BS approaches –76 dBm.

On the other hand, the BS RX sensitivity requirement (Ps,BS) can be calculated with

, 10174 10logS BSP BW NF SNR , (2)

where BW is the effective signal bandwidth, NF is the BS RX noise figure and SNR is the

signal-to-noise ratio required to achieve less than 0.1% bit error rate (BER). By assuming BW of 3

MHz, SNR of 10 dB for QPSK and typical NF < 10 dB, a link margin of 13 dB is calculated from (1)

and (2), which can be easily met with off-the-shelf components.

For the low-data-rate downlink, the BER performance is often limited by the noisy energy

detector if there is insufficient RF front-end gain. However, the available RF front-end gain is

usually limited due to power consideration. From our study on the energy detector, it reveals that

the employed energy detector exhibits an output noise level of 150 Vrms. To achieve an output

SNR of 13 dB, the detector should give an equivalent signal output of 670 Vrms. Given an RF

front-end gain of 25 dB and a squarer conversion gain of –5 dB, this will translate into an input

signal level of 70 Vrms or –70 dBm at the LNA. In this design, BS TX EIRP of +20 dBm, overall

path loss of 60 dB and –10 dBi implantable antenna gain are assumed, resulting in a received

8

power of –50 dBm at the capsule RX input. This will lead to a link margin of 20 dB, which is

sufficient to ensure the system robustness under channel fading and antenna polarization

mismatch.

D. System Architecture

The proposed WCE is shown in Fig. 2 which consists of two chips, i.e. an RF SoC and a JPEG

encoder IC. The RF SoC includes a QPSK/OOK RF transceiver, a DBB physical layer (PHY) for

synchronization/error correction, a power management unit (PMU) and a serial peripheral

interface (SPI) for communication with a micro-controller unit (MCU). The image is first taken

using a commercial 1/8 inch CMOS VGA image sensor. The captured data will then go through a

low-power JPEG encoder for compression to relax the uplink data rate requirement. A low-power

MCU (TI MSP430) will interface with the RF SoC and JPEG encoder IC to facilitate data

transmission. It also serves as a system controller for the image sensor and actuators.

Time-division multiplexing is adopted to activate the TX and RX alternately within WCE. Most of

the time, the TX is enabled for image transmission to the BS. The RX is only activated during the

interval between the transmission slots of two image frames. During TX/RX operation, the LNA

or PA will exhibit high input/output impedance so that there would be no influence on the RX or

TX operation. This eliminates the need of a transmit/receive (T/R) switch which introduces further

insertion loss. The proposed architecture optimizes the WCE energy efficiency by pushing the

power-hungry coherent QPSK RX and high-power OOK TX to the BS where no stringent power

and size constraints exist.

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III. CMOS IMPLEMENTATION

A. Transmitter

The QPSK TX schematic is shown in Fig. 3. It consists of a fundamental-mode crystal oscillator,

a duty-cycle tuning circuit, an LC injection-locked oscillator (ILO), a 180o phase swap circuit and

two PAs. The VCO core consists of a symmetrical NMOS cross-couple pair (NM1-2), an LC tank

including an on-chip center-tapped differential inductor (LD1, LD2) and a capacitor bank.

Differential pair NM4-5 are used for signal injection, tail current source Iosc and Iinj set the VCO

core bias current and injection current, respectively. The QPSK TX operation principle has been

explained in [12] where phase versus self-resonant frequency characteristic of ILO is exploited to

produce the desired quadrature phases for QPSK modulation. However, the design in [12]

employed an external reference signal generated by equipment to provide testing flexibility and

did not address the design consideration and performance limitation associated with the reference.

The desired ILO output frequency of 922.5 MHz will directly impact the choice of crystal

oscillator frequency. A low-frequency (< 40 MHz) fundamental-mode crystal is generally

preferred due to cost consideration. However, this will result in injection locking with 23rd

harmonics or higher. On the other hand, a high-frequency (> 40 MHz) fundamental-mode crystal

is often custom-made and more expensive. Although a cheap overtone crystal oscillator can be

built, it is usually more power hungry and requires additional filtering element to suppress the

fundamental-mode oscillation. In this implementation, an external fundamental-mode crystal

together with an on-chip Pierce oscillator circuit generates the 102.5 MHz injection signal. The 9th

harmonic provides 2.5 times higher injection signal strength than 23rd harmonic, which translates

to 2.5 times smaller transconductance for the injection transistor to achieve the same ILO locking

range. This will reduce the current consumption of the injection transistor pair. We also insert an

10

additional duty-cycle tuning circuit to further boost up the 9th-harmonic injection signal strength.

Compared to the pulse slimmer approach [23], this technique gives more precise control on the

strength of 9th harmonic injection. The total power consumption including the Pierce oscillator, a

clock buffer and a duty-cycle tuning circuit is only 500 W and further power reduction is limited

by its output phase noise performance requirement.

The unit capacitance of the 7-bit binary weighted VCO capacitor array is also further reduced to

25 fF for better phase resolution control. Through calibration, the values of two control words

CH[6:0] and CL[6:0] are determined to accurately generate ±45o output phases. The phase swap circuit

will produce the remaining ±135o phases. The incoming I/Q data bits D0 and D1 are used to toggle

between CH[6:0] and CL[6:0] and also swap the output phase, resulting in QPSK modulation. The

ILO differential outputs drive a pair of inverter-based PAs which consists of a self-biased driver

stage and an inverter stage. The complementary TX_EN and TX_ENB signals enable/disable the

control transistors PMT3 and NMT3. NMT3 also acts as the current source for gain control through

tunable resistor Rt. Two PAs drive an off-chip differential coil antenna with 100-Ω differential

input impedance. An off-chip impedance transformation network is used to boost the impedance

of the antenna for better output efficiency. The matching network is co-designed with LNA input

so that inductor sharing (L1 and L2 in Fig. 2) can be applied. The design details will be presented in

next section.

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B. Receiver

As shown in Fig. 2, the non-coherent OOK RX consists of an LNA, a squarer as an energy

detector, a variable-gain amplifier (VGA) to amplify the analog baseband signal and a 1-bit slicer

to digitize the data.

1) LNA:

A fully differential LNA architecture is employed in this design. A half circuit of the proposed

LNA core is shown in Fig. 4(a) for clarity. It comprises two stages of current-reuse common

source (CS) inverter-type amplifiers. Each inverter-type amplifier has a CS NMOS/PMOS

transistor pair to maximize the transconductance per stage. The NMOS and PMOS MOSFETs are

separately biased to operate in weak-inversion region for optimum gain performance. A bypass

capacitor Cb provides the AC ground needed for the two stacked amplifiers. A resistor R1 is chosen

based on bandwidth consideration.

For accurate biasing under PVT variations, a replica biasing circuit is employed to provide 4

biasing voltages (VBN1, VBN2, VBP1, VBP2) needed for the amplifying transistors as shown in Fig. 4(b).

Here, NM1A, NM2A, PM1A and PM2A are mirror transistors from their amplifying transistor

counterparts NM1, NM2, PM1, and PM2. Due to virtual short, the negative feedback loop formed

using an operational amplifier will force V2 to the desired voltage (Vref), which can be changed

through an external trimmer R2. Based on replica biasing property, V1 will then closely track Vref

with all the transistors operating at saturation region under PVT variations. LNA variable gain

function is realized by varying the bias current resistors Rbias through SPI.

Capacitive shunt feedback technique, which was first reported in [24] and then further

investigated in [25–29], is applied in this design to achieve LNA input impedance matching. The

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feedback via MOSFET gate-to-drain capacitance Cgd provides the real-part of the input impedance,

eliminating the need of source degeneration inductor.

The input admittance Yin of LNA input stage shown in Fig. 4 (a) can be written as [29]

1 11 1

1 1

1

1m Load

in gs gdgd Load

G ZY sC sC

sC Z

, (3)

where Cgs1, Cgd1, Gm1 are the combined gate-to-source capacitance, gate-to-drain capacitance and

transconductance of input pair, respectively (Cgs1 = Cgs_NM1+Cgs_PM1, Cgd1 = Cgd_NM1+Cgd_PM1,

Gm1=gm_NM1+gm_PM1), and ZLoad1 is the output load impedance of first stage. To simplify the

analysis, assume ZLoad1 is a purely capacitance CLoad1, (3) can be simplified to

1 1 1 11 1 1 1

1 11 1

1 gd m gd min gs gd gs gd

gd Loadgd Load

sC G C GY sC sC s C C

C Cs C C

. (4)

Eq. (4) shows that input admittance is a capacitor in parallel with a resistor. If a gate inductor is

added to cancel the imaginary part, resistive input impedance can be obtained. In reality, the real

load ZLoad1 is a combination of resistance (R1) and capacitance (Cgs_NM2, Cgs_PM2). The resistive part

of ZLoad1 will contribute to both real and imaginary part of Yin. In this design, an external inductor

L1 is employed for input impedance matching. At the targeted output frequency of 0, the input

matching network has a quality factor of

0 1in

s LG

LQ

R R

, (5)

where Rs is the source impedance and RLG is the serial resistance of L1. The total voltage gain of the

LNA can be expressed as

1 2 1 1 2 2|| ||V in m m ds Load ds LoadA Q G G R Z R Z , (6)

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where Rds1 and Rds2 are the combined output impedance for each amplifier stage, and ZLoad2 is the

input impedance of next stage circuit after LNA.

Neglecting the noise contribution from 2nd stage LNA, the noise factor of the LNA can be

derived in a similar procedure as [30]

2

20 012

1 1

11 2 1

5 51LG

in m ss m L T Tin m s

RF c Q G R

R G Z Q G R

, (7)

where α is the ratio between device transconductance and the zero-bias drain conductance, γ is the

factor of channel thermal noise, δ is the factor of induced gate noise and c is the correlation

coefficient between the induced gate noise and the drain noise.

To achieve low noise figure, high-Q L1 is used to improve Qin which results in smaller RLG.

Higher Gm1 and ωT can help to lower noise figure, but are constrained by target power

consumption. Hence, to determine the optimum sizing and current biasing of the LNA for a given

power constrain, individual transistor characteristics are studied. Fig. 5 illustrates the gm, rds and

unity current gain frequency (fT) versus various drain current settings with 3 different transistor

widths (50 m, 100 m, 150 m) for both NMOS and PMOS transistors. To ensure fT that is eight

to ten times larger than the LNA bandwidth, sufficient gm to provide the desired gain, and large rds

to avoid overloading the output, Id of 300 A is chosen and the transistors sizing are shown in Fig.

4.

2) Energy Detector:

The energy detector shown in Fig. 6 has a similar structure as [31]. However, the performance

has been re-optimized for this application. This optimization includes the sizing of transistors for

900-MHz input frequency instead of 3–5 GHz and the scaling of output bandwidth down to 3 MHz

by tuning the RC constant of the active load and output capacitance. After squaring operation, the

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OOK signal envelop will be down-converted to baseband for further processing. Consuming 0.8

mA, the energy detector provides a conversion gain of –5 dB for a minimum signal input of 1.2

mV.

3) Analog Baseband:

As shown in Fig. 7 (a), the VGA consists of two fixed-gain (10 dB) stages and one variable-gain

stage (-15 dB to 15 dB) in cascade to provide a tunable gain from -15 dB to 35 dB in 1-dB step. AC

coupling is used to avoid DC-offset issue. The designed low/high cut-off frequency is 50 kHz and

3 MHz respectively. The amplified signal is digitized by a slicer consisting of a pre-amplifier and

a dynamic latch. The dynamic latch output is synchronized by a clock signal (RX_CLK) from the

DBB.

As shown in Fig. 7 (b), the VGA fixed gain stage is a CS amplifier with PMOS active load

employing simple resistive common mode feedback (CMFB) circuit. The gain will be mainly

determined by R1-2 in this design. Unlike fixed gain stage, the variable-gain stage shown in Fig. 7(c)

consists of an active PMOS load with active CMFB to allow separate PMOS drain and gate

biasing. The variable gain is achieved through gm-ratioed architecture for dB-linear gain tuning

[32]. To compensate for gain fluctuation due to resistance variation (R1-2) in the fabrication, an

adaptive current biasing block consisting of an OPA and a sensing resistor R3 is employed. This is

possible as R1-3 are chosen to be same resistor type so that they have same process variation trend.

The schematic of the slicer pre-amplifier and latch is shown in Fig. 7 (d). The pre-amplifier

prevents the kick-back noise in latch from coupling back to the VGA.

4) Shared TX/RX Matching Network:

T/R switch is eliminated in this transceiver to reduce insertion loss and improve system

performance. The design challenge is to minimize the loading effect of LNA/PA during OFF state

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to the PA/LNA during ON state. Fig. 8 illustrates the PA/LNA configuration in TX/RX modes

respectively. In TX mode, LNA is disabled by connecting gate bias of NMR1, NMR2 to GND and

gate bias of PMR1, PMR2 to VDD. Therefore, PA output voltage swing will not cause any harmful

stress to LNA input MOSFETs. In addition, the gate overlap capacitance from LNA (Cpar_LNA) and

L1 will form an L matching network, converting 50 Ω load to 400 Ω to enhance PA efficiency. In

RX mode, the PA is disabled by connecting PMT3 and NMT3 switch to VDD and GND respectively.

L1 will resonate out the imaginary-part of LNA input impedance and the parasitic output

capacitance of PA (Cpar_PA) for input impedance matching. The LNA/PA transistors sizing are

carefully chosen such that inductor sharing can be achieved.

TX/RX isolation is another important issue in RF transceiver. In this design, the TX VCO core is

always ON even during the RX mode to minimize the switching time from RX to TX. The leakage

from VCO output to LNA input must therefore be minimized to prevent potential RX sensitivity

degradation. From simulation, the two-stage PA in OFF state can provide more than 40 dB

isolation to avoid the desensitization of RX LNA.

C. Digital Baseband

As shown in Fig. 9 (a), the DBB consists of various digital signal processing blocks to support

the uplink and downlink data communication. For uplink, the raw data goes through a TX buffer to

separate the data chunk into multiple packets suitable for data packet transmission. The data

packet then goes through a cyclic redundancy check (CRC) generator block to incorporate error

detection capability. After that, it will go through a Reed-Solomon (RS) encoder block which is

good at providing forward error correction (FEC) capability for burst-mode data transmission with

low overhead. The resulting data packet is then assembled into a packet frame by adding a 64-bit

preamble, an 8-bit start frame delimiter (SFD), a 16-bit PHY header (PHR), and a 8-bit header

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checksum (HCS) in front, as shown in Fig. 9 (b). The 64-bit preamble pattern is a repetition of an

8-bit sequence [1 1 –1 1 –1 –1 1 –1]. It is coded with BPSK rather than QPSK to gain additional

3-dB SNR advantage. The preamble helps the synchronization between RX and TX. The SFD

consists of an 8-bit sequence [1 1 –1 1 1 1 –1 1] which is exactly orthogonal to the preamble

sequence. Hence, a sliding correlator can be employed to detect the start of the packet. The 16-bit

PHR sequence defines the RS code rate for encoding the data and the size of the data payload. The

HCS provides error detection to ensure that the decoded information from PHR is valid. The

packet can accommodate the maximum data payload of 255 bytes. This maximum length is chosen

to ensure that negligible frequency drift between TX and RX occurs within the packet interval.

Using the proposed DBB, the BER performance for uplink can be improved from 10–3 to 10–6,

which is sufficient for transmission of one entire frame of JPEG image.

For downlink, the corresponding DBB includes a correlator, a CRC decoder and a RX buffer

block. The RX packet frame structure is shown in Fig. 9 (c) with a 24-bit preamble, an 8-bit SFD,

an 8-bit PHR, a maximum data payload of 15 bytes, and an 8-bit error checksum (ECS). The data

payload for RX is much shorter than that of TX as it is only for command transmission. CRC-8 is

implemented as the ECS to provide error detection. In order to provide a spreading gain to improve

RX sensitivity and aid clock recovery, each transmission of data ‘1’ and ‘0’ is mapped into 6-chip

sequences of ‘101100’ and ‘010011’ respectively. After considering all the coding and baseband

overheads, the DBB will have raw data throughputs of 2.57 Mb/s and 60 kb/s for TX and RX,

respectively.

D. JPEG Encoder IC

The block diagram of the JPEG encoder is shown in Fig. 10. It consists of four major building

blocks which are an input buffer, a JPEG encoder core, a data packer and an output

17

first-in-first-out (FIFO) buffer [33]. The image sensor output in 8-bit Bayer-pattern RGB format is

first converted to YUV422 format. Here, Y represents luminance while U and V are chrominance

components of color difference in blue and red. YUV422 means sub-sampling in chrominance by

transmitting two Y components with one U and one V components. Since human eyes are less

sensitive to color variation than to luminance, chrominance components can be sub-sampled to

reduce the amount of transmitted data, while preserving almost the same image quality.

As shown in Fig. 9, the whole compression module is divided into 6 stages of pipelining to

improve processing speed and reduce power consumption. The first stage is the input buffer

consisting of two RAM blocks to store incoming data alternately for continuous data

reading/writing. The JPEG encoder core, which comprises a 2-D discrete cosine transform (DCT)

block, a quantizer and a Huffman encoder with a zero-run-length counter, is further divided into 3

stages of pipelining. The 2-D DCT is implemented by pipelining two 1-D DCT blocks. At the

second stage, the first 1-D DCT block performs row-wise transformation. It is then followed by the

third stage where the second 1-D DCT block carries out column-wise transformation. Within the

same stage, the quantization operation is also performed. The image quality factor is fixed at 90 as

a trade-off between compression ratio and image peak-signal-noise-ratio (PSNR), leading to 9 bits

of data length requirement for luminance and chrominance quantization tables. In addition, instead

of doing division directly, multiplication is performed with the quantization values being inversed.

At the fourth stage, Huffman encoding is performed with differential pulse-code modulation

(DPCM) used for DC coefficients and with zero-run-length encoding used for AC coefficients. A

static compression technique and standard JPEG Huffman codes are employed here [34].

Furthermore, a zero counter is used for zero-run-length encoding while a zero detector is used for

end-of-block (EOB) encoding. At the fifth stage, the data packer, which consists of a FIFO and a

18

controller, will organize the variable-length output of the JPEG compression into 8-bit data format.

The sixth stage is particularly reserved for direct memory access (DMA) interface. The write

operation is controlled by the data packer while the read operation is determined by the MCU. The

controller also sends out FIFO status signal to the MCU to prevent overflow or underflow

condition.

IV. MEASUREMENT RESULTS

Both the RF transceiver SoC and JPEG encoder IC have been fabricated in 0.18 μm CMOS

process with their die micrographs shown in Fig. 11. The transceiver SoC and JPEG encoder IC

occupy die area of 2.6 × 2.8 mm2 and 2.6 × 2.6 mm2 respectively. Individual circuit blocks are first

characterized with bench test, following which the full system is assembled and the performance is

verified with animal experiments.

A. Circuit Block Measurement Results

Fig. 12 shows the measured phase noise of the ILO with the integrated crystal oscillator. With

injection locking, the measured phase noise exhibits –122 dBc/Hz at 1-MHz offset with a total

integrated phase error of 0.38rms, which is good enough to achieve reliable QPSK modulation.

Fig. 13 presents the measured error-vector-magnitude (EVM) performance of QPSK transmission

signal and spectrum at 3 Mb/s data rate. Consuming 5 mW, the TX achieved an EVM of 5.01%

with an output power of –6 dBm. By consuming additional 1-mW power, the TX can support the

data rate up to 20 Mb/s while maintaining the EVM below 10%. Fig. 14 (a) shows PA output

power and efficiency with respect to the input power. It achieves output P1dB of -4.5 dBm with

23% efficiency and saturated power of -2.7 dBm with efficiency of 37%. Fig. 14 (b) shows the

measured LNA S-parameters and noise figure in high/low gain modes. The maximum voltage gain

19

in high/low gain mode is 26.8 dB/15.7 dB with a corresponding minimum noise figure of 3.6

dB/4.8 dB. As shown in Fig.14(c), the measured VGA gain varies from -14.2 dB to 35.3 dB with a

step size of 0.96 dB. The low and high 3-dB cut-off frequencies are 13 kHz – 20 kHz and 2.2 MHz

– 3 MHz respectively, depending on gain settings. Fig. 15 shows the measured OOK RX

time-domain waveforms. Fig. 16 shows the measured BER for raw data at the slicer output under

high and low gain settings. The RX achieves a sensitivity of –65 dBm at 500 kb/s data rate with

0.1% BER while consuming 4.5 mW.

The JPEG encoder consumes 1 mW from 1.2-V supply when operating with 6-MHz clock for

7.5-fps VGA images. JPEG encoder performance has been tested with endoscopic images

provided by a doctor as shown in Fig. 17. As illustrated, there is no noticeable difference between

the original and compressed images. The average compression ratio is 15.6 and the average PSNR

is 44.56. The achieved compression ratio depends on the inherent nature of the image content. Any

fine features in the image such as bubbles can degrade the compression ratio. Measurement results

indidate that both the RF transceiver SoC and JPEG encoder IC can support an image transmission

up to 7.5 fps with the reported power consumption.

Table I summarizes the measured performance and makes a comparison with other

state-of-the-art RF transceiver designs for WCE application. As shown, our design can support

high data rate up to 20 Mb/s with the highest image compression ratio. This can potentially

facilitate transmitting images with even higher quality (SVGA, XVGA or HD) and frame rate. The

design in [35] is used in commercial WCE Given Imaging Pillcam SBTM, it lacks the downlink RX

and has much lower image resolution. The lowest TX power is achieved in [31] due to heavy duty

cycling characteristics of ultra-wideband (UWB) radio, but the RX power efficiency is very low.

In addition, the chosen frequency band from 3 GHz to 5 GHz suffers from prohibitively high loss

20

in through-body communication. The RX presented in [36] provides much lower data rate at more

than twice of our power consumption.

B. Capsule System and Animal Trial

A prototype multifunctional endoscopy capsule has been built using this chipset. The overall

capsule dimensions are 37 mm (L) by 11.5 mm (Φ). About 16% of the capsule space is reserved for

a tagging actuator to cater for lesion localization. As shown in Fig. 18(a), the RF SoC, JPEG

encoder and image sensor chips are directly assembled on a rigid-flex PCB and protected by epoxy.

The front and back sides of the assembled PCB system are shown in Fig. 18(b). When the

proposed WCE is deployed with external commercial QPSK receiver and OOK transmitter,

communication distance of more than 10 meters can be achieved for both uplink and downlink.

The maximum achievable frame rate of current capsule design is limited by MCU processing

speed to 3 fps, which is lower than the capability of the designed chipset. Hence, duty cycling is

adopted for TX, resulting in 2.5 mW at 3 fps. The power breakdown of this prototype WCE in TX

and RX modes at 3 fps are shown in Fig. 19. During TX mode, the total power consumption is 33.8

mW with 41% consumption by the image sensor and LED, and 44% consumption by the MCU.

The high MCU power consumption is due to both high clock frequency and extensive data transfer

from JPEG encoder to MCU and from MCU to DBB. The MCU power consumption can be

reduced to sub-mW if the JPEG encoder transfers data directly to DBB. During RX mode, the

overall power consumption is 7.7 mW with 58% consumption by the RF RX. Two Energizer 399

button batteries are stacked as a power source. They can provide approximately 54 mAh under 3 V

and power the system to work for 2 to 3 hours at 3 fps.

The full system performance has been verified by an in vivo animal experiment on porcine

model. This in vivo study was carried out with a 40-kg domestic pig. The capsule was delivered

21

into the porcine stomach by peroral endoscopy and the receiving antenna was positioned on the

porcine body as shown in Fig. 20 (a). The endoscopic view of the capsule inside the stomach is

shown in Fig. 20 (b). An external transceiver is implemented with discrete components including a

LNA, a PA, an I/Q demodulator, an ADC and a baseband implemented in FPGA as shown in Fig.

20 (c). The internal images of the stomach muscle were successfully transmitted to the external RX

and displayed on the PC screen as shown in Fig. 20 (d).

V. CONCLUSION

A chipset including an asymmetrical QPSK/OOK transceiver SoC and a JPEG image

compressor IC is presented for WCE. The QPSK TX consumes 5 mW at a data rate of 3 Mb/s and

an output power of –6 dBm. The OOK RX achieves a sensitivity of –65 dBm at 500 kb/s data rate

with 4.5 mW consumption. A prototype wireless capsule system has been developed to achieve

VGA image transmission at 3 fps with an average image compression ratio of 15.6. The frame rate

is currently limited by the MCU and can be further improved up to 7.5 fps.

ACKNOWLEGEMENT

The authors would like to acknowledge Prof. Zhining Chen and Terence See from the Institute

for Infocomm Research, A*STAR for providing the miniature antenna, Lim Ruiqi and packaging

team from the Institute of Microelectronics, A*STAR for chip packaging, Prof. Louis Phee Soo

Jay and his team from Nanyang Technological University for capsule assembly and system

testing.

22

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26

CAPTIONS Figure 1: WCE system.

Figure 2: System block diagram of the proposed WCE.

Figure 3: Schematic of QPSK TX and its operation principle.

Figure 4: Schematic of (a) LNA core (half circuit) and (b) replica bias circuit.

Figure 5: Simulated gm, fT and rds versus the drain current (Id) for (a) NMOS and (b) PMOS

transistors.

Figure 6: Schematic of energy detector.

Figure 7: (a) Analog baseband chain block diagram, (b) schematic of VGA fix gain stage, (c)

schematic of VGA variable gain stage, (d) schematic of slicer

Fig. 8: (a) LNA/PA configuration in TX mode, (b) LNA/PA configuration in RX mode.

Figure 9: DBB block diagram and data frame structures – (a) TX/RX DBB block diagram, (b)

QPSK frame structure, (c) OOK frame structure.

Figure 10: Block diagram of JPEG encoder IC.

Figure 11: Chip photographs of (a) RF SoC and (b) JPEG encoder.

Figure 12: Measured ILO output phase noise after injection locking.

Figure 13: Measured QPSK TX EVM.

Figure 14: (a) Measured PA output power and efficiency. (b) Measured LNA S-parameters and

noise figure in high/low gain modes. (c) Measured VGA frequency response.

Figure 15: Measured OOK RX waveforms.

Figure 16: Measured OOK RX BER.

Figure 17: Comparison of (a) original and (b) compressed images for low compression ratio of 11,

and (c) original and (d) compressed images for average compression ratio of 15.

Figure 18: (a) Assembled WCE prototype and (b) front and back sides of the rigid-flex PCB

system.

Figure 19: Power break down of (a) system in TX mode, (b) system in RX mode.

Figure 20: In-vivo animal experiment: (a) Measurement setup, (b) Endoscopic view of the WCE in

the stomach, (c) External transceiver setup, and (d) Received image displayed on the PC.

Table I: Performance Summary and Comparison.

27

Figure 1: WCE system.

Figure 2: System block diagram of the proposed WCE.

28

Figure 3: Schematic of QPSK TX and its operation principle.

(a) (b) Figure 4: Schematic of (a) LNA core (half circuit) and (b) replica bias circuit.

29

(a) (b)

Figure 5: Simulated gm, fT and rds versus the drain current (Id) for (a) NMOS and (b) PMOS transistors.

Figure 6: Schematic of energy detector.

30

(a)

(b) (c)

(d)

Figure 7: (a) Analog baseband chain block diagram, (b) schematic of VGA fix gain stage, (c) schematic of VGA variable gain stage, (d) schematic of slicer

31

(a)

(b)

Fig. 8 (a) LNA/PA configuration in TX mode, (b) LNA/PA configuration in RX mode.

32

(a)

(b)

(c)

Figure 9: DBB block diagrams: (a) TX/RX baseband block diagram, (b) QPSK frame structure, (c) OOK frame structure.

Figure 10: Block diagram of JPEG encoder IC.

33

(a) (b)

Figure 11: Chip photographs of (a) RF SoC and (b) JPEG encoder.

Figure 12: Measured ILO output phase noise after injection locking.

34

Figure 13: Measured QPSK TX EVM.

(a) (b)

(c)

Figure 14: (a) Measured PA output power and efficiency. (b) Measured LNA S-parameters and noise figure in high/low gain modes. (c) Measured VGA frequency response.

35

Figure 15: Measured OOK RX waveforms.

Figure 16: Measured OOK RX BER.

36

(a) (b)

(c) (d) Figure 17: Comparison of (a) original and (b) compressed images for low compression ratio of 11, and (c) original and (d) compressed images for high compression ratio of 16.5.

37

(a)

(b)

Figure 18: (a) Assembled WCE prototype and (b) front and back sides of the rigid-flex PCB system.

(a) (b)

Figure 19: Power break down of (a) system in TX mode, (b) system in RX mode.

38

(a) (b)

(c) (d)

Figure 20: In-vivo animal experiment: (a) Measurement setup, (b) Endoscopic view of the WCE in the stomach, (c) External transceiver setup, and (d) Received image displayed on the PC.

39

Manuscript received February 6, 2013; revised May 16, 2013 and July 3, 2013; accepted July 5, 2013. This work was supported by the Science and Engineering Research Council of Agency for Science, Technology and Research (A*STAR), Singapore, under Grant 082 140 0033 and 082 140 0034. Y. Gao, W.-D. Toh, X. Chen and B. Zhao are with the Institute of Microelectronics, Agency for Science, Technology and Research (A*STAR), Singapore 117685 (e-mail: gaoy@ime.a-star.edu.sg). S.-J. Cheng was with the Institute of Microelectronics, A*STAR, Singapore, 117685. He is now with DSO National Laboratories, Singapore 118230 (e-mail: sanjeow@yahoo.com.sg). Y.-S. Kwok, K.-C. Tan, H.-H. Win and S. Sun are with the Institute for Infocomm Research, A*STAR, Singapore 138632 (e-mail: sunsm@i2r.a-star.edu.sg). S. Diao was with the Institute of Microelectronics, A*STAR, Singapore, 117685. He is now with University of Science and Technology of China, Hefei, China 230027 (e-mail: diaosxi@ustc.edu.cn). A. Cabuk was with the Institute of Microelectronics, A*STAR, Singapore, 117685. He is now with Mikroelektronik Ar-Ge Ltd., Istanbul, Turkey 34469 (e-mail: alpersing@yahoo.com). Y. Zheng was with the Institute of Microelectronics, A*STAR, Singapore, 117685. He is now with Nanyang Technological University, Singapore 639798 (e-mail: yjzheng@ntu.edu.sg). M. Je is with the Institute of Microelectronics, A*STAR, 117685 Singapore, and also with the Department of Electrical and Computer Engineering, National University of Singapore, Singapore, 117576 (e-mail: jemk@ime.a-star.edu.sg). C.-H Heng is with the Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117576 (e-mail: elehch@nus.edu.sg).

Yuan Gao (S’04-M’08) received the B.Eng. and M.Eng. degrees in electrical engineering from Huazhong University of Science and Technology, Wuhan, China in 2000, 2003, respectively, and the Ph.D. degree in electrical engineering from the National University of Singapore, Singapore, in 2008.

Since 2007, he has been with Institute of Microelectronics (IME), Agency for Science, Technology and Research (A*STAR), Singapore, where he is currently a research scientist and the principal investigator of Biomedical IC group in Integrated Circuits and Systems Laboratory. His current research interests include low-power low-voltage circuit technologies for wireless and biomedical applications, energy harvesting and biosensor interface circuits design.

San-Jeow Cheng (S’06–M’11) received the Ph.D. degree in electrical engineering from the National University of Singapore in 2012.

From 2000 to 2006, he was with Agere Systems Singapore, as a design kit and model developer. In 2010, he joined the Integrated Circuits and Systems Laboratory of IME, A*STAR, Singapore as a

research scientist, working on efficient wireless transmitters for biomedical applications. Since 2013, he is a senior member of technical staff with DSO National Laboratories, Singapore, working on miniaturized circuit solutions. His current research interests include frequency synthesizers, delay locked loops and data converters.

Wei-Da Toh received the B.Eng. and M.Eng. degrees in electrical engineering from the National University of Singapore in 2007 and 2010, respectively.

In 2007, he was with National University of Singapore, as a research engineer. Since 2010, he has been with Institute of Microelectronics (IME), A*STAR, Singapore, as a research engineer.

His current research interests include algorithm optimization for digital integrated circuits and low-power digital design.

Yuen-Sam Kwok received the B.Eng. degree in electrical engineering from National University of Singapore in 1995 and the M.Eng. degree in Telecommunications from Royal Melbourne Institute of Technology in 1999.

He has been with Institute for Infocomm Research (previously known as Centre for Wireless Communications), A*STAR,

Singapore since 1999. He has worked on a number of projects on wireless communications systems. This include the development of a defence-related wireless communications link, the investigation of the performance of turbo coding with blind channel estimation, mobility modelling in 3G cellular systems, participation in standardization activities in IEE 802.15.4a/b, and evaluation of the performance of modulation and coding schemes for UWB signalling and ranging. He has also worked on the design and implementation of meter reading and routing protocol of a multi-communications module used in smart metering applications.

Kay-Chuan Tan Benny received the B. Eng. degree in electronic and electrical engineering from Loughborough University, England, United Kingdom in 1997 and Ph.D. degree in low power DSP algorithm and VLSI architecture implementation and design from the University of Edinburgh in 2005.

From 2005 to 2010, he had been working in the semiconductor microsystems industries before he joined Institute for Infocomm Research (I2R), A*STAR, Singapore, as a Senior Research Fellow. He is currently the Digital Design

Laboratory Head of Engineering Department at I2R. His primary research interests include low-power VLSI DSP implementation for communication applications on SOC, low-power system and energy harvesting system design.

Xi Chen received the B.Eng. degree in communication engineering from Sichuan University, Chengdu, China, in 2001. He received the M.Sc. and Ph.D. degrees, both in wireless communication from the National University of Singapore in 2003 and 2009, respectively.

From 2009 to 2011, he worked with the Institute for Infocomm Research (I2R), A*STAR, Singapore, where he was mainly involved

in projects related to wireless communication and biomedical engineering. Since 2012, he has been with Institute of Microelectronics (IME), A*STAR, Singapore, where he is working on signal processing and communication system development. His current research interests include biomedical engineering, wireless communication, blind identification and blind source separation, array signal processing, and applications of signal processing to speech and audio. Wai-Meng Mok Photo and biography are not available at the time of publication.

Htun-Htun Win received the B. Eng. degree from Nanyang Technological University, Singapore, in 2007. Since then, He has been working as a Research Engineer in Institute for Infocomm Research (I2R), A*STAR, Singapore. His research interests include physical layer algorithm development, integration with RF for wireless communication as well as embedded system.

Bin Zhao received the B.S. degree from Peking University in 1990, majoring in Microelectronics. He then received M.S. and M. Eng. degrees from Chinese Academy of Sciences, China and National University of Singapore, Singapore in 1993 and 1998, respectively.

He has worked in Trident Technology Pte Ltd (Beijing Branch), Myson Technology Pte Ltd (Beijing Branch) before he moved to

Singapore. From 1998 to 2000, he worked at Philips Electronics Pte Ltd, Singapore. Since July 2000, he is with Institute of Microelectronics (IME), A*STAR, where he is now a senior research engineer. He has been involved in many digital IC design projects, such as WLAN Baseband, ONFIG ONU unit, RFID tag/reader, ZigBee Baseband, NVM memory etc. His research interest is in low-power digital IC design and implementation.

Shengxi Diao received the B.S. degree from East China Normal University, Shanghai, China, in 2001 and M.S. degree from Nanyang Technological University, Singapore, in 2006.

From 2002 to 2006, he worked on RFID systems development in TOPPAN Electronics, Singapore. At the end of 2006 he joined

Institute of Microelectronics, A*STAR, Singapore as a senior research engineer in the Biomedical IC group in Miniaturized Medical Devices Programme. He has been working on low-power ultra wideband and high data rate Biomedical integrated circuit design. At August 2011, he joined University of Science and Technology of China as an Associate Researcher and worked on low-power RFIC design.

Alper Cabuk (M’07) was born in Istanbul, Turkey, in 1977. He received the B.Sc. degree in electrical and electronic engineering from the Middle East Technical University (METU), Ankara, Turkey, in 1999, and the M.Eng. and Ph.D. degrees in electrical and electronic engineering from Nanyang Technological University (NTU), Singapore, in 2002 and 2006, respectively.

From 1998 to 1999, he was with the Information Technologies Institute (Bilten), Ankara, Turkey, where he was an engineer designing ICs for transmitter systems. From 2005 to 2006, he was a Research Associate with NTU. From 2006 to 2010, he was a Teaching-Research Fellow with NTU. From 2010 to 2012, he was a Senior Research Engineer with IME, A*STAR, Singapore. While at IME, he designed RF and analog integrated circuits in CMOS for wireless communication applications, ultra-low-power body area network systems, and miniaturized medical devices. Since joining Mikroelektronik Ar Ge Ltd., Istanbul, Turkey, as a Senior Design Engineer in 2012, his primary responsibilities have been circuit design and testing for microwave systems. His main interests include design and analysis of ICs and passive structures using CMOS and SiGe Technologies at mm-wave frequencies, low-power analog circuit design, and on wafer/on-board device and prototype testing.

Yuanjin Zheng (M’02) received the B.Eng. and M.Eng. degrees from Xi’an Jiaotong University, Xi’an, China, in 1993 and 1996, respectively, and the Ph.D. degree from the Nanyang Technological University, Singapore, in 2001.

From July 1996 to April 1998, he was with the National Key Laboratory of Optical Communication Technology, University of

Electronic Science and Technology of China. In 2001, he joined the Institute of Microelectronics (IME), A*STAR, Singapore, as a Senior Research Engineer, and was then promoted to a Principle Investigator. With the IME, he has led and developed various projects like CMOS RF transceivers, baseband system-on-a-chip (SoC) for wireless systems, ultra-wideband (UWB), and low-power biomedical ICs etc. In July 2009, he joined the NanyangTechnologicalUniversity, as an Assistant Professor. His research interests are gigahertz RFIC and SoC design, bio-IC sensors and imaging, and SAW/BAW/MEMS sensors. He has authored or coauthored over 100 international journal and conference papers, 15 patents filed/granted, and several book chapters.

Sumei Sun obtained the B.Sc.(Honours) degree from Peking University, China, the M.Eng. Degree from Nanyang Technological University, and Ph.D. degree from National University of Singapore.

She has been with Institute for Infocomm Research (formerly Centre for Wireless Communications), A*STAR, since 1995 and is

currently Head of Modulation & Coding department, developing physical layer-related solutions for next-generation communication systems. Her recent research interests are in energy efficient multiuser cooperative MIMO systems, joint source-channel processing for wireless multimedia communications, and wireless transceiver design.

She has served as the TPC Chair of 12th IEEE International Conference on Communications in 2010 (ICCS 2010), General Co-Chair of 7th and 8th IEEE Vehicular Technology Society Asia Pacific Wireless Communications Symposium (APWCS), and Track Co-Chair of Transmission Technologies, IEEE VTC 2012 Spring. She’s an Associate Editor of IEEE Transactions on Vehicular Technology, and Editor of IEEE Wireless Communication Letters. She is co-recipient of IEEE PIMRC'2005 Best Paper Award.

Minkyu Je (S’97-M’03-SM’12) received the M.S. and Ph.D. degrees, both in electrical engineering and computer science, from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1998 and 2003, respectively. In 2003, he joined Samsung Electronics, Giheung, Korea, as a Senior Engineer and worked on multi-mode multi-band RF transceiver SoCs for

GSM/GPRS/EDGE/WCDMA standards. Since 2006 he has been with Institute of Microelectronics (IME), Agency for

Science, Technology and Research (A*STAR), Singapore, and is currently working as a Senior Scientist and leading the Integrated Circuits and Systems Laboratory. Since he joined IME, he has led various projects developing a low-power 3D accelerometer ASIC for high-end medical motion sensing applications, a readout ASIC for nanowire biosensor arrays detecting DNA/RNA and protein biomarkers for point-of-care diagnostics, an ultra-low-power sensor node SoC for continuous real-time wireless health monitoring, a wireless implantable sensor ASIC for medical devices, and MEMS interface & control SoCs for consumer electronics. His main research areas are low-power analog & mixed-signal circuits and systems interfacing with bio and MEMS sensors, circuit design and multi-functional system integration with novel nano devices, wireless telemetry circuits and systems for bio-medical applications, and heterogeneous 3D IC systems. He has more than 140 peer-reviewed international conference and journal publications in the areas of sensor interface IC, wireless IC, biomedical microsystem, 3D IC, device modeling and nanoelectronics. He also has more than 20 patents issued or filed.

He is a Program Manager of NeuroDevices Program under A*STAR Science and Engineering Research Council (SERC) and an Adjunct Assistant Professor in the

Department of Electrical and Computer Engineering at National University of Singapore (NUS). He currently serves on the Technical Program Committee of the IEEE International Solid-State Circuits Conference (ISSCC).

Chun-Huat Heng (S’96–M’04–SM’13) received the B. Eng. and M. Eng. degrees from the National University of Singapore in 1996 and 1999, respectively, and the Ph.D. degree from the University of Illinois at Urbana-Champaign, in 2003. He has been working on CMOS integrated circuits involving synthesizer, delay-locked loop, and transceiver circuits.

From 2001 to 2004, he was with Wireless Interface Technologies, which was later acquired by Chrontel. Since 2004, he has been with the National University of Singapore. He has received NUS Annual Teaching Excellence Award in 2008 and 2011. He has also won Faculty Innovative Teaching Award in 2009. He is currently serving as an Associate Editor for IEEE Transaction on Circuits and Systems II, and a Technical Program Committee member for Asian Solid-State Circuits Conference.