APPLICATION NOTEAn Atlas of ESD Failure Signatures in VerticalCavity Surface Emitting Lasers

ABSTRACT

AOC herein describes a collection of material degradation features observedin Vertical Cavity Surface Emitting Lasers (VCSELs) that have been intentionallydegraded with a range of electrostatic discharge (ESD) stress conditions.Failure analysis techniques employed include emission microscopy, FocusedIon Beam (FIB) microscopy and Transmission Electron Microscopy (TEM). Theresults have enabled higher confidence in root-cause determination for failedVCSEL devices.

INTRODUCTION

The application of sophisticated characterization techniques (e.g. emissionmicroscopy, FIB, and TEM) to understanding VCSEL failure mechanisms hasbeen well documented1, and analysts continue to add to3 and improve onthese techniques4. Typically, in the absence of gross mechanical or electricaloverstress damage, these techniques often reveal that the active layers of afailed VCSEL contain a complex patterned dislocation array1,5 . Acting as non-radiative recombination sites these arrays degrade the optical and electricalproperties of the laser device. However, while visually imposing, the dislocationarrays represent only the final cause, not root cause of failure. Rather, non-radiative recombination of minority carriers at a defect site in the activelayers of a light emitting diode provides a positive feedback mechanism thattypically leads to the self-supporting growth of a dislocation array from thatdefect site. Consequently, a single defect such as a dislocation propagatingfrom the substrate is able to generate a dense dislocation array that coversthe entire active region of the device.

Thus, the goal in the analysis of many failed VCSELs is to find the sourcedefect of the dislocation array. Once discovered, the next challenge is toattribute that defect to some outside event, design flaw, or growth anomaly.The emphasis of this paper is on the characterization of defects caused byoutside events, primarily Electrostatic Discharge (ESD) and minor ElectricalOverstress (EOS) events. The data shown below was generated with AOC’s14um oxide confined devicesi though the principles described are applicableto other VCSEL designs.

i Human Body Model and Machine Model pulses were generated using an Oryx 700 System.

BACKGROUND

The 2004 annual Electrostatic Discharge Association (ESDA)Symposium included no obvious representation from theoptical semiconductor device community in either the tutorialor technical programs. Nevertheless, optical devices are suscep-tible to ESD events and many of the concepts discussed in theESDA community are as applicable to the manufacturers andusers of VCSELs as they are to the silicon IC industry6. Thefollowing data show a range of material degradation featuresin oxide confined VCSELs intentionally exposed to ESD underlaboratory conditions, the characteristics of which depend onthe type of ESD stress applied.

Several texts7,8 describe in detail these various forms of ESDand AOC has previously shown the application of thesemodels to the oxide VCSEL9. Briefly, the Human Body Model(HBM) describes the discharge of a fully charged capacitor(~100pf), through an inductor (~10uH) and resistor (~1500Ω)in series with the device (where the values of the componentsused are intended to represent the electrical properties of the average human). The Machine Model (MM) describes thedischarge of a fully charged capacitor (~100pf) through asmaller inductor (~100nH) in series with the device. Here thecomponent values typify the circuit when a device is contactedby a charged metal object. In the Charged Device Model (CDM),the device discharges through a zero ohm, zero inductancecircuit. Figure 1 shows a comparison of the electrical signalsthat a device would experience via these models.

Historically, pinpointing the exact cause of ESD damage sothat improved controls can be implemented has proven to benotoriously difficult. However, if it is possible to determinewhich type of ESD event (HBM, MM, or CDM) is associatedwith a particular failure, it is then possible to determine howthe part is being exposed to ESD, thereby making it possibleto correct the issue. For example, a failure with HBM-typedamage would lead to better controls on factory employees –e.g. wrist straps, heel straps, etc. Damage induced by MMwould indict equipment fixtures or handling tools (tweezersfor example). CDM failures would most likely be caused byautomated equipment or improper device handling whichinduces charging on the devices. Thus, a means of narrowingthe search for the ESD source can lead to much faster actionsto prevent future failures.

VCSELS DAMAGED BY CHARGED HUMANS –THE HBM EVENT

The electrostatic discharge pulse from a charged human isslow and of lower magnitude relative to other models. Underthese conditions, current is restricted by the oxide apertureand the highest fluxes occur in the active area, near the oxideaperture9. Reverse bias ESD events dissipate more power thanforward bias events (i.e. due to the fact that the reversebreakdown voltage is about an order of magnitude greaterthan the forward voltage of the device) and thus, the VCSELhas a lower threshold of damage from reverse bias events.

Figure 1. Comparison of the signals from three common ESD events.Image courtesy of Joe Bernier, Intersil Corp.

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Figure 2. Reverse Bias IV trace from a device subjected to a RB HBMevent of 500V (red) and a known good device.

The power dissipation for a reverse bias event should occur inthe plane of the junction as is demonstrated below by thefailure analysis of a device subjected to an event slightly abovethe threshold (500V in this case) which causes immediateoutput degradation.

Electrical characterization (Figure 2) shows excessive reversebias leakage current and sub-threshold forward biaselectroluminescence, or emission, imaging (Figure 3) showsdark areas in the emission patterns. Both results demonstratea degradation of the diode properties of the device. Plan-view TEM analysis shows that the dark areas observed in theemission image correspond to large defects (i.e. dislocationtangles) within the active area of the device (Figure 4). Cross-section analysis of this type of defect (Figure 5) shows that the quantum well layers have fused in, and adjacent to, thedamage center and that a dense dislocation tangle existsthere. Dislocation tangles and loss of architecture also occur inother nearby high gallium-containing layers presumably duein part to the lower melting temperature and greater opticalenergy absorption in those lower bandgap layers.

Electrical characterization (Figure 6) of a device subject to aforward bias HBM ESD event (1800V; just above the thresholdfor output degradation) reveals no significant change in thediode properties of the device. Furthermore, there are no

Figure 3. Electroluminescence image from a device subjected to a RB HBM event of 500V.

Figure 4. Plan-view TEM micrograph showing the oxide andquantum well active layers from a reverse bias HBM degraded VCSEL.

Oxide tip

Fused quantum wells

Figure 5. Cross-section TEM micrograph of device subjected to 500VRB HBM ESD event.

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Figure 6. Reverse bias IV trace from device subjected to a FB HBMevent of 1800V (red) and a known good device.

easily recognizable dark area defects in the electrolumines-cence image (Figure 7). Plan-view TEM analysis (Figure 8)shows that the damage areas are located close to the oxideaperture where current densities are expected to be greatest.

The damaged area is smaller relative to the reverse bias case,presumably due to the lower power dissipation under forwardbias. Cross-section TEM analysis (Figure 9) of a similar defectshows relatively high mechanical stress (dark contrast) at theoxide tip and a single dislocation arching through the other-wise preserved active layers. Thus, the forward bias HBMevent may not cause sufficient damage to the active layers to be reflected in immediate degradation of the electricalproperties, though subsequent operation can extend thedislocations (i.e. by the growth of an array) in the active layers and lead to early failure.

Figure 7. Sub-threshold forward-bias electroluminescence image ofdevice subjected to a FB HBM event of 1800V.

Figure 8. Plan-view TEM micrograph showing the oxide andquantum well active layers from a forward bias HBM degradedVCSEL. The arrow indicates a dislocation tangle.

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Figure 9. Cross-section TEM micrograph of device subjected to FBHBM event.

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Figure 10. Reverse bias IV trace from a device subjected to a 100VMM ESD event (red) and a known good device.

DAMAGE CAUSED BY THE VCSEL ITSELF –THE CDM EVENT

Mishandling of a packaged VCSEL may lead to the triboelectricbuildup of a charge on the device. A CDM event may resultupon subsequent contact with another body at a differentpotential. Among ESD events, CDM pulses are of the highestmagnitude and shortest duration. Thus, the power dissipationis greater than for other ESD models and the damage thresholdfor VCSELs is expected to be low. For the high speed of thepulse, normally insulating elements of the VCSEL (e.g. theoxide layer) will become more conductive. Furthermore, SPICE modeling of ESD events in oxide VCSELs has shown that for a CDM event, the voltage expressed across the oxidelayer is easily sufficient to cause dielectric breakdown9.

To intentionally induce a CDM event for this work, a VCSELwas charged with an ion gun and subsequently discharged to a metal block. Electrical characterization (Figure 14) shows degradation of the diode properties of the device (e.g. increased reverse bias leakage and a soft-knee) while the electroluminescence image (Figure 15) shows no signi-ficant dark area defects. This data suggests that there is somedegradation of the active layers of the device but does notindicate the location. However, plan-view TEM analysis (Figure16) shows numerous damage sites in the oxide. The damageoccurs in circles of two different radii which may reflect aninitial discharge pulse (larger circle) and a subsequent pulsefrom the metal block back to the chip (smaller circle). Thedamage-type observed in the circle of greater radius hasnever been observed in devices that were subjected to HBM

Figure 11. Electroluminescence image from a device subjected to a100V MM ESD event.

oxide tip

Figure 13. Cross-section TEM image of a section lifted from the plan-view membrane shown in Figure 12 (dotted line box).

Figure 12. Plan-view TEM micrograph of device subjected to MM ESD event.

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Figure 14. Reverse bias IV trace from a device subjected to arelatively strong CDM ESD event (red) and a known good device.

or MM events. Cross-section TEM analysis of one of thesedamage sites in the oxide (Figure 17) shows dielectricbreakdown for which the crystallinity of the site is disrupted(likely due to local melting and freezing).

The damage extends vertically through the oxide layer evenphysically moving a section of the oxide in the image shown.Other cross-section analyses have shown damage sites thatextend vertically to the active layers of the device which isconsistent with the increased leakage current. In contrast,cross-section analysis (not shown) of the damage near theoxide aperture edge shows junction damage similar to, and in roughly the same location as, damage caused by MM ESD events.

DAMAGE FROM LONGER DURATIONELECTRICAL PULSES

Within the broader class of electrical overstress occurrences(of which the relatively short ESD events comprise a subset)the more severe cases of abuse are often detected with anoptical microscope (e.g. by the presence of cavities where the active area should be). However, weaker EOS events may generate outward characteristics that are similar to those observed in ESD-degraded devices.

Figure 15. Electroluminescence image from a device subjected to arelatively strong CDM ESD event.

Figure 16. Plan-view TEM micrograph showing the oxide andquantum well active layers from a CDM degraded VCSEL. The oxidelayer is populated by two circular distributions of damage sites.

Figure 17. Cross-section TEM micrograph through a defect caused bya CDM event.

Electrical characterization (Figure 18) of a device subjected to 5 minutes of 1% duty cycle 100ns 300mA pulses showsincreased leakage current and a lower breakdown voltage.Electroluminescence imaging (Figure 19) shows a non-uniform emission pattern with a “dim” area defect. Plan-viewTEM imaging (Figure 20) reveals punched-out dislocations

which have undergone some recombination enhanceddislocation growth. Thus, whereas the ESD causes localizeddamage sites, the short pulse EOS event appears to create a broader thermal stress, that acting on the active areagenerates dislocations at the oxide terminus.

ESD IN CUSTOMER-RETURNED DEVICES

Thus far, we have shown how the location and characteristicsof ESD damage in VCSELs depends on the electrical propertiesof the ESD source. The data shown (with the exception of theCDM example) was generated using standardized test circuits.In the field, VCSELs will be subjected to ESD sources that mayclosely resemble these circuit models but there will likely besome variation in the real-world circuit values from thosespecified in the models.

To conclude, we show evidence that the intentionally gener-ated ESD damage mechanisms explored here are found infield returns and that these ESD damage sites can act as thenucleation centers for dislocation arrays.

Figure 19. Electroluminescence image from a device subjected to ashort pulse EOS event.

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Figure 18. Reverse bias IV trace from a device subjected to a shortpulse EOS event (red) and a known good device.

Figure 20. Plan-view TEM micrograph showing the oxide andquantum well active layers from a forward bias EOS pulse degradedVCSEL. Several punched-out dislocations have moved through theactive area, segments of which have experienced recombinationenhanced dislocation growth.

The plan-view TEM data in Figure 21 shows that the dislocationarray found in a field return device was nucleated on damagethat appears to be due to a reverse bias HBM ESD. The factthat the centers of the damage occur at the oxide edgesuggests that the power was dissipated in a faster pulse than the HBM example shown in Figure 4.

Similarly, the plan-view TEM data shown in Figure 22demonstrates that a dislocation array can nucleate ondamage created by a what appears to be a CDM ESD event.

SUMMARY

In this paper we have shown how the degradation presentin an ESD damaged oxide VCSEL depends on the electrical

properties of the ESD source and subsequent pulse charac-teristics. The damage resulting from relatively slow ESDmodels (e.g. HBM) occurs well within the oxide confinementaperture. As the speed of the ESD pulse increases, thedamage occurs in a wider circumference as the impendenceof the oxide layer decreases and as greater bias is expressedacross the oxide layer. In general, the damage can extendfrom the mirror layers above the oxide layer though thequantum wells to the mirrors layers below. Where the damagedoes intersect the quantum wells, it is possible for a dislocationarray to grow. Laterally, the dislocation arrays nucleated onESD damage sites generally grow towards the active areawhere carrier concentrations are high. AOC has not observeddislocation array growth from the oxide trenches due to ESDor any other defect.

The ESD failure signatures revealed by this work have beenobserved in field returned devices. An understanding of thefailure signatures has improved AOC’s ability to assign a moreprecise root cause to those field returned devices. Knowingwhich the type of ESD caused the failure has greatly aided indetermining the source of the event and in implementingappropriate corrective action.

Figure 21. Plan-view TEM micrograph showing the oxide andquantum well active layers from a field-failed VCSEL that wassubjected to an HBM ESD event.

Figure 22. Plan-view TEM micrograph of a field-failed devicesubjected to a CDM event.

REFERENCES

1 D.T. Mathes, R. Hull, Kent Choquette, K. Geib, A. Allerman,J. Guenter, B. Hawkins, R. Hawthorne, “NanoscaleMaterials Characterization of Degradation in VCSELs”,Proc. of SPIE, vol. 4994, pp 67-83, (2003).

2 R. W. Herrick, Degradation in Vertical Cavity Lasers,Dissertation, Department of Electrical and ComputerEngineering, University of California, Santa Barbara, CA(1997).

3 R.W. Herrick, “Failure Analysis and Reliability ofOptoelectronic Devices,” published in “MicroelectronicsFailure Analysis Desk Reference, 5th ed.,” by ASMInternational, Materials Park Ohio, pp. 230-254 (2004).

4 Terence J. Stark, Phillip E. Russell, and Corey Nevers, “3-Ddefect characterization using plan view and cross-sectional TEM / STEM analysis,” to be published in theproceedings of ISTFA 2005 (this volume).

5 F. Siegelin, C. Brillert, “Failure Analysis of Vertical CavitySurface Emission Laser Diodes”, Proceedings from the29th International Symposium for Testing and failureAnalysis, p. 426, 2003.

6 J. Krueger, R. Sabharwal, S. McHugo, K. Nguyen, N.X. Tan,N. Janda, M. Mayonte, M. Heidecker, D. Eastley, M. Keever,and C. Kocot, "Studies of ESD-related failure patterns ofAgilent oxide VCSELs," Proc of SPIE, vol. 4994, pp. 162-172,(2003).

7 O. Mcateer, Electrostatic Discharge Control, (Mcgraw-HillPublishing Company, 1990).

8 S. Voldman, ESD Physics and Devices, (John Wiley andSons, 2004).

9 James K. Guenter, Jim A. Tatum, Robert A. Hawthorne III,Ralph H. Johnson, David T. Mathes, Bobby M. Hawkins, “Aplot twist: the continuing story of VCSELs at AOC, “ Proc ofthe SPIE, vol 5737, pp. 20-34, (2005).

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