an empirical guide to scalable persistent memory · persistent memory joseph izraelevitz, jian...

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An Empirical Guide to Scalable Persistent Memory

Joseph Izraelevitz, Jian Yang, Lu Zhang, Juno Kim, Xiao Liu, Amirsaman Memaripour, Yun Joon Soh, Zixuan Wang, Yi Xu,

Subramanya R. Dulloor, Jishen Zhao, Steven Swanson

Non-Volatile Systems LaboratoryDepartment of Computer Science & Engineering

University of California, San Diego

Department of Electrical, Computer & Energy EngineeringUniversity of Colorado, Boulder

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Optane DIMMs are Here!

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• Not Just Slow Dense DRAMTM

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• Not Just Slow Dense DRAMTM

• Slower, denser, media

-> More complex architecture

-> Second-order performance anomalies

-> Fundamentally different

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Basics: Emulation is misleading

RocksDB

OptaneDRAM

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Outline

• Background

• Basics: Optane DIMM Performance

• Lessons: Optane DIMM Best Practices

• Conclusion

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Background

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Background: Optane in the Machine

Core CoreCore

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Core Core

L1/2 L1/2

L3

Core

L1/2

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Core Core

L1/2 L1/2

L3

iMC iMC

Core

L1/2

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Core Core

L1/2 L1/2

L3

iMC iMC

Core

L1/2

DRAM

DRAM

DRAM

DRAM

DRAM

DRAM

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Core Core

L1/2 L1/2

L3

iMC iMC

Core

L1/2

DRAM

DRAM

DRAM

Optane DIMM

Optane DIMM

Optane DIMM

DRAM

DRAM

DRAM

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Core Core

L1/2 L1/2

L3

iMC iMC

AppDirectMode

Core

L1/2

DRAM

DRAM

DRAM

Optane DIMM

Optane DIMM

Optane DIMM

DRAM

DRAM

DRAM

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Core Core

L1/2 L1/2

L3

iMC iMC

Core

L1/2

AppDirectMode

DRAM

DRAM

DRAM

Optane DIMM

Optane DIMM

Optane DIMM

Optane DIMM

Optane DIMM

Optane DIMM

DRAM

DRAM

DRAM

Far MemoryNear Memory

(Direct Mapped Cache)

Memory Mode

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Core Core

L1/2 L1/2

L3

iMC iMC

Optane DIMM

Optane DIMM

Optane DIMM

DRAM

DRAM

DRAM

Far MemoryNear Memory

(Direct Mapped Cache)

Memory Mode Core

L1/2

AppDirectMode

DRAM

DRAM

DRAM

Optane DIMM

Optane DIMM

Optane DIMM

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Background: Optane Internals

$

MC

Optane

DRAM

Optane DIMM

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$

MC

Optane

DRAM

WPQ

iMC

Optane DIMM

From CPU

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$

MC DRAM

Optane Controller

WPQ

iMC

Optane DIMM

From CPU

Optane

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$

MC DRAM

Optane Media

Optane Controller

WPQ

iMC

Optane DIMM

From CPU

256B Block

Optane

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$

MC DRAM

Optane Media

Optane ControllerOptaneBuffer

WPQ

iMC

Optane DIMM

From CPU

256B Block

Optane

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$

MC DRAM

Optane Media


AIT Cache

AIT

WPQ

iMC

Optane DIMM

From CPU

256B Block

Optane

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$

MC DRAM

Optane Media


AIT Cache

AIT

WPQ

iMC

Optane DIMM

From CPU

256B Block

ADR (Asynchronous DRAM Refresh)

Optane

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Background: Optane Interleaving

• Optane is interleaved across NVDIMMs at 4KB granularity.

Optane4

Optane5

Optane6

Optane1

Optane2

Optane3

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Background: Optane Interleaving

• Optane is interleaved across NVDIMMs at 4KB granularity.

Optane4

Optane5

Optane6

Optane1

Optane2

Optane3

4 5 61 2 3

Phys. Addr: 4KB 12KB 20KB0 8KB 16KB

1

24KB

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Basics: How does Optane DC perform?

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Basics: Our Approach

• Microbenchmark sweeps across state space– Access Patterns (random, sequential)

– Operations (read, ntstore, clflush, etc.)

– Access/Stride Size

– Power Budget

– NUMA Configuration

– Address Space Interleaving

• Targeted experiments

• Total: 10,000 experiments

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Test Platform

• CPU– Intel Cascade Lake, 24 cores at 2.2 GHz in 2 sockets

– Hyperthreading off

• DRAM– 32 GB Micron DDR4 2666 MHz

– 384 GB across 2 sockets w/ 6 channels

• Optane– 256 GB Intel Optane 2666 MHz QS

– 3 TB across 2 sockets w/ 6 channels

• OS– Fedora 27, 4.13.0

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Basics: Latency

• 2x -3x as slow as DRAM

• Write latency masked by ADR

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Basics: Bandwidth

• ~Scalable reads, Non-scalable writes

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Basics: Bandwidth

• Access size matters

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Basics: Bandwidth

• A mystery!

*answer in ~10 minutes

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Lessons: What are Optane Best Practices?

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Lessons: What are Optane Best Practices?

• Avoid small random accesses

• Use ntstores for large writes

• Limit threads accessing one NVDIMM

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Lesson #1: Avoid small random accesses

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Optane Media


AIT Cache

AIT

WPQ

iMC

Optane DIMM

From CPU

256B Block

$

MC

Optane

DRAM

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Optane Media


AIT Cache

AIT

WPQ

iMC

Optane DIMM

From CPU

256B Block

$

MC

Optane

DRAM

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Optane Media


AIT Cache

AIT

WPQ

iMC

Optane DIMM

From CPU

256B Block

$

MC

Optane

DRAM

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Lessons: Optane Buffer Size

• Write amplification if working set is larger than Optane Buffer

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• Bad bandwidth with:

– Small random writes (<256B)

– Not tiny working set / NVDIMM (>16KB)

• Good bandwidth with

– Sequential accesses

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Lesson #2: Use ntstores for large writes

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• Non-temporal stores bypass the cache

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Lessons: Store instructions

ntstore store + clwb store

$

MC

Optane

DRAM

1

2

3

1

2

3

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Lessons: Store instructions

ntstore store + clwb store

$

MC

Optane

DRAM

1

2

3

1

2

3

*lost bandwidth *lost locality

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• Non-temporal stores bypass the cache

– Avoid cache-line read

– Maintain locality

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Lesson #3: Limit threads accessing one NVDIMM

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• Contention at Optane Buffer

• Contention at iMC

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Lessons: Contention at Optane Buffer

• More threads = access amplification = lower bandwidth

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Lessons: Contention at media & iMC

• iMCs queues are small & media is slow

– Short queues end up clogged

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• Contention is largest when random access size = interleave size (4KB)

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• Contention is largest when random access size = interleave size (4KB)

• Load is fairest when access size = #DIMMs x interleave size (24KB)

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• Contention at Optane Buffer

– Increase access amplification

• Contention at media/iMC

– Lose bandwidth through uneven NVDIMM load

– Avoid interleave aligned random accesses

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Conclusion

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Conclusion

• Not Just Slow Dense DRAM

• Slower media

-> More complex architecture

-> Second-order performance anomalies

-> Fundamentally different

• Max performance is tricky– Avoid small random accesses

– Use ntstores for large writes

– Limit threads accessing one NVDIMM

an empirical guide to scalable persistent memory · persistent memory joseph izraelevitz, jian...

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