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An FPGA-based frequency response analyzer for multisine and stepped sine measurements

on stationary and time-varying impedance

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2014 Meas. Sci. Technol. 25 015501

(http://iopscience.iop.org/0957-0233/25/1/015501)

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Measurement Science and Technology

Meas. Sci. Technol. 25 (2014) 015501 (12pp) doi:10.1088/0957-0233/25/1/015501

An FPGA-based frequency responseanalyzer for multisine and stepped sinemeasurements on stationary andtime-varying impedance

B Sanchez1, X Fernandez, S Reig and R Bragos

Electronic and Biomedical Instrumentation Group, Department of Electronic Engineering, UniversitatPolitecnica de Catalunya (UPC), E-08034, Barcelona, Spain

E-mail: benjamin.sanchez@upc.edu

Received 2 August 2013, in final form 15 October 2013Published 26 November 2013

AbstractWe report the development of a field programmable gate array (FPGA) based frequencyresponse analyzer (FRA) for impedance frequency response function (FRF) measurementsusing periodic excitations, i.e. sine waves and multisines. The stepped sine measurement usestwo dedicated hardware-built digital embedded multiplier blocks to extract the phase andquadrature components of the output signal. The multisine FRF measurements compute thefast Fourier transform (FFT) of the input/output signals. In this paper, we describe its design,implementation and performance evaluation, performing electrical impedance spectroscopy(EIS) measurements on phantoms. The stepped sine accuracy is 1.21% at 1 k� (1%), theprecision is 35 m� and the total harmonic distortion plus noise (THD+N) is −120 dB. As forthe multisine impedance FRF measurements, the magnitude and phase precision are,respectively, 0.23 � at 48.828 kHz and 0.021 deg at 8.087 MHz when measuring a resistor505 � (1%). The magnitude accuracy is 0.55% at 8.087 MHz while the phase accuracy is0.17 deg at 6.54 MHz. In all, the stepped sine signal-to-noise ratio (SNR) is 84 dB and 65 dBat frequencies below and above 1 MHz respectively. The SNR for the multisine FRFmeasurements is above 65 dB (30 kHz–10 MHz). The FRA bandwidth is610.4 mHz–12.5 MHz and the maximum FRF measurement rate exciting with multisinesstarting at 30 kHz is 200 spectra s−1. Based on its technical specifications and versatility, theFRA presented can be used in many applications, e.g. for getting insight quickly into theinstantaneous impedance FRF of the time-varying impedance under test.

Keywords: frequency response analyzer (FRA), frequency response function (FRF), electricalimpedance spectroscopy (EIS), time-varying impedance, multisine FRF measurements,stepped sine FRF measurements, digital detection hardware

(Some figures may appear in colour only in the online journal)

1. Introduction

Instrumenting state-of-the-art impedance frequency responseanalyzers (FRA) requires a dedicated hardware and robust

1 Present address: C/Jordi Girona 1–3, Department d’Enginyeria Electronica,Ed C4 Campus Nord, Universitat Politecnica de Catalunya (UPC), E-08034,Barcelona, Spain.

software architecture, along with an external analogue frontend (AFE) to interface the electrodes (Bragos et al 1994,Denyer et al 1994, Ross et al 2003, Saulnier et al2006, Hong et al 2009, Yang et al 2011). Despite thegood accuracy of impedance bridges (Geddes et al 1971,Awad et al 1994), phasemeters (Barnett and Bagno 1935)and phase sensitive detectors (such as those found in

0957-0233/14/015501+12$33.00 1 © 2014 IOP Publishing Ltd Printed in the UK

Meas. Sci. Technol. 25 (2014) 015501 B Sanchez et al

lock-in amplifiers) (Ackmann 1993), recent advances ininstrumentation technology have allowed many applications tobenefit from low-cost (10–100 $) impedance converter systemsincluding direct digital synthesizer (DDS) and analogue-to-digital converters (ADC/DAC) (Seoane et al 2008, Margo et al2013, Sanchez et al 2013c). However, it is not always feasibleto use these DDS-spectroscopy based devices to measureimpedance accurately. Although the DDS architecture allows asimple and low-cost implementation of an arbitrary waveformgenerator (AWG) (it requires just a fixed sampling clockand, as a consequence, a single interpolation low-pass filter),depending on the phase increment value, a given sample maybe read more than once, or one or more contiguous samplesmay be skipped. While this behavior may be acceptable forrelatively low frequency and smooth waveforms, it can beunacceptable when spectral purity and timing accuracy arerelevant, as the DDS architecture inherently produces jitter inthe signal.

In these situations, the most commonly adopted solutionfrom an instrumentation standpoint is to implement a systemincluding a signal AWG architecture, the signal acquisitionand the on-board signal processing (Sanchez et al 2011,Mohamadou et al 2012, Trebbels et al 2012). In 2011, wedesigned our current PCI Extensions for Instrumentation(PXI)-based arbitrary impedance FRA. The system includesan embedded dual-core controller, PXIe-8130, running theLabVIEW software, a 2-channel high-speed digitizer card,PXIe-5122 (100 Ms s−1, 64 MB/channel, 14 bits), an8-channel high-density digitizer card, PXI-5105 (60 Ms s−1,128 MB, 12 bits), and an arbitrary waveform card PXI-5422 (200 Ms s−1, 32 MB, 16 bits). The system is capableof continuously generating an arbitrary reference excitationand acquiring and storing multiple acquisition channels ata maximum sampling rate of 5 Msamples s−1. For that,data streaming from the digitizers to the controller hard-disk is performed to store the sampled data in real-time.The impedance frequency response function (FRF) and itsuncertainty bounds (noise and nonlinear distortions) areestimated in Matlab (Sanchez et al 2013a, 2013b).

In this paper we describe the design and implementationof a fully digital field programmable gate array (FPGA)-basedFRA for FRF measurements using periodic excitations. Theperformance is evaluated by means of electrical impedancespectroscopy measurements on stationary (time-invariant)and time-varying phantoms. This new FRA aims to be areduced size, performance and cost version of our high-performance PXI-based FRA which can be easily duplicatedto match our current needs. The system developed implements(i) the AWG, (ii) the signal acquisition and (iii) the on-board signal processing. To this end, we chose the FPGAStratix III evaluation board from Altera along with theADC/DAC hardware shown in figure 1. The user’s interface isprogrammed in LabVIEW. The system developed comprisesa computer as a controller connected via a USB 2.0 to theevaluation board. To interface the frequency response analyzerwith the electrodes we developed a custom voltage controlledcurrent source (VCCS) AFE.

Input Channel A

Input Channel B

JTAGUSB 2.0 to PC

Power supply

Arbitrary signal

Analogue front end

DDR2

14 cm

16 cm

8 cm 5 cm

Electrodesconnector

Figure 1. The core of the FRA is based on the FPGA Stratix III DE3evaluation board from Altera. The system communicates with thePC control software via USB. The ADC/DAC signal board isconnected through an expansion connector. The AFE is interfacedwith the reference signal and the acquisition input/output signals.

2. System description and specification

Figure 2 shows a top-level hardware description of the system.The system architecture consists of three different modules inorder to provide high versatility: (i) the FPGA core unit, (ii)the reconstruction and anti-alias filters (Mini-Circuits 15542SLP-15+) and (iii) the AFE (see section 2.1). The signalgeneration/acquisition and data processing is implementedin the FPGA-core unit. Additionally, there are two signalchains: one for digital-to-analogue (D/A) reference signalgeneration and the other for the analogue-to-digital (A/D)signal input–output signals acquisition. Both chains are based,respectively, on a high-speed 1 dual A/D converter AD9248(14 bit resolution, 65 Ms s−1) and 1 dual D/A converterAD9767 (14 bit, 125 Ms s−1).

The designed hardware is programmed in hardwaredescription language using Quartus II 11.0 SP1 tool of Altera.Simulations are performed in Modelsim, and Altera SignalTapis used for on-chip program debugging. The developmentplatform is based on the FPGA Stratix III 3SL150 from Altera.The FPGA includes 142 K logic elements, 5.499 K totalmemory Kbits, 384 18 × 18 bit multiplier blocks and 736user I/Os. The implemented FPGA-hardware architecture asshown in figure 3 includes an embedded soft microprocessorNios II operating at 266 MHz, an external 1 GB DDR2 memory(266 MHz), an AWG block, the digital signal processing blockand the ADC/DAC communication blocks. The next sectionsdescribe in detail the working principle of each of these blocks.

2.1. Unipolar voltage controlled current source-based (VCCS)analogue front end (AFE)

To measure impedance with an FRA, an electronic circuit, i.e.AFE, is needed to interface the electrodes with the reference,input and output channels. The AFE’s function is to measure

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Meas. Sci. Technol. 25 (2014) 015501 B Sanchez et al

50 MHz

STRATIX III EP3SL150

DDR2

USB 2.0

JTAG

AD9248

AD9767

RECONSTRUCCION FILTER

ELECTRODEFPGA CORE UNIT

ANTI-ALIAS FILTERS

ANALOGUEFRONT

END

Figure 2. Functional block diagram of the arbitrary impedance FRA. The system consists of an FPGA Stratix III 3SL150, a dual A/Dconverter AD9248 (14 bit, 65 Msamples s−1 ) and a dual D/A converter AD9767 (14 bit, 125 Msamples s−1). The AFE (see section 2.1 fordetails) and the reconstruction and anti-alias filters are shown in gray and can be replaced according to the application requirements.

50 MHz

FPGA

USBdevice

JTAG

USB controller

DDR2 controller

NIOS II processor

DDR2memory

ArbitraryWaveformGenerator

Clock Control

266 MHz

DigitalSignal

Processing

DACCommunication

ADCCommunication

ANALOGUEFRONT

END

r(t)

u(t)

y(t)

AD9767

AD9248

Figure 3. Architecture diagram of the embedded digital hardware: r(t), u(t) and y(t) are, respectively, the arbitrary reference excitation(a sine wave or a periodic broadband signal, i.e. multisine) and the input–output signals.

and adapt the current i (t) and voltage drop v (t) of theimpedance under test Z(ω, t) when a reference signal r(t)is applied (in V or A) (Denyer et al 1994, Ross et al 2003,Saulnier et al 2006, Hong et al 2009, Yang et al 2011).

The AFE shown in figure 4 is an evolution of theprevious systems developed in our group. It includes aVCCS, a transimpedance amplifier and a wideband differentialamplifier. Although it is possible to measure impedanceimplementing a voltage source-based AFE, we chose acurrent source (CS)-based structure because a CS AFE leadsto an open-loop frequency-domain impedance identificationproblem (Sanchez et al 2013b).

The VCCS was previously described in Bragos et al(1994) and it is based on the AD844 current feedback amplifierfrom Analog Devices. The internal structure of this amplifierincludes a second generation current conveyor followed by avoltage buffer. The working principle of the AFE is as follows.The reference signal r(t) is applied to the high input impedanceY node and copied to the low impedance X node generating aninput current with 1 mA V−1 gain. The input current via the Xnode is copied (conveyed) to the Z node which constitutes the

VCCS output high current terminal with a characteristic outputimpedance of about 3 M� // 4.5 pF. The residual output dccurrent is blocked by a series capacitor for safety purposes. Toavoid driving the current source to saturation because of thisdc residual current, a dc feedback circuit (gain 10, bandwidth16 Hz) is inserted in the circuit loop.

The unity-gain differential amplifier is based on theresistor-free wideband differential amplifier AD8130 (CMRR70 dB at 10 MHz). To enhance its input impedance, twoOPA656 FET-input wideband operational amplifiers are used.Their inputs are coupled through a series capacitor to the lowand high voltage terminals, LPOT and HPOT respectively. AT-network of 10 M� resistors provides a path for the OPA656bias current while keeping high differential and common-mode input impedances. To reduce the LPOT and HPOT inputcapacitances when coaxial cables are used between the AFEand the electrodes, we added two optional driven-guard circuitsconnected to the cable shields. The driven-guard circuits arebased on a voltage follower and an RC network that limits theblock gain to 0.8 above 1.6 MHz to avoid oscillations. Finally,an OPA656-based transimpedance amplifier (1 V mA−1) is

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Meas. Sci. Technol. 25 (2014) 015501 B Sanchez et al

+-

OPA656

+-

100p

1k220

1uOPA65610M

10M10M

+-

+-

OPA656

1u

OPA656

220

100p1k

+-

AD8130

HCUR

LCUR

LPOT

HPOT

Impedanceundertest

+-

YX

Z

AD844

AD8038

1k10k

100k

100n

1k

0

0

1u

+

−1

+-

1u

OPA656

1k

10p

Output

Input

Referencer(t)

y(t)

u(t)

Active guard

DC feedback

Active guard

Figure 4. Schematic of the voltage controlled current source-based(VCCS) analogue front end designed to interface the FRA with theimpedance under test. The notation for the electrodes is high current(HCUR), high potential (HPOT), low potential (LPOT) and lowcurrent (LCUR). Note that the integrated circuits not visible in thetop layer shown in figure 1 are soldered at the bottom layer of theAFE.

used to measure the current through the impedance undertest.

2.2. Clock control block

The clock frequencies are generated with a single hardware-built phase-locked loop (PLL) circuit (refer to figure 5). Theinput PLL clock frequency is driven by an external 50 MHzoscillator. The PLL parameters (the pre-divider, the feedbackmultiplier and the post-divider counters), are parameterized togenerate 266 MHz, 50 MHz, 5 MHz and 5 kHz clock signals.The 266 MHz clock is used for the Nios II embedded processorand the external DDR2 memory (see section 2.3). The otherclock frequencies are driven to a multiplexer, after which theselected global clock fGCLK ∈ {50 MHz, 5 MHz, 5 kHz} isdriven to the AWG and the signal processing blocks describedin section 2.4 and section 2.5 respectively. The global clockfGCLK source selection can be dynamically changed by theNios II output pins by changing the clock multiplexer selectorinputs. This block also enables dynamic powerdown of theglobal clock to disable some parts of the hardware to reducepower consumption. Importantly, the global clock fGCLK

reaches all hardware blocks with the same skew.

2

GCLK

POWERDOWN

CLKSELECT [1..0]

Enable/DisablePLL

RESET

ENABLE

EXTCLK50MHz

CLK266MHz

Figure 5. Schematic of the global clock control block. The FPGAinternal global clock can be selected dynamicallyfGCLK ∈ {50 MHz, 5 MHz, 5 kHz} to adjust the arbitrary frequencyresponse analyzer bandwidth. The 266 MHz clock signal is usedonly for the embedded processor and external DDR2 memory.

2.3. Nios II soft microprocessor

Nios II is a 32-bit RISC soft embedded-processor architecturedesigned and implemented using logic synthesis. The programcode for the Nios II processor is located in an external memoryDDR2 with 1 GB capacity operating at a clock frequencyof 266 MHz. The Nios II processor is designed to includethe DDR2 memory controller to interface the external DDR2memory, the USB controller interface to communicate directlywith the computer and general purpose input/output pins/busfor the internal control of the hardware.

The microprocessor is programmed with Eclipse-basedNios II software build tools for Eclipse. The Nios II codeimplements a state machine to communicate via USB 2.0 toLabVIEW-based user interface software running on a personalcomputer. The main tasks are (i) the storage of samples ofthe arbitrary reference signal and (ii) the control of internalhardware.

2.4. Arbitrary waveform generator (AWG) block

The digital hardware architecture implemented to generate thereference excitation corresponds to the working principle of atrue AWG. Unlike the DDS where the DAC works at a fixedsample rate and the signal repetition rate of the waveformstored in memory is controlled by changing the value to beadded to a phase accumulator, here the access to the waveformmemory is sequential at a variable sampling rate.

The AWG implementation shown in figure 6 stores thesamples corresponding to one period of the arbitrary referencesignal in a waveform memory, synthesized with a dual portRAM memory with a dedicated data and address bus (14 bitsdata, 65536 samples memory depth). The write operation inthe RAM is controlled by the Nios II by forcing to high-levelthe write request signal. The output RAM data REFDAC aredriven to the AD9767 D/A converter. If the user selects thephase and quadrature (IQ) demodulator, one RAM memorycontains in REFDAC the samples of a sine wave while thesamples of a 90◦ phase shift cosine wave are stored in anadditional RAM. Otherwise, REFDAC is an arbitrary spread-spectrum excitation and the second RAM is disabled sincethe demodulation is performed with the fast Fourier transform(FFT) (see section 2.5).

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Meas. Sci. Technol. 25 (2014) 015501 B Sanchez et al

CLK266MHzWREQ1

GCLK

RAMADDR1 [15..0]

SIGNAL1 [13..0]

REF_DAC [13..0]

GCLK

CLK266MHzWREQ2

GCLK

RAMADDR2 [15..0]

SIGNAL2 [13..0]

COS [13..0]Q

I

COUNTERADDR1 [15..0]

GCLKENABLE

COUNTER

GCLKQENABLE

ADDR2 [15..0]

AD9767

Figure 6. Dual-port RAM-based hardware implementation of the arbitrary reference generation block. The RAMs store the waveformsamples, e.g. a sine/cosine wave or an arbitrary broadband excitation depending on the demodulation technique.

GCLKWREQ

RREQ

GCLK

GCLKWREQ

RREQ

GCLK

COS [13..0]

REF_DAC [13..0]

DATA_CHANNEL_A [13.0]

QUAD[31..0]

PHASE[31..0]

AVG[13..0]

AVG[13..0]

I [31..0]

Q [31..0]

dcFIFO

GCLKWREQ

RREQ

FFT(8192)

GCLK

GCLKWREQ

RREQ

FFT(8192)

GCLK

DATA_CHANNEL_A [13..0]

DATA_CHANNEL_B [13..0]

dcFIFO

dcFIFO

dcFIFOreal_Y [31..0], imag_Y [31..0]

real_U [31..0], imag_U [31..0]

(SIN [13..0])

(SIN WAVE)

(A)

(B)

Figure 7. Functional block diagram based on the fast Fourier transform (FFT) to calculate {U (k),Y (k)} the complex Fourier coefficients atthe excitation bins k of the input–output signals available in channels A and B (A); diagram of digital coherent lock-in detection hardwareimplemented on the output signal available in channel A (B).

Regarding the signal generation, the Nios II loads intothe counters the number of samples stored in the RAM.Next, the address counters are enabled. The samples in theRAM memory are read consecutively. When the counters’value reaches the last memory location, a reset pulse isgenerated by combinatorial logic such that the counter valueis initialized to its default value (first memory address).The reference excitation is generated continuously until thecounters are disabled by the Nios II. Ultimately, the waveformgenerator block and the signal processing block are completelysynchronized to avoid spectral leakage.

The excitation bandwidth of the arbitrary reference signalblock depends on the global clock fGCLK selection. The

lowest frequency that can be generated corresponds to asignal with just one period stored in the RAM memoryand fGCLK = 5 kHz, this is fmin = fGCLK

2n = 76.3 mHz.Regarding the theoretical upper generation frequency, this isgiven by the Nyquist frequency when fGCLK = 50 MHz, i.e.fmax = fGCLK

2 = 25 MHz. However, we do not measure abovefmax = 12.5 MHz to ensure that the minimum number ofsamples within a cycle of a sine wave is fGCLK

fmax= 4.

2.5. Signal processing block

This block can perform (i) an FFT-based demodulation onthe input–output signals or (ii) a phase/quadrature (IQ)coherent output signal demodulation (see figure 7 (A)

5

Meas. Sci. Technol. 25 (2014) 015501 B Sanchez et al

(A) (B)

(C) (D)

Figure 8. IQ output magnitude for 2000 consecutive experiments of a resistance of 510 � (1%) measured at f0 = 625 kHz and N = 8192(A); μ and σ are the mean value and standard deviation respectively; histogram (B) corresponding to data shown in (A); resistance to IQresistance transfer curve from 100 to 1000 � (1%) (C); IQ resistance transfer curve error (D).

and (B) respectively). As for the FFT-based demodulationtechnique, the Fourier coefficients at the user definedbins, e.g. at the excitation frequencies, are stored in twointernal dual clock FIFOs for Nios II data synchronization(dcFIFOs in figure 7(A)). The lowest frequency that canbe analyzed with the FFT-based impedance frequencyresponse analyzer is fmin � fGCLK

M = 610.4 mHz, withM = 8192, the number of FFT points and fGCLK = 5 kHz.As for the highest frequency, this is fmax = 12.5 MHz (seesection 2.4). Although it is possible to excite the systemunder test with non-periodic excitations, i.e. random noise, wehave not implemented any hardware in the signal processingblock to minimize the spectral leakage as we only contemplateperforming FRF measurements with periodic signals, i.e. sinewaves and multisine excitations.

Regarding the IQ demodulation, the reference sinewave REFDAC and the corresponding 90◦ phase shiftedcosine wave COS are driven internally to the hardware-built multiplier–adder structure shown in figure 7(B). Thenumber of sample averages is determined by the value ofthe bus AVG[13..0] which can be modified dynamicallyby the Nios II. The possible numbers of samples averagedare N ∈ {8192, 4096, 2048, 1024, 512}. The bandwidth ofthe IQ demodulator is the same as the block of arbitrarysignal generation (see section 2.4, fmin � 610.4 mHz and

fmax = 12.5 MHz). The output IQ sampling frequency is givenby the ratio fGCLK

N , 97.656 kHz ( fGCLK = 50 MHz, N = 512) and610.3516 mHz ( fGCLK = 5 kHz, N = 8192) being the fastestand lowest output IQ sampling frequencies respectively.

3. Experimental results

In order to evaluate the FRA implemented, we carried outstepped sine and multisine FRF measurements on stationaryand time-varying impedance phantoms in sections 3.1.1–3.1.3and 3.2.1–3.2.3 respectively.

The phantoms were connected with an adaptor to theelectrode connector in figure 1. High current/voltage andlow current/voltage terminals (see figure 4) were shortcutsrespectively to perform 2-terminal electrode free impedancemeasurement.

3.1. Stepped sine FRF measurements

3.1.1. Precision, accuracy and linearity. To characterize thecoherent phase and quadrature IQ demodulator, we generate asine wave excitation at f0 = 625 kHz, fs = fGCLK = 5 MHz, thesampling frequency. The averaging filter is N = 8192 such thatthe IQ output sampling frequency is 610.3516 Hz. Figure 8(A)shows the mean value μ = 1.4685 × 107 (counts) and the

6

Meas. Sci. Technol. 25 (2014) 015501 B Sanchez et al

0

(A) (B)

Figure 9. Simulated total harmonic distortion (THD) (A) and measured THD plus noise (THD+N) (B) at the output of the IQ demodulatorconsidering 1024 cycles of a sine wave ( f0 = 625 kHz, fs = 5 MHz the sampling frequency and N = {8191, 8192} the length of theaveraging filter).

standard deviation σ = 452 (counts) of 2000 consecutiveexperiments of a resistor of 510 � (1%). The reader canobserve in figure 8(B) the Gaussian-like noise nature presentat the output of the IQ demodulator when fitting the histogramdata to a normal probability density function.

To test the IQ linearity, we measured a set of ten resistorsfrom 100 to 1000 � (1%). As can be observed in figure 8(C),the IQ works in a linear region (R2 = 0.998 23) for the rangeof resistors measured. The linear relationship between the IQoutput magnitude and the resistance R given by the followingformula √

I2 + Q2 = aR + b, (1)

was determined in Matlab performing a linear regressionwith a = 2.6 × 104 and b = 1.4851 × 106, the gain andoffset coefficients respectively. The resultant root mean squareerror (rmse) shown in figure 8(D) is 12.1 �, this is 1.21 %accuracy at full scale. Given (1), the estimated resistance andprecision (95.45% confidence interval, 2σ ) for the data shownin figure 8(A), (B) are 507.7 � and 35 m� respectively.

3.1.2. Total harmonic distortion plus noise (THD+N) andsignal-to-noise ratio (SNR). The measurement frequencieschosen to characterize the IQ frequency response are f0 ∈{39.0625, 78.125, 156.25, 312.5, 625, 1250, 3125, 6250,

12500} kHz. Consequently, note that an integer number ofperiods is averaged in N samples, i.e. N = k fs

f0with k ∈ N,

fs = fGCLK ∈ {5, 50} MHz being the ADC/DAC samplingfrequency selected to generate f0. In that way, the zerosof the frequency response filter match a natural multipleof the frequency f0, achieving the best possible harmonicsuppression for this particular IQ demodulation structure(Wellstead 2003). To verify that, we simulated in Matlab thetheoretical total harmonic distortion (THD) rejection of anoiseless IQ demodulator. The intermediate frequency signal

to demodulate corresponds to a sine wave (1024 cycles), f0 =625 kHz being the fundamental frequency of the sine waveand fs = 5 MHz. It can be seen in figure 9(A) that when theaveraging filter is set to N = 8192, the THD is −288 dB,limited by the Matlab precision. By forcing N �= k fs

f0with

k ∈ N, for example considering N = 8191, the THD increasesto −84 dB.

To ensure that indeed the simulations predict the correctbehavior of the hardware implemented, we measured infigure 9(B) a 510 � resistor with the same setup as theMatlab simulations. By setting N = 8191 and consideringonly the contribution of the second order harmonic, it can beseen that the THD+N is −82.6 dB while the predicted THDgiven by the simulations in (A) is −84 dB. An estimate of theharmonic distortion due to measurement (and quantization)noise at this frequency follows from THD − THD+N, this is2.6 dB. In general, the value of the THD+N will depend onthe combination of f0 and N as the averaging filter frequencyrejection curves will change. For the frequencies f0 evaluated,the THD+N is given mainly by the equivalent noise bandwidthof the averaging filter as the harmonics are indeed suppressedin the spectrum by the zeros of the averaging frequencyresponse filter. The THD+N is as low as −120 dB (seefigure 9(B)) when N = 8192 (THD+N � 10−12%), this beingthe best scenario.

Regarding the signal-to-noise ratio (SNR), the valuesare shown in table 1. The fact that the SNR deteriorates20 dB over 1 MHz is not unexpected since, for the sameN samples averaged, the equivalent noise bandwidth ofaveraging filter when fs = 50 MHz is ten times larger thanfs = 5 MHz.

3.1.3. Instantaneous FRF measurement of time-varyingimpedance Z (ω, t ). Finally, figure 10 shows the suitability

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Meas. Sci. Technol. 25 (2014) 015501 B Sanchez et al

(A)

(B)

(C)

Figure 10. Temporal evolution of the raw impedance data (black) measured with the IQ demodulator at f0 = 156.25 kHz (N = 8192)using the patient simulator Fluke PS420. The patient simulator respiration parameters are R = 500 � and �R = {3, 0.5, 0.2} � (A–C).The red temporal impedance evolution corresponds to the IQ data filtered with a low pass Butterworth filter (5th order, 1 Hz cutofffrequency).

Table 1. SNR of the coherent phase and quadrature IQ demodulator considering N = 8192 the number of samples averaged.

39.0625 kHz 78.125 kHz 156.25 kHz 312.5 kHz 625 kHz 1.250 MHz84.6 dB 85.2 dB 86.4 dB 85.5 dB 89.5 dB 64.0 dB

3.125 MHz 6.25 MHz 12.5 MHz69.38 dB 69.74 dB 68.13 dB

of the IQ demodulator to track and detect time-varyingelectrical impedance Z(ω, t) at a single frequency fk, i.e.fk = ωk

2π. The impedance temporal dependence is generated

using the patient simulator Fluke PS420 emulating respirationimpedance changes. The parameters of the patient simulatorare baseline R = 500 � and peak-to-peak impedance amplitude�R = {3, 0.5, 0.2} �. The impedance is measured at f0 =156.25 kHz with N = 8192. The results shown in figure 10confirm the IQ-based capabilities of detecting with precisionand accuracy the temporal changes in impedance, beingpossible to detect changes less than 100 m�.

3.2. Multisine FRF results

To determine the ability to perform multisine FRFmeasurements, we synthesized a periodic multisine excitationr[n]

r[n] =∑

k ∈Kexc

Rk sin

(2π

k

TmsnTs + ϕk

), (2)

with Tms = 1 ms being the period of the multisine andfs = 1

T s = fGCLK = 50 MHz the sampling ADC/DACfrequency. The amplitudes Rk � 0 are chosen to be equal(flat multisine) and the phases ϕk are randomly chosen in

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Meas. Sci. Technol. 25 (2014) 015501 B Sanchez et al

(A) (B)

Figure 11. (A) Magnitude and phase frequency dependence corresponding to an electrode-free resistor 505 � (1%). The error bars denotethe impedance spectrum standard deviation of 1000 experiments. (B) Impedance SNR of data shown in (A).

(B)(A)

Figure 12. (A) Magnitude and phase frequency dependence corresponding to an electrode-free RC phantom measurement. The error barsdenote the impedance spectrum standard deviation of 1000 experiments. (B) Impedance SNR of data shown in (A).

the interval [0, 2π) (Sanchez et al 2012). Kexc is the setof excited bins corresponding to F = 25 frequencies quasilogarithmically distributed from fmin = 30 kHz to fmax =10 MHz according to

fn = α fn−1 ∀n ∈ {2, . . . , F}, (3)

for a given lower measurement frequency f1 = fmin anda frequency ratio α > 1. The parameter α can be readilyextracted as the number of measurement frequencies F withinthe frequency range of interest is known

F =⌊

log10 fmax − log10 fmin

log10α

⌋, (4)

where the operator �•� stands for nearest lower integer.To avoid spectral leakage, an integer number of periods

of the multisine excitation was measured and the entiremeasurement setup was synchronized with the referenceexcitation (2). The input–output signals were passed throughthe anti-alias filters (see schematic in figure 2) before thesignals were sampled, such that aliasing was also avoided.

3.2.1. Impedance signal-to-noise ratio (SNR). Given thatthe reference excitation (2) is by construction periodic andan integer number of periods is measured/processed, i.e.P = MTs

T ∈ N, with T and Ts the period of the referenceexcitation and Ts = 1

fGCLKthe sampling interval between

samples respectively, a consistent impedance spectrumestimator Z (ωk) when P → ∞ is obtained from the divisionof the input–output sample mean Fourier coefficients at theexcited bins k (Pintelon and Schoukens 2012), namely

Z(ωk) = Y (k)

U (k)=

1P

∑Pp=1 Y [p](k)

1P

∑Pp=1 U [p](k)

, (5)

with ωk = 2π kT ,

{Y [p],U [p]

}the excited DFT bins of the pth

period of the input–output signals calculated in real time in theFPGA (see section 2.5). Afterwards, Z (ωk) is divided by thecalibration (admittance) frequency response with units �−1 toget a meaningful impedance estimate in � units performinga three-reference calibration method (Bao et al 1993). The

9

Meas. Sci. Technol. 25 (2014) 015501 B Sanchez et al

(A)

(B)

(C.1) (C.2)

Figure 13. Time–frequency representation of the impedance spectrum (A). Mean impedance spectrum over 1000 experiments (black) (B);the red lines denote the maximum and minimum impedance values at each frequency respectively. Details of the impedance dynamics at48.83 kHz (C.1) and 634.77 kHz (C.2).

values of the reference resistors measured to perform the three-reference calibration procedure are Rref ∈ {50, 427, 624} �

(1%).To determine the quality, we performed 1000 experiments

on a resistance of 505 � (1%) (see figure 11(A)). Theimpedance magnitude and the phase uncertainty noise analysisis performed averaging at the level of the magnitude andphase spectrum estimated in (5). The worst standard deviationvalues for the resistor measured are 0.23 � at 48.828 kHzand 0.021 deg at 8.087 MHz. The largest absolute error is2.78 � (0.55% relative error) at 8.087 MHz and 0.17 deg at6.54 MHz. The impedance SNR is shown in figure 11(B),66.6 dB at 48.83 kHz and 71.8 dB at 512.7 kHz being theworst and the best measurements respectively.

3.2.2. Multisine FRF measurements on an RC phantom. Wecarried out 1000 multisine FRF experiments on an RC phantomin figure 12(A) (black). A commercial impedance analyzerHP4192A was used as a reference for comparison (grey).Visually, the reader can see the good agreement betweenmeasurements, even having done the multisine measurementsin much less time compared to the several tens of secondsneeded by the HP4192A. The quality of the measurements aresummarized in the form of the SNR in figure 12(B), beingabove 65 dB at the excited frequencies.

3.2.3. Multisine FRF measurements on a time-varyingimpedance Z (ω, t ). To generate an impedance FRF that istime-varying to some extent, we modulated an RC phantomincluding a light-dependent resistor with a light emitting diode

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Meas. Sci. Technol. 25 (2014) 015501 B Sanchez et al

(LED). The reason why we did not measure the patientsimulator Fluke PS420 is that this device has a limitedfrequency response (< 200 kHz). The temporal evolutionof the impedance is then obtained by applying to the anodeof the LED a sine wave with a peak-to-peak amplitude ofVPP = 0.5 V, a dc amplitude of VDC = 2.5 V and a sinusoidalperiodicity of TZ = 1 s.

In total 1000 consecutive periods are processed, andthe time–frequency evolution of the impedance spectrumcan be observed in figure 13(A). The maximum frequencyresponse measurement rate exciting with multisine signals(25 frequencies, 30 kHz–10 MHz) is 200 spectra s−1. Infigure 13(B), we show in black the mean magnitude and phasespectrum at the excitation frequencies, and in red the maximumand the minimum values of the impedance frequency responseare depicted to show the time-varying dynamic range in thefrequency domain. Finally, the figures shown in (C) illustratein black the temporal evolution of the impedance spectra oftwo specific frequencies.

4. Discussion

Techniques to measure impedance based on broadbandimpedance FRF measurements have gained increasingattention in recent years (Sanchez et al 2013b). Accordingto the excitation used, the measurement methods available canbe classified into (i) frequency-domain and (ii) time-domainmethods. Although step-based time-domain spectroscopysystems are interesting for their relatively simple hardwarerequirements (Barsoukov et al 2002, Huang et al 2011), thelimited accuracy and frequency band inherent to this workingprinciple make this approach inappropriate for accuratewideband (MHz) FRF measurements. Instead, frequency-domain based methods are more convenient for extracting theFRF with good accuracy (Schoukens et al 2000).

Regarding frequency-domain approaches, the mostcommon is to measure the impedance FRF with the steppedsine technique. Several options are possible, depending on theexperiment. For example, Mohamadou et al (2012) developedan FRA implementing a least square algorithm for stepped sineimpedance FRF measurements with an SNR above 60 dB from10 Hz to 2.2 MHz. A more recent contribution can be foundin Li et al (2013), where the authors based their stepped sineimpedance FRA on a digital auto-balancing bridge measuringtechnique.

Compared to the system described in Li et al (2013),our system’s impedance accuracy working with the IQdemodulator is similar for the range of the impedance loadstested (100 � to 1 k�). The magnitude of the relative errorvaries between 0.1% and 1.5% and the SNR is above 84 dBbelow 625 kHz and 65 dB up to 12.5 MHz. Compared toMohamadou et al (2012), we achieved a larger and moreaccurate measurement frequency range.

The system precision (35 m�) and accuracy (1.21%at 1 k�) measuring at a single frequency enable trackingof time-varying impedance, for example, to detect cardiacand lung related changes in body impedance measurements.Unlike the devices described in Mohamadou et al (2012)

and Li et al (2013), that only allow impedance measurementusing the stepped sine method, our FRA offers the possibilityto perform broadband impedance FRF measurements. Thisadditional feature makes it possible to extract the instantaneousFRF of the time-varying system under test with a maximumacquisition speed of 200 FRFs per second (kHz–MHz) usingtest excitation in the form of multisines.

5. Conclusion

We have developed and evaluated the performance of anew frequency response analyzer for frequency responsefunction (FRF) measurements on stationary and time-varying impedance. The core of the system is a field gateprogrammable array (FPGA), which includes the arbitrarywaveform generator and on-board digital signal processing.The signal generation and acquisition are achieved with twosignal analogue chains, one for digital-to-analogue referencesignal generation and the other for the analogue-to-digitalinput–output signals acquisition. Adopting a single on-chipdigital FPGA structure, we have achieved (i) maximum clockcontrol (the global clock including its jitter and phase noisereaches all the hardware parts with the same skew) and (ii)perfect synchronization between the signal generation andacquisition necessary to avoid spectral leakage. The in-builtdigital signal processing is based on (i) a digital coherent phaseand quadrature technique and (ii) the fast Fourier transform forthe stepped sine and multisine FRF measurements respectively.The major feature of our system is that it can perform FRFmeasurements in the frequency range 610.4 mHz to 12.5 MHzwith a maximum FRF acquisition speed of 200 FRFs persecond (kHz–MHz).

The system developed can be used in many engineeringapplications (biomedical, electrochemical, mechanical, acous-tical, etc) to perform fast FRF measurements for getting insightquickly into the frequency response of the stationary or time-varying system under test.

Acknowledgments

This work has been supported by the Spanish MinistryMICINN SAF2011-30067-C02-02, by Redes de Investigaciondel Instituto Carlos III (REDINSCOR, RD06/0003) andFondo Europeo de Desarrollo Regional (FEDER).

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