an introduction to - ieee web hosting28 july 2014 school of engineering―electrical &...

www.tyndall.ie

Michael Peter Kennedy FIEEE

Circuits and Systems Group

IEEE Circuits and Systems Society

Santa Clara Valley Chapter

28 July 2014

School of Engineering―Electrical & Electronic Engineering,

University College Cork, and Tyndall National Institute, Cork, Ireland

An Introduction to

Digital Delta-Sigma Modulators

www.tyndall.ie

Dedication

• William F. Egan

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Digital Delta Sigma Modulators

“Although the number of commercially

deployed DDSMs far exceeds that of analog

Δ∑ modulators, most of the published Δ∑

modulator analyses apply only to analog Δ∑

modulators.

Interestingly, most of these analyses do not

apply or even readily extend to the case

of DDSMs”

[PWG07]

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Outline

• The ideal DDSM The Big Idea

Signal processing assumptions

Applications of DDSMs

• The real DDSM DDSM architectures

Origins of spurious tones

Minimization of spurious tones

• Current research

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The ideal DDSM

• The Big Idea

• Signal processing assumptions

• Applications of DDSMs

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The ideal DDSM

• A bandlimited digital signal x (n bits) is

requantized to a shorter word y (m bits)

• The additive quantization noise eq is

highpass filtered for later removal by a

lowpass filter

n bits m bits

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The ideal DDSM 7/115

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The ideal DDSM

• x is bandlimited

• y includes highpass filtered quantization noise

• quantization noise can be removed by lowpass filtering

X

Eq X

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The ideal DDSM




X

X Eq

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The ideal DDSM

• The oversampled output has almost the

same S/N ratio as the input but much

fewer bits (e.g. 16 reduced to 1)

• Fewer bits means it’s easier to implement

the digital to analog conversion further

along the signal processing path

• Oversampling makes it easier to do

continuous-time reconstruction filtering

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The ideal DDSM

• One typically assumes that the Classical

Model of Quantization (CMQ) applies…

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Classical model of quantization (CMQ)

• eq is statistically independent of x

• eq is uniformly distributed in [-Δ/2, + Δ/2]

• eq is stationary with a flat power spectrum

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Classical model of quantization (CMQ)

“CMQ can be applied when the quantizer

input traverses several quantization levels

between two successive samples”

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The ideal DDSM

• The output depends on the signal x and the quantization noise eq

Y(z) = STF(z) X(z) + NTF(z) Eq(z)

• The signal is typically scaled by the DDSM

STF(z) = (1/M)

• The quantization noise is highpass filtered

NTF(z) = (1-z-1)l

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The ideal DDSM

• The output comprises the signal plus the

filtered quantization noise

Y(z) = (1/M)X(z) + Eq(z) (1-z-1)l

x[n] spectrum

y[n] spectrum

Shaped white quantization

noise

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The ideal DDSM

• The noise scales as f2l at low frequencies

|Eq(z) (1-z-1)l|2 = (Δ2/12) 22l sin2l(πf/fs)

≈ (Δ2/12) (2πf/fs)2l when f « fs

+20l dB/decade

CMQ approximation

Simulation

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The ideal DDSM




X

X Eq

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• Example 1: Class D audio amplifier

• Example 2: Oversampled DAC

• Example 3: Fractional-N frequency

synthesizer

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• Example 1: Class D audio amplifier

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Class D digital audio power amplifier

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Class D digital audio power amplifier

• Example: uniformly-sampled PWM; N=16

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• Example 2: Oversampled DAC

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Oversampled DAC

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Oversampled DAC

• By using oversampling and DDSM, the filter

rolloff and DAC linearity specifications are

relaxed

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• Example 3: Fractional-N frequency

synthesizer

[R90]

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Fractional-N Frequency Synthesis

Phase Detector

(PFD) LPF VCO

fout

fref

÷ (Nint+y)

fd

1800 MHz 13 MHz

DDSM

X

y

refnout fX

Nf )2

( int

n bits

m bits

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• DDSM sets the average division ratio

• The frequency resolution is determined by

the wordlength of the DDSM

refnout fX

Nf )2

( int

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• GSM example:

fref = 13 MHz; fout = 1.8 GHz

N (INT )= 138

X (FRAC) = 30

M (MOD) = 65

fout = fref (INT + FRAC/MOD)

= 13 (138 + 30/65) MHz

= 1794 + 6 MHz

= 1800 MHz

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• Output phase noise [PTS02]

Nint+y

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• DDSM contributes little in-band noise; loop

filter attenuates out-of-band components

MASH 1-1 with 2nd order loop

+20(l-1) dB/decade

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• Quantization noise is first highpass filtered

by the DDSM’s NTF

• Shaped quantization noise is then

attenuated by the (lowpass CT) loop filter

• We get high frequency resolution for free!

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The ideal DDSM: Summary

• The Big Idea Linear; allpass STF, NTF attenuates quantization noise in the signal

band

• Signal processing assumptions CMQ applies, quantization noise is uncorrelated with the signal

• Applications of DDSMs Digital Power Amplifiers, DACs, Fractional-N Frequency

Synthesizers

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The real DDSM

• DDSM architectures

• Origins of spurious tones (spurs)

• Minimization of spurious tones

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The real DDSM

• The output depends on the signal x and

the quantization noise eq

Y(z) = STF(z) X(z) + NTF(z) Eq(z)

where STF(z) = 1/M and NTF(z) = (1-z-1)l

• Consider the simplest case l=1

Y(z) = (1/M)X(z) + (1-z-1) Eq(z)

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The real DDSM

• A 1st order DDSM can be implemented

using a digital accumulator

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The real DDSM

• 1st order Error Feedback Modulator (EFM1)

• x is the input; y (the carry out) is the

output; s (the value stored in the register)

is the state; M is the modulus

y

vM

1

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The real DDSM


s[n+1] = (x[n] + s[n]) mod M

y[n] = Q(x[n] + s[n])

y

vM

1

s[n]

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The real DDSM


Q(v[n]) = (1/M)v[n] + eq[n]

e[n] = v[n]- My[n] = -M eq[n]

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The real DDSM


y[n] = Q(x[n] + s[n])

= Q(x[n]+e[n-1])

= (1/M)(x[n] + e[n-1]) + eq[n]

= (1/M)(x[n] - Meq[n-1]) + eq[n]

= (1/M)(x[n]) + (eq[n] - eq[n-1])

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The real DDSM


Y(z) = (1/M)X(z) + Eq1(z) (1-z-1)1

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The real DDSM

Spurs

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The real DDSM

• Higher-order noise-shaping architectures Single Quantizer (SQ-DDSM)

Multi-Stage Noise Shaping(MASH)

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The real DDSM

• MASH: Higher order filtering with exact

cancellation of intermediate errors

Y(z) = (1/M)X(z) + Eql(z) (1-z-1)l

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The real DDSM

• MASH: Idealized power spectra (white

noise with 2nd and 3rd order filters)

+60 dB/decade

+40 dB/decade

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The real DDSM 48/115

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The real DDSM 49/115

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The real DDSM

• A MASH 1-1-1 with a constant input and an

even initial condition can produce spurious

tones (spurs)

MASH 1-1-1

wordlength: 18 bits

Spurs

+60 dB/decade

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The real DDSM

• In audio DACs, these are called idle tones

MASH 1-1-1

wordlength: 18 bits

Spurs

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The real DDSM

• Phase noise in fractional-N frequency

synthesizer with odd initial condition in

MASH 1-1-1

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The real DDSM

• Phase noise in fractional-N frequency

synthesizer with constant input and even

initial condition in MASH 1-1-1

Spurs

Spurs

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What can go wrong and why?

• Different wordlengths can produce

different spectra

• Different inputs can produce different

spectra

• Different initial conditions can produce

different spectra

• All of the above can cause spurs!

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• Different wordlengths produce different

spectra

MASH 1-1-1

green plot: 9 bits

magenta plot: 18 bits

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• Different inputs produce different spectra

MASH 1-1-1

wordlength: 17 bits

(i) X=1

(ii) X=216

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• Different initial conditions produce

different spectra MASH 1-1-1

Input = 8 (decimal)

accumulator word length: 14 bits

cycle length for green plot: 4096

cycle length for blue plot: 32768

red plot: CMQ approximation

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• Fundamental problem: Short cycles

produce strong tones

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“CMQ can be applied when the quantizer

input traverses several quantization levels

between two successive samples”

• When the input is constant or slowly

moving, CMQ does not apply…

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• The DDSM is a Finite State Machine (FSM)

• The FSM has a finite state space S

(containing Ns states) and a deterministic

rule GD (called the dynamic) that governs

the evolution of states

• The next state is determined completely

by the current state and the input:

s[n+1] = GD(s[n], x[n])

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• If the input is fixed, the most complex

trajectory visits each state in the state

space once before repeating; the longest

cycle has period N = Ns-1

• In the worst case, the trajectory in a MASH

1-1-1 repeats with period N = 4

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• Example worst case period: N = 4

MASH 1-1-1

wordlength: 17 bits

(i) X=1

(ii) X=216

fs/4

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• Parseval’s theorem

(1/N) ∑n=0,1,…,N-1 |x[n]|2 = ∑k=0,1,…,N-1 |X[k]|2

power in time domain = power in frequency domain

• X[k] are the Discrete Time Fourier Series

(DTFS) coefficients

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• Quantization noise power is distributed

over N tones

• Fewer tones results in greater power per

tone

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How to fix the problem?

• Problem: When the cycle length is short,

the quantization noise is distributed over a

small number of tones, resulting in high

average quantization noise power per tone

• Solution: Maximize the cycle length to

distribute the quantization noise power

over more tones, thereby reducing the

average noise per tone

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How to fix the problem?

• Stochastic approach Add dither

• Deterministic approaches Set initial states

Restrict inputs

Change the architecture

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Stochastic approach

• Make the dynamic stochastic

• The next state depends on the current

state s, the input x, and a random dither

signal d

s[n+1] = GS(s[n], x[n], d[n])

• Periodicity is destroyed

• Trajectories can be much longer than Ns

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Stochastic approach: LSB dither

• Additive “LSB” dither: V(z) = (1-z-1)R

DDSM

n0-bit

][nx

][ny

][nd

1-bit

V(z)

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• Dither spreads the power over more tones

9 bit without dither 9 bit with LSB dither

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Fractional-N frequency synthesizer

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• LSB dither is indistinguishable from x…

Y(z) = X(z) + Eql (z)(1-z-1)l + D(z) (1-z-1)R

DDSM

n0-bit

][nx

][ny

][nd

1-bit

V(z)

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• MASH 1-1-1 with LSB dither: V(z) = (1-z-1)R

Green: V(z)= 0

Red: V(z)=1

Blue: V(z)=1-z-1

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• Maximum filter order for LSB dither [PG07]

Type of

MASH Filter

V(z) = (1-z-1)R

allowed R

1-1 lowpass z-2(1-z-1)2 0

1-1-1, 1-2,

2-1 lowpass z-3(1-z-1)3 1

m1-m2-…-mk,

∑mj = l z-l(1-z-1)l l-2

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Deterministic approaches: ICs

• MASH 1-1-1: Choose s1[0] odd (“seeding”)

MASH 1-1-1

Input = 8 (decimal),

accumulator word length: 14 bits

cycle length for green plot: 4096

cycle length for blue plot: 32768

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Deterministic approaches: ICs

• MASH cycle lengths with s1[0] odd (M=2n)

Modulator

order l

Guaranteed

minimum N Maximum N

2 M/2 2M

3 2M 2M

4 2M 4M

5 4M 4M

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Deterministic approaches: Architecture

• HK-MASH: for maximum length cycles

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• Guaranteed minimum cycle lengths

Order (l) Conventional

MASH with odd

initial condition

HK-MASH

2 M/2 ≈ M2

3 (M=512)

2M (1024)

≈ M3

(5093 ≈ 132 x 106)

4 2M ≈ M4

5 4M ≈ M5

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• HK-MASH vs seeded and dithered MASH

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The real DDSM: Summary

• DDSM architectures Nonlinear, CMQ does not always apply

• Origins of spurious tones Constant and/or period inputs produce periodic quantization noise

Shorter cycles yield higher power per tone

Cycle lengths depend on the input, initial conditions, and word

length

• Minimization of spurious tones Stochastic: add filtered dither

Deterministic: choose odd input or initial condition, or modify

architecture

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Current research 1

• Error masking Deliberately introduce errors and then mask their effects spectrally

• Bus-splitting Save area and power by nesting DDSMs

• Mixed-radix divider controller Set frequency precisely by using mixed-radix fractions

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Current research 2

• Dither Determine the effects of periodic dither

• Nonlinearity Spurs regrow when the “noiselike” output of the DDSM encounters a

nonlinearity

• Successive requantizers Sequences which are less likely to produce tones when they

encounter nonlinearities

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Error Masking

• The output of a DDSM contains two terms:

Y(z) = STF(z)X(z) + NTF(z)Eq(z)

• The second (shaped noise) term is

removed by filtering further along the

signal processing chain

• Any additional quantization noise that lies

below the mask of the shaped noise will

also be removed by that filter!

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Error Masking

• The signal itself is also quantized,

providing a noise floor below which other

errors can be masked

Quantization noise (of DDSM)

Quantization noise (of input)

“Corner” frequency

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Error Masking

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Error Masking

• Exploit error masking to reduce the bus

width, thereby reducing area and power

and increasing speed

• We consider two ideas: MASH DDSMs with interstage quantization

Bus-splitting

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All modulators have the same wordlength N.

Exact 3rd order MASH architecture 88/115

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Exact 3rd order MASH architecture

• All stages have the same wordlength N

• The hardware requirement scales as 3N

• This is overkill…

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Later stages have smaller wordlengths: L<M<N.

Reduced complexity MASH DDSM 90/115

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Reduced complexity 3rd order MASH

• Successive stages have decreasing

wordlengths

• The hardware requirement scales less than

3N

• This is optimal…

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• 3rd order MASH with interstage errors

Y1(z) = (1/2N)X(z) + Eq1(z) (1-z-1)

Y2(z) = (1/2M)(-2MEq1(z) + Eq12(z)) + Eq2(z) (1-z-1)

Y3(z) = (1/2L)(-2LEq2(z) + Eq23(z)) + Eq3(z) (1-z-1)

Y(z) = Y1(z) + Y2(z) (1-z-1) + Y3(z) (1-z-1)2

= (1/2N)X(z) + Eq3(z) (1-z-1)3

+ (1/2M)Eq12(z) (1-z-1) + (1/2L)Eq23(z) (1-z-1)2

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Error Masking

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• Relative Hardware Consumption (RHC):

• For large N, RHC approaches 67%, representing a 33% saving in area relative to a MASH DDSM with identical EFM1 stages

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Bus-splitting

• We can split the bus multiple times…

• Example: Nested bus-splitting 1-2-3 DDSM3

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Bus-splitting accelerator

[PC12] Park & Cho, IEEE J. Solid-State Circuits, 2012.

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Bus-splitting

Y(z) = (1/2N)X(z) + (1/2(NMSB+NISB))Eq1(z) (1-z-1)

+ (1/2NMSB)Eq2(z) (1-z-1)2 + Eq3(z) (1-z-1)3

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Comparison

DDSM3 1-2-3 DDSM3

ENOB = 19.54 ENOB = 19.22

area, power = 1, 1 area, power = 0.62, 0.51

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Frequency synthesis: State of the art

• Conventional frac-N frequency synthesizer

Phase

Detector (PFD)

LPF VCO

fVCO

fPD

÷ (INT+FRAC/MOD)

fd

3999.999… MHz 122.88 MHz

2n DDSM

FRAC

y

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Frequency synthesis

• Mixed-radix frac-N frequency synthesizer

Phase Detector

(PFD) LPF VCO

fVCO

fPD

÷ (INT+FRAC/MOD+Δ)

fd

4000.0000 MHz 122.88 MHz

Mixed-Radix DDSM

FRAC

y

Δ

[KMFHSK14] Kennedy et al., IEEE J. Solid-State Circuits, 2014.

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Frequency synthesis

• Conventional

• Mixed-radix

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Frequency synthesis

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Frequency synthesis

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Frequency synthesis

[KFHSK14] Kennedy et al., J. Solid-State Circuits, 2014.

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• Dither second and third stages…

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• “Efficient dithering” [GDGAFVM10]

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Simplified model

Requantizer

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Simplified model

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Simplified model

[SNK13] Sadeghi et al., IEEE Trans. Circuits Syst. II, 2013.

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Simplified model

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Simplified model

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Spurs due to the PFD-CP nonlinearity

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Acknowledgements

• FIRB Italian National Research Program

RBAP06L4S5

• Irish Research Council for Science,

Engineering & Technology (IRCSET)

• Science Foundation Ireland Grants

02/IN1/I45 and 08/IN1/I1854

[email protected]

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• [FKM11] B. Fitzgibbon, M.P. Kennedy and F. Maloberti.

Hardware Reduction in Digital Delta-Sigma Modulators via

Bus-Splitting and Error Masking―Part I: Constant Input.

IEEE Trans. Circuits and Systems-Part I, 58(9):2137-2148,

Sep. 2011.

• [FKM12] B. Fitzgibbon, M.P. Kennedy and F. Maloberti.

Hardware Reduction in Digital Delta-Sigma Modulators via

Bus-Splitting and Error Masking―Part II: Non-constant

Input. IEEE Trans. Circuits and Systems-Part I,

59(9):1980-1991, Sep. 2012.

• [FPK11] B. Fitzgibbon, S. Pamarti and M.P. Kennedy. A

Spur-Free MASH DDSM with High-Order Filtered Dither.

IEEE Trans. Circuits and Systems-Part II, 58(9):585-588,

Sep. 2011.

References 116/115

www.tyndall.ie

• [GDGAFVM10] V.R. Gonzalez-Diaz, M.A. Garcia-Andrade,

G.E. Flores-Verdad and F. Maloberti. Efficient Dithering

in MASH Sigma-Delta Modulators for Fractional-N

Frequency Synthesizers. IEEE Trans. Circuits and

Systems-Part I, 57(9):2394-2403, Sep. 2010.

• [GDPM11] V.R. Gonzalez-Diaz, A. Pena Perez and F.

Maloberti. Use of Time Variant Digital Sigma-Delta for

Fractional Frequency Synthesizers. In Proc. IEEE Int.

Symp. Circuits and Systems, pages 169-172, May 2011.

• [HK07a] K. Hosseini and M.P. Kennedy. Mathematical

Analysis of a Prime Modulus Quantizer MASH Digital

Delta-Sigma Modulator. IEEE Trans. Circuits and Systems-

Part II, 54(12):1105-1109, Dec. 2007.

References 117/115

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References

• [HK07b] K. Hosseini and M.P. Kennedy. Maximum

Sequence Length MASH Digital Delta-Sigma Modulators.

IEEE Trans. Circuits and Systems-Part I, 54(12):2628-

2638, Dec. 2007.

• [HK08] K. Hosseini and M.P. Kennedy. Architectures for

Maximum-Sequence-Length Digital Delta-Sigma

Modulators. IEEE Trans. Circuits and Systems-Part II,

55(11):1104-1108, Nov. 2008.

• [HK11] K. Hosseini and M.P. Kennedy. Minimizing Tones

in Digital Delta-Sigma Modulators. Springer, New York,

2011.

118/115

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References

• [K12] M.P. Kennedy. Recent Advances in the Design,

Analysis and Optimization of Digital Delta-Sigma

Modulators. NOLTA, 3(3):258-286, Jul. 2012.

• [KFHSK13] M.P. Kennedy, B. Fitzgibbon, A. Harney, H.

Shanan and M. Keaveney. High Speed, High Accuracy

Fractional-N Frequency Synthesizer using Nested Mixed-

Radix Digital Δ-Σ Modulators. In Proc. ESSCIRC, Sep.

2013.

• [KK03] M. Kozak and I. Kale. Oversampled Delta-Sigma

Modulators. Springer, New York, 2003.

119/115

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• [NRV96] S.R. Norsworthy, D.A. Rich, and T.R.

Viswanathan. A Minimal Multibit Digital Noise Shaping

Architecture. In Proc. IEEE Int. Symp. Circuits and

Systems, pages 5-8, May 1996.

• [MBFMCB03] P. Malcovati, S. Brigati, F. Francesconi, F.

Maloberti, P. Cusinato, and A. Baschirotto. Behavioral

Modeling of Switched-Capacitor Sigma-Delta Modulators.

IEEE Trans. Circuits and Systems-Part I, 50(3):352-364,

Mar. 2003.

References 120/115

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• [PC12] D. Park and S.H. Cho. A 14.2mW 2.55-to-3GHz

Cascaded PLL with Reference Injection, 800MHz Delta-

Sigma Modulator and 255fsrms Integrated Jitter in 0.13µm

CMOS. In Proc. ISSCC 2012, pages 344-345, San Francisco,

19-23 February 2012.

• [PWG07] S. Pamarti, J. Welz and I. Galton. Statistics of

the Quantization Noise in 1-Bit Dithered Single-Quantizer

Digital Delta-Sigma Modulators. IEEE Trans. Circuits and

Systems-Part I, 54(3):492-503, Mar. 2007.

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