analog circuit optimization system based on hybrid evolutionary algorithms

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Analog Circuit Optimization System Based on Hybrid Evolutionary Algorithms

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  • dao

    Analog circuit synthesis

    Analog circuit optimization

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    ign

    MA

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    d b

    stringent design requirements. The results show that the design specications are closely met, even in

    highly-constrained situations. Comparisons with available methods like genetic algorithms and

    differential evolution, which use static penalty functions to handle design constraints, have also been

    esses tcomp

    ction othe coits. W

    replace tedious and ad-hoc manual trade-offs by automatic design

    ancets. Iner to

    Kirchhoffs current law (KCL) and Kirchhoffs voltage law (KVL)

    and XH are their lower and upper bounds, respectively. The vector

    ARTICLE IN PRESS

    Contents lists available at ScienceDirect

    w.e

    th

    INTEGRATION, the VLSI journal 42 (2009) 137148 1run-time are necessary for a circuit synthesis solution to gainacceptance [3]. Other than those requirements, ability to deal withlarge-scale problems, closely meet the designers requirements,even for highly-constrained problems, and ability to achieve

    g(x)X0 corresponds to user-dened constraints.The proposed system uses the formulation of the analog circuit

    design problem in Eq. (1) as a constrained optimization problemand, then, solves it by evolutionary algorithms. A new algorithm,

    Corresponding author.

    E-mail address: [email protected] (Y. Wang).

    The maximization of a design objective can easily be transformed into a

    minimization problem by just inverting its sign.0167-92

    doi:10.1of parameters; second, solve problems that are hard to design byhand. Accuracy, ease of use, generality, robustness, and reasonable

    equations. Vector x corresponds to the design variables, and XLtopology.There are two main purposes of a synthesis system: rst,

    In this equation, the objective function f(x) is the performfunction to be minimized and h(x) are the equality constrainanalog circuit design, the equality constraints mainly refsynthesis methodology, analog circuit design suffers from longdesign time, high complexity, high cost and requires highlyskilled designers. Consequently, automated synthesis methodol-ogies for analog circuits have received much attention. The analogdesign procedure consists of topological-level design and para-meter-level design (also called circuit sizing) [1,2]. This paperconcentrates on the latter, aiming at parameter selection andoptimization to improve the performances for a given circuit

    certain value). They can be formulated as follows:

    minx

    f xgxX0

    subject to hx 0XLoxoXH (1)Co-evolutionary differential evolution

    (CODE)

    Analog circuit sizing

    1. Introduction

    Nowadays, VLSI technology progrof mixed analogdigital circuits as aThough the analog part is a small framuch more difcult to design due tointensive nature of analog circu60/$ - see front matter & 2008 Elsevier B.V. A

    016/j.vlsi.2008.04.003quality and robustness. Moreover, the algorithm is shown to be efcient.

    & 2008 Elsevier B.V. All rights reserved.

    owards the integrationlete system-on-a-chip.f the entire circuit, it ismplex and knowledge-ithout an automated

    optimum results are signicant objectives of the proposed system.Many parameter-level design strategies, methods, and tools havebeen published in recent years [123], and some have evenreached commercialization [24].

    Most analog circuit sizing problems can be naturally expressedas the minimization of an objective1 (e.g., power consumption),usually subject to some constraints (e.g., DC gain larger than aDifferential evolution (DE)carried out, showing that the proposed algorithm offers important advantages in terms of optimizationAnalog circuit optimization system base

    Bo Liu a, Yan Wang a,, Zhiping Yu a, Leibo Liu a, MiJing Lu a, Francisco V. Fernandez b

    a Institute of Microelectronics, Tsinghua University, Chinab IMSE, CSIC and University of Seville, Spain

    a r t i c l e i n f o

    Article history:

    Received 29 July 2007

    Received in revised form

    28 January 2008

    Accepted 10 April 2008

    Keywords:

    a b s t r a c t

    This paper investigates a

    integrated circuits (ICs). A

    (CODE), is proposed to des

    combination of HSPICE and

    simulation, to the optimiz

    The system has been teste

    journal homepage: ww

    INTEGRATION,ll rights reserved.on hybrid evolutionary algorithms

    Li a, Zheng Wang a,

    rid evolutionary-based design system for automated sizing of analog

    w algorithm, called competitive co-evolutionary differential evolution

    analog ICs with practical user-dened specications. On the basis of the

    TLAB, the system links circuit performances, evaluated through electrical

    n system in the MATLAB environment, once a circuit topology is selected.

    y typical and hard-to-design cases, such as complex analog blocks with

    lsevier.com/locate/vlsi

    e VLSI journal

  • function minimization problems that can be solved through

    elecmiztheminrequSomin Rpreproglobofdisastoc(ECproyeasatiasandmohanproaut

    (1)

    ARTICLE IN PRESS

    e VLSI jounumerical methods. Essentially, they are based on the introduc-tion of a performance evaluator within an iterative optimizationloop. The system is called equation-based when the performanceevaluator is based on equations capturing the behavior of a circuittopology [711]. However, creating the equations often consumesmuch more time than manually designing the circuit. In addition,the simplications required in the closed form analyticalequations cause low accuracy and incompleteness. On thecontrary, simulation-based methods do not rely on analyticalequations but on SPICE-like simulations to evaluate the circuitperformances in the optimization process, which result in super-ior accuracy, generality, and ease of use [1215]. Therefore, oursystem is simulation-based. Through the link between HSPICE andMATLAB, the candidate parameters are transmitted from theoptimization system to the simulation engine, and the circuitperformances obtained by the electrical simulator are returned tothe optimization system. The penalty to pay is a relatively longcomputation time (compared to other methods), although, as theexperimental results in Section 5 demonstrate, it can be keptwithin acceptable limits.

    Techniques for analog circuit optimization that appeared inliterature can be broadly classied into two main categories:deterministic optimization algorithms and stochastic searchcalled competitive co-evolutionary differential evolution (CODE)algorithm, is proposed to deal with this constrained opti-mization problem. The algorithm has several novel features,which enable it to deal with large-scale and highly-con-strained problems in an acceptable computation time with highrobustness.

    The evolutionary algorithm has been implemented in MATLAB[25]. Evaluation of the objective function and constraints (valuesof f(x) and g(x) in Eq. (1)) is performed by using an electricalsimulator, HSPICE [26], for which an appropriate link withMATLAB has been implemented.

    The structure of the paper is as follows. Section 2 reviewsrelated work and motivates the strategy of our optimizationapproach. The evolutionary algorithm used in this approach,differential evolution, and its implementation, are discussed inSection 3. Section 4 formulates the competitive co-evolutionapproach to handle constraints in the differential evolutionalgorithm. Section 5 provides practical examples and benchmarktests to show the efciency, effectiveness and advantagesof the proposed approach. Comparisons with other commonmethods are also carried out. Finally, some concluding remarksare given.

    2. Related work

    Synthesis can be carried out by the following two differentapproaches: knowledge- and optimization-based. The basicidea of knowledge-based synthesis is to formulate designequations in such a way that given the performance character-istics, the design parameters can be calculated [46]. In thesetools, the quality of the solutions in terms of both accuracy androbustness is not acceptable since the very concept of knowledge-based sizing forces the design equations to be simple. Otherdrawbacks are the large preparatory time/effort required todevelop design plans or equations, the difculty in using themin a different technology, and the limitation to a xed set ofcircuits.

    In optimization-based synthesis, the problem is translated into

    B. Liu et al. / INTEGRATION, th138algorithms (evolutionary computation algorithms, simulatedannealing, etc.). The traditional deterministic optimization meth-ods mainly include steepest-descent algorithm and downhill(2) The constraint handling problem is very important in analogcircuit design, especially for high performance circuits, whichare always highly constrained. Most reported synthesismethods use penalty functions to handle constraints, andfew of them investigated solution algorithms for highperformance design problems. In these methods, the con-strained optimization problem is transformed into an un-constrained one by minimizing the following function:

    f 0x f x Xni1

    wihgixi, (2)

    where the parameters wi are the penalty coefcients and/gi(x)S returns the absolute value of gi(x) if it is negative, andzero otherwise. The results of the methods based on penaltyfunctions are very sensitive to the penalty coefcients, andmay not meet the designers specications in many cases.Small values of penalty coefcients drive the search outsidethe feasible region and often produce infeasible solutions,while imposing very severe penalties make it difcult to drivethe population to the optimum solution. Usually, exactsolutions are hard to nd without tuning the penaltycoefcients for many times. Although several penalty strate-gies have been developed [30,31], there has been no generalrule for designing penalty coefcients till now.

    (3) Ability to handle large-scale design problems is still underGA is the most popular evolutionary algorithm, but its searchability and convergence rate have been criticized. It has alsobeen proved that canonical GA cannot converge to the globaloptimum [27]. GA with elitism converges to the globaloptimum theoretically, but it is not always the case inpractice. On the other hand, some other population-basedmetaheuristics (PBMH) methods, such as swarm intelligence[28] and differential evolution [29] are attracting muchattention in the community of operations research becauseof their advantages over GAs. Their potentials in analog circuitdesign automation still need to be exploited.follorithm. These techniques are available in some commercialtrical simulators [26]. The drawbacks of deterministic opti-ation algorithms are mainly in the following three aspects: (1)y require a good starting point, (2) an unsatisfactory localimum may be reached in many cases, and (3) they oftenire continuity and differentiability of the objective function.e researchers have tried to address these difculties, such asef. [16], where a method to determine the initial point issented. Another approach is the application of geometricgramming methods, which guarantee the convergence to aal minimum [11]. However, they require a special formulationdesign equations, which make them share many of thedvantages of equation-based systems. Research efforts onhastic search algorithms, especially evolutionary computation) algorithms (genetic algorithms, differential evolution, geneticgramming, etc.) have begun to appear in literature in recentrs [1,1723]. Due to the ability and efciency to nd asfactory solution, genetic algorithms (GA) have been employedoptimization routines for analog circuits in both, industryacademia. For problems with practical design specications,

    st reported approaches use the penalty function method todle constraints. Though these works have made a signicantgress, the optimization algorithms for analog circuit designomation remain an active research area because of thewing reasons:algornal 42 (2009) 137148investigation. Most of the available methods can deal withabout 1020 variables simultaneously, but analog circuitswith 30 or more unknown variables are common.

  • 3. Differential evolution and its implementation

    The differential evolution (DE) algorithm and its implementa-tion are introduced briey in this section. The DE algorithm issuitable for unconstrained problems, and it is also a basiccomponent in CODE.

    Differential evolution is a population-based evolutionarycomputation technique, which uses a simple differential operatorto create new candidate solutions, and a one-to-one competitionscheme to greedily select new candidates. Recently, DE hasattracted much attention in various technical elds [32,33].

    The ow diagram of the DE algorithm is summarized in Fig. 1. TheDE algorithm starts with the random initialization of a population ofindividuals in the search space and works on the cooperativebehaviors of the individuals in the population. At each generation,the mutation and crossover operators are applied to the individuals,and a new population arises. Then, selection takes place, and thecorresponding individuals from both populations compete to buildthe next generation. The algorithm tries to nd the globally optimalsolution by utilizing the distribution of solutions in the search spaceand differences between pairs of solutions as search directions.However, the searching behavior of each individual in the searchspace is adjusted by dynamically altering the direction and steplength in which the search is performed.

    The ith individual in the d-dimensional search space at

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    B. Liu et al. / INTEGRATION, the VLYesgeneration t can be represented as

    Xt xi;1; xi;2; . . . ; xi;d; i 1;2; . . . ;NP, (3)where NP denotes the size of the population.

    For each target individual i, according to themutation operator,a mutant vector:

    Vit 1 vi;1t 1; . . . ; vi;dt 1 (4)is generated by adding the weighted difference between a pair ofindividuals, randomly selected from the population at generationt, to another individual, as described by the following equation:

    Vit Xr0t FXr1t Xr2t, (5)

    Set Ranges

    Initialization

    Select BaseVector

    DE Mutation

    DE Crossover

    DE Selection

    UpdateParameters

    Reach MaximumGenerations?

    NoOutput

    Fig. 1. Flow diagram of the DE algorithm.where indices r1 and r2 (r1, r2A{1, 2,y, NP}) are randomly chosenand mutually different, and also different from the current index i.The scaling factor F (FA(0, 1+)) controls the amplication of thedifferential variation (Xr1(t)Xr2(t)). Although F has not an upperlimit, FA(0, 2] is commonly used. The population size NP must beat least 4, so that the mutation operator can be applied. VectorXr0(t) is the base vector to be perturbed. There is a variety ofmechanisms to select this base vector.

    After the mutation phase, the crossover operator is applied toincrease the diversity of the population. Thus, for each targetindividual, a trial vector Ui(t) [ui,1(t), y, ui,d(t)] is generated asfollows:

    ui;jt vi;jt if randjpCR or j randni;xi;jt otherwise;

    ((6)

    where rand(j) is a random number uniformly distributed in therange [0,1]. The index randn(i) is randomly chosen from the set {1,2,y, d}, and prevents the trial vector from being identical to thetarget vector. The parameter CRA[0,1] is a constant calledcrossover parameter that controls the diversity of the population.

    Following the crossover operation, the selection arises to decidewhether the trial vector Ui(t) will be a member of the population ofthe next generation t+1. For a minimization problem, Ui(t) iscompared to the initial target individual Xi(t) by the followingone-to-one based greedy selection criterion:

    Xit 1 Uit if f Uitof Xit;Xit otherwise;

    ((7)

    where Xi(t+1) is the new individual of the population of the nextgeneration, and f(x) is the objective function.

    The procedure described above is considered as the standardversion of DE. Several strategies of DE have been proposed,depending on the selection of the base vector to be perturbed, thenumber and selection of the trial vectors and the type of crossoveroperators [32,33]. In our implementation, the base vector Xr0(t) isselected to be the best member of the current population to shareits information among the individuals of the population and biassolutions towards better vectors.

    Special care has been taken for handling boundaries of theparameters of the search space. Two classes of boundaries aredistinguished: hard and weak. Hard boundaries are those thatcannot be exceeded (e.g., a passive resistance cannot be negativeor the transistor gate length cannot be below the minimum valueallowed in the technological process), even if there are mathe-matically better solutions beyond those points. During theexecution of the DE algorithm, the overstepped individuals areset to the nearest bounds. Weak boundaries are those roughlyestimated to reasonably limit the search space. Although allindividuals in the initial population are selected within thesebounds, mutations during the evolution of the population mayyield individuals beyond those limits if better solutions are found.Unlike GA and particle swarm optimization (PSO), DE can dealwith this problem. DE is also more effective as the accuracy oflocal search is better than that of GA and PSO [29].

    For some parameters it is also interesting to use logarithmicscales to favor lower values of the parameters with large spans,e.g., if a bias current spans over several decades, high values,hence high power consumption, will be favored if a linear scale isused. Other parameters must be discretized, e.g., device sizes canonly change according to a given grid. In our implementation,

    SI journal 42 (2009) 137148 139mutant vectors are allowed to vary continuously, to promotediversity. However, the parameters are set to the nearest gridvalue when evaluating the tness of the individual.

  • minimize F(x, r, h) with individuals in this population encoding

    ARTICLE IN PRESS

    e VL4. Constrained analog circuit optimization problem

    Though DE is very effective and efcient, it is not enoughfor the sizing of analog circuits. All EC algorithms them-selves lack a mechanism to deal with the constraints of aproblem, which remains an open research area. However,there exist user-dened specications for most analog circuitdesign problems, and these constraints must be appropriatelyhandled.

    The use of penalty functions is the most common method, butit is very sensitive to penalty coefcients and can hardly getsatisfactory results without proper penalty coefcients. Thoughseveral penalty strategies [30,31] have been developed to improvestatic penalty coefcients, there is no general rule to determineproper penalty coefcients till now. Michalewicz describesthe difculties in each available penalty strategy in [34]. More-over, Michalewicz and Schoenauer [35] concluded that thestatic penalty function method without any sophisticationis more robust, as one such sophisticated method may workwell on some problems but may not work well on anotherproblem.

    In this paper, constraints are handled by using the augmentedLagrangian method, which transforms the constrained optimiza-tion problem into a problem amenable to the DE algorithmdescribed in Section 3. Penalty parameters in the augmentedLagrangian formulation are automatically updated during execu-tion of the algorithm to reach the optimum point, hence avoidingthe problems related to inappropriate settings of the penaltyparameters. Parameters are updated based on a co-evolutionmethodology.

    In recent years, co-evolution methodologies, including co-operative and competitive mode, have attracted much attention.Methods based on cooperative mode mainly aim at unconstrainedoptimization problem [36,37]. Cooperative co-evolution for con-strained optimization problems has been proposed in Ref. [38]. Inthis paper, the competitive co-evolution concept [3941] and themodied DE algorithm based on the augmented Lagrangianmethod are combined to formulate a hybrid algorithm, CODE,for constrained optimization problems in analog IC synthesis. Wewill begin by introducing augmented Lagrangians, and thendiscuss the combination of augmented Lagrangians with compe-titive co-evolution methodology.

    4.1. Augmented Lagrangians

    A constrained non-linear optimization problem can be ex-pressed as

    minimize f xgixp0; i 1; . . . ;m

    subject to

    gjx 0; j m 1; . . . ;n. (8)

    These functions can be combined into a single transformationfunction U, called the augmented Lagrangians [42]:

    Fx; r; h f x 12

    Xmi1

    rigi yi2 y2i 1

    2

    Xnjm1

    rjgj yj2 y2j .

    (9)

    In analog circuit design, equality constraints are limited to currentand voltage relationships imposed by Kirchhoffs laws: KCL andKVL. Kirchhoffs laws are automatically included in the circuit

    B. Liu et al. / INTEGRATION, th140equations in electrical simulators, so only the inequality con-straints dened by design specications have to be taken intoaccount in the optimization process. Therefore, the augmentedvalues of x and using a xed l generated from the secondpopulation. The evolution of this population tries to satisfy thefollowing property of the saddle point: F(x0, l0)pF(x, l0) inEq. (11). The second population aims to maximize F(x, r, h) withits individuals encoding values of l and using a xed x generatedfrom the rst population. The reason of this operation is F(x0,l)pF(x0, l0) in Eq. (11). This process establishes arm races of thetwo populations. Once the rst population achieves a solution xwith a previous value of l, the second population gets a better lbased on x to defeat it. Then the rst population generates a betterx to defeat the second population. At last, the saddle point inEq. (11) can be reached, which is the optimal point of x. Values of rand h are initialized at the beginning of the optimization process,and are updated at the end of each cycle of DE-based optimiza-tion. The penalty coefcients should increase as ri+1 ri a aftereach cycle, where r0 and a should be initialized rst. The owdiagram of CODE is summarized in Fig. 2.

    In the rst iteration of the DE-based optimization cycle, anLagrangian formulation is reduced to:

    Fx; r; h f x 12

    Xmi1

    rigi yi2 y2i . (10)

    Here, x is the vector of decision variables, r is the vector of penaltyparameters, and mi riyi is the Lagrangian multiplier associatedwith the ith constraint. This process is repeated until convergence.The optimization objective is to nd the saddle point (x0, l0), suchthat:

    Fx0; l0pFx0;l0pFx0; l0. (11)In the Lagrangian dual method, there is not such a saddle point

    for non-convex problems. However, augmented Lagrangiansaddresses the problem by convexifying the objective functionwith quadratic penalty terms associated with the constraints [43].For most practical problems, a saddle point always exists, and x0 isthe optimal solution of the optimization problem.

    4.2. Combination of co-evolutionary methodology and augmented

    Lagrangians

    The main problem of the augmented Lagrangian method ishow to update the Lagrange multipliers so that it converges to thesaddle point to avoid local optimization. A predeterminedupdating scheme may work well on some problems but may notwork well on another problem. Co-evolution methodology, relyingon the current evolution result of decision variables, solves thisproblem.

    Competitive co-evolution method was inspired by observingpredatorprey relationship, where organisms adapt to each otherin a dynamic environment. Groups are rewarded if they defeatindividuals that compete with them. Competitive co-evolutionstrategy can be viewed as arm races of two groups [39,40]. Toarouse competition, two populations, whose values of tnessfunctions are opposite to each other, must be generated.

    In order to nd the saddle point in augmented Lagrangians, theproblem can be formulated as

    minxmaxmFx; r; h f x 1

    2

    Xmi1

    rigi yi2 y2i , (12)

    where x is vector of design variables, and l is the vector ofLagrangian multipliers. The purpose of the rst population is to

    SI journal 42 (2009) 137148individual is randomly selected from the second population. Itspurpose is that the rst population needs a xed Lagrangianmultiplier from the second population in the rst generation, but

  • ARTICLE IN PRESS

    Yes

    No

    e VLUpdate parameters

    DesignvariableInitializepopulation A

    DE operations

    Reach generation A?

    Start

    No

    B. Liu et al. / INTEGRATION, ththe second population does not start its evolution operations atthe same time.

    It can be seen that the CODE algorithm fully inherits theadvantages of the augmented Lagrangian method. The exactsolution can be achieved by augmented Lagrangian method,whereas this is not true for the static penalty function method[43]. In addition, the advantages of the differential evolutionalgorithm, as described in Section 3, are also inherited. As anyother stochastic optimization algorithm, it cannot be guaranteedthat the global optimum solution is found for every problem, butthe experimental results demonstrate that better solutions thanprevious methods are obtained in all cases.

    5. Experimental results

    In this section, the developed algorithmwill be applied to threepractical analog circuit sizing problems and four mathematicalbenchmark problems. The three circuit sizing problems corre-spond to three ampliers of increasing complexity. The purpose ofthese examples is to test the ability of CODE to handle highly-constrained optimization problems, the ability to handle largesearch spaces (large number of design parameters), its compar-ison to other optimization algorithms and its low sensitivity to theinitial values of the optimization parameters. Finally, benchmarktests of the evolutionary computation eld for constrainedoptimization are shown.

    In all the examples, the DE step size F is 0.8 and the crossoverprobability CR is 0.8. The inner generations of populationencoding values of x is 80 for problems with less than 20variables, and 100 for other problems, and the generations ofpopulation encoding values of l is 80. The above parameters arecommonly used in DE based algorithms. We used r0 1 and

    Fig. 2. Flow diagrInitializepopulation B

    DE operations

    Reach generation B?

    Convergence?

    Best result

    No

    Multiplier

    Yes

    Yes

    SI journal 42 (2009) 137148 141a 1.5 for all the problems, except in the specic experimentswhich demonstrate the low sensitivity of the results to theseparameter values. The design parameter search space is quitewide in all cases. Transistor lengths were allowed to vary betweenthe minimum value allowed by the technological process to10 mm. Transistor widths were changed between the minimumtechnology value to several hundreds of micrometers. Capacitorvalues and bias currents and voltages also had broad (yetreasonable) ranges.

    The inputs to the system are a SPICE net list le containing thestructure, and user dened specications. All the examples arerun on a 2.4GHz PC with 1GB RAM, in the MATLAB environment.Reported computation times include processing time in MATLAB,the communication time between HSPICE and MATLAB, and thesimulation time of HSPICE.

    5.1. Example 1: Design of a two-stage amplier

    The main purpose of this example is to test the capability ofCODE to handle constraints. A typical Miller-compensated two-stage amplier, shown in Fig. 3, is chosen rst to test thealgorithm. The technology used is a 0.25mm CMOS process andthe load capacitance CL is 30pF. The design parameters are:transistor widths and lengths, compensation capacitor and biascurrents.

    The rst experiment tries to achieve the design objectives andconstraints shown in Table 1. Appropriate matching constraintswere established and appropriate operating region was ensuredby imposing constraints like VDS/(VGSVTH)41 for NMOS transis-tors. The same experiment was tried with the standard geneticand differential evolution algorithms and using the static penaltyfunction method to handle constraints (denoted GA+PF andDE+PF, respectively). We tried to manually improve the penalty

    am of CODE.

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    Specications and results of CODE, GA+PF and DE+PF

    e VLB. Liu et al. / INTEGRATION, th142coefcients through ve runs of the GA+PF and DE+PF algorithms.At each new run, the penalty coefcients were updated trying toincrease the relative importance of the constraints not met in theprevious run. Table 1 shows the best result from these ve runs. Itcan be seen that the GA+PF algorithm slightly violates the phasemargin specication and gets a considerably higher powerconsumption. Both, the DE+PF and CODE algorithms, meet thedesign specications but CODE achieves a signicantly lowerpower consumption. Notice that CODE was run only once as nomanual adjustment of penalty parameters is needed.

    Table 1 also shows the execution time of the algorithms. Thistime includes the communication between MATLAB and SPICE.Approximately, half of this time is spent in the electricalsimulator. The total CPU time can, hence, be very signicantlyreduced by implementing the optimizer in a compiled languageand improving the efciency of the communication between theoptimizer and the electrical simulator.

    To test the ability to handle tighter specications let usconsider now the specications in Table 2. It can be observed thatCODE is still able to meet the specications. However, neither theGA+PF algorithm nor the DE+PF algorithm are able to, even thoughve different sets of penalty coefcients were tried. The

    Fig. 3. The Miller-compensated two-stage amplier.

    Table 1Specications and results of CODE, GA+PF and DE+PF

    Specications Constraints CODE GA+PF DE+PF

    DC gain (dB) X70 76.48 72.601 80.659GBW (MHz) X2 2.068 4.523 2.0406Phase margin (1) X50 55.946 49.876 55.641Output swing (V) X2 2.2017 2.1256 1.9182CMRR (dB) X70 90.01 70.99 70.018PSRR (dB) X70 76.571 74.658 80.802

    Input noise nV=Hz

    p p60 53.653 50.302 57.004

    Slow rate (V/ms) X1.5 1.5209 1.649 1.503Power (mW) Minimize 0.73118 2.215 1.1164

    Total run time (s) 10097 10126 9865Specications Constraints CODE GA+PF DE+PF

    DC gain (dB) X85 86.1 78.436 85.92GBW (MHz) X2.5 2.5052 6.6431 2.7684Phase margin (1) X55 57.746 54.958 54.785Output swing (V) X2 2.0965 2.2274 2.0446CMRR (dB) X80 80.452 77.553 75.667PSRR (dB) X85 86.13 78.641 81.02

    Noise nV=Hz

    p p20 18.537 7.979 12.575

    Slow rate (V/ms) X1.8 1.9709 1.9249 1.8629Power (mW) Minimize 1.0143 2.4344 2.1298

    Total run time (s) 11206 10533 11037

    Table 3Parameters of the two-stage amplier

    W1 (mm) 10.3 W3 (mm) 99.48 W5 (mm) 99.48W6 (mm) 85.66 W7 (mm) 46.27 L1 (mm) 4.34L3 (mm) 0.7 L5 (mm) 4.77 L6 (mm) 0.59Table 2

    SI journal 42 (2009) 137148design parameters obtained by CODE for this case are shown inTable 3.

    An important advantage of CODE is that the algorithm has alow sensitivity to the initial settings of the penalty parameters. Toillustrate this, Table 4 shows the results of the application of theCODE algorithm when different initial values of the optimizationparameters are used. By comparing this table with Table 2, it canbe checked that all constraints are met independently of the initialvalues of the optimization parameters. Moreover, variations in thenal value of the objective function keep below 3%.

    From these experiments, we can conclude that for lowrequirements, CODE and the static penalty methods workrelatively well (the latter usually needs several sets of penaltycoefcients before an acceptable value is found). However, forproblems with many and restrictive constraints, such as the caseabove, the drawbacks of both algorithms based on static penaltymethods, GA+PF and DE+PF, become obvious, whereas CODEconsistently performs well.

    5.2. Example 2: Design of a TCFC amplier

    The second example will use an amplier based on thetransconductance with capacitance feedback compensation

    L7 (mm) 3.88 Cc (pF) 40.023 Ib (mA) 0.2173

    Table 4Experiments with different initial values of r0 and a

    Specications Constraints r0 2, a 2 r0 1, a 3

    DC gain (dB) X85 93.603 86.117GBW (MHz) X2.5 2.5072 3.3719Phase margin (1) X55 59.708 57.402Output swing (V) X2 2.029 2.07CMRR (dB) X80 82.9 80.873PSRR (dB) X85 93.622 86.154

    Noise nV=Hz

    p p20 16.204 10.088

    Slow rate (V/ms) X1.8 1.9555 2.0359Power (mW) Minimize 1.0535 1.0217

    Total run time (s) 10957 11031

  • ARTICLE IN PRESS

    e VLB. Liu et al. / INTEGRATION, th(TCFC) technique [44]. The TCFC amplier is shown in Fig. 4 andthe target technology is a 0.35mm CMOS process. The optimiza-tion problem contains 36 design parameters, hence, it isconsiderably more complex than the previous example.

    Table 5 shows the design specications and the results ofCODE, which successfully meets the constraints. We tried todesign the same circuit using the GA+PF algorithm and using a setof ve penalty coefcients: 20, 50, 5, 50 and 100 for the designconstraints and objectives. The second column in Table 6 showsthe results after the execution of the GA+PF algorithm. It can beseen that GBW and SR specications are not met. Therefore, weincreased the penalties of both constraints, GBW and SR, by afactor 3 and executed the algorithm again. The results, in thethird column of Table 6, show that the slew rate specication isnot met yet, the GBW spec is met now but the DC gain and SRspecs are not met. Then, we tried a third time, increasing thepenalties of SR and DC gain by a factor 2 , resulting in theperformances shown in the fourth column, in which all theconstraints are violated. Although we tried for another 10 times to

    Fig. 4. The TCFC

    Table 5Specications and results of the CODE algorithm for the TCFC amplier

    Specications Constraints Result

    DC gain (dB) X80 82.3830GBW (MHz) X2 2.2186Phase margin (1) X50 54.4970Slow rate (V/ms) X1.5 1.56Power (mW) Minimize 0.1425

    Total run time (s) 12553

    Table 6Results of the GA+PF algorithm (same specications than Table 5)

    Specications PF1 PF2 PF3

    DC gain (dB) 83.401 67.794 72.199

    GBW (MHz) 0.50004 2.5645 1.5086

    Phase margin (1) 65.336 54.98 36.5Slow rate (V/ms) 0.0022227 0.2096 1.41Power (mW) 0.041669 0.15166 1.06

    Total run time (s) 15950 15231 15606amplier.

    Table 7Results of the DE+PF algorithm (same specications than Table 5)

    Specications PF1 PF2 PF3

    DC gain (dB) 80.217 76.901 81.083

    GBW (MHz) 0.9242 1.8462 2.0853

    Phase margin (1) 50.6 53.66 58.85Slow rate (V/ms) 0.033218 0.8295 3.2081SI journal 42 (2009) 137148 143adjust the penalty parameters, still a satisfactory result cannot beachieved.

    We followed a similar procedure with the DE+PF algorithm.The results are shown in Table 7. It can be seen that theconstraints are met for one set of penalty coefcients in this case.But the power consumption obtained is much higher than withthe CODE algorithm.

    It can be concluded that in high-performance designs, thereoften exist tedious trade-offs to nd proper penalty parameters.Sometimes, a good result can be achieved with static penaltymethods by using a proper set of penalty coefcients, but thesearch of such penalty coefcients may yield a long and tediousprocess.

    5.3. Example 3: Design of a gain-boosted folded-cascode amplier

    Finally, we will use the gain-boosted folded-cascode amplierin Fig. 5. This is the most complex example in this paper withalmost 50 design parameters.

    Table 8 shows the specications for this amplier, to bedesigned in a 0.25mm CMOS process. The table also shows theconstraints (dm parameters represent the ratio of the drain-source voltage over the drainsource saturation voltage) that areused to ensure that all transistors are in the saturation region. Thethird column shows the results of the CODE algorithm. Allconstraints are met. The best of ve executions of the GA+PFalgorithm is shown in the fourth column. Performance specica-tions are marginally met but several transistors are out of thesaturation region and power consumption is much higher than inthe solution provided by CODE. The application of the DE+PF

    Power (mW) 0.050 0.7234 1.6024

    Total run time (s) 12486 12891 13762

  • ARTICLE IN PRESS

    e VLSI journal 42 (2009) 137148B. Liu et al. / INTEGRATION, th144algorithm is not able to meet the performance specications andseveral transistors are not in the correct operating region.

    As stated above, an important advantage of the CODEalgorithm, is that the competitive co-evolution adjusts the penaltycoefcients to the appropriate values. As an illustration, Table 9shows the evolution of the Lagrange multipliers for all constraintsalong several cycles of the co-evolutionary algorithm. It can beseen that in a few cycles, the multipliers converge to the rightvalues to achieve a proper solution.

    5.4. Benchmark problems for constrained optimization

    In computer science, especially in evolutionary computation,benchmark problems are of great importance to evaluate andcompare different algorithms. Benchmark problems are tough,and if an algorithm works well in benchmark problems, it is oftenregarded as very effective for medium-sized optimization pro-blems. Three highly-constrained benchmark problems [45],described in Appendix are tested rst. The results for three

    Fig. 5. (a) Gain-boosted folded-cascode amplexperiments with different number of generations are shown inTables 10 and 11. Best, worst and average results were extractedfrom 15 runs of the algorithm. The results show that the proposedalgorithm for constrained optimization problems, CODE, is quiteeffective.

    To show the advantages of CODE, the same benchmarkproblems were tried with the DE+PF and GA+PF algorithms.Different penalty coefcients were used in each of the 15 runs andthe best result among them is shown in Table 12.2 The comparisonof computation times is shown in Table 13.

    From the comparison, we can conclude that methods based onpenalty functions are worse than the methods based on co-evolution methods. In particular, unlike many previous works, inall cases, we use the same optimization parameters introducedabove, which have not undergone any specic calculation in view

    ier; (b) P amplier and (c) N amplier.

    2 This is the most favorable comparison for the GA+PF and DE+PF algorithms,

    since bad sets of penalty coefcients tend to decrease the mean value.

  • ARTICLE IN PRESS

    Table 8Specications and results of CODE, GA+PF and DE+PF

    Specications Constraints CODE GA+PF DE+PF

    DC gain (dB) 480 112.17 79.995 69.953GBW (MHz) 4250 256.88 253.93 250.34Phase margin (1) 465 70.128 72.665 72.94Gain margin o 1 0.99952 0.90579 2.7761dm1a 41.2 19.162 19.269 14.627dm2 41.2 5.9545 5.0727 0.54239dm3a 41.2 15.856 26.476 26.554dm4a 41.2 4.8841 2.029e-6 4.6684e-8dm5a 41.2 2.6609 2.3041 0.37412dm6a 41.2 8.6422 1.0149 2.6458dm1bp 41.2 7.7727 4.9564 4.6678dm3bp 41.2 2.8415 1.1078 0.23445dm5bp 41.2 18.277 4.8062 0.66502dm6bp 41.2 5.581 2.0614 0.071441dm8bp 41.2 12.483 0.00039371 0.96522dm10bp 41.2 4.263 8.2996 21.63dm1bn 41.2 6.8212 1.6035 1.6045dm3bn 41.2 6.2987 0.0082057 0.00012044dm5bn 41.2 6.9101 0.0198 0.00031191dm6bn 41.2 2.0146 0.00074711 0.035939dm8bn 41.2 4.5137 4.0393 4.4812dm10bn 41.2 2.9358 0.00020514 7.5559e-5Power (mW) Minimize 4.004 15.508 0.87602

    Total run time (s) 5472 6124 5220

    Table 9Evolution of Lagrangian multipliers

    Specications Cycle 1 Cycle 2 Cycle 3 Cycle 4

    DC gain (dB) 3.4197 0.001318 0.00046544 0.0002567

    GBW (MHz) 2.8973 0.025275 0.01 0.01

    Phase margin 3.4119 0.01 0.01 0.01

    Gain margin 5.3408 0.029214 0.01 0.01

    dm1a 7.2711 0.0043268 0.0018774 0.0015662

    dm2 3.0929 0.011876 0.0054239 0.0033819

    dm3a 8.385 0.010797 0.0049222 0.0038691

    dm4a 5.6807 0.032155 0.01 0.01

    dm5a 3.7041 0.01 0.01 0.01

    dm6a 7.0274 0.023379 0.003503 0.0020054

    dm1bp 5.4657 0.0089035 0.0048879 0.0033824

    dm3bp 4.4488 0.010513 0.003444 0.0017828

    dm5bp 6.9457 0.034867 0.01466 0.01

    dm6bp 6.2131 0.0078141 0.0027322 0.0019259

    dm8bp 7.9482 0.052685 0.01 0.01

    dm10bp 9.5684 0.0095579 0.0036852 0.0024163

    dm1bn 5.2259 0.0048001 0.0019227 0.0015987

    dm3bn 8.8014 0.00042661 0.00014712 8.7983e-5

    dm5bn 1.7296 0.01 0.01 0.01

    dm6bn 9.7975 0.051865 0.001417 0.0013897

    dm8bn 2.7145 0.0037478 0.0028153 0.0016745

    dm10bn 2.5233 0.0079334 0.0028515 0.0020671

    Table 10Results of benchmark problems as a function of the number of generations in

    CODE

    Problem Generations

    100 300 500

    G1

    Best 14.9501 14.9999 15.0000Average 13.2311 14.8068 14.8821Worst 11.4860 13.8913 13.9021

    Results of benchmark problems as a function of the number of generations in

    CODE

    B. Liu et al. / INTEGRATION, the VLTable 12Results of benchmark problems

    Method Problem

    G1 G7 G9

    GA+PF 13.7597 685.9112 30.9991DE+PF 14.9583 683.0213 25.0172CODE 15.0000 680.6900 24.8946Problem Generations

    500 1000 1500

    G9

    Best 682.9565 682.8185 680.6900

    Average 684.4214 683.6447 682.3335

    Worst 689.3154 687.3919 686.9259

    G7

    Best 25.2218 25.2109 24.8946

    Average 28.2832 26.1763 25.6317

    Worst 34.4057 28.9355 27.0023Table 11

    SI journal 42 (2009) 137148 145of different problems; that is, the algorithm can achieve goodresult without detailed parameters studies.

    In addition, in order to test the ability of CODE to deal withactive constraints in optimization problems, the benchmarkproblem in Ref. [46] was selected (Test problem 4 in Appendix)In this problem, both constraints are active at the optimum. Thebest results of CODE, GA+PF and DE+PF after 15 runs are 5.5080,5.6833 and 5.5538, respectively.

    6. Conclusions

    This paper presents CODE: an evolutionary-based system forparameter-level design of analog integrated circuits. The basicelements of the system are a co-evolutionary methodology basedon a differential evolution algorithm and the use of augmentedLagrangians to represent the constrained non-linear optimizationproblem. CODE achieves the following three novel features: (1) itavoids the tedious tuning of penalty coefcients, (2) it can closelymeet the designers specications even for highly-constrainedproblems, and (3) it is suitable for medium or large-scaleproblems. Moreover, CODE is efcient.

    Acknowledgments

    This work has been supported by National Natural ScienceFoundation of China grant no. 60676012 and Special Funds for

    Table 13Computation time on benchmark problems

    Method Problem

    G1 G7 G9

    GA+PF 15.87s 79.74s 133.15s

    DE+PF 16.02s 61.53s 97.86s

    CODE 10.55s 43.32s 76.30s

  • 7x26 x47 4x6x7 10x6 8x7

    ARTICLE IN PRESS

    e VLsubject to

    2x21 3x42 x3 4x24 5x5 127p0,7x1 3x2 10x23 x4 x5 282p0,23x1 x22 6x26 8x7 196p0,4x21 x22 3x1x2 2x23 5x6 11x7p0,with

    10pxip10; i 1; . . . ;7.The optimum solution is:

    xn 2:330499;1:951372;0:4775414;4:365726,Major State Basic Research Projects no. 2002CB311907. Weacknowledge valuable discussions with Dr. Ziqiang Wang andDr. Xueyi Yu, Institute of Microelectronics of Tsinghua University,China. We are grateful to Mr. Hannan Ma, Department ofElectronic Engineering, for his contribution to the program. Dr.F.V. Fernandez thanks the support of the TEC2004-01752 andTEC2007-67247 Projects, funded by the Spanish Ministry ofEducation and Science with support from ERDF, and by the TIC-2532 Project, funded by Consejera de Innovacion, Ciencia yEmpresa, Junta de Andaluca. We also thank the reviewers fortheir comments that helped to improve the presentation of thepaper.

    Appendix. Description of benchmark test problems

    Test problem 1

    Minimize

    G1x 5x1 5x2 5x3 5x4 5X4i1

    x2i X13i5

    xi

    subject to:

    2x1 2x2 x10 x11 10p0,2x1 2x3 x10 x12 10p0,2x2 2x3 x11 x12 10p0, 2x4 x5 x10p0, 2x6 x7 x11p0, 2x8 x9 x12p0, 8x1 x10p0, 8x2 x11p0, 8x3 x12p0,with

    0pxip1; i 1; . . . ;90pxip100; i 10;11;120px13p1

    The optimum solution is xn 1;1;11;1;1;1;1;1;3;3;3;1 and thefunction value is G1(x

    ) 15.

    Test problem 2

    Minimize

    G9x x1 102 5x2 122 x43 3x4 112 10x65

    B. Liu et al. / INTEGRATION, th146 0:6244870;1:038131;1:594227and the function value is: G9xn 680:6300573.Test problem 3

    Minimize

    G7x x21 x22 x1x2 14x1 16x2 x3 102

    4x4 52 x5 32 2x6 12 5x27 7x8 112 2x9 102 x10 72 45

    subject to

    105 4x1 5x2 3x7 9x8X0, 3x1 22 4x2 32 2x23 7x4 120X0, 10x1 8x2 17x7 2x8X0, x21 2x2 22 2x1x2 14x5 6x6X0,8x1 2x2 5x9 2x10 12X0, 5x21 8x2 x3 62 2x4 40X0,3x1 6x2 12x9 82 7x10X0, 0:5x1 82 2x2 4 3x25 x6 30X0,with

    10pxip10; i 1; . . . ;10.The optimum solution is

    xn 2:171996;2:363683;8:773926;5:095984,0:9906548;1:430574;1:321644;9:828726;8:280092;8:375927

    and the function value is: G7xn 24:3062091.

    Test problem 4

    Minimize

    G0x x1 x2subject to:

    x2 2x41 8x31 8x21 2p0x2 4x41 32x31 88x21 96x1 36p0with

    0px1p3;0px2p4.The optimum solution is:

    xn 2:32952024;3:17849288and the function value is: G0 5:508013271.

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    Miao Li received the B.S. in electronic engineering fromTsinghua University, PR China, in 2006. He was at theInstitute of Microelectronics of Tsinghua Universityfrom the September of 2006 to now. His researchfocuses on modeling of IIIV compound semiconductormaterials and devices.2002 and holds Pericom Microelectronics Professor-ship (2002-2004) established by Pericom Semiconduc-tor Corp. in San Jose, USA. His research interests

    include device simulation for nano-scale MOSFETs, quantum transport innanoelectronic devices, compact circuit modeling of passive and active compo-nents in RF CMOS, and numerical analysis techniques.

    Leibo Liu received the B.S. and Ph.D. degrees inelectronic engineering from Tsinghua University, Beij-ing, China, in 1999 and 2004, respectively. He iscurrently an associate professor with the Institute ofMicroelectronics, Tsinghua University, Beijing, China.His research interests include recongurable processorZhiping Yu graduated from Tsinghua University, Beij-ing, China, in 1967 with B.S. degree. He received hisM.S. and Ph. D degrees from Stanford University,Stanford, CA, USA in 1980, and 1985, respectively. Heis presently the professor in the Institute of Microelec-tronics, Tsinghua University, Beijing, China. From 1989to 2002, he has been a senior research scientist in theDept. of Electrical Engineering in Stanford University,USA, while serving as the faculty member in Tsinghua.He returned to Tsinghua full time since Septemberresearch interests include analog integrated circuitsynthesis and evolutionary computation algorithms.

    Yan Wang received the B.S. and M.S. degrees inelectrical engineering from Xian Jiaotong University,Xian, China, in 1988 and 1991, respectively, and thePh.D. degree in semiconductor device and physics fromthe Institute of Semiconductors, Chinese Academy ofScience, Beijing, China, in 1995. Since 1999, she hasbeen a Professor with the Institute of Microelectronics,Tsinghua University, Beijing, China. Her researchfocuses on semiconductor device modeling.mappings, and constrained parameter optimization, Evol. Comput. 7 (1)(1999) 1944.

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    Bo Liu was born in Beijing, China, on September 23,1984. He is currently a senior undergraduate student inTsinghua University, Beijing, China. Since 2005, he hasbeen a Research Assistant at the Tsinghua NationalLaboratory for Information Science and Technology,Beijing, China. Since 2007, he has been a ResearchAssistant at the CAD Laboratory, Institute of Micro-electronics, Tsinghua University, Beijing, China. He isalso a member of Analog Design Automation ResearchGroup of University of Sevilla, Sevilla, Spain. His[41] H. Barbosa, A coevolutionary genetic algorithm for constrained optimization,IEEE Cong. Evolut. Comput. (1999) 16051611.

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    SI journal 42 (2009) 137148 147

  • Zheng Wang is an undergraduate student in electronicengineering from Tsinghua University, Beijing, China.

    Jing Lu received the B.S. in electronic engineering fromTsinghua University, China, in 2005. She was agraduate student at the Institute of Microelectronicsof Tsinghua University from 2005 and will receive themaster degree in 2008. Her research focuses onmodeling of IIIV compound semiconductor materialsand devices.

    F.V. Fernandez got the Physics-Electronics degree fromthe University of Seville in 1988 and his Ph.D. degree in1992. In 1993, he worked as a postdoctoral researchfellow at Katholieke Universiteit Leuven (Belgium).Since 1995, he is an Associate Professor at theDepartment of Electronics and Electromagnetism ofUniversity of Sevilla. He is also a researcher at CSIC-IMSE-CNM. His research interests lie in the design anddesign methodologies of analog and mixed-signalcircuits. Dr. Fernandez has authored or edited threebooks and has co-authored more than 100 papers ininternational journals and conferences. Dr. Fernandezis currently the Editor-in-Chief of Integration, the VLSI

    Journal (Elsevier). He regularly serves at the Program Committee of severalinternational conferences. He has also participated as researcher or mainresearcher in several National and European R&D projects.

    ARTICLE IN PRESS

    B. Liu et al. / INTEGRATION, the VLSI journal 42 (2009) 137148148

    Analog circuit optimization system based on hybrid evolutionary algorithmsIntroductionRelated workDifferential evolution and its implementationConstrained analog circuit optimization problemAugmented LagrangiansCombination of co-evolutionary methodology and augmented Lagrangians

    Experimental resultsExample 1: Design of a two-stage amplifierExample 2: Design of a TCFC amplifierExample 3: Design of a gain-boosted folded-cascode amplifierBenchmark problems for constrained optimization

    ConclusionsAcknowledgmentsDescription of benchmark test problemsTest problem 1Test problem 2Test problem 3Test problem 4

    References