analogue input/output

5-1

Analogue Input/Output Many sensors & transducers produce voltages representing

physical data. To process transducer data in a computer requires conversion to digital

form.

Many output devices require variable control, not just two digital logic levels To control these devices from a computer requires conversion from

digital to analogue form (usually an analogue voltage).

The conversion from analogue signals to digital values is performed by Analogue to Digital Converter (ADC)

The conversion from a digital value to an analogue signal is performed by a Digital to Analogue Converter (DAC).

DAC function

5-2

VrefVAgnd

DA ConverterAnalogue

outputn bit value

Parallel DAC

Serial DAC would typically have a single data input line and a clock input signal which would be used to clock in the serial data stream.

Adv. : - Fewer pins.

Disadv. : Slower data transfer.

5-3

Analogue Output Digital to Analogue Converter (DAC) DAC Characteristics

resolution = 1/2n where n is the number of bits Max. digital value = 2n – 1 output voltage range – determined by reference voltage

(Vref and AGND)

Step size in volts = resolution x voltage range Max output voltage = (2n – 1)/ 2n x voltage range uni-polar / bipolar types slew rate – rate of change of output. interface – parallel (fast) or serial (slower but uses fewer

connections)

5-4

DAC principles – Example 4-bit DAC Sum currents with operational amplifier

Vo = - Vref(Rf/Rinput)

Example: with 4-bit value = 1011

Vo = -Vref(d3/2 + d2/4 + d1/8 + d0/16)

Vo = -Vref(1/2 + 1/8 + 1/16)

Vo = -Vref(11/16)

Vref

d3

d2

d0

d1

2R

4R

8R

16R

Vref/2

Vref/4

Vref/8

Vref/16

-

+

Vo

1

1

0

1 AGND

R

Vo = -(Vref-AGND)(digital value/2n)

Vo α digval/ 2n

Output from DAC

5-5

Output Voltage

Digital Value

MAXVAL = Maximum digital value

= 2n -1

where n is number of bits

MAXVAL

VMAX

VMAX = Maximum output voltage

where n is number of bits

VrefV *2

1-2max

n

n

Example DAC device M AX5722 dual,12-bit, low-power, buffered voltage output, digital-to-analog

converter (DAC) is packaged in a space-saving 8-pin μMAX package (5mm ✕3mm).

5-6

Ultra-Low Power Consumption

112μA at VDD = +3.6V

135μA at VDD = +5.5V

Wide +2.7V to +5.5V Single-Supply Range

8-Pin μMAX Package

0.3μA Power-Down Current

Guaranteed 12-Bit Monotonicity (±1LSB DNL)

Safe Power-Up Reset to Zero Volts at DAC Output

Three Software-Selectable Power-Down

Impedances (100kΩ, 1kΩ, Hi-Z)

Fast 20MHz, 3-Wire SPI, QSPI, and MICROWIRECompatible

Serial Interface

Rail-to-Rail Output Buffer Amplifiers

Schmitt-Triggered Logic Inputs for Direct

Interfacing to Optocouplers

Wide -40°C to +125°C Operating Temperature

Range

Audio & LPC 23xx DAC example Recreate audio

5-7

1 2 3 4 5 6 7 8 9 10000

001

010

011

100

101

110

111

What resolution? What sampling rate ?

5-8

Analogue Input Analogue to Digital Converter (ADC) ADC Characteristics

resolution = 1/2n where n is the number of bits Max. digital value = 2n – 1 input voltage range – determined by the reference voltages

(Vref and AGND)

Step size in volts = resolution x voltage range uni-polar / bipolar types interface – parallel (fast) or serial (slower but uses fewer

connections) often integrated into microcontrollers.

5-9

General ADC function

The analogue input voltage is converted into a value. The value is dependent on the reference voltages

and the number of bits n.

VrefVAgnd

ConverterAnalogue

input n bit result

5-10

Analogue Input Main types (i.e.methods) of ADC

Successive approximation – good all-rounder Flash – fastest type Sigma-delta – good for audio Dual slope integrating – slow but high resolution with good

noise immunity others – Sampling, ramp, charge balancing

Characteristics resolution conversion method conversion time input voltage range interface – parallel (fast) or serial(fewer connections)

MCP3208 Features

12-bit resolution

± 1 LSB max DNL

± 1 LSB max INL (MCP3204/3208-B)

± 2 LSB max INL (MCP3204/3208-C)

4 (MCP3204) or 8 (MCP3208) input channels

Analog inputs programmable as single-ended or

pseudo-differential pairs

On-chip sample and hold

SPI serial interface (modes 0,0 and 1,1)

Single supply operation: 2.7V - 5.5V

100 ksps max. sampling rate at VDD = 5V

50 ksps max. sampling rate at VDD = 2.7V

Low power CMOS technology:

500 nA typical standby current, 2 μA max.

400 μA max. active current at 5V

Industrial temp range: -40°C to +85°C

Available in PDIP, SOIC and TSSOP packages

5-11

5-12

Example:8-bit ADC with Vref +5v and 0v VAgnd

Number of steps (values) = 2n = 28 = 256 steps are numbered 0 to 255 step size = reference voltage range / number of steps

= (5v – 0v) / 256 = 19.53125 x10-3v 20mv

number range 0 to 255 corresponds to voltage range of 0 to 5v

ADC value = (Vin / (Vref – Agnd)) * 256 : remember max ADC value is 255 so max input voltage that can be converted accurately is less than 5 volts.

What is the maximum convertible input voltage?

5-13

8-bit ADC with 5v reference

0

255

4.98

ADC value

Volts

ADC value

V

1

2

10mv

3

4

30mv

50mv

70mv

20mv

40mv 60m

v

5-14

Cont.

Volts

1

2

10mv

3

4

30mv

50mv 70mv

20mv

40mv 60mv

ADC value

0

80mv

Quantization Error

Each input sample is assigned a quantization interval that is closest to its amplitude height. If an input sample is not assigned a quantization interval that matches its actual height, then an error is introduced into the conversion process.

This error is called quantization error/noise.

0 1 2 3 4 5 6

001

010

011

100

101

Reducing quantization error One way to reduce quantization noise is to increase the amount of quantization intervals. The difference between the input signal amplitude height and the quantization interval

decreases as the quantization intervals are increased (increases in the intervals decrease the quantization noise).

Solved by increasing the ADC resolution (number of bit) in proportion to the increase in quantization intervals.

5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 60

10

20

30

40

50

60

70

80

5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 60

10

20

30

40

50

60

70

80

0

1

2

3

4

5

6

7

8

Analogue Input Example

Example - The LM35 series are precision integrated-circuit temperature sensors, whose output voltage is linearly proportional to the Celsius (Centigrade) temperature.

5-17

•Calibrated directly in ° Celsius (Centigrade)

• Linear + 10.0 mV/°C scale factor

• 0.5°C accuracy guarantee able (at +25°C)

• Rated for full -55° to +150°C range

• Suitable for remote applications

• Low cost due to wafer-level trimming

• Operates from 4 to 30 volts

• Less than 60 µA current drain

• Low self-heating, 0.08°C in still air

• Nonlinearity only ±¼°C typical

•Low impedance output, 0.1 Ohm for 1 mA load

LM35 & LPC23xx Interface Example ADC range (LPC23xx) 0V to + 3.3 V LM35 Linear + 10.0 mV/°C scale factor Use a basic Centigrade temperature sensor +2°C to +150°C

5-18

Max voltage from sensor = 10mV×150 = 1.5V

-

+3

21

84

+5 V

0 - 3VLM35 Input0 - 1.5V

Scale the input voltage accordingly to match input the range of the ADC

LM35 & LPC23xx Interface Example step size = reference voltage range / number of steps

= (3.3v – 0v) / 1024 = 3.22265625 x10-3v Every 1°C is now equivalent to 20.0 mV Temperature resolution > 0.2°C

5-19

-

+3

21

84

+5 V

0 - 3VLM35 Input0 - 1.5V

LPC23xxLPC23xx

AI0

ADC input

Good practice to Limit the voltage range (input protection) Filter the signal

5-20

E XT_ TE M P _ F

D 4 1

B A T5 4 S / S O T

+

-

U 3 8 C

M C P 6 0 4

1 0

98

TP 3 7TP _ E XT_ TE M P _ F

+5 V

R 1 6 2

8 . 8 7 k

R 1 6 3

1 5 k

E XT_ TE M P

C 1 3 31 u

C 1 3 40 . 4 7 u

From sensor To ADC

input

5-21

ADC Block diagram

Reference voltage

VAREF VAGND

Conversion Control

Interrupt request

Mut iplexer

Sample & Hold Converter

Result Register

AN0

AN1

ANn

Busy

Start conversion

Interface to uP

5-22

ADC – principle of operation1. The voltage is presented to the ADC input.

2. The ADC is sent a signal to start conversion

3. While the conversion takes place the input voltage should remain stable.

4. The ADC outputs a signal to indicate that it is busy doing the conversion and should not be disturbed.

5. When the conversion is completed the ADC makes the result available and outputs a signal to indicate that the conversion has completed (e.g remove the busy signal)

5-23

Multiplexer and Sample/Hold To convert several analogue inputs

1. use an ADC for each input or more usually …

2. use one ADC and switch the inputs through a multiplexer requires selection of input before each conversion is started and a

short delay is required before conversion started to allow switching to occur and signal to settle.

Sample and Hold (S&H) while conversion takes place voltage must remain stable sample voltage – input connected to S&H voltage held on a capacitor sample time – charging time of capacitor input signal disconnected from S&H

5-24

Summary Analogue inputs are often required in embedded

applications and so ADCs are integrated into most microcontrollers (DACs less so)

ADCs and DAC also exist as standalone IC devices - often specialist devices e.g. High speed or high resolution ADCs, fast DACs for video output.

Main characteristics of interest is resolution - number of bits voltage range ADC - conversion time DAC - slew rate

ADC on the LPC23xx LPC23xx ADC Features

10 bit successive approximation analogue to digital converter. Input multiplexing among 6 pins or 8 pins. Power down mode. Measurement range 0 to 3.3 V. 10 bit conversion time ≥ 2.44 μs. Burst conversion mode for single or multiple inputs. Optional conversion on transition on input pin or Timer Match signal. Individual result registers for each A/D channel to reduce interrupt overhead.

5-25

Using the ADC The ADC like all other peripherals is accessed through a group

of associated registers. (see pages 575ff of the user manual for a detailed description)

As an example we will look at the A/D Control Register (AD0CR)

5-26

AD0CR

5-27

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R R R R EDGE R R PDN R BURST

AD0CR Bit number

SELCLKDIVCLKSSTART

Selects which of the AD0.7:0 pins is (are) to be sampled and converted. For AD0, bit 0 selects Pin AD0.0, and bit 7 selects pin AD0.7. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones. All zeroes is equivalent to 0x01.

This field selects the number of clocks used for each conversion in

Burst mode, and the number of bits of accuracy of the result in the

LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3

bits).

000 11 clocks / 10 bits








The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D converter, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable.

0- Conversions are software controlled and require 11 clocks. 1- The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1 bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that’s in progress when this bit is cleared will be completed.

1 The A/D converter is

operational. 0 - The A/D converter is in power-down

mode.

When the BURST bit is 0, these bits control whether and when an A/D conversion is started:

000 No start (this value should be used when clearing PDN to 0).

001 Start now.

010 Start when the edge selected by bit 27 occurs on P2.10/EINT0.

011 Start when the edge selected by bit 27 occurs on P1.27/CAP0.1.

100 Start when the edge selected by bit 27 occurs on MAT0.1.

101 Start when the edge selected by bit 27 occurs on MAT0.3[1].



This bit is significant only when the START field contains 010-111. In these cases:1- Start

conversion on a falling edge on the selected CAP/MAT signal. 0 Start conversion on a rising edge on the selected CAP/MAT signal

R = Reserved, user software should not write or read ones to reserved bits.

AD0CR

5-28

AD0CR = ( 0x01 << 0 ) | /* SEL=1,select channel 0~7 on ADC0 */

( ( Fpclk / ADC_Clk - 1 ) << 8 ) | /* CLKDIV = Fpclk / 1000000 - 1 */

( 0 << 16 ) | /* BURST = 0, no BURST, software controlled */

( 0 << 17 ) | /* CLKS = 0, 11 clocks/10 bits */

( 1 << 21 ) | /* PDN = 1, normal operation */

( 0 << 24 ) | /* START = 0 A/D conversion stops */

( 0 << 27 ); /* EDGE = 0 (CAP/MAT singal falling,trigger A/D conv */

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R R R R 0 0 0 0 R R 1 R 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 1

R R R R EDGE R R PDN R BURSTSTART CLKS CLKDIV SEL

AD0CR Bit number

Enable the ADC input pins Before using the ADC the appropriate pins must be set as ADC inputs.

This is accomplished using the PINSEL register(s)

5-29PINSEL1 |= 0x00004000; // Select only ADC channel 0

PINSEL1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 4 0 0 0

Reading the ADC See example programs!

5-30

Example question A 5 bit ADC is used to encode an analogue signal in

the range 0V to +5V for linear PCM encoding determine: The step size Calculate the percentage resolution Calculate the dynamic range in dB Calculate the input voltage level corresponding 10110.

Solution

322 steps ofNumber 5

V31025.15632

05 size step

1.The step size

%310032

1 Resolution %

2. Calculate the percentage resolution

Solution

5-33

3 Calculate the dynamic range in dB

dB1.30log2 20 5

VDec 4375.33125.022 2210110

4 Calculate the input voltage level corresponding 10110

Voice signal

Signal

Energy Distribution for

Human Speech

0 Hz 300 Hz 3,400 Hz 20 kHz

Bandwidth (3.1 kHz)

Bandpass Filtering

The human voice can produce sounds up to 20 kHz,

but most sound is between 300 Hz and 3.4 kHz.The bandpass filter only passes this sound to reduce bandwidth.

analogue input/output

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