analysis and simulation of a cic-filter-based multiplexed
TRANSCRIPT
Analysis and Simulation of a CIC-Filter-Based Multiplexed-Input Sigma-Delta Analog-to-Digital Converter
by
Seungmyon Park
SUBMITTED TO THE DEPARTMENT OFELECTRICAL ENGINEERING AND COMPUTER SCIENCE
IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FORTHE DEGREE OF MASTER OF ENGINEERING
IN ELECTRICAL ENGINEERING AND COMPUTER SCIENC MASSACHUSETTS INSTITUTE
AT THE MASSACHUSETTS INSTITUTE OF TECHNOLOG OF TECHNOLOGY
May 1,2001 e U > JUL 11 200
© 2001 Seungmyon Park. All rights reserved. LIBRARIES
The author hereby grants to MIT permission to reproduce and to distribute publicly paper andelectronic copies of this thesis document in whole or in part.
Signature of AuthorDepartment of Electrical Engp einin'd Computer Science
Certified byPaul Ward
Charles Stark Draper LaboratoryThesis Supervisor
Certified by __ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _ _ _ _ _
Professor James K§ RobergeProfessor of Electricaltngneering and-9mputer Science
Thasis Advisor
Accepted byFrolessor Arthur C. Smith
Chairman, Departmental Committee on Graduate Theses
Analysis and Simulation of a CIC-Filter-Based Multiplexed-Input Sigma-Delta Analog-to-Digital Converter
by
Seungmyon Park
SUBMITTED TO THE DEPARTMENT OFELECTRICAL ENGINEERING AND COMPUTER SCIENCE
ON MAY 23, 2001IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR
THE DEGREE OF MASTER OF ENGINEERINGIN ELECTRICAL ENGINEERING AND COMPUTER SCIENCEAT THE MASSACHUSETTS INSTITUTE OF TECHNOLOGY
Abstract
Draper Laboratory's MEMS inertial instruments used for navigation demand extremelyhigh dynamic range and low power consumption. In this thesis, a multiplexed-inputsigma-delta analog-to-digital converter using a cascaded integrator-comb filter used inthe MEMS instrument electronics is analyzed and simulated in order to determine thetradeoff between resolution and multiplexing rate. A simulation model created inSimulink is used in order to verify the correctness of the analysis and to predictperformance. A VHDL simulation model is also created in order to further evaluateperformance and to check synthesizability and power consumption. Simulation datashows that the design evaluated is capable of providing a signal-to-noise ratio of up to~100dB when four slowly-varying ( 5 5Hz) inputs are multiplexed.
Technical Supervisor: Paul WardTitle: Group Leader, Charles Stark Draper Laboratory
Thesis Advisor: Professor James K. RobergeTitle: Professor of Electrical Engineering and Computer Science
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ACKNOWLEDGMENTMay 23, 2001
This thesis was prepared at The Charles Stark Draper Laboratory, Inc., under InternalCompany Sponsored Research Project 3050, HPG1 ASIC Test and Evaluation.Publication of this thesis does not constitute approval by Draper or the sponsoring agencyof the findings or conclusions contained herein. It is published for the exchange andstimulation of ideas.
or's signature)
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Acknowledgements
I would first like to thank the Charles Stark Draper Laboratory for sponsoring my work onthis project. I would also like to thank my Draper supervisor Paul Ward and faculty advisorProfessor James Roberge for their invaluable technical guidance, insight, and patience. Inaddition, I would like to thank David McGorty of Draper Laboratory, for this project could nothave been completed without his technical guidance. I would also like to express my gratitudetowards the following people at Draper who made this thesis possible: Bob Kelley, Phil Juang,Amy Duwel, and Rob Bousquet. Finally, I would like to thank Dr. Marc Weinberg for providingme the opportunity to work at Draper.
5
Contents
1 Introduction
1.1 Background . . . . . . . . . . . . . . . . .
1.1.1 Application . . . . . . . . . . . . .
1.1.2 Choosing the ADC Architecture . .
1.2 Purpose and Organization of this Paper. .
1.3 Definition of Resolution . . . . . . . . . .
2 Analysis of the Draper]
2.1 Sigma-Delta Modulato
2.1.1 Sources of Nois
2.1.2 Signal and Nois
2.1.3 Performance ..
Design
r - - - - - -
e . . . . . . .
se Transfer Fuinctions.
2.2 Digital Filter . . . . . . . . . . . .
2.2.1 Overview . . . . . . . . . .
2.2.2 Architecture . . . . . . . . .
2.3 Combined Analysis . . . . . . . . .
2.3.1 Signal and Noise Power . . .
2.3.2 Downsampling . . . . . . .
2.3.3 Obtaining Filter Parameters
2.4 Results . . . . . . . . . . . . . . . .
2.4.1 Filter Parameters . . . . . .
2.4.2 Multiplexing . . . . . . . . .
2.5 Laboratory Setup and Measurements
6
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. . . 19
21
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25
. . . 27
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28
. . . 30
30
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37
. . . . . . . . . . . .
. . . . . . . . . . . .
3 Simulation Using Simulink
3.1 Overview . . . . . . . . . . . . . .
3.2 Sigma-Delta Modulator . . . . . .
3.2.1 Thermal Noise . . . . . .
3.3 CIC Filter . . . . . . . . . . . . .
3.4 Results . . . . . . . . . . . . . . .
3.4.1 SDM Settling Time .
3.4.2 ADC Performance . . . .
4 Simulation of the Hardware Using
4.1 Overview of the Test Bench . . .
4.2 Thermal Noise Blocks . . . . . .
4.3 VHDL Implementation of the SDIM
4.4 VHDL Implementation of the CIC
4.4.1 Architecture . . . . . . . .
4.4.2 Register Sizing . . . . . .
4.4.3 Performance . . . . . . . .
4.5 Design Guidelines . . . . . . . . .
4.5.1 Truncation Noise Analysis
4.5.2 Approach to Design . . . .
4.5.3 Multiplexing . . . . . . . .
4.6 Synthesis of VHDL Code . . . . .
4.6.1 Synthesizability and Power
4.6.2 Alternate Architecture . .
VHD
Filter
Consi
5 Conclusion
Bibliography
A Matlab Scripts
A.1 rn-choose.m..... .. ................................
A.2 cic-filt.spec.m ... .. .. . ... .. . ... . . . . . . . . .. ... . .
7
IL
. . . . . .
. . . . . .
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B VHDL Code 87
B.1 read-prn.vhd . ... .... .... . ... .. .. ... . .. ... . . 87
B .2 prn.vhd .. .. ... ..... .. ... .. .. .. .. .. .... .. . 89
B .3 prn2.vhd .. .. ... ..... .... ... .. .. ... .. ... .. . 91
BA com p-cic.vhd ............................... 95
B.5 com p-cic2.vhd . ... ..... .... ... .. .. ... .. .... . . 99
B.6 comp-sdm .vhd . ... ....... .. ... .. .. ... ... ... . . 103
B.7 comp-allAb.vhd ... ..... .. .. ... .. .. ... ... ... . . 107
List of Figures
1-1 Flash ADC Architecture . . . . . . . . . . . . . . .
1-2 Semi-Flash ADC Architecture . . . . . . . . . . . .
1-3 Sigma-Delta ADC Architecture . . . . . . . . . . .
14
14
15
2-1 SDM Block Diagram ....... ........................... 20
2-2 SDM Discrete-Time Representation . . . . . . . . . . . . . . . . . . . 20
2-3 Distribution of e[n] based on input voltage . . . . . . . . . . . . . . . 21
2-4 Signal and noise transfer functions of the SD2-ADC . . . . . . . . . . 24
2-5 CIC Filter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 28
2-6 Magnitude response of a CIC filter with N=3, R=1000. . . . . . . . . 30
2-7 Laboratory measurement of SDM settling time . . . . . . . . . . . . . 36
2-8 Layout of the Test Chip . . . . . . . . . . . . . . . . . . . . . . . . . 37
2-9 SDM Thermal Noise Plot . . . . . . . . . . . . . . . . . . . . . . . . . 38
3-1 Top-level Simulink Model Block Diagram . . . . . . . . . . . . . . . . 41
3-2 SDM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3-3 Details of "Stage 2" of the SDM . . . . . . . . . . . . . . . . . . . . . 42
3-4 Simulink CIC Filter Implementation . . . . . . . . . . . . . . . . . . 44
3-5 Modified SDM Block Diagram . . . . . . . . . . . . . . . . . . . . . . 45
3-6 SDM Settling Response . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3-7 Decay of the SDM output oscillation . . . . . . . . . . . . . . . . . . 46
3-8 SDM Simulation PSD .-. . . . . . . . . . . . . . . . . . . . . . . . . . 48
3-9 ADC Output for 5Hz Sine Input . . . . . . . . . . . . . . . . . . . . . 49
3-10 PSD for ADC Output with 5Hz Sine plus thermal noise input 50
9
3-11 PSD of Thermal-Noise-Stimulated ADC Output . . . . . . . . . . . . 50
3-12 ADC Output with Multiplexed Inputs . . . . . . . . . . . . . . . . . 51
4-1 VHDL Test Bench Block Diagram . . . . . . . . . . . . . . . . . . . . 53
4-2 Shift-Register-Based Pseudorandom Number Generator . . . . . . . . 55
4-3 PSDs of simulated thermal noise using prn.vhd . . . . . . . . . . . . . 56
4-4 PSDs of simulated thermal noise using prn2.vhd . . . . . . . . . . . . 57
4-5 Block Diagram of COMP..SDM . . . . . . . . . . . . . . . . . . . . . . 58
4-6 VHDL-Generated Sine Wave with a Non-Integer Fundamental Frequency 59
4-7 Effect of Resetting the Variable count . . . . . . . . . . . . . . . . . . 60
4-8 Comparison of VHDL- and Simulink-generated Sine Waves . . . . . . 60
4-9 PSD of the VHDL and Simulink SDM Outputs . . . . . . . . . . . . 61
4-10 PSD of the Simulink CIC Filter Output when Using Different SDM
M odels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4-11 Block Diagram of the CIC Filter Implemented in VHDL . . . . . . . 62
4-12 Magnitude Response Comparison . . . . . . . . . . . . . . . . . . . . 64
4-13 Thermal Noise - Noise Floor Mismatch in VHDL . . . . . . . . . . . 68
4-14 Distribution of Truncation Noise . . . . . . . . . . . . . . . . . . . . . 70
4-15 Comparison of the Predicted and Actual output SNR for R=900, N=3 73
10
List of Tables
2.1 Filter parameters for various ENOB values . . . . . . . . . . . . . . . 34
2.2 Settling time for various ENOB values . . . . . . . . . . . . . . . . . 36
3.1 SDM settling time for various output widths . . . . . . . . . . . . . . 47
3.2 Simulation Summary for a 5Hz, 4V Peak-to-Peak Sine Input . . . . . 50
4.1 Register widths for R and N values used in the Simulink model . . . . 66
4.2 Approximate VHDL ADC signal-to-noise ratio in dB, N=3 . . . . . . 68
4.3 SNRn for 5Hz, 4V Peak-to-Peak Sinusoid Input, N=3 . . . . . . . . 72
4.4 Power consumption for CIC filter, R=900, N=3 . . . . . . . . . . . . 75
4.5 Power consumption for CIC filter, N=3, B0 st = 18 . . . . . . . . . . . 75
4.6 Power consumption for comp.cic2.vhd, N=3, B0 st = 18 . . . . . . . . 76
11
Chapter 1
Introduction
1.1 Background
1.1.1 Application
Draper Laboratory's high-precision MEMS-based inertial instruments for navigation
(such as gyroscopes and accelerometers) are capable of providing an extremely high
dynamic range difficult to achieve with conventional techniques. MEMS-based in-
struments have the added advantage that the sensor is extremely small, significantly
reducing the size of the overall package.
In order to successfully design such sensors, however, one important issue must
be resolved. There are several environmental factors that can affect the behavior
of MEMS sensors, and to a much lesser degree, the analog circuitry. Because some
applications for these instruments demand extremely high dynamic range, the errors
induced by these environmental factors can become very significant. For example,
changes in temperature can significantly affect the bias and scale factor of MEMS-
based instruments. This dilemma is made more significant by the fact that naviga-
tional instruments are typically exposed to various different environmental conditions
and need to perform consistently in all conditions.
To resolve this problem, various analog sensors are used to measure the environ-
mental conditions that affect the performance of the MEMS sensor. The obtained
12
analog signals, called compensation variables, are then digitized by an analog-to-
digital converter (ADC). This digital data is processed by an on-board computer
using a model of the error introduced by the various environmental stimuli on the
MEMS sensor, and the output of the instrument is compensated accordingly.
For the application examined in this paper, it is necessary for the electronics sur-
rounding the MEMS sensor to be low-power and minimum-hardware. For this reason,
one ADC is shared by multiple compensation variables present in this application.
This sharing is done by multiplexing the compensation variables to the ADC input
and switching the multiplexer at a constant rate.
The next section briefly discusses various common analog-to-digital conversion
techniques, and the design choices made in the ADC examined in this paper.
1.1.2 Choosing the ADC Architecture
Analog-to-Digital Converter Architectures
The topic of analog-to-digital conversion has been studied extensively, and a wide va-
riety of conversion methods exists as a result. Some of the more widely-used methods
will be mentioned here.
One of the most common type of ADCs is the flash converter. Flash converters
can reach very high sampling rates since the only analog building blocks are the
comparator and the resistor ladder [1]. Figure 1-1 illustrates the architecture.
As the figure shows, the resistor ladder provides various reference levels for the
comparators. Each comparator reads in one reference level and compares it against
the analog input, and the collective outputs of the comparators are decoded to form
a digital output. The main problem with this architecture is that the number of com-
parators increases exponentially with the number of bits. Because of this hardware
requirement, the power and area requirements become unreasonably large for a high
number of output bits [1]. In addition, because the resistors must be well-matched,
extremely precise analog circuitry is needed.
To reduce the number of comparators, the semi-flash converter can be used. As
13
AnaloNV tInpl x
rl+
Dlecoder
Digi tal
Ou-tpuIt
Figure 1-1: Flash ADC Architecture
Figure 1-2 shows, the analog-to-digital conversion is done in two stages. In the first
stage, a coarse ADC is used to generate N1 most-significant-bits (MSBs) of the output.
A digital-to-analog converter (DAC) then converts the output of the coarse ADC and
subtracts it from the original analog input to produce a "residue" signal. A second
ADC is then used to convert the residue signal and generate N2 least-significant-bits
(LSBs). This ADC architecture is much slower than the flash architecture, but it only
requires 2N1 + 2 N2 -2 comparators, as opposed to the 2N1+N2 -1 comparators needed
for the flash architecture [1]. However, like the flash converter, semi-flash converters
also require high-precision analog circuitry in order to achieve good resolution.
ig Residue
ADC1 DAC
Ni Coars e Bits
ADC2 -
N2 Fine Bits
Figure 1-2: Semi-Flash ADC Architecture
There are several other ADC architectures based on the architectures shown so
far. The folding and interpolating ADC architecture is similar to the semi-flash
architecture, but instead of using a DAC and a subtractor to create the residue
14
AnaloInput
signal, it uses an analog "folding circuit" that takes in the analog input and produces
the same signal. Thus, the coarse and the fine ADCs can convert the input signal
almost simultaneously. The multi-stage pipelined ADC is similar to the semi-flash
ADC, but it differs in that there are many more stages (Figure 1-2 shows only two),
and each stage is pipelined. This variation allows the pipelined ADC to have a much
higher sampling rate than the semi-flash ADC [1].
The oversampling sigma-delta ADC architecture is quite different from the ar-
chitectures mentioned thus far. Figure 1-3 shows a simplified block diagram of the
sigma-delta ADC.
-----------------------------
filter ' QuantizerAnalog Digital
Input Output
clk
DAC *- -
Sigma-Delta Modulator
Figure 1-3: Sigma-Delta ADC Architecture
As the figure shows, the sigma-delta ADC is divided into two major parts: the
sigma-delta modulator (SDM) and the digital filter. The basic thought behind sigma-
delta modulation is the exchange of resolution in time for resolution in amplitude. As
shown in the figure, the quantizer (which can be thought of as a very coarse ADC)
quantizes the signal at its input, creating a digital output. This digital output is
converted back to an analog signal by the DAC, and the DAC output is compared
to the input of the modulator by the subtractor. This negative feedback of the loop
suppresses the error caused by the quantizer for the signals falling within the passband
of the loop filter [2]. Also, by oversampling the quantizer, noise power is spread over
to frequencies beyond the band of interest. Thus, the output of the SDM will have
extremely low error in the passband of the ADC (as defined by the loop filter). The
digital filter following the SDM has two purposes. First, because the input signal is
15
oversampled, the output of the SDM must be downsampled to the original analog
input bandwidth. However, because there is a large amount of out-of-band noise in
the SDM output, simply downsampling the SDM output will result in the aliasing of
out-of-band noise into the band of interest. Thus, the digital filter must first remove
the out-of-band noise, and then downsample the result. Unlike the architectures based
on resistor ladder networks, oversampling sigma-delta converters do not require high-
precision analog circuitry. Since its resolution is not limited by imperfections in the
circuitry, sigma-delta ADCs are suitable for high-resolution applications that require
a complete integration of the circuit onto an application-specific integrated circuit
(ASIC) [1]. However, because it oversamples the input, sigma-delta ADCs are more
suited for narrow-bandwidth applications. Also, sigma-delta ADCs are much slower
than the other architectures mentioned, mostly due to the settling time (the time
between the initial reading of the input and the output of the filter becoming valid)
of the digital filter.
As mentioned earlier, this section mentions only some of the more commonly-used
ADC architectures. Several other architectures not mentioned in this section, such as
the successive approximation converters and various types of integrating converters,
are still widely used today.
Design Choices
For the application described in the previous section, it was decided that a sigma-
delta ADC design would be used. There are several reasons for this choice. One
is that sigma-delta ADCs do not require precision analog hardware required by the
other architectures, thus reducing cost and complexity of the analog circuitry. The
reduction of complexity results in a reduction of area and power. In addition, for
low-speed, narrow-band applications, sigma-delta ADCs can achieve a much higher
signal-to-noise ratio (SNR) compared to other designs, which makes it suitable for
high-precision applications like navigational instruments. One major shortcoming of
the sigma-delta design is its large settling time. However, this shortcoming is not a
cause for great concern since the compensation variables vary at an extremely low
16
rate. Because of this low rate of change, even if the multiplexer switchs the input
to the sigma-delta ADC at a rate slow enough for the ADC to settle, all of the
compensation variables can be digitized at a satisfactory rate.
Prior to the start of this project, the sigma-delta modulator used for the ADC was
designed, and the architecture of the filter used for decimation was selected. Some
simulation models were created prior to the start of this project to test the feasibility
of the planned implementation. The following section discusses the topics covered in
this paper.
1.2 Purpose and Organization of this Paper
The main focus of this project is to accurately analyze, model, and simulate the
performance of the proposed sigma-delta ADC in order to determine the tradeoff
between resolution and the multiplexing of the inputs. This tradeoff can more simply
be seen as a tradeoff between resolution and settling time. By understanding this
relationship, one can easily design the ADC such that it will achieve the desired
resolution for multiple inputs.
The paper is organized as follows. Chapter 2 analyzes the SDM and digital filter
mathematically in order to predict its behavior. It also discusses some laboratory
work done in order to verify the performance of the SDM. Chapter 3 describes the
ADC simulation model created in Simulink and discusses the results obtained in
simulation. Chapter 4 discusses the ADC simulation model created in VHDL and
the simulation results. It also discusses issues regarding the implementation of the
digital filter in hardware, such as synthesizability and power consumption. Chapter
5 is conclusion.
1.3 Definition of Resolution
In order to study the tradeoff between resolution and settling time, the term resolution
must be clearly defined. In the analysis shown in the next several chapters, resolution
17
is defined in terms of effective number of bits (ENOB).
For an ADC with a finite number of bits at the output to represent an analog input
signal, some quantization noise at the output is inherent. Given this fact, Engelen
[2] determines the maximum possible signal-to-noise ratio (SNR) of an ADC with B
output bits, SNRmax, as follows. The maximum amplitude of a sinusoid that does
not cause the quantizer to overload is Ama , - 2, where q is the quantization step
size. The root-mean-square (rms) amplitude of this sinusoid is then Amax,rms = 2.
The total quantization error power in the Nyquist frequency range is Nq = e. The12
derivation of this value is explained in Section 2.1.1. The rms amplitude of Nq is
Nq,rms =q. SNRmax is then calculated as
SNRmax = 20 - log 10 (A,"r""') = 20 -log 1 0 ( qlV-12)
=B -6.02 + 1.76 (1.1)
For a given B, SNRmax is the highest attainable signal-to-noise ratio. By rear-
ranging Equation 1.1, we can solve for B, which can be construed as the effective
number of bits for a given SNR.
ENOB = Rmax -1.76 (1.2)6.02
The concept of ENOB will be used in the following chapters as a guideline for
design.
18
Chapter 2
Analysis of the Draper Design
As mentioned earlier, the sigma-delta ADC design being evaluated is comprised
mainly of a second-order sigma-delta modulator (SDM) coupled with a digital low-
pass filter. In this section, these components will be analyzed mathematically. The
resulting calculations will be used as a guideline to determine the achievable resolution
and the associated multiplexing rate.
2.1 Sigma-Delta Modulator
The sigma-delta ADC used in the inertial instrument to convert compensation vari-
able signals incorporates the sigma-Delta modulator SD2ADC, a second-order switched-
capacitor-based design. This SDM typically runs at a sampling rate of 320KHz and
consumes 7mW of power at 5V. Figure 2-1 is a block diagram of the modulator.
Although the SDM is an analog circuit, it operates like a digital circuit and can
be analyzed as such. Figure 2-2 is a discrete-time equivalent of Figure 2-1. In this
block diagram, the switched-capacitor-based integrators are represented with the ac-
cumulator system function G(z) = __. Also, the 1-bit digital-to-analog converter
used to feed back the digital output y[n] can be removed since the system is already
digital. The gain values a, b, c, d, and e are chosen as such in order to keep the
system stable.
19
e=1/31-bitquantizer
IN a=1/5 - dt b=1/3 d dt §
d=1/6
Figure 2-1: SDM Block Diagram
e [n]
=15G(z) bn G(z)
s[n]= 1-bix[n]+t[n] quan izer
c=1/5 d=1/6
20
Figure 2-2: SDM Discrete-Time Representation
2.1.1 Sources of Noise
Quantization Noise
The 1-bit quantizer, which lies at the output of the SDM, produces an output of
2.5V if the input is positive, and -2.5V if it is negative. As shown in Figure 2-2,
the effect of the quantizer can be approximated simply as an additive noise sequence
e[n]. Typically, given the quantization level A = 5.OV, e[n] can be approximated as
a uniformly distributed white-noise sequence, distributed over ± with a probability
of A. This distribution is shown by Figure 2-3. The variance of uniformly distributed
white noise is calculated as follows:
A 'A2-2 Te2 de = -=2.0833 (2.1)
2
P (e)
1/5
e-2.50 2.50
Figure 2-3: Distribution of e[n] based on input voltage
In the case of a white noise sequence, its power spectral density (PSD) is constant
over all frequency with its magnitude equal to its variance. Thus, for e[n]:
V2
<De(ejw) = 2.0833- (2.2)rad
In reality, the quantization error sequence e[n] is not exactly a white noise sequence
due to the fact that e[n] is correlated with the input x[n]. However, the white noise
approximation is made more valid by the fact that other sources of noise in the SDM
act as a dither signal that randomizes the input.
21
Thermal Noise
Because the SD2_ADC is a switched-capacitor-based design, it is also susceptible to
thermal noise. According to Norsworthy [3], thermal noise is caused by the random
fluctuation of carriers due to thermal energy. Because thermal noise is present even at
equilibrium (e.g., in a turned-on MOSFET with zero average current flow), it needs
to be taken into account for both the switches and op-amps in a switched-capacitor
circuit. Thermal noise can be approximated as having a flat spectrum and a wide band
that is limited by the time constants of the switched capacitors (which is determined
by the size of the capacitors and the on-resistance of the switches) or the bandwidth
of the op-amps. Thermal noise spectrm is flat because it is generally uncorrelated
with the input. Because the sampling rate of the circuit is typically lower than the
bandwidth of the thermal noise, the effect of the noise is worsened by aliasing.
The thermal noise performance of an SDM is determined mainly by the switch
noise and the op-amp noise of the first integrator (that is, the integrator closest to the
input) because of the gain this integrator provides for the lower in-band frequencies
[3]. Thus, as shown in Figure 2-2, thermal noise can be modeled as additive noise
t[n] at the input of the SDM.
As mentioned earlier, thermal noise is generally uncorrelated with the input [2].
Because of this fact, thermal noise can be modeled as a normally distributed band-
limited white noise sequence. Previous testing of the SDM indicate that the thermal
noise level is approximately -1 14 dBv 2 1HZ
Other Sources of Noise
In addition to quantization and thermal noise, there are several other sources of noise
in the SDM. They are not considered in the analysis because they are insignificant
compared to thermal and quantization noise. Aliasing noise and idle tones are two
such sources of noise. Because the input signal is bandlimited by a low-pass filter,
the effect of aliasing due to SDM sampling is minimized. In this analysis, this type
'From an unpublishable Draper internal memorandum
22
of aliasing noise will be simply grouped with thermal noise. Idle tones can become
a noticeable noise source in the passband for constant inputs near the rail. Such
inputs cause problems because a constant positive input near the rail may produce
an output pattern that consists mostly of I's with an occasional, periodic 0, while
the converse will occur with a constant negative input. These occasional O's or l's
have low periodicity and are reflected as spikes in the passband. In order to avoid
this form of noise, the input voltage to the SDM is limited to +2. Thus, this source
of noise need not be considered.
2.1.2 Signal and Noise Transfer Functions
The behavior of the SDM is characterized by its signal transfer function (STF) and
noise transfer function (NTF). As the name suggests, the STF determines how the
input signal x[n] is affected by the modulator, while the NTF determines how the
quantization noise sequence, in this case e[n], is shaped. By using superposition, the
STF YN)and the NTF Y can be determined independently. Based on Figure 2-2,X(z) E(z)
the STF is determined as follows:
Y(z) = V(z)G(z) (2.3)
V(z) = eX(z) + bG(z)W(z) - dY(z) (2.4)
W(z) = aX(z) - cY(z) (2.5)
which combine to form:
Y(z) _ abG2 (z) + eG(z) (2.6)X(z) - 1+dG(z)+bcG2(z)
Substituting in appropriate values for a, b, c, d, e, and G(z):
2 _ 1-1STF(z) = - 3 (2.7)37 13 Z-1 + Z- 2
30 T
23
The NTF of the SDM can be determined similarly. To determine the NTF:
Y(z) = E(z) + G(z)V(z) (2.8)
V(z) = bG(z)W(z) -dY(z) (2.9)
W(z) = -cY(z) (2.10)
which combine to form:
1 - 2z-' + z-2NTF (z)--7-13 z- 1 + z- 2 (2.11)
TO- 6
2-T
1.8-
1.6 -
1.4-
0.8-
0.6
0.4-
0.2-
0 0.05 0.1 0.15 0.2 0.25 0. 3 0.35 0.4 0.45 0.5frequency (rad)
Figure 2-4: Signal and noise transfer functions of the SD2_ADC
The frequency characteristics of the STF and the NTF can be examined by re-
placing the variable z in Equations 2.7 and 2.11 with ej'. The variable W ranges
from 0 to 27r, which is equivalent to 0Hz to the sampling frequency f,. Figure 2-4
shows the magnitude response of the STF and the NTF, with the x-axis being the
radian frequency w. It can be seen from Figure 2-4 that at low frequencies, the signal
x[n] will be minimally affected by the SDM since it is shaped by the STF. However,
the quantization noise will be shaped by the NTF such that it is minimized at low
frequencies.
24
2.1.3 Performance
The performance of an SDM is typically measured in terms of its signal-to-noise
ratio (SNR), a ratio of the signal and the noise power. Before introducing the non-
idealities associated with the actual filter used in the Draper Laboratory design, a
100Hz brick-wall low-pass filter can be applied in order to get a good sense of the
SDM performance.
In [4], total power in signal g[n], P9 is defined as:
P9 = E(g 2 [n]) = Ogg [0] = 1 jD.,(eiW)dw (2.12)
where E(g2 [n]) is the expected value of g2[n], qgg[r] is the autocorrelation of g[n], and
4bg,(eiw) is the fourier tranform of #gg [7]. bgg(eiw) is also the power spectral density
(PSD) of the sequence g[n].
In determining the power of the input signal x[n], the signal transfer function of
the SDM, STF(ew), and the low-pass filter must also be taken into account.
Px = -Lfw_". (ew) -ISTF(w)| 2 dW (2.13)
w, = 27rfcT = 27r(lOOHz)( 3 2 KH 0.2rad (2.14)
Some simplifying assumptions can be made with regards to Equation 2.13. In
this analysis, the input x[n] is simply a 5Hz, 4V peak-to-peak sinusoid. Thus, the
signal is unaffected by the low-pass filter. Also, since the signal is a at relatively low
frequency, the STF can be approximated as unity. This simplification makes power
easy to determine. If x[n] = 2 cos(t), then using Equation 2.12
Px = E([2cos(t)]2) = 4. E( 1[1 + cos(2t)]) = 2V 2 (2.15)
The quantization noise power is calculated in a similar manner, but its PSD is
25
shaped by the noise transfer function rather than the signal transfer function.
Pe = -Lf_', 'De(ew) - INTF(w) 2 dw (2.16)
= f_"': -(2.0833) - INTF(ew) 2 dw
= 8.62 x 10-13V 2 (2.17)
It can be seen from Equation 2.16 that quantization noise in the low-pass-filtered
region is significantly reduced by the noise transfer function. Given the power of the
signal and the quantization noise, the SNR of the SDM due to the quantization noise
can be determined.
SNRq = 10- log10 (Pi) ~ 123.66dB (2.18)Pe
Using the definition of effective number of bits (ENOB) described in Section 1.3,
123.66dB translates to approximately 20 bits of resolution. However, thermal noise
further limits the effective resolution of the SDM. In fact, because thermal noise is
not shaped by the NTF, it could actually be more significant at lower frequencies.
Earlier, the thermal noise level was given as -114 2. The value -114dbV 2 can alsoHz
be represented as follows.
-114dB V2 = 10. log 1 o ((V 2 2.\ dB1 2 V2 ) (2.19)
x = 3.98 x 10~ 2 V2
bth (f) = 3.98 x 1 0 -12V 2 (2.20)
As shown above, the thermal noise level can also be expressed as 3.98 x 10-12V ForHz
a 100Hz band, the resulting thermal noise power is:
Pth = 0 Pth (f)df = 3.98 x 10- _- 100Hz = 3.98 x 10~ 10V2 (2.21)f H z
26
resulting in a signal-to-noise ratio of
S NRh = 10 -log 0 y ~ 97.01dB (2.22)(Pth
This value, which is significantly lower than SNRq, is equivalent to approximately 16
bits of resolution.
These calculations assume an ideal filter in order to focus on the performance
of the SDM. In reality, non-idealities associated with the digital filter actually used
further limit the achievable resolution. This relationship is examined in later sections.
2.2 Digital Filter
2.2.1 Overview
The output of the SDM represents an oversampled input sequence along with various
in- and out-of-band noise. The purpose of the digital filter is to preserve the original
input while removing the out-of-band noise. Once the filtering is done, the signal
must be downsampled in order to reflect the original input. Insufficient filtering can
result in significant noise penalty due to aliasing caused by downsampling.
In the Draper sigma-delta ADC design, the architecture used for digital filtering
is a finite-input-response (FIR) low-pass filter implentation known as the cascaded
integrator-comb (CIC) filter [5]. This implementation is used for two main reasons.
First, it has a simple hardware implementation. As mentioned earlier, one of the main
design considerations for the Draper sigma-delta ADC is low power consumption. As
shown in the next section, the CIC filter is extremely hardware efficient, requiring
only adders and registers. Because of its hardware simplicity, it consumes less power
than FIR architectures that require multipliers. Second, the filter architecture is
such that a separate decimator is not needed. The downsampling rate can simply be
specified as a filter parameter.
27
Integrator Section
Stage N
Z-1
ffs -.s
R
Stage N+1 S
Z-1 * *
-1
* *
Figure 2-5: CIC Filter Block Diagram
2.2.2 Architecture
A block diagram of the CIC decimation filter is shown in Figure 2-5. As the figure
shows, the filter is divided into two main sections, the integrator section consisting of
a set of N integration stages and the comb (differentiator) section formed by a set of
N differentiation stages.
Each integration stage is implemented as a one-pole filter with a unity feedback
coefficient. It runs at the high sampling rate of f8, which is the same as the clock
rate of the SDM. The system function of each integrator stage is
1Hi(z) = 1 (2.23)
As seen from Figure 2-5, the comb section receives only every Rt" dati sample from
the integrator section. Also, each differentiation stage runs at the downsampled
frequency of L. This reduced clock-rate operation of the comb section effectively
results in the downsampling of the output data by a factor of R. The system function
of a single differentiation stage, relative to the high sample rate f, is
28
Stage 1
Z-1
fs
* S S
OSO
OSS
Stage 2N
Z-1
-1
R
Comb Section
Hc(z) =1 - z- (2.24)
Combining equations 2.23 and 2.24, the system function of the overall filter can
be determined.
N N 1 -Z-R )N -1 lN
H(z) = HIN(z)HC = -g-1 = [ -k] (2.25)( ) k=O
It can be seen from Equation 2.25 that a CIC filter with N stages in each section is
essentially an Nth-order FIR filter. The magnitude response of the Nth order CIC
filter is as follows.
|H(ejw)I2 _ _ n)N N _ 1 N (sin N(e ± -2j sin t)N 2
~ N_ (2.26)
As Equation 2.26 shows, the magnitude response of a CIC filter is approximately
equal to an Nh -order sinc function. The shape of the sinc function is dependent
solely on the order N and the downsampling rate R. Thus, these variables can be
manipulated to provide the desired passband and rolloff characteristics of the filter.
Figure 2-6 is an example with N = 3 and R = 1000.
It should be noted that the system functions of the CIC filter shown above apply
to the filter operating at the high sample rate f,. The operation of the CIC filter
can be viewed as a two-step process. First, the SDM data, which is sampled at
f, = 320KHz, is shaped by the function shown in Equation 2.26. The variable W in
this function is calculated relative to the sampling rate of the SDM (the high sample
rate). Next, output of the filter is resampled at the low sample rate of L'. This
resampled output is the final output of the filter. The effect of decimation, as well as
the details regarding the hardware implementation of the filter, are discussed in later
sections.
29
CIC Filter Power Response, R=1000, N=3
1010
10
10-51 -4 2 0
log frequency (rad)
Figure 2-6: Magnitude response of a CIC filter with N=3, R=1000.
2.3 Combined Analysis
In this section, the results of the SDM analysis and the CIC filter analysis will be
combined to estimate the performance of the Draper sigma-delta ADC.
2.3.1 Signal and Noise Power
In the case of the ideal 100Hz brickwall filter, the signal remained unchanged, while
noise remained only in the passband. However, because the CIC filter exhibits some
attenuation in the passband, signal power must be reevaluated. Also, noise must
be evaluated over the entire spectrum since out-of-band noise cannot be removed
completely by the CIC filter.
The input signal in this analysis is a fi, = 5Hz, 4V peak-to-peak sinusoid.
Since all of its power is contained at one frequency, the filtered signal power, P'f, is
calculated simply as
Pxf = Px -jH(ewaig)12 (2.27)
Wig = 27rfsigT = 27r(5Hz)(2 1kH) = 9.8175 x 10-5rad
30
where IH(ej')I is from Equation 2.26. As long as the design of the filter is such that
W,8 g is less than the cutoff (-3dB) frequency of the filter, the attenuation of the signal
in the passband is not significant.
Out-of-band quantization noise power is significantly reduced by the CIC filter,
but it cannot be completely removed. Power of the shaped quantization noise is
calculated as:
Pef = +Jc e(e3) -|NTF(w)12 - H(ejw) dW (2.28)2,7r - w
While most of Pef comes from the noise in the passband, filtered out-out-band noise
covers a wide frequency band and cannot be ignored for several reasons. One is that
the out-of-band noise covers a much wider spectrum than the in-band noise. More
importantly, the out-of-band noise is shaped by the NTF, which increases according
to the order of the SDM at high frequencies. The filter must be good enough to
attenuate the rising noise.
It was previously stated that the thermal noise level of the SDM running at
320KHz was - 114 dbv, which is equal to 3.98 x 10-12V2 (Equation 2.20). Given thisHz 7Hz
information, the thermal noise PSD in radians, cJth(ejw), and thermal noise power
after filtering, Pthf, can be calculated.
foo4 Dth(f)df = ot (2.29)
= (3.98 x 10-12) - ( ) = 6.368 x 10- 7V2
Noting that Dth (eiw) is also constant over the entire spectrum,
2 = _L~T~j'r=th 2 Jr Dth (ejw)dW (2.30)
4Dth(ejw) = a2 (2.31)
Pthf = -Lf, rIth(ejw) - |STF(w)12 -_IH(ejw)12 dw (2.32)
Equations 2.29 and 2.31 can be found in [6] and [4], respectively. The above
equations assume that thermal noise, like quantization noise, is white. While both
quantization and thermal noise are approximately white, out-of-band thermal noise
31
is less significant than quantization noise due to its shaping by the STF rather than
the NTF.
Using Equations 2.27, 2.28, and 2.32, the signal-to-noise ratio of the overall SDM
can be calculated as:
SNR = 10 - log 0 (2.33)\Pef + Pthf (
2.3.2 Downsampling
As mentioned earlier, the CIC filter not only low-pass-filters the signal but also down-
samples the output by a factor R relative to the input. In order to prevent the aliasing
of the passband that could result from downsampling, R must satisfy the following
inequality.
2f >fp b
R < (2.34)2fpb
fpb in the above equation represents the highest frequency in the passband. In the
case of the input signal a~n], fpb can be replaced with foig = 5Hz, resulting in the
Rnax = 32, 000.
Even if R is less than Rmax and the signal in the passband is not aliased, because
the CIC filter cannot completely remove out-of-band noise, aliasing of noise outside of
the passband cannot be avoided. As a result, the out-of-band noise essentially "folds
into" the passband after downsampling, resulting in an increase in the noise level in
the passband. However, the total signal and noise power in the spectrum remains
unchanged after downsampling. Since the equations in the previous section take into
consideration the signal and noise power over the entire spectrum rather than just
the passband, the analysis need not be altered.
32
2.3.3 Obtaining Filter Parameters
Given a desired ADC resolution in terms of ENOB (effective number of bits), the
equations for signal and noise power in the previous section can be used to determine
the necessary filter parameters. However, because it is exceedingly difficult to come
up with a closed form expression to solve for the filter parameters N (filter order) and
R (decimation rate) given the ENOB, a Matlab script was created to automate this
task. This script, rn-choose.m, can be found in Appendix A.1.
The following parameters are specified in the script.
" Desired ENOB
" SDM sampling rate f,
* SDM order p
" SDM transfer functions STF(ew) and NTF(ew)
" Signal frequency f8ig
" Quantization noise PSD <I,(ew) =a,.
* Thermal noise PSD bIth(e=w) _h
Given this information, the script iteratively produces the CIC filter magnitude re-
sponse IH(eiw)l and calculates the values Pj 1, Pef, and Pthf in order to determine
the ADC signal-to-noise ratio. As the starting point, the script chooses N = p + 1.
Setting N as such is to ensure that the rolloff of the filter, which is determined by its
order, is greater than the rate at which the NTF rises. For each value of N, R starts
from 0 and is incremented by 1 until the calculated SNR is high enough to obtain the
desired ENOB. In case the given ENOB cannot be achieved due to the limitations
of the SDM and the filter, the script also stops running when increasing R lowers
the SNR (which would happen when the cutoff frequency of the filter is low enough
to severely attenuate the input signal). The script produces matching R values for
N = p+1....-, p + 3. Multiple R-N pairs are obtained in order to find a pair that
produces the optimal settling time.
33
2.4 Results
2.4.1 Filter Parameters
Using the Matlab script rn-choose.m, filter parameters were obtained for ENOB of 14
bits and higher. The resulting filter parameters and the corresponding signal-to-noise
ratio are summarized in Table 2.1.
ENOB (bits) R SNR (dB)N=3 N=4 N=5 N=3 N=4 N=5
14 243 207 186 86.20 86.21 86.1715 387 333 300 92.07 92.10 92.1116 1171 1021 916 98.08 98.09 98.0817 5587 4875 4381 104.10 104.10 104.10
17.26 (max) 12550 10909 9781 105.66 105.65 105.64
Table 2.1: Filter parameters for various ENOB values
As shown in Table 2.1, for a 5Hz input signal, the maximum possible resolution is
approximately 17.26 bits according to this analysis. There are two reasons why the
ENOB cannot be increased beyond this point. One is that the filter cutoff frequency
cannot be less than fig, which results in an unavoidable minimum amount of noise
power. The other reason is that the filter's passband gets narrower with increasing R.
Since the passband attenuation is greater at higher frequencies, increasing R results
in greater input signal attenuation.
The calculations also show that the downsampling rate R increases significantly
for each additional bit of resolution, regardless of the choice of N. Thus, this filter
architecture, and perhaps the overall ADC design, may not be suitable for achieving
a significantly higher resolution.
2.4.2 Multiplexing
Much analysis and calculation were done so far in order to determine what the filter
parameter needs to be for a given resolution of the ADC. This data can now be used
to determine how fast the inputs to the ADC can be switched when the inputs are
34
multiplexed into one ADC.
In order to determine the optimal rate of switching the multiplexer, the settling
time of the ADC must be determined. In this analysis, settling time is defined as
the amount of time it takes for the output to reach a steady-state value given a step
input. The settling time of the ADC is determined by the settling time of the SDM,
tsdm, and the settling time of the digital filter, tfilt. Because these are the dominant
delays in the ADC circuit, settling time of the ADC is approximately
tadc = tsdm + filt (2.35)
The filter settling time tf il can be determined quite easily. In the case of an FIR
filter, the settling time of the filter is simply the amount of time it takes to fill every
tap of the filter with new data. That is, when the multiplexer switches the input to
the ADC from one source to another, the settling time of the filter is the amount of
time it takes for all the taps of the filter to contain a data sample of the new source.
Thus, in the case of the CIC filter (or any other FIR filter), the settling time can
be regarded as being independent of the inputs being multiplexed. In Equation 2.25,
the transfer function of the CIC filter was expressed as a summation notation. This
equation can be expanded as such.
H(z) = 1 + aiz-1 + a2 z~2 + ... + a(R-1)Nz-(2)36)
As expressed by this equation, a CIC filter with order N and downsampling rate R
will have (R - 1)N taps. Given this value, the settling time of such a CIC filter is:
1tfilt= N (R - 1) - 1 (2.37)
The settling time of the SDM is harder to derive analytically. Thus, the settling
time of the SDM was obtained by testing it in the laboratory. The details of the
laboratory setup is discussed in a later section. The SDM settling time was estimated
by injecting the SDM with a 20Hz, 4V peak-to-peak square wave. Figure 2-7 is a
35
screen capture of the oscilloscope with this setup. As seen in Figure 2-7, the SDM
Tek Run: 2.50MS/s Average
MM 2.65v L25 2OV M7W2.OJJs 4
A: 20.Opis@D: 20.Ops
2.UV V10Mar 200113:23:54
Figure 2-7: Laboratory measurement of SDM settling time
seems to settle approximately 20pus. However, this value is somewhat inaccurate and
will be discussed in more detail in Section 3.4.1.
Table 2.2 summarizes the settling times for different ENOBs and filter order.
Because the SDM settling time is orders of magnitude smaller than the filter settling
time, the values in this table only reflect the filter settling time. As the table shows,
ENOB (bits) Settling time (s)N=3 N=4 N=5
14 0.0023 0.0026 0.002915 0.0036 0.0042 0.004716 0.0110 0.0128 0.014317 0.0524 0.0609 0.0684
17.26 (max) 0.1176 0.1363 0.1528
Table 2.2: Settling time for various ENOB values
settling time consistently increases as the filter order goes up. Thus, when optimizing
the CIC filter for settling time, the lowest possible order filter should be chosen.
For the application in the inertial instrument, it was desired that four multiplexed
inputs be switched at a rate of 20Hz, essentially digitizing each input source at 5Hz.
This rate of multiplexing would require the settling time of the ADC to be -O-=
0.05s. It can be seen from the above table that such multiplexing would be possible
36
.. . . . . . . . . . . . . . .. .. . .
.. ..... ..............
. . . . . . . . . . . . . . . . . . ...... . . . . . . . . . . . . . . . . . . . . . .
.. . . . . . . . .
for upto 16 bits of resolution. For higher resolution, the multiplexer must be switched
at a slower rate to avoid error.
2.5 Laboratory Setup and Measurements
In order to verify the previously measured data and gather new data, various tests
were run on the SDM in the laboratory. Due to the lack of availability of the actual
inertial instrument electronics, the tests were run on a test chip, shown in Figure 2-8.
Figure 2-8: Layout of the test chip
One of the main difference between the actual SDM chip and the SDM in the
analysis is that the actual SDM does not produce output signals ranging from -2.5V
to +2.5V but rather produces t2.5V centered around a DC offset of +2.5V. This
offset, known as MID, can be seen as one of the inputs to the SDM core in Figure ??.
Both MID and the reference signal PREF are supplied by the a power source, while
the SDM clock was generated by the HP3325B Synthesizer/Function Generator.
In order to examine the settling behavior of the SDM, the SDM input was con-
nected to a 20Hz, 4V peak-to-peak square wave generated by the HP3325B function
generator. The output was viewed with a Tektronix TDS 754D Digital Phosphor Os-
37
cilloscope. In order to view the settling behavior in the SDM output, the averaging
function of the oscilloscope was used. This function reduces random noise in periodic
signals by storing the waveforms generated after each trigger event and then display-
ing the average of the collected waveforms. Thus, the output of the oscilloscope does
not exhibit any time delays. Figure 2-7 shows the result of averaging 100 samples.
Another test of interest was to verify the previously measured thermal noise level
of -114dY2 . Because sine waves generated by the function generator HP3325A hasHZ
a harmonic distortion of upto -65dB relative to the fundamental in the frequency
range of interest, the input to the SDM was simply tied to MID for this test. Also,
in order to reduce the noise associated with PREF, PREF was first passed through
a passive low-pass filter with a cutoff of 1KHz (R = 5KQ, C = 100pF). The output
of the SDM was viewed using the spectrum analyzer HP3585B. In order to improve
the resolution on the spectrum analyzer, a passive low-pass filter with a 1KHz cutoff
(R = 1.5KQ, C = 0.1puF) was used to reduce the noise level in higher frequencies.
Figure 2-9 shows the output of the spectrum analyzer.
REF 12.6 mV MARKER 451.0 Hz10 dB/OIV RANGE 12-6 mV 183 nV/.rHz
.-... ......-... .. ...-... 1- ----
. .-i--- ---------------i1 i....._.. ........
_ _ . ..L.............
CENTER 500.0 Hz SPAN 1 000.0 HzRBW 30 Hz VBW 100 Hz ST 2-4 SEC
Figure 2-9: SDM Thermal Noise Plot
The plot shows the thermal noise level to be approximately 180 V Since a
1oX probe was used, this value is actually 1.8--, which is approximately equal to
38
2 ___2-115dBvy. This value closely matches the previously measured valueHz
2From an unpublishable Draper internal memorandum
39
Chapter 3
Simulation Using Simulink
3.1 Overview
In order to determine the validity and the accuracy of the analysis shown in the
previous section, the sigma-delta ADC was simulated using Simulink, a graphical,
block-diagram-based tool that facilitates modeling and simulating dynamic systems in
Matlab. Simulink was used to simulate the design before implementing and simulating
the hardware in VHDL because of its speed and flexibility. The original Simulink
model of the overall compensation variable electronics was created by Ed Balboni of
Draper Laboratory, and the model was modified in order to focus on the SDM-CIC
filter interaction.
The top-level block diagram of the Simulink ADC model is shown in Figure 3-1.
As the figure shows, the model is comprised of the inputs, multiplexer, SDM, CIC
filter, a random number generator, and blocks to capture the data at various points
of the design. The switch s is used to choose between a single input or a multiplexed
input based on the type of simulation. All of these components operate on a common
clock running at of 320KHz.
The following sections discuss the implementation of each component in Simulink
and the results of simulation.
40
Corpensaton WriableAD Swimjtion
11heraW os
31 2nd order Sna-Deka
sMW Fs =4 MHzwwmWFsdmn=Ms125= 320Khz
sintWe
CIC Decmtn FierN=3
R=1167
__4
Figure 3-1: Top-level Simulink Model Block Diagram
3.2 Sigma-Delta Modulator
The SDM model created in Simulink is a discrete-time approximation of the actual
SDM design. Although it does not exhibit the various non-ideal qualities of an actual
SDM, this model does produce realistic quantization noise. Thus, its output is much
more reliable than the white noise approximation used in the previous section.
Figure 3-2 is the block diagram of the SDM. In this figure, The quantizer block is
followed by a gain of 2.5 in order to simulate a quantization level of 2.5V. The two
"stage" blocks are identical except for the inputs they take. Figure 3-3 shows the
components of the Stage 2 block.
Each stage associates its inputs with the appropriate gain and integrates them.
The discrete-time switched-capactior integrator is simulated by a continuous-time
adder with a unit delay in its feedback loop. A saturation block is used to keep the
integrator from going above or below ±2.5V.
41
Figure 3-2: SDM Block Diagram
abcd24
In2abcd2l + Y12
+1-2.5 Ot
In3 >Wbc25
Figure 3-3: Details of "Stage 2" of the SDM
42
SDM kn
lnn00 --
Stage IStage 2
6DM Out
3.2.1 Thermal Noise
As mentioned earlier, this SDM model does not exhibit any non-ideal behavior. Thus
it does not include thermal noise, which puts a significant limit on the resolution of
the ADC. In order to incorporate thermal noise into this model, a pseudorandom
number generator (PRN) block was added to the input of the SDM.
The PRN block used in the model generates a pseudorandom number with a
Gaussian distribution on every SDM clock cycle using a table lookup algorithm to
generate the output. This algorithm is similar to the Fortran function RNOR de-
scribed in [7] but uses a different uniform random number generator to produce the
index to the table. The period of this algorithm is much larger than 21, providing suf-
ficient randomness even for very long simulations. The mean and the variance of the
pseudorandom number sequence was set to 0 and 3.98 x 10-12 -160000 = 6.368 x 10-7,
respectively.
3.3 CIC Filter
The Simulink model of the CIC filter, like the model used in the analysis section, is
ideal. As shown in Figure 3-4, ideal delay units are used in the feedback and feed-
forward paths instead of the finite number of registers used in the actual hardware.
This substitution could mask the potential rounding errors associated with having
finite number of registers in the hardware. However, the purpose of this model is to
verify the correctness of the analysis in the previous section, which did not take such
matters into consideration. Thus, this model is sufficiently accurate.
The registers a, b, and c are clocked at the same rate as the SDM, f, = 320KHz,
while registers d, e, f, and g are clocked at the downsampled rate of L. Register d in
this model essentially acts as the switch shown in Figure 2-5. Since CIC filters have
an inherent gain of RN, the gain block G found at the input of the filter reduces the
gain by g = g, thus allowing the output magnitude to correctly reflect that of the
input.
43
3d order CIC fler
G
p. . dawneaMh by R
ab C +
d
Figure 3-4: Simulink CIC Filter Implementation
3.4 Results
3.4.1 SDM Settling Time
Although an estimate for SDM settling time was obtained in the lab, this value is
somewhat unreliable due to the resolution limiation of the instrument used. However,
a more accurate settling time value can be obtained through simulation.
It is difficult to measure the settling time of the SDM because it is hard to observe a
settling behavior from an output that is strictly digital in the time domain. However,
this problem can be remedied by replacing the quantizer with a gain block. Such
replacement is valid since the quantizer does not affect the dynamics of the SDM
loop but simply adds noise. This replacement effectively removes the quantization
noise, making it possible to observe and measure the settling behavior.
Figure 3-6 shows the settling of the SDM when the input transitions from negative
rail to positive rail. Although a quick transition occurs in the output approximately
(6samples) - ( 1second );t~ 19ps after the input transitions from low to high, (sim-
ilar to - 20ps observed in the lab), the plot shows that the output oscillates for quite
a while longer. The oscillation is a decaying sinusoid in the form of CePt sin(wt - a).
Based on the simulation results, the oscillation exhibited by the settling of the SDM
44
GD-5DM hn
Outi - -t
1n2
Stage I
Mn2 Outi
Sten
quantizerreplaed by
Figure 3-5: Modified SDM Block Diagram
2
0
-1
4.8 4.801 4.802 4.803samples~n]
Figure 3-6: SDM Settling Response
45
SDM Out
SDIF I IputSDK Output
4.804 4.805x 10'
was found to decay at the rate expressed by Equation 3.1, where f, is the sampling
rate of the SDM.
x(t) = 7.38.- e~0 3 7 f-,(3.1)
This decay is shown in Figure 3-7.
- SDM Output
5----
4 -
0-
5 10 15 20 25 30 35 40 45 50samples (n)
Figure 3-7: Decay of the SDM output oscillation
In order to determine the exact settling time of the SDM, it is important to first
come up with an accurate definition for the SDM settling time. For this analysis,
SDM settling time will be defined as the amount of time it takes for the SDM output
to reach a value that is within -- LSB (least-significant-bit) of the output of the2
ADC when the input transitions from negative rail to positive rail. The half-LSB
value is calculated as 2 (*sitg" ,iloltage), where Bout is the number of bits at the
ADC output (which is not necessarily ENOB). Using this definition and Equation
3.1, the settling time of the SDM can be estimated for various ADC output widths.
Table 3.1 summarizes this information.
In Table 3.1, the upper bound for ADC output width is set rather generously at
30 bits. Thus, this entry is labeled "Max", and the corresponding settling time value
will be considered the maximum settling time of the SDM.
46
Output Width Settling Time (ps)14 266.915 282.816 298.617 314.418 330.219 346.020 361.8
Max (30) 520.0
Table 3.1: SDM settling time for various output widths
3.4.2 ADC Performance
Data Evaluation Approach
In order to evaluate the performance of the ADC, all the raw time-domain data needs
to be represented in the frequency domain in the form of power spectral density (PSD).
To obtain the PSD, the matlab function PSD was used. The PSD function basically
takes the FFT of the specified data sequence and returns the squared magnitude of
the result. Unless otherwise specified, each data sequence was obtained by running
the simulation for one second. Because the length of the data sequence is finite (and
rather short), running an FFT directly on such a sequence is the same as windowing
the sequence with a small rectangular window. This type of windowing is undesirable,
since the high side lobe amplitude of the rectangular filter in the frequency domain
compromises the PSD resolution. Thus, prior to running the PSD function on any
data sequence, the data was first windowed by a Blackman window of the same length
as the data sequence. While a rectangular window has a side lobe amplitude of -13dB
relative to its peak, the Blackman window side lobe is -57dB, providing a higher
resolution PSD [4]. The number of points in the FFT also matches the number of
points in the time-domain data.
Performance
Before evaluating the performance of the CIC filter and the overall ADC simulation
design, the correctness of the SDM simulation model must be verified. In order to
47
verify the correctness of this model, SDM signal-to-noise ratio was obtained for the
case when an ideal 100Hz brickwall filter was used. Figure 3-8 shows the PSD of the
SDM output when the input is a 5Hz, 4V peak-to-peak sine wave.
10,
10
10-2
10-4 --
10 -
10
1010
10-12
10~1-
10'10 10 10 10P 106 106 10
log frequency (Hz)
Figure 3-8: SDM Simulation PSD
In order to obtain the SDM signal-to-noise ratio, the noise between 0Hz and 100Hz
must be integrated. Since there is a spike at 5Hz in the PSD shown in Figure 3-8 due
to the signal, noise power is actually obtained by injecting an out-of-band signal and
integrating the PSD in the band of interest. The SNR of the SDM using this method
is -95dB, which is similar to the -97dB calculated in the analysis section, and very
close to the -94dB value which was measured in a previous laboratory measurement.
The 2dB difference between the analysis result and the simulation result is much
smaller than the 14dB SNR overestimation Hauser reports for the additive-white-
noise model in the case of second-order noise shaping [8]. The reason for such a
small discrepancy is that the dominant source of noise is not quantization but rather
thermal noise. Based on these results, it is safe to assume that the Simulink model
accurately emulates the actual SDM.
Since the analysis in the previous section showed that the lowest-order CIC filters
have the smallest settling time, the overall design was simulated with N = 3 and R
at the values calculated for various ENOB shown in Table 2.1. Figure 3-9 shows a
48
sample output of the sigma-delta ADC for a 5Hz, 4V peak-to-peak input, with R and
N set at 1171 and 3, respectively.
50 100 150Samples (n)
Figure 3-9: ADC Output for
200 250 300
5Hz sine input
Figure 3-10 is the PSD of the plot shown in Figure 3-9. In order to determine
the SNR of the ADC output, a ratio of the signal power and the noise power was
taken. For signal power, the peak of the PSD plot that results from having the sine
wave plus the thermal noise as input, such as Figure 3-10, was used. Noise power
calculation requires integration of noise over the entire spectrum. In order to do this
integration without the interference of the input signal in the PSD, the ADC model
was stimulated with only thermal noise as input. The PSD of the resulting output
was integrated and used as noise power. Figure 3-11 shows such a PSD.
Table 3.2 shows the results of the simulation using the aforementioned method.
Simulation of the last two R-N pair in the table were run for 5 seconds instead of 1
second in order to collect enough data points to produce a PSD with good resolution.
As the table shows, the SNR and the ENOB obtained from simulation is very
similar to the values obtained from the analysis, with the average discrepancy between
the simulation and the analysis being approximately 1 to 2 decibels. This small
discrepancy is most likely due to the fact that in Section 2.1.1, quantization noise
49
1.5}
0.5
> 0
-0.5
-1
-1.5
0
102
100
10-2
10
I10,CD9I
10 -10
1012
10-14
101log frequency (Hz)
102 103
Figure 3-10: PSD for ADC output with 5Hz sine plus thermal noise input
10
10-2
10-4
10
10'
10"0
10
101410 10'
log frequency (Hz)102
Figure 3-11: PSD of thermal-noise-stimulated ADC output
N R SNR ENOB3 243 89.31 14.543 387 91.30 14.873 1171 96.16 15.683 5587 103.14 16.843 12550 105.75 17.27
Table 3.2: Simulation summary for a 5Hz, 4V peak-to-peak sine input
50
' ' ' ' 'lc
" I e
was approximated as being white. Because the CIC filter design is ideal, it does not
add to the discrepancy between the analysis and the simulation.
Figure 3-12 shows the ADC output when four DC inputs of -2V, -IV, IV, and 2V
are multiplexed and switched at 20Hz, with R = 1171 and N = 3. While the mul-
tiplexer switching rate allows the ADC output 50ms to settle, Equations 2.35 and 2.37
show that the settling time of this ADC is only [okHZ)- (1170) - (3)]2 + (298.6ps)2
11.0ms. Thus, it can be seen from the figure that the output correctly reflects the
multiplexed input signals.
2.5
2
1.5-
0.5-
> 0
-0.5
-1
-1.5
-2
-2.5 J0-. 5 100 S 0 200 250 300
samples (n)
Figure 3-12: ADC output with multiplexed inputs
The Simulink simulation results verify that the calculations shown in the analysis
section do indeed closely model the behavior of the ADC. In the next section, the
implementation of the CIC filter in hardware will be examined.
51
Chapter 4
Simulation of the Hardware Using
VHDL
Some parts of the sigma-delta ADC, most importantly the CIC filter, are implemented
in hardware by programming a field-programmable gate array (FPGA) using VHDL
(VHSIC Hardware Description Language). Thus, in order to more accurately predict
the behavior of the sigma-delta ADC as implemented in hardware, a VHDL test
bench was constructed to simulate the most realistic design of the CIC filter. This
chapter discusses the design of the VHDL test bench, performance of the hardware
implementation of the CIC filter, and guidelines for designing the desired hardware.
It concludes with an analysis of synthesis and power consumption.
4.1 Overview of the Test Bench
The main purpose of the VHDL test bench is to create a simulation environment that
can accurately measure the performance of the CIC filter implemented in VHDL. Be-
cause the behavior of the actual hardware implemented using FPGAs exactly matches
that of the VHDL simulation model, a synthesizable (that is, realizable in hardware)
CIC filter model coupled with a realistic test bench allows one to accurately charac-
terize the behavior of the overall ADC hardware. Synthesis will be discussed in more
detail in a later section. All simulation was done using ModelSim version 5.3a.
52
STARTUPRESET
dc
INTERFACE-icout- ---
Figure 4-1: VHDL Test Bench Block Diagram
53
FPGA
w-cocR
TFGTIM sdmclock T ITIMING
astcic slo..clock _c1
COMPSDM sdmxo t COMPCIC
PRNthermal_oise
2/ mux_select
Figure 4-1 shows the block diagram of the overall test bench. As the diagram
shows, some components are part of the hardware implemented using an FPGA, while
other components are ADC hardware outside of the FPGA. However, all components
are coded using VHDL in order to create a homogeneous test bench environment.
The component TFGTIM simulates various clock signals. The component TIMING,
which is part of the FPGA hardware, takes in external clock signals and generates
various new clock and strobe signals to be used within the FPGA. The block labeled
STARTUP-RESET handles the proper initialization of the FPGA upon powering up.
The block INTERFACES, also part of the FPGA, mainly serves to communicate the
data generated in the FPGA with various outside components. It is also responsible
for generating the multiplexer select signals for the input multiplexer. The rest of the
components will be discssed in greater detail in the following sections.
4.2 Thermal Noise Blocks
Figure 4-1 shows a block labeled PRN, which stands for pseudorandom number. This
block is responsible for simulating thermal noise which is to be injected at the input
of the SDM. Unlike Simulink (i.e. Matlab), VHDL does not have a built-in random
number generator. Two approaches were examined in order to provide the VHDL
model with a realistic thermal noise source.
First approach was to simply generate a Gaussian noise sequence using Matlab,
write to a file, and create a VHDL block that reads and incorporates the data into the
model at the appropriate clock edges. The source to this approach, read-prn.vhd, can
be found in Appendix B.1. One advantage of this approach is that the same algorithm
for random number (noise) generation is used in Simulink, thus introducing fewer
inconsistencies between the Simulink and the VHDL models. Another advantage is
that minimal computation is needed for generating noise, allowing the simulation
to run fast. A major downside to this approach is that the simulation is always
dependent on the random noise file it reads from. For example, running an extremely
long simulation would require an extremely long data file which is large and thus
54
cumbersome to work with. Also, there is the general inconvenience of creating a
noise file outside the homogeneous VHDL simulation environment.
The second approach was to implement a pseudorandom number generator algo-
rithm directly in VHDL. Gaussian random number sequences are typically generated
by first obtaining uniformly distributed random number sequences using one algo-
rithm and mapping them to a Gaussian distribution using another algorithm [9].
One of the simplest of such mapping algorithm is the summing of a large number
of independent uniformly distributed random numbers, for the central limit theorem
states that such a sum has a Gaussian distribution [10]. However, it was initially de-
cided that a simple, uniformly distributed random number sequence would be used for
thermal noise simulation. The reason for this decision was that Simulink simulations
showed minimal difference in ADC signal-to-noise ratio when a uniformly distributed
noise sequence was used as opposed to a Gaussian sequence as long as the variance
and the mean of the two sequences were identical. For the uniformly distributed
noise sequence, a shift-register-based pseudorandom number algorithm was selected
because of the availability of some previous work. The algorithm used is similar to
the R250 algorithm developed by Kirkpatrick and Stoll [11].
30 2928 27 260 000 1 0
Direction of Shift sdmclo
Figure 4-2: Shift-Register-Based Pseudorandom Number Generator
As Figure 4-2 shows, the 29th and the 26th bit of a 31-bit shift register is XORed
and then fed back into the shift register as the least-significant-bit (LSB). The code
for this block, prn.vhd, is found in Appendix B.2. Figure 4-3 shows the PSDs of the
noise generated by both methods.
55
1.2I-read .pm.vhd
P.vh.J
1
0.8
i.0.6
0.4
0.2
00 0.5 1 1.5 2 2.5 3 3.5frequency (rad)
Figure 4-3: PSDs of simulated thermal noise using prn.vhd
Although the PSD of a white noise sequence should be flat across the entire
spectrum, Figure 4-3 shows that this flatness is not exhibited when using prn.vhd,
with some non-ideal behavior in the low-frequency region. This low-frequency non-
ideality is significant, since it is the thermal noise at low frequency that limits the
ADC performance.
In order to resolve this problem, prn2.vhd, a modified version of prn.vhd, was cre-
ated. In this model, six shift registers are used to generate six independent uniformly
distributed random numbers. Each shift register is initialized with the same starting
value, but different bit locations are XOR'ed and fed back. The choice of the bit
locations for the XOR operation is extremely important, because for a given shift
register initialization value, choosing certain bit locations will result in a cyclic pat-
tern that gives a much worse PSD than the one shown in Figure 4-3. Once they are
generated, the six random variables are summed together. The main purpose of this
summation is not to create a Gaussian sequence (although the summation will have
such an effect) but rather to enhance the randomness of the thermal noise sequence.
Before using this sum as the noise sequence, the sum of uniform random numbers
must be calibrated in order for it to have the desired variance. The easiest way to
calibrate is to first obtain the uncalibrated variance, u2, and multiply the sum of uni-
56
form random numbers with 1h, where e-th is the square root of the desired variance
(Equation 2.29 shows the a-2h value used for this particular SDM).
Figure 4-4 shows the output of prn2.vhd described above. As the figure shows, the
PSD is flat throughout the spectrum and matches closely with the PSD of the output
of read-prn.vhd. Simulations have shown that the two models have nearly the same
effect on the ADC output. The code for prn2.vhd can be found in Appendix B.3.
X 1 O-
pm2.vhd
0.9- -- read pm.vhd
0.8 .
0.7-
0.6-
0.5
0.4-
0.3
0.2-
0.1-
0 . 1 15 2 . 3.5frequency (red)
Figure 4-4: PSDs of simulated thermal noise using prn2.vhd
4.3 VHDL Implementation of the SDM
The sigma-delta modulator block, COMP.SDM in Figure 4-1, is the VHDL imple-
mentation of the digital approximation of the actual SDM chip used in Simulink.
However, the COMPSDM block, shown in greater detail in Figure 4-5, also contains
some extra functionalities.
As shown in Figure 4-5, all test input signals, such as sinusoids and constants, are
generated inside the COMP-SDM block. In addition, the block contains a multiplexer,
which selects the appropriate input signal as determined by the select bits it takes
as input. The selected signal is then summed with the thermal noise the block also
takes in as input, and this sum is fed into the input of the SDM.
57
sdmclock COMP_SDM
k -mux -- SDMselect -- sdmout
2
thermal_noise-
Figure 4-5: Block Diagram of COMPSDM
It is important to note that values are represented with far less precision in VHDL
compared to Matlab and Simulink (32 bits vs. 53 bits). For this reason, great care
must be taken in order to ensure that the inherent noise in the VHDL-generated
signal, such as sinusoids, is significantly less than other simulated noise sources (in
this case thermal and quantization noise). For sinusoids, two factors seem to affect
the amount of noise in the VHDL-generated signal. Assume that the following lines
of pseudocode was used to generate a sine wave with an amplitude of 2 in VHDL.
count=O;
period=2*pi/x;
if rising-edge(clk) then
sin_input=2*sin(count*period);
count=count+1;
end if;
where sinO is the built-in VHDL sine function.
Given the above code, one factor that affects the noise level in the generated sine
wave is the choice of x. If x is chosen such that the frequency of the sine wave is not
an integer value, the noise level of the sine wave becomes excessively high. Figure
58
4-6 shows a comparison of VHDL-generated sine waves with integer and non-integer
frequencies.
100
-- 5Hz Sine Wave-5.051Hz Sine Wave
10-5
10-'0
10'
20 IIT~
10-25110-5 10, 10 -3 10 10 10010
log frequency (rad)
Figure 4-6: VHDL-generated sine wave with a non-integer fundamental frequency
Another factor that affects the noise level in the VHDL-generated sine wave is
the resetting of the variable count. If this variable is reset after each period of the
sine wave (perhaps to limit the amount of memory committed to this variable), a
significant amount of noise is introduced. This observation is shown in Figure 4-7.
Avoiding both of these issues, sine wave with a sufficiently low noise noise floor
can be obtained. Figure 4-8 compares such a sine wave with a Simulink-generated
sine wave. As the figure shows, while the Simulink-generated sine wave has a lower
noise floor, the noise level of the VHDL-generated sine is low enough to prevent the
masking of other noise sources.
The performance of the VHDL SDM was determined by evaluating how closely
the design matched the Simulink version of the SDM. As Figure 4-9 shows, when the
input to the SDM is a sine wave plus thermal noise, the PSDs of the VHDL and
Simulink SDM outputs matched closely. In order to further compare the two designs,
the output of the VHDL SDM was written to a file and read into the Simulink CIC
filter. The SNR of the CIC filter output typically did not vary more than a few
decibels bewteen the two SDM models, verifying that the Simulink and the VHDL
59
10P
10 -
10-
n.
10
io-20
10
10
10-5
10-10
0 10-'1C-
0
0 - 104 10 -3 10 10 10 1log frequency (rad)
Figure 4-7: Effect of resetting the variable count
10 [10
0
10 -' ' ' '''' -' ' ' ' '' '0']
10 10, 10 10 10~ 10 10log frequency (rad)
Figure 4-8: Comparison of VHDL- and Simulink-generated sine waves
60
count not resetcount reset
I,
'1'
VHDL Sine Wave .
Simulink Sine Wave -
N
-N
test benches had virutally identical SDM models. Figure 4-10 is a PSD plot of the
Simulink CIC filter output (R=1171, N=3) when the input is the output of the
Simulink and the VHDL SDM model. The code for COMPSDM, compsdm.vhd, can
be found in Appendix B.6.
10*-VHDL SDM
1Simulink SDM
10 -
10 -
0
10 10 1010 10 10 10log frequency (rad)
Figure 4-9: PSD of the VHDL and Simulink SDM outputs
4.4 VHDL Implementation of the CIC Filter
In the previous sections, an ideal CIC filter model was analyzed and simulated. This
model did not take into consideration finite hardware and other implementation is-
sues. The VHDL model, however, is the exact representation of the actual hardware.
In the following sections, new issues arising from implementing the filter in hardware
and the filter performance will be examined.
4.4.1 Architecture
Figure 2-5 from Section 2.2.2 shows the block diagram of the CIC filter originally
introduced by Hogenauer [5]. The actual architecture of the CIC filter implemented
in VHDL, however, is slightly different from this model. The block diagram of the
implemented filter is shown in Figure 4-11.
61
10
10
10
10110
R=1171, N=3
10 tlog frequency (f)
les10
Figure 4-10: PSD of the Simulink CIC filter output when using different SDM models
Stage 1
sdmz~ -izfi
Stage 2
-40Z-1
Stage 3
-Ef
S
R
Stage 4 Stage 5 Stage 6
-1 -1 -1
cic_out
R
Figure 4-11: Block diagram of the CIC filter implemented in VHDL
62
Using Simulink SDM-Using VHDL 5DM I
- FRIM!M5 - -- - - - ----
' ' ' ' '
I
The reason for the modification is that the new design introduces a shorter critical
path in the integrator section. As Figure 2-5 shows, the original design has a signal
propagation path that spans three adders. By moving the registers to the new location
shown in Figure 4-11, the length of this path is reduced by a factor N, where N is
the filter order. This modification is beneficial because it allows the filter to have a
higher limit in terms of operating frequency. The 3-adder signal propation path in
the comb section is less of a concern, since this section runs at a significantly lower
frequency.
The aforementioned architectural modification changes the system function of the
filter. Hi(z), the system function of a single integrator stage, now becomes
y[n] = x[n - 1] + y[n - 1]
Hi(z) = Y(z) - Z-1 4.1X(z) - 1-Z(4.1)
This modification changes the overall CIC filter transfer function to
H (z) = HIN(z) . HCN(z) z- 1 )N. (1 - z-R)N
- N
= -N [ Z-k (4.2)
lk=0
Figure 4-12 shows the magnitude response of both the original and the modified
CIC filter architectures. As the figure shows, the frequency response of the two
architectures is virtually identical.
In addition, it can be seen from Equation 4.2 that the settling time of the new
design is longer by N - (f. is the fast sampling frequency of the filter), resulting in
the following expression for settling time.
1 (43tfil = (N - (R - 1) + N) - -=N - R. - -(4.3)
Since R is usually much larger than N, this increase in settling time compared to the
original design is negligible. Adding in the maximum SDM settling time determined
63
104 10 10log frequency (rad)
101 10P 101
Figure 4-12: Magnitude Response Comparison
in Section 3.4.1, the overall settling time of the ADC can be approximated as
tadc= N- R ) 2 + (520S)2
4.4.2 Register Sizing
(4.4)
In the CIC filter model used in Chapter 2 and Chapter 3, delay components of in-
finite precision were used for integration and differentiation. However, in the actual
hardware, such delay components must be replaced with registers. The appropriate
width of the registers in each stage is determined by the filter's maximum register
growth, which is defined as the maximum output magnitude resulting from the worst
possible input signal. This value is the same as the gain of the ideal CIC filter, which
is
Gmax = H (ew)( = [z-k = RN (4.5)k=0 z=1
Given this gain value, the width of the register must be set such that there is no
register overflow. If Bin represents the number of bits at the input, Hogenauer defines
64
F Moifie CICFilter- riginal CIC Filter
10 10
10
E
1CF10
10-15L10~
'l. I. . . - I ....... ...... ----- ----- ----- --- I ..... ----- ----- ..... .....
110
s1 -
5
Bmax, the most-significant-bit (MSB) of the register in each stage, as
Bmax = [N- log2R + Bi - 1] (4.6)
The LSB of each register is bit number 0, making the width of the registers Bmax +1.
It is of critical importance that the register width, especially at the first stage, is
set to Bmax +1. Overflow occurs if the register width at the first stage is set at a value
less than Bmax + 1, which introduces a significant amount of error. If the register
width is set at a value greater than Bmax +1, the higher-bit registers do not fill up.
Since the output of the filter is the top Bout MSBs of the last comb stage (where Bout
represents the number of output bits of the ADC), not all of the available bits get
used, significantly reducing the maximum SNR of the ADC.
In [5], a method of reducing the total number of registers in the hardware is
discussed. This method is centered around the idea that since Bmax + 1 is typically
much larger than Bout, there is always some truncation that occurs at the last stage
of the filter. Since this truncation will introduce some error, the intermediate stages
of the filter can truncate their registers to a point that the sum of truncation errors
at the intermediate stages does not exceed the last-stage error.
The number of bits that can be truncated from each stage, Bj, is calculated as
follows. Assuming that truncation at each stage produces white noise, the variance
of the error at stage j is
? !( 2 B3 )2 (4.7)12
The statistics at the output due to the jth error source is dependent on hj(k), the
system function of the filter from the jth stage upto the last stage. The impulse
response coefficients correspond to independent random processes that are summed
to produce one output. Thus, the variance due to the kth coefficient in the jth stage
is simply uah?(k), and the total error variance at the jth stage, 17,1is
2 =c F2 (4.8)T, j .
65
where F is
(4.9)
Stage 2N + 1 refers to the
stage. hj(k) is defined as
hj (k) =
[klR (E (-1)11=0
( 2N
Bout-wide output register stage that follows the last comb
N)
+1-j
k
N -j + k - RI
k - R1, , (4.10)
j= N+1,..., 2N
As mentioned earlier, Hogenauer in [5] makes the design decision that the truncation
of intermediate stages is done such that the sum of their errors does not exceed that
of the last stage. This decision is expressed through the following inequality.
a, _< 2N' ) , j = 1,2, .. ., 2N (4.11)
When substitutions are made with Equations 4.7 and 4.8, Bj, the number of bits of
truncation allowed at each stage, can be solved as
16B = -log 2 Fj + log 2 T 2N+1 + 102 (4.12)
The Matlab script cic-filt-spec.m, found in Appendix A.2, automatically solves for
B, given Bi., Bout, R, and N. Table 4.1 shows the reduced register widths for R and
N values used for the Simulink model simulation.
Register Width
Bi Bout R N Stage 1 Stage 2 Stage 3 Stage 4 Stage 5 Stage 61 14 243 3 25 25 21 18 17 161 15 387 3 27 27 22 19 18 171 16 1171 3 32 32 24 20 19 181 17 5587 3 39 37 26 21 20 19
Table 4.1: Register widths for R and N values used in the Simulink model
66
Jh 2(k), j =1, 2, . .. , 2NF = k
1, 7 2N + I
4.4.3 Performance
The performance of the VHDL ADC model was tested by duplicating the setup used
in the Simulink simulation. A 5Hz, 4V peak-to-peak sine wave summed with the
simulated thermal noise was used as input, and PSD of the output of the filter was
used to evaluate the SNR.
As mentioned in Section 3.4.2, the SNR of the Simulink ADC model output was
determined by taking a ratio of two values: the peak of the ADC output PSD with
sine wave plus thermal noise as input, and the integral of the ADC output PSD
with the input simply being the thermal noise. This method was valid with the
Simulink model because the output PSD generated with only thermal noise as input
accurately reflected the noise floor of the case where the input is the sine wave plus
the noise. However, duplicating this method of obtaining the ADC SNR with the
VHDL model produces extremely unreliable SNR values. The error arises from the
fact that the thermal noise signal amplitude is far smaller than the amplitude of
the input signal and thus does not fill up the registers representing bits of higher
significance. Since truncation of registers removes the LSBs of each stage, which are
used to distinguish one thermal noise sample from another, much accuracy is removed
from the representation of thermal noise with truncation. This reduction of accuracy
results in a PSD that does not match with the noise floor of the signal-plus-noise
PSD. Figure 4-13 illustrates this point.
Because of this problem, the noise power of the VHDL ADC output is estimated
in a different way. As the signal-plus-noise plot in Figure 4-13 shows, the effect of the
smearing of the spike respresenting the signal power becomes unnoticeable in higher
frequencies, allowing one to clearly determine the noise floor. Since the noise floor
level is constant over all frequencies (as shown by Simulink simulations), the noise
power was calculated by averaging the signal-plus-noise PSD in the region unaffected
by the smeared spike and then multiplying this value by the output bandwidth. There
is one limitation with this method. As R increases, the cutoff of the filter gets closer
to the spike representing the input signal. Eventually, it will reach a point where the
67
R=1171, N=3
102
10,
10-
10-a
10
10 101log frequency (f)
102
Figure 4-13: Thermal noise - noise floor mismatch in VHDL
Nyquist frequency of the ADC output overlaps with the region that is still affected
by the smearing of the spike, masking the true noise floor. Thus, an evaluation of
SNR for high R cases would require very long data sequences that can be acquired
much more easily with actual hardware rather than simulation. For this reason, SNR
of the filter output with R=5587 and up were not evaluated.
Truncation R=243 R=387 R=1171All Stages 80 84 89Last Stage 80 85 90No Stages 87 90 95Simulink 89 91 96
Table 4.2: Approximate VHDL ADC signal-to-noise ratio in dB, N=3
Table 4.2 shows the result of simulating with the same R and N values used in the
Simulink simulation. SNR values were obtained for the cases where no truncations
are made, truncation is made only at the last stage, and truncations are made in
every stage according to the calculations shown in the previous section. The data
reveals the following points:
As long as the last stage is truncated, truncating the registers in the intermediate
stages has no adverse effect (verifying the validity of the design decision made
68
16, -signa-plus-noise
in the previous section).
* The VHDL model results match that of the Simulink model if no truncation of
any kind are made.
* Truncation of the last stage severely degrades the ADC SNR.
Although truncation at the last stage reduces the SNR significantly, it cannot
be avoided since the number of bits at the output of the ADC, B0,±, will always
be smaller than Bma, + 1, the width of the first stage of the CIC filter. Thus, the
approach to obtaining R and N values for the desired ADC SNR must be modified.
The following section analyzes truncation noise and discusses design guidelines for
implementing the CIC filter in hardware.
4.5 Design Guidelines
4.5.1 Truncation Noise Analysis
Because the VHDL implementation of the CIC filter introduces the new issue of
truncation, the approach to design and metrics for performance must be modified
accordingly. However, in order to revise the design approach, the effect of truncation
must first be analyzed.
As shown in the previous section, avoiding truncation at the output allows the
VHDL simulation model performance to match that of the Simulink model. However,
as the LSBs of the output get truncated, additional noise is introduced. As mentioned
in Section 4.4.2, this noise can be modeled as uniformly distributed white noise.
Figure 4-14 illustrates the noise distribution.
The value Bt shown in the figure is the number of bits truncated. Given this
figure, the variance of truncation noise o and the mean of the truncation noise Mtn
are1
a42 = - (2 Bt)2 (4.13)tn 12
69
P (e)
1/2 Bt
e2 Bt
Figure 4-14: Distribution of truncation noise
and1
n = -- (4.14)2
respectively. These values can be used to obtain Pt, the truncation noise power.
P = Or2 + m2
= 1-( 2 Bt)2 + 1 Bt 2
- 2 2Bt (4.15)3
In order to calculate SNRtn, the signal-to-truncation-noise ratio, Pig, the signal
power at the CIC filter output, must be calculated. Assuming that the input is a
sinusoid with an amplitude of A, its power can be calculated as follows.
Psi9 = A (R). ]2 (4.16)2 ,2
The expression inside the brackets of Equation 4.16 is the root-mean-squared voltage
of the sinusoidal input signal multiplied by the filter gain. The gain value in this
expression is R N instead of RN because this gain is applied to the positive and the
negative amplitude, resulting in an overall gain of RN. In the case that A = 2V,
which is the value used in the simulations, Pi9 = I -R 2 N2
Before combining Pi9 and Pt to determine the expression for SNRtn, one sub-
stitution must be made. Given Equation 4.6, Bt can be expressed in terms of R, N,
70
and Bout, the number of bits at the output of the ADC.
Bt = Bmax + 1- Bout
= [N log 2 Ri + 1 - Bout (4.17)
Combining the above equations results in the following expression for SNRt" (for
a sinusoid with an amplitude of 2).
SSNRnotruc, Bt = 0SN R1 = l )2N (18)
10 - log1 I.*22([N 1092 R+1-BoUt) , ..W.
SNRnotrunc represents the SNR of the ADC when no output bits are truncated. This
value is identical to the SNR that would be attained in the Simulink model given the
same R and N. It must be noted that SNRtn is always less than SNRnotrunc. It is
also important to note that, based on the findings in the previous section, Equation
4.18 is applicable not only to the case where the truncation occurs only at the output,
but also to the case where truncation is done at the intermediate stages.
4.5.2 Approach to Design
With the ideal CIC filter model examined in In Chapters 2 and 3, an SNR value
corresponding to the number of bits at the output of the ADC was obtained using
the definition of ENOB (effective number of bits) shown in Section 1.3. Using this
SNR value, which represents the highest achievable SNR for the given number of bits
at the ADC output, the filter parameters R and N were calculated. This is a good
approach in the ideal case since the ENOB definition gives a good starting point for
design, and the resulting design is always optimal.
When truncation is involved in the design, however, this method can result in
suboptimal filter parameters. The reason for this is that for a fixed Bout, the number of
bits truncated, Bt, changes as the filter parameters change. That is, truncation noise
is a noise source that depends on both the output width and the filter parameters.
71
Because of this dependency between the output width and the truncation noise, the
noise level in the output can actually go up as the filter parameters are increased (noise
level always goes down in the ideal model if the filter parameters are increased). Thus,
in most cases, the SNR corresponding to a particular ENOB cannot even be obtained.
In addition, although equal filter parameters guarantee equal output SNR regardless
of the output width in the ideal model, this is not the case when truncation noise is
involved. A wider output can have a higher or lower SNR than a narrower output.
Considering these facts regarding the truncation noise, a better design approach
is to start with a target ADC output SNR and choose the lowest filter parameters
that will satisfy the SNR requirement, regardless of what the output width may be
(unless it is unreasonably large for a particular application). By doing this, it will be
guaranteed that the hardware size as well as the filter settling time will be minimized.
Table 4.3 can be used as a guideline for a third-order filter (N=3) with a 5Hz, 4V peak-
to-peak sinusoid as input. The values were obtained using Simulink for SNRnotunc
and Equation 4.18 for the various values of Bout. Settling time was obtained using
Equation 4.4.
Settling SNR for Various B,t (dB) SNRnotruncR Bma + 1 Time (ms) 14 15 16 17 18 19 20 (dB)
300 26 2.803 78.1 84.2 90.2 91 91 91 91 91600 29 5.615 78.1 84.2 90.2 93 93 93 93 93900 31 8.428 76.7 82.7 88.7 94.7 95 95 95 95
1200 32 11.241 78.1 84.2 90.2 96 96 96 96 961500 33 14.053 77.9 83.9 90.0 96.0 97 97 97 972000 34 18.741 79.4 85.4 91.5 97.5 99 99 99 993000 36 28.115 77.9 84.0 90.0 96.0 101 101 101 1014000 37 37.491 79.4 85.4 91.5 97.5 102 102 102 1025000 38 46.866 79.2 85.2 91.2 97.3 103 103 103 103
Table 4.3: SNRtn for 5Hz, 4V peak-to-peak sinusoid input, N=3
Extensive simulation in VHDL has shown that the truncation noise analysis de-
tailed thus far matches closely with the actual VHDL model. Figure 4-15 plots the
SNR predicted by the truncation noise analysis and the actual SNR obtained from
VHDL simulation for a CIC filter with R=900 and N=3.
72
R=900, N=31001
9 5 - . -- - -- -- - -- - - - - .- --.- -- - -- --.- - -- -
90-
5 -85-
80-
75 - d[ed-... actual!f
14 15 16 17 is 19 20Bout
Figure 4-15: Comparison of the predicted and actual output SNR for R=900, N=3
4.5.3 Multiplexing
The method for selecting a filter design that is optimal in terms of settling time is
simple: choose the lowest R and N that will provide a satisfactory SNR. The number
of bits at the output and the size of the hardware after truncation of LSBs in every
stage does not affect settling time.
From Table 4.3, it can be seen that for a given R, much flexibility is provided
in terms of setting the output SNR by the means of truncating different number of
bits at the output. This fact makes it very natural to use multiplexing rate as the
starting point of CIC filter design. In order to design a filter that would satisfy a
certain multiplexing rate, the following steps can be taken.
1. Using Equation 4.4, Determine the highest R and N pair that will satisfy the
multiplexing rate specification.
2. Using either the analysis shown in Chapter 2 or the Simulink model, determine
SNRtrunc associated with the chosen R and N.
3. Using Equation 4.18, determine Bout by truncating until SNR becomes affected.
4. Using the R, N, and Bout values, truncate intermediate stages following the
73
analysis in Section 4.4.2.
Following these steps guarantees mimimum hardware for the highest attainable
SNR for a given multiplexing rate.
4.6 Synthesis of VHDL Code
4.6.1 Synthesizability and Power Consumption
In order to successfully create the desired hardware using FPGAs (Field Programmable
Gate Array), care must be taken in writing the VHDL code such that only the syn-
thesizable constructs are used. In order to verify the synthesizability of the VHDL
CIC filter code, the logic synthesis tool Synplify was used. This tool not only veri-
fies the synthesizability of a design but also gives details regarding the size and the
composition of the hardware.
In order to compensate for the fact that the final design may run at a system clock
frequency that is higher than 4Mhz, the VHDL CIC filter code was synthesized for
a clock frequency of 6Mhz. With this specification, Synplify was able to successfully
synthesize the VHDL CIC filter code comp-cic.vhd for the Xilinx XCV200E FPGA
that is used for the inertial instrument electronics.
Using the hardware information provided by Synplify and a power estimation tool
provided by the Xilinx web site, the effect of changing certain filter parameters on
power consumption of a third-order CIC filter was examined. One experiment was to
set R at 900 and measure power for output widths ranging from 14 to 20. The other
experiment was to set the output width at 18 and varying the R from 300 to 5000.
Tables 4.4 and 4.5 summarize the results provided by the power estimation tool.
It can be seen from Table 4.4 that changing the output width has a minimal effect
on the power consumed by the filter. The small variation in the filter power is made
even less significant when considering the fact that the quiescent power of the FPGA
is approximately 29mW. From these results, it is safe to conclude that power need
not be a concern when opting for a wider filter output.
74
Bout Filter Power(mW) Total Power(mW) Gate Count14 7 35 325915 7 36 336516 7 36 347117 7 36 357718 7 36 368319 8 37 378920 8 37 3895
Table 4.4: Power consumption for CIC filter, R=900, N=3
R Filter Power(mW) Total Power(mW) Gate Count300 7 36 3463600 7 36 3603900 7 36 3683
1200 8 36 37231500 8 36 37632000 8 37 38233000 8 37 39034000 8 37 39435000F 8 37 3983
Table 4.5: Power consumption for CIC filter, N=3, Bout = 18
75
The same conclusion can be made about changing the variable R of the CIC
filter. As Table 4.5 shows, increasing the R of the CIC filter from 300 to 5000 causes
only a 1mW increase in the CIC filter power, an insignificant value when compared
to the total power consumed by the FPGA. Thus, it can be concluded that power
consumption need not be a concern when varying the filter parameters within a
reasonable range.
4.6.2 Alternate Architecture
In Section 4.4.1, it is mentioned that the model shown by Figure 4-11 is the CIC filter
architecture implemented in VHDL due to its shorter critical path. However, as long
as extremely high clock frequencies are not needed, the original CIC filter architecture
shown in Figure 2-5 could be a better option in terms of hardware efficiency. This is
due to the fact that the integrator section can be written as a finite state machine
(FSM) in VHDL if the longer critical path is allowed. Tests have shown that finite
state machines are more efficiently synthesized into hardware compared to a more
straight-forward implementation of a sequential circuit. Because the comb section
runs at a much slower clock rate, it is already implemented as an FSM. The resulting
reduction in hardware could reduce the overall power consumption.
The VHDL code for this version of the CIC filter, compcic2.vhd, can be found
in Appendix B.5. This VHDL code was successfully synthesized using the same
setup as described in the previous section. VHDL simulation has shown that its
output is virtually identical to that of the shorter-critical-path architecture. Table
4.6 summarizes the result of synthesis with various R values and B0.t fixed at 18.
R Filter Power(mW) Total Power(mW) Gate Count1200 8 36 34732000 8 37 35583000 8 37 36264000 8 37 36605000 8 37 3694
Table 4.6: Power consumption for comp-cic2.vhd, N=3, B,,t = 18
76
As Table 4.6 shows, comp-cic2.vhd does have a lower gate count compared to
comp.cic.vhd with identical filter parameters. However, the savings in hardware was
not significant enough to show a visible difference in power consumption. Since the
savings in power is so small, comp-cic2.vhd may be a better architecture only if FPGA
area absolutely has to be optimized. Finally, in order to further optimize hardware,
the CIC filter code was written such that the three integration stages would share
one adder. However, the overhead involved in sharing the adders made the overall
gatecount higher than the gatecount for comp-cic2.vhd.
77
Chapter 5
Conclusion
Draper Laboratory's multiplexed-input sigma-delta analog-to-digital converter (ADC)
has been examined in this paper. The sigma-delta converter design was first analyzed
mathematically in order to predict its performance. A model was then created in
Simulink to test the accuracy of the analysis. Finally, a VHDL model was created in
order to accurately test the feasibility and the performance of the actual hardware.
One important conclusion that can be drawn is that the optimum converter design
cannot be obtained by simply increasing all the filter parameters. A careful combi-
nation of three ADC parameters, R (the downsampling rate of the digital filter), N
(the order of the digital filter), and B0,t (the width of the ADC output in bits), must
be selected in order to ensure the best performance with minimum hardware. The
analog-to-digital converter performance not only depends on the cascaded integrator-
comb filter parameters R and N, but also the number of bits at the output of the filter,
B.Ut. The ideal filter model used in Chapters 2 and 3 does not take into consideration
that the precision of the storage units used in the filter and the output of the converter
are finite. Simulation of the actual hardware in VHDL showed that due to truncation
of bits that must occur at the output of the digital filter, optimal signal-to-noise ratio
values obtained in the Simulink simulation cannot be achieved with the number of
output bits given by the effective-number-of-bits (ENOB) definition. Based on the
data collected from the VHDL simulation model, the best approach to designing the
digital filter is to decide what the target multiplexing rate is, and then using that
78
value to calculate the filter parameters that provides the smallest hardware.
Another important point to note is that when creating a simulation model in
VHDL, great care must be taken when simulating signals and hardware that are not
part of the final synthesized hardware. For example, because of limited precision,
signals such as sine waves must be generated such that the noise caused by limited
precision is not greater than other noise that needs to be measured.
VHDL simulation data has shown that the ADC created by combining the SD2_ADC
sigma-delta modulator with a cascaded integrator-comb (CIC) filter can achieve a
signal-to-noise ratio of approximtely 99dB while settling at about 19ms. This settling
time would allow four multiplexed ADC inputs to be digitized at 5Hz, which is a sat-
isfactory rate for inertial instrument compensation variables. A signal-to-noise ratio
higher than 99dB can be achieved, but increasing the resolution further comes at a
significant settling time penalty.
The simulation models used in this project have shown that high resolution
(~ 100dB) can be achieved at low power (< 20mW) with the current design. How-
ever, there are several areas where more work can be done. Analysis has shown that
signal-to-noise ratio of the current design is limited most significantly by the thermal
noise of the sigma-delta modulator. Due to the significant amount of thermal noise
present in the current SDM design, a filter with a large number of taps is required in
order to achieve a high resolution. However, finite-input-response filters with a large
number of taps take a long time to settle. If higher performance is needed in terms of
settling time or resolution, a sigma-delta modulator design that does not use switched
capacitors should be considered. Although there are other tradeoffs that could com-
promise performance, this type of sigma-delta modulator does not suffer from high
thermal noise and thus could potentially require filters with smaller hardware. In
terms of the simulation model, the current models only simulate quantization and
thermal noise. In order to more accurately study the effects of multiplexing inputs,
it may be worthwhile to examine noise and settling time associated with the multi-
plexer. Finally, it may be useful to evaluate the performance of the sigma-delta ADC
with inputs that more accurately reflect the actual compensation variables.
79
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[1] Gustavsson, M., Wilkner, J. J., and Tan, N. N., CMOS Data Converters for
Communications, Kluwer Academic Publishers, Boston, 2000, pp. 67-72.
[2] van Engelen, J., van de Plassche, R., Bandpass Sigma Delta Modulators, Kluwer
Academic Publishers, Boston, 1999, pp. 1-2, 14-15.
[3] Norsworthy, S. R., Schreier, R., and Temes, G. C., Delta-Sigma Data Converters:
Theory, Design, and Simulation, IEEE Press, New York, 1997, pp. 353-355.
[4] Oppenheim, A. V., and schafer, R. W., Discrete-Time Signal Processing, 2nd
ed., Prentice-Hall, Upper Saddle River, NJ, 1999, pp. 65-70, 187-213, 471.
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Interpolation", IEEE Transactions on Acoustics, Speech, and Signal Processing,
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[10] Orfandis, Blah, Blah blah blah blah, Blah Publishing, Blahtown, 19xx, pp. x-x.
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[12] Ashenden, P. J., The Designer's Guide to VHDL, Morgan Kaufmann Publishers,
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Hall, Upper Saddle River, NJ, 1997.
[14] Medeiro, F., Perez-Verdu, A., and Rodriguez-Vaizquez, A., Top-Down Design
of High-Performance Sigma-Delta Modulators, Kluwer Academic Publishers,
Boston, 1999
81
Appendix A
Matlab Scripts
A.1 rn-choose.m
The script rn-choose.m was used in order to obtain the R and N values for the CICfilter for a specified effective-number-of-bits (ENOB), analog-to-digital converter sam-pling rate, and sigma-delta modulator order.
% rnchoose.m - Script to determine R and N that will satisfy% the SNR requirements for both quantization and thermal7 noise for the given ENOB.
% 4/7/2001 - fixed bug in the signal transfer function.% Steve Park 2/6/2001
clear;
. sampling and signal frequencyfsamp = 320000;
% signal bandwidthfsig = 5;% sample representing signalsig.samp = ceil(fsig/(fsamp/2)*32768);
X Specifying ENOBENOB = 17;
% Desired (Equivalent) SNRSNRD = 6.02*ENOB + 1.76;
X Specifying order of the SDMsdm-o = 2;
snr = 0;
82
X Vector holding the SNR valuessnrs = linspace(0,0,3);
% PSD of quant and thermal noise (variance)delta = 5; % quantization level
quantvar = (delta^2)/12;thermvar = (3.98e-12)*(160000); % refer to snrtherm.m for origin of value
X signal transfer functionstf = abs(freqz([2/5 -1/3], [37/30 -13/6 1], 32768));stfsq = stf.^2;
% noise transfer functionntf = abs(freqz([1 -2 1], [37/30 -13/6 1], 32768));ntfsq = ntf.^2;
% vectors holding 3 R values corresponding to N through N+2Rs = linspace(0,0,3);
w = linspace(0, pi, 32768);
%check upto 3 orders higher than SDM orderfor N=(sdm-o+1):(sdm-o+3),
R = 1;snr = 0;snrprev = -1; %variable used to check if SNR decreasing
% run loop as long as desired SNR not reached or SNR starts% decreasing with increased R value
while ((snr < SNRD) & (snr-prev < snr))R = R+3;% hsq is the PSD of the CIC filter
h = linspace(0, 0, 32768);h(1) = R^N; % correct value for H(e-jw) at w=0for j=2:32768
h(j) = (abs(sin((w(j)*R/2))./(w(j)/2))).^N;endhsq = h'.^2;
% PSD of filtered thermal noisephith = thermvar*stfsq.*hsq;% Power of filtered thermal noisePth = 2*(1/2/pi)*sum(phith)*(pi/(32768));
83
% PSD of shaped and filtered quantization noisephiq = quantvar*ntfsq.*hsq;phiq(1) = 0; % to remove NaN at index=1.% Avg. power of quant. noise
Pq = 2*(1/2/pi)*sum(phiq)*(pi/(32768));
% hsq at signal freq multiplied by amplitude of sinusoidPs = 2*hsq(sigsamp);snr-prev = snr; % to check if the SNR is decreasingsnr = -1*(10*loglO((Pth+Pq)/Ps));
end
snrs(N-sdm-o) = snr;
Rs(N-sdm-o) = Rend% display signal-to-noise ratio valuessnrs
84
A.2 cic-..flltspec.m
The script cic-filt-spec.m automates the register sizing calculations shown in Section4.4.2. Approprite register widths are provided for the specified R, N, Bj, and B0,,values.
% cicfiltspec.m - CIC filter register sizing script% 1/30/2001 - Modified to calculate integrator and comb section% register widths at the same time.% 11/6/2000 -% Given R, N, Bin, and Bout, this script calculates the number'. of LSBs to truncate from each stage of the CIC filter. These% values are stored in the matrix B.
clear;R=1171; . specifying RN=3; % specifying NBin = 1; % specifying BinBout = 16; 7 specifying Boutfs = 320000;fd = fs/R;
G = R^N;Bmax = ceil(N*log2(R)+Bin-1);7 Bmax = 26 at R=400, 32 at R=1600B2np1 = Bmax-Bout+1;
%==== Calculating register widths for the integrator section
sigma = sqrt((1/12)*(2-(2*(Bmax-Bout+1))));thatval = log2(sigma) + .5*log2(6/N);B = linspace(0, 0, 2*N);
for j=1:N
kmax = (R - 1)*N + j - 1;k = linspace(O, kmax, kmax+1);hl = linspace(0, 0, kmax+1);
for i = 0:kmax %for khsum = 0;for 1 = 0:floor(i/R)
hsum = hsum + (-1)^l*nchoosek(N, 1)*nchoosek(N-j+i-R*l, i-R*1);endhl(i+1) = hsum;
85
end
h1sq = h1.^2;Flsq = sum(hlsq);F1 = Flsq^(0.5);
B(j) = floor(-l*log2(Fl) + thatval)
end
%==== Calculating register widths for the comb section
for j=l+N:2*Nkmax = (R - 1)*N + j - 1;
for i = 0:(2*N+l-j)h2(i+1) = (-l)^i*nchoosek(2*N+l-j, i);
end
o/ This following line is to compensate for the suckiness of% Matlab's nchoosek command.h2((2*N+1-j+1+1):kmax+l) = linspace(O, 0, kmax+1-(2*N+1-j+1));
h2sq = h2.-2;F2sq = sum(h2sq);F2 = F2sq^(0.5);B(j) = floor(-1*log2(F2) + thatval)end
Bmax+1
% display widthsBmax+l-B
86
Appendix B
VHDL Code
B.1 read-prn.vhd
read-prn.vhd reads an ASCII text file named thermaLnoise.m which contains thermalnoise data. On every SDM clock edge, a sample of thermal noise is added to theinput of the SDM.
-- readprn.vhd - Reads matlab-generated Gaussian pseudorandom numbers
-- from the file thermal-noise.m and feeds it to the SDM modeled by-- comp-sdm.vhd on every SDM clock cycle.
-- smp3454 -2/28/2001
library ieee;use ieee.stdlogic1164.all;use ieee.std-logic-arith.all;
use ieee.std-logic-unsigned.all;use work.constants.all;use std.textio.all;
entity READPRN isport(RANDNUM: out real:=0.0;
RESET: IN stdjlogic;SYSCLK: IN std-logic);
end READPRN;
architecture archREADPRN of READPRN is
signal randnum: real:=0.0;signal flag : std-logic := '0';
begin -- archREADPRN
RANDNUM <= randnum;
87
-- This process reads the data file until the end of the file
-- is reached. If the system is reset, the file is reopened
-- and data is read from the beginning of the file again.
read-data: process is
type real.filetype is file of real;
variable open-status: file-open-status;
variable tnoise: real;
file noisefile: text open read-mode is "thermalnoise.m";
variable L: line;
beginwait until SYSCLK = '1';
if RESET='1' thenfile-open(open.status, noise-file, "thermalnoise.m", read-mode);randnum <= 0.0;
flag <= '1';
elseif (endfile(noise.file)=false) then
flag<='O';readline(noisefile, L);
read(L, t-noise);rand-num <= t-noise;
end if;
end if;
end process;
-- Write output to another text file (thermal-noise.rec) in order to
-- make sure the correct values were read in.
output-check: processvariable buf: line;
file fouti: text is out "thermalnoise.rec";
beginwait until SYSCLK='1';
write(buf, rand-num);
writeline(foutl, buf);
end process;
end archREAD-PRN
88
B.2 prn.vhd
prn.vhd generates a uniformly distributed random noise sequence using a feedbackshift register.
-- prn.vhd - Pseudorandom number generator based on the file prn-gen.vhd-- created by Dave McGorty.-- smp3454 -2/27/2001
library ieee;use ieee.stdilogic_1164.all;use ieee.stdlogic-arith.all;use ieee.std-logic-unsigned.all;
use work.constants.all;use std.textio.all;
entity PRN isport(RANDNUM: out real:=0.0;
RESET: IN std-logic;SYSCLK: IN stdlogic);
end PRN;
architecture archPRN of PRN is
signal prn: signed(30 downto 0); -- "0101001011110100101111010010111";signal prnreal : real:=O.0;signal temp-xor std-logic;signal flag : stdlogic := '0';constant half-delta: real := 0.0014;constant zero_31: signed(30 downto 0) := (others => '0');constant prnload: signed(30 downto 0) := "0101001011110100101111010010111"-
attribute syn-preserve : boolean;attribute syn-preserve of prn: signal is true;attribute syn-state-machine : boolean;attribute syn.statemachine of prn: signal is false;
begin
-- maximal length pseudo random sequence generator-- 31 bit wide
RANDNUM <= prn-real;
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-- This process shifts the register on every clock cycle and feeds back
-- the XORed value.
random.gen : PROCESS
BEGINwait until SYSCLK = '1';
IF RESET = '1' THEN
flag <= '1';prn <= prnjload;
ELSEflag <= '0';IF prn = zero_31 THEN
prn <= prnjload;ELSE
prn <= prn(29 downto 0) & temp-xor;
END IF;END IF;END PROCESS;
-- XOR 2 bit locationstemp.xor <= prn(30) xor prn(27) after 1 ns;
-- Converting the signed prn to the appropriate real value with
-- the uniform distribution range of plus or minus half-delta.
-- Multiply real(conv-integer(prn)) with a different value to change
-- variance.
prn.real <= real(conv-integer(prn))*(0.0014/2**30);
output-capture: processvariable buf: line;
file fouti: text is out "prn-out.rec";
beginwait until SYSCLK='1';
write(buf, prn-real);
writeline(foutl, buf);
end process;
end archPRN;
90
B.3 prn2.vhd
prn2.vhd generates a pseudo-Gaussian random noise sequence using a sum of six feed-back shift registers used in prn.vhd.
-- prn2.vhd - modified version of PRN.VHD to fix the non-idealities at-- low frequencies. Modified using the advice from Prof. Roberge.-- smp3454 -4/16/2001
library ieee;use ieee.stdlogic_1164.all;use ieee.std-logic-arith.all;use ieee.stdilogic-unsigned.all;
use work.constants.all;use std.textio.all;
entity PRN2 isport(RANDNUM: out real:=0.0;
RESET: IN stdjlogic;SYSCLK: IN std-logic);
end PRN2;
architecture archPRN2 of PRN2 is
signal prnl: signed(30 downto 0); -- : "0101001011110100101111010010111";signal prn2: signed(30 downto 0); -- := "0101001011110100101111010010111";
signal prn3: signed(30 downto 0); -- := "0101001011110100101111010010111"
signal prn4: signed(30 downto 0); -- : "0101001011110100101111010010111";signal prn5: signed(30 downto 0); -- : "0101001011110100101111010010111";signal prn6: signed(30 downto 0); -- : "0101001011110100101111010010111";
signal prnreal : real:=0.0;signal prnone : real:=0.O;signal prn.two : real:=0.O;signal prnthr : real:=0.0;signal prnjfou : real:=0.0;signal prnrfiv : real:=0.0;signal prnsix : real:=0.O;signal prn-sum: real:=0.0;signal temp.xorl, temp-xor2, temp-xor3,
temp-xor4, temp-xor5, temp-xor6: std-logic;signal flag : std-logic := '0';constant halfdelta: real := 0.0014;
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constant zero_31: signed(30 downto 0) := (others => '0');
constant prn-loadl: signed(30 downto 0) :="0101001011110100101111010010111";
attribute syn-preserve : boolean;
--attribute syn-preserve of prn: signal is true;
attribute syn-state-machine : boolean;--attribute synrstate.machine of prn: signal is false;
begin
-- maximal length pseudo random sequence generator
-- 31 bit wide
RANDNUM <= prn-real;
random-gen : PROCESS
BEGINwait until SYSCLK = '1';
IF RESET = '1' THEN
flag <= '1';
prnl <= prn-loadl;prn2 <= prnjloadl;
prn3 <= prn-loadl;
prn4 <= prnjloadl;
prn5 <= prnjloadl;prn6 <= prnjloadl;
ELSEflag <= '0';IF prnl = zero_31 THENprnl <= prnjloadl;
prn2 <= prn-loadl;
prn3 <= prnjloadl;
prn4 <= prnjloadl;
prn5 <= prnjloadl;
prn6 <= prnjloadl;
ELSEprnl <= prnl(29 downto 0) & temp-xorl;prn2 <= prn2(29 downto 0) & temp-xor2;prn3 <= prn3(29 downto 0) & temp-xor3;
prn4 <= prn4(29 downto 0) & temp-xor4;prn5 <= prn5(29 downto 0) & temp-xor5;
prn6 <= prn6(29 downto 0) & temp-xor6;
END IF;
END IF;END PROCESS;
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-- The XOR'ed bit pairs for each feedback register is
-- carefully selected such that good random number is generated
-- by each shift register.
temp.xorl <= prnl(30) xor prnl(27) after 1 ns;
temp-xor2 <= prn2(25) xor prn2(22) after 1 ns;
tempxor3 <= prn3(28) xor prn3(25) after 1 ns;
temp.xor4 <= prn4(4) xor prn4(26) after 1 ns;
tempxor5 <= prn5(27) xor prn5(24) after 1 ns;
temp-xor6 <= prn6(24) xor prn6(21) after 1 ns;
-- Summing the six random variables and scaling it to have the desired-- variance.
prnrsum <= real (conv-integer(prnl)+convinteger(prn2)+convjinteger(prn3)
+convjinteger(prn4)+conv-integer(prn5)+conv-integer(prn6))
*(7.98e-4/1.1854e9);
-- Used for file output to verify the output quality of each shift register.prnone <= real(conv-integer(prnl))*(0.0014/2**30);prntwo <= real(conv-integer(prn2))*(0.0014/2**30);
prnthr <= real(convjinteger(prn3))*(0.0014/2**30);prnfou <= real(conv-integer(prn4))*(0.0014/2**30);prn_fiv <= real(conv-integer(prn5))*(0.0014/2**30);
prn-six <= real(conv-integer(prn6))*(0.0014/2**30);
output-capture: processvariable buf: line;
file fouti: text is out "prnsum.rec";file fout2: text is out "prn-one.rec";
file fout3: text is out "prntwo.rec";
file fout4: text is out "prn-thr.rec";
file fout5: text is out "prn-fou.rec";
file fout6: text is out "prnfiv.rec";file fout7: text is out "prn.six.rec";
beginwait until SYSCLK='1';
write(buf, prnsum);
writeline(foutl, buf);
write(buf, prn-one);
writeline(fout2, buf);
write(buf, prntwo);
writeline(fout3, buf);
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write(buf, prn-thr);
writeline(fout4, buf);
write(buf, prn.fou);
writeline(fout5, buf);
write(buf, prn-fiv);
writeline(fout6, buf);write(buf, prn.six);
writeline(fout7, buf);end process;end archPRN2;
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B.4 comp-cic.vhd
This is the VHDL code for the CIC filter used in the VHDL simulation and synthesis.
-- $Id: compcic.vhd,v 1.7 2000/08/11 20:52:54 nch2506 Exp $
-- Steve Park smp3454-- 2/18/2001
-- Modified the filter to match hand calculations.-- Bmax=31, Bj's are -11,-1,8,12,13,14, Bin=1, Bout=16,-- fs=320KHz.
-- CIC filter for the compensation variables in the HPG revised design-- Nick Homer-- June 5, 2000-- The coefficients used in this CIC filter are based on the following-- calculations. The equations used were derived in "An Economical-- Class of Digital Filters for Decimation and Interpolation" by-- Hogenauer, 1981.
library ieee;use ieee.std-logic-1164.all;use ieee.std-logicarith.all;use ieee.std-logicunsigned.all;
--pragma translateoffuse std.textio.all;--pragma translateon
entity COMPCIC isport(CLKFS: IN STDLOGIC; -- System clock
DATAIN: IN stdjlogic; -- data from SDMDATAVALID: OUT std-logic; -- output validDOUT: OUT stdjlogic-vector(17 downto 0); -- outputRESET: IN STD-LOGIC; -- resetSTBFSH: IN STDLOGIC; -- CIC high sampling rateSTBFSL: IN STDLOGIC); -- CIC low sampling rate
end COMPCIC;
architecture archCOMPCIC of COMPCIC is-- set integration stage register widths
constant BI1 : integer : 31;constant B12 : integer := 31;constant B13 : integer := 26;
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-- set comb stage register widths
constant BC1 : integer 22;constant BC2 : integer 21;constant BC3 : integer 20;
-- number of bits for the output
constant TAPWIDTH : integer := 18;
-- used to synchronize inputs to system clock.
signal reset-sync : std-logic;signal sdms : std-logic;
-- signals used for accumulators
signal acci : signed(BI1-1 downto 0);signal acc2 : signed(BI1-1 downto 0);signal acc3 : signed(BI1-1 downto 0);
-- signals used for comb filters
signal combi: signed(BC1-1 downto 0);signal comb2: signed(BC2-1 downto 0);signal comb3: signed(BC3-1 downto 0);signal tempdin : std-logic;signal bminusa, b, a : signed(BC1-1 downto 0) := (others => '0');signal validcount : integer range 0 to 3;signal dout-i : signed(17 downto 0);
type states is ( idle, comb-stagel, comb-stage2,comb-stage3, comb-stage4);
signal state : states;
begin
-- Synchronize the inputs to our system clock
register-inputs : processbeginwait until CLKFS = '1';sdm-s <= DATA-IN after I ns;reset-sync <= RESET after 1 ns;
end process;
-- perform the integrations:
-- note: some of the least significant digits are truncated in the-- later stages of integration, because they are unimportant for the-- 16-bit output.
integrators : processbegin
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wait until CLKFS = '1';if reset-sync = '1' then
acci <= (others => '0') after 1 ns;
acc2 <= (others => '0') after 1 ns;acc3 <= (others => 0'') after 1 ns;
elsif STBFSH = '1' then
if sdm-s = '1' then
acci <= acci + 1 after 1 ns;else
acci <= acci - 1 after 1 ns;
end if;acc2 <= acc2 + accl(BI1-1 downto BI1-BI2) after 1 ns;acc3 <= acc3 + acc2(BI2-1 downto B12-BI3) after 1 ns;
end if;end process integrators;
b_minusa <= b - a;
-- comb filters: These comb filters are set up in a state machine,-- where each stage corresponds to a state. Usually, we are in the
-- idle state, and when the low frequency strobe goes high, the data-- is run through all of the comb stages, and the output is updated.
-- When the filtering is done, the system returns to idle state.
comb-registers : process
variable temp : signed(BC1-1 downto 0) : (others => '0');
beginwait until CLKFS = '1';
if RESET = '1' then
state <= idle;
DATA-VALID <= '0';
douti <= (others => '0');else
case state iswhen idle =>
if STBFSL = '1' then
b <= acc3(BI3-1 downto B13-BC1);
a <= combi;
state <= comb-stagel;
end if;
DATAVALID <= '0';when comb-stagel =>
combi <= b;temp := bminusa;b <= b-minus-a;a <= comb2 & CONV-SIGNED('0', BC1-BC2);
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state <= comb-stage2;DATAVALID <= '0';
when combstage2 =>comb2 <= temp(BC1-1 downto BC1-BC2);temp := bminus-a;b <= b-minus-a;a <= comb3 & CONVSIGNED('0', BC1-BC3);state <= comb-stage3;DATA-VALID <= '0';
when comb-stage3 =>comb3 <= temp(BC1-1 downto BC1-BC3);dout-i <= bminus.a(BC1-1 downto BC1-DOUT'length);DATAVALID <= '1';state <= comb-stage4;
when comb-stage4 =>DATAVALID <= '0';state <= idle;
when others =>DATAVALID <= '0';state <= idle;
end case;end if;
end process comb-registers;
-- update the actual output with the value in our internal variable.DOUT <= std-logic-vector(dout-i);temp-din <= DATAIN after 1 ns;
-- pragma translate-off
recorddata: process (STBFSL)variable buf : line;file fouti : text open write-mode is "dout.rec";
begin -- processif risingedge(STBFSL) then
write(buf, CONVJINTEGER(dout i));writeline(foutl, buf);
end if;end process;
end archCOMP-CIC;
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B.5 comp-cic2.vhd
This version of the CIC filter more closely resembles the model described by Hogenauer.compcic2.vhd uses a finite state machine (FSM) for both the integrator and comb sec-tions. While using an FSM in the integrator section reduces the maximum frequencyat which the filter can be clocked, it reduces the overall hardware.
-- Steve Park smp3454-- comp-cic2.vhd-- CIC Filter that more closely resembles the one described in-- Hogenauer's paper. This is done by replacing the code in the-- integrator section with another FSM.-- 4/8/2001
library ieee;use ieee.std-logic1164.all;use ieee.std-logic-arith.all;use ieee.std-logic-unsigned.all;
-- pragma translateoffuse std.textio.all;--pragma translate-on
entity COMPCIC2 isport(CLK-FS
DATAIN
DATAVALIDDOUT
RESETSTB_FSH :STBFSL
end COMP-CIC2;
ININOUTOUTINININ
STDLOGIC; -- System clockstd-logic; -- data from SDMstd-logic; -- output validstd.logic.vector(17 downto 0); -- outputSTD-LOGIC; -- resetSTDLOGIC; -- CIC high sampling rateSTDLOGIC); -- CIC low sampling rate
architecture archCOMPCIC2 of COMPCIC2 is
-- Number of
constant BIlconstant B12constant B13
-- Number of
constant BC1constant BC2constant BC3-- number of
bits in each stage of integration: integer 31;: integer 31;: integer 26;bits for each of the combs: integer 22;: integer 21;: integer 20;bits for the output
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constant TAPWIDTH : integer := 18;
-- integration registerssignal isl-reg : signed(BI1-1 downto 0);signal is2.reg : signed(B12-1 downto 0);signal is3_reg : signed(B13-1 downto 0);
-- comb registerssignal cslreg : signed(BC1-1 downto 0);signal cs2_reg : signed(BC2-1 downto 0);signal cs3_reg : signed(BC3-1 downto 0);
type states is (iidle, isi, is2, is3, cjidle, cs1, cs2, cs3, cs4);signal i-state, cstate: states;
-- number of bits at the output
signal dout-i : signed(17 downto 0);signal bminusa, b, a : signed(BC1-1 downto 0) : (others => '0');
signal reset-sync : stdlogic;signal sdms : stdlogic;
begin -- archCOMPCIC2
-- Synchronize the inputs to our system clock
sync-inputs : processbegin
wait until CLKFS = '1';sdmns <= DATA-IN after 1 ns;resetsync <= RESET after 1 ns;
end process;
-- the following process implments the FSM that acts as the
-- 3 integrator stages of the 3rd order CIC filter.
integratorsection: process(clkfs)begin
if reset-sync = '1' thenislreg <= (others => '0') after 1 ns;
is2_reg <= (others => '0') after 1 ns;
is3_reg <= (others => '0') after 1 ns;
i-state <= ijidle;else
case i-state iswhen i-idle =>
if STBFSH='1' theni_state <= isi;
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elsei-state <= i-idle;
end if;when isi =>
if sdm-s = '1' thenisireg <= islreg + 1 after 1 ns;
elseislreg <= islreg - 1 after 1 ns;
end if;i_state <= is2;
when is2 =>is2_reg <= is2_reg + islreg(BI1-1 downto BI1-BI2);i-state <= is3;
when is3 =>is3_reg <= is3_reg + is2.reg(BI2-1 downto B12-BI3);i_state <= i.idle;
when others =>i_state <= iLidle;
end case;end if;
end process;
b_minusa <= b - a;combsection processvariable temp : signed(BC1-1 downto 0) (others => '0');
beginwait until CLKFS = '1';if reset-sync = '1' thencslreg <= (others =>'0');cs2_reg <= (others =>'0');cs3_reg <= (others =>'0');c-state <= c-idle;
elsecase c-state iswhen c-idle =>
if STBFSL = '1' thenb <= is3_reg(BI3-1 downto B13-BC1);a <= csl-reg;
cstate <= csl;
elsec-state <= c-idle;
end if;DATA.VALID <= '0';
when csl =>cslreg <= b;
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temp := b_minusa;b <= bminus-a;a <= cs2_reg & CONVSIGNED(&O', BC1-BC2);c_state <= cs2;DATAVALID <= '0';
when cs2 =>cs2.reg <= temp(BC1-1 downto BC1-BC2);temp := b_minusa;b <= bminus-a;a <= cs3-reg & CONV-SIGNED('O', BC1-BC3);c_state <= cs3;DATAVALID <= '0';
when cs3 =>cs3_reg <= temp(BC1-1 downto BC1-BC3);douti <= bminusa(BC1-1 downto BC1-DOUT'length);DATAVALID <= '1';c_state <= cs4;
when cs4 =>DATAVALID <= '0';c_state <= cjidle;
when others =>DATAVALID <= '0';c_state <= cjidle;
end case;end if;
end process comb-section;
DOUT <= std-logic-vector(dout-i);
-- pragma translateoff-- Record data.record-data : process (STBFSL)variable buf : line;file fouti : text open writemode is "dout2.rec";
begin -- processif rising-edge(STBFSL) thenwrite(buf, CONVINTEGER(douti));writeline(foutl, buf);
end if;end process;
--pragma translate-onend archCOMPCIC2;
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B.6 compsdm.vhd
compsdm.vhd is the VHDL version of the sigma-delta modulator used in the Simulinksimulation.
-- $Id: comp-sdm.vhd,v 1.6 2000/08/09 18:29:28 nch2506 Exp $
-- Nick Homer June 5, 2000-- Compensation Variable Sigma-Delta converter model for the testbench-- of the revised design of the HPGD Rate processing logic. This SDM-- pushes noise away from frequencies around DC, as opposed to the-- rate channel SDM, which is centered around 20KHz. Based on Ed-- Balboni's sigma-delta Matlab module.
library ieee;use ieee.std-logic_1164.all;use ieee.std.logic.arith.all;
use ieee.std-logic-unsigned.all;-- synthesis translate-off
use ieee.MATHREAL.all;
use std.textio.all;-- synthesis translate-on
entity COMP_SDM isport(CVSDMDATA : out std-logic; -- SDM data output
--EN : in stdjlogic; -- MUX enable
SO : in std-logic; -- MUX select 0
Si : in std.logic; -- MUX select 1
THERMNOISE : in real:=0.0;SDM_CLK_IN : in std-logic); -- SDM sampling clock
end COMPSDM;
architecture archCOMPSDM of COMP_SDM isconstant OUTPUTONES : std-logic := '0';type sample is array (0 to 1) of real;
-- for mux select
signal sel: std-logic.vector(1 downto 0);
-- INPUT SIGNALS:
signal step-input, sin-input, sin-fast,impulse, squarewave, ramp-input : real : 0.0;
103
signal sincount : integer 0;
-- Output monitors for writing to file
signal fn-mon, input-mon : real 0.0;
-- Matrix to hold coefficients for calculating outputtype abcdmatrix-type is array (1 to 2, 1 to 3) of real;constant ABCD : abcd-matrix-type (
-- 1 => (-0.001, 0.999, 0.2, -0.2),-- 2 => ( 0.001, 0.999, 0.33333, -0.16667));
1 => (1.000, 0.2, -0.2),2 => (1.000, 0.3333333, -0.16666667));
-- Periods for resetting the generated sin waves.constant SINCOUNTMAX : integer 6666667;
-- constant SIN5_PERIOD : real (2*3.1415/66666.666667);constant SIN5_PERIOD : real := (2*3.1415/66667);constant SINFASTPERIOD: real:= (2*3.1415/10);
begin
sel(l) <= Si;sel(0) <= SO;
-- synthesis translateoff-- Make simple inputs: step and impulse
GenerateSDMInput : processbeginwait until SDM_CLK_IN = '1';
-- make sine wavesif sincount >= SINCOUNTMAX thensincount <= 0; -- Reset counter so that it doesn't overflow
elsesincount <= sin-count + 1;
end if;sin-input <= 2.0 * sin(real(sincount) * SIN5_PERIOD) after 1 ns;sin-fast <= 2.0 * sin(real(sin-count) * SINFASTPERIOD) after 1 ns;
end process;
-- synthesis translate-on
-- Sigma Delta Modulator test module-- optimized to reduce noise at low frequencies
104
SigmaDeltaModulator : processvariable xn : real 0.0; -- input to SDM
variable z : real : 0.0; -- output of first stage
variable w : real : 0.0; -- output of second stage
variable yl : sample (0.0, 0.0); -- remembers history of z
variable y2 : sample : (0.0, 0.0); -- remembers history of w
variable fn : real : 0.0; -- output of SDM: quantized to 1 bit
constant L : real 2.5; -- magnitude limit on values
constant n : integer 0; -- used for keeping track of samples:
variable count3 : integer 0;
beginwait until SDMCLKIN = '1';
-- 11/29/00 smp3454-- Changing it so that only one input is read. Uncomment to make
-- input dependent on mux select signals sO and si
-- case sel is
-- when "00" =>xn := sininput+THERMNOISE;
-- when "01" =>-- xn := -0.5;-- when "10" =>-- xn := 1.0;-- when "11" =>-- xn := 0.5;-- when others =>-- xn := 0.0;-- end case;
-- comparator:
-- we need to do this here so that it doesn't get registered.
if y2(n) > 0.0 thenfn := 2.5;CVSDMDATA <= '1';
elsefn := -2.5;CVSDMDATA <= '0';
end if;
-- used for writing output to file
input-mon <= xn;fnmon <= fn;
-- calculate value at first stage-- purpose of 1st term?
105
z := ABCD(1, 1)*yl(n) + ABCD(1, 2)*xn + ABCD(1, 3)*fn;
-- restrict magnitude to less than or equal to Lif z > L thenyl(n+1) := L;
elsif z < -L thenyl(n+1) -L;
elseyl(n+1) z;
end if;
-- calculate value at second stage
-- purpose of 1st term?w := ABCD(2, 1)*y2(n) + ABCD(2, 2)*yl(n) + ABCD(2, 3)*fn;
-- restrict magnitude to less than or equal to Lif w > L theny2(n+1) := L;
elsif w < -L theny2(n+1) -L;
elsey2(n+1) w;
end if;
y1(n) yl(n+1);
y2(n) y2(n+1);
end process;
-- synthesis translate-off-- write simulation variables to file for graphingSIMULATIONOUTPUT : process
variable buf : line;file fouti : text is out "s-d-in.dat";file fout2 : text is out "s-d-out.dat";
begin
wait until SDM-CLK-IN = '1';write(buf, inputmon);
writeline(foutl, buf);
write(buf, fn-mon);
writeline(fout2, buf);
end process;-- synthesis translateon
end archCOMP-SDM;
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B.7 compalL-tb.vhd
This is a VHDL testbench file created in order to speed up simulation by not incor-porating the INTERFACES block. The input to the SDM should be set such that itdoes not depend on multiplexer-select signals. In the code shown below, READPRNis used for thermal noise generation.
library ieee;use ieee.stdlogic_1164.all;use ieee.std-logic-arith.all;use ieee.std-logicunsigned.all;
use work.constants.all;use std.textio.all;
entity COMPALLTB isend COMPALLTB;
architecture archCOMPALLTB of COMPALLTB is
-- choose random noise block
component READPRNport(RANDNUM: out real;
RESET: IN std-logic;SYSCLK: IN std-logic);
end component;
component COMP_SDM is
port(CVSDMDATA : out stdjlogic; -- SDM data output
--EN : in stdlogic; -- MUX enable
SO : in stdlogic; -- MUX select 0Si : in stdlogic; -- MUX select 1
THERMNOISE : in real;
SDM_CLK_IN : in stdilogic); -- SDM sampling clock
end component;
component COMPCIC isport(CLK-FS: IN STD-LOGIC; -- System clock
DATAIN: IN stdlogic; -- data from SDM
DATAVALID: OUT std-logic; -- output valid
DOUT: OUT stdlogic-vector(17 downto 0); -- output
RESET: IN STDLOGIC; -- reset
STBFSH: IN STD-LOGIC; -- CIC high sampling rateSTB_FSL: IN STDLOGIC); -- CIC low sampling rate
end component;
107
-- set R of CIC filter here
constant R: integer := 900;signal reset: stdilogic:='O';
signal randnum : real;
signal cv-sdmdata stdlogic;
signal sdmclkin : std-logic := '0';signal clkfs : std-logic : '0';
signal stbfsh : std-logic := '0';
signal stbfsl : stdlogic := '0';
-- set the output width of the CIC filter here
signal dout: stdlogic.vector(17 downto 0);
signal datavalid: stdjlogic;
begin
Ul: READPRNport map(RANDNUM => randnum,
RESET => reset,SYSCLK => sdm_clk_in); --sysclk is a misnomer. it's 333KHz.
U2: COMPSDM
port map(CV-SDMDATA => cv-sdmdata,SO => '0',S1 => '0',THERMNOISE => randnum,SDMCLKIN => sdmclkjin);
U3: COMPCIC
port map(CLKFS => clk-fs,DATAIN => cvsdmdata,DATAVALID => data-valid,DOUT => dout,RESET => reset,STBFSH => stbjfsh,
STBFSL => stbfsl);
-- The following section generates clocks and strobes so that a separate
-- clock generation block is not needed.
-- generating simple clock signals
reset <= '1' after 1000 ns, '0' after 2000 ns;
sdmclk-in <= not sdmclkin after 1500 ns;clkfs <= not clk-fs after 125 ns;
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-- generating strobe signals for CIC filtercvtiming: processvariable cfsh: integer range 0 to 20; -- for stb_fsh
variable cfsl: integer range 0 to R; -- for stbfsl
beginwait until clkjfs = '1';if cfsh = 11 then -- 4e6/12 = 333.33KHzc_fsh : 0;stbjfsh <= '1' after 1 ns;if c-fsl = (R-1) then -- 333.333KHz/Rcfsl := 0;stb-fsl <= '1' after I ns;
else c-fsl := cfsl + 1;end if;
else c-fsh := c-fsh + 1;stbfsh <= '0' after 1 ns;stbfsl <= '0' after 1 ns;
end if;end process;
end archCOMPALLTB;
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