analysis of pattern area reduction for logic circuit and...

Contemporary Engineering Sciences, Vol. 8, 2015, no. 13, 589 - 601

HIKARI Ltd, www.m-hikari.com http://dx.doi.org/10.12988/ces.2015.54134

Analysis of Pattern Area Reduction for

Logic Circuit and System LSI with SGT

Tomohiro Yokota

DNP data techno Co., Ltd. Warabi-shi, Saitama, Japan

Shigeyoshi Watanabe

Department of Information Science

Shonan Institute of Technology, Fujisawa, Japan

Copyright © 2015 Tomohiro Yokota and Shigeyoshi Watanabe. This article distributed under

the Creative Commons Attribution License, which permits unrestricted use, distribution, and

reproduction in any medium, provided the original work is properly cited.

Abstract

The analysis of pattern area reduction with SGT for inverter, NAND gates, and

system LSI focusing in the placement direction of SGT has been described.

Except for inverter with small channel width the pattern area of these circuits with

SGT featured by the horizontal placement are smaller (4.5%-11.2% for system

LSI) than that with SGT featured by vertical placement. And also flip-flop and

multiplexer is firstly designed with SGT. The reduction rate of pattern area to

planar transistor case of these circuits is 65-86%. These values are almost the

same as previously presented full adder case. SGT with horizontal placement is

promising candidates for realizing high packing density logic circuit and system

LSI.

Keywords: SGT, pattern area, placement direction, system LSI, flip-flop, multi-

plexer, logic circuit

1 Introduction

Recently, the scaling of the conventional planar transistor becomes increasingly

difficult because of its large short channel effect [1]. In order to overcome this

problem FinFET [2][3] which use the 3 planes and SGT (Surrounding Gate

Transistor) [4] which use the 4 planes as the channel for reducing the short

channel effect has been developed. By using SGT not only reduction the short

590 Tomohiro Yokota and Shigeyoshi Watanabe

channel effect but also the reduction of the pattern area compared with that of the

conventional planar transistor can be realized. This is because not only the planar

region but also the sidewall can be used as the channel for this newly proposed

structure.

The structure of SGT is shown in Fig.1. Four sidewalls can be used as the channel.

Assuming that the sidewall channel width is defined as Ws, within the small

pattern area large total channel width of 4Ws can be successfully realized. The

drain current flows along vertical direction which is perpendicular to the

conventional planar transistor case.

Figure 1: Structure of SGT

The research of LSI with SGT is focused on the device technology of transistor

and memory such as DRAM [5]-[9]. The research of LSI with SGT about the

pattern area is very few. These research about system LSI [10] is limited to the

simple logic circuit such as inverter, NAND gates, and full adder circuit. In this paper, the study of pattern area reduction with SGT for inverter, NAND

gates and system LSI focusing in the placement direction of SGT has been

described. And also, flip-flop and multiplexer circuit is firstly designed with SGT.

This reduction of pattern area with SGT has been compared with that with

formally designed full adder circuit.

2 Pattern area dependence on placement direction with SGT for

inverter and NAND gates

The design rule for this study is summarized in table 1. F is feature size. In this

study it is assumed that the same drain current flows, if the gate length, the

channel width, and applied voltage are the same value. The channel width is set to

8F. The top view is shown in Fig.2. For placement direction of SGT both

horizontal layout featured by parallel direction placement of SGT and vertical

layout featured by vertical direction placement of SGT are considered.

Gate

Silicon pillar

Gate oxide

Sidewall channel width :Ws

Analysis of pattern area reduction 591

Table 1. Design rule

Figure 2: Top view of SGT.

(A) (B) (C)

Figure 3: Designed pattern of inverter of 8F, (A)planar, (B)SGT(vertical) and (C)SGT(horizontal).

Using this design rule inverter, 2-, 3- and 4-input NAND gates have been

designed. Layout pattern of inverter using the conventional planar transistor,

SGT(vertical) and SGT(horizontal) is shown in Fig.3 with channel width of 8F.

The pattern area of SGT(vertical) and SGT(horizontal) can be reduced to 60% and

65% respectively compared with those of planar case. The larger pattern area of

SGT(horizontal) is due to the larger unused pattern area between NMOS and

PMOS. This larger pattern area is feature of inverter with small channel width of

8F.

Layout pattern of 4-input NAND gates using the conventional planar transistor,

SGT(vertical) and SGT(horizontal) is shown in Fig.4 with channel width of 8F.

The pattern area of SGT(vertical) and SGT(horizontal) can be reduced to 92% and

Planar SGTgate length F F

gate to contact 0.5F 0.5FnMOS to pMOS 3F 3Fwiring to wiring F Fcontact size F*F F*F

silicon pillar size 2F*2Fdeep contact size F*F


65% respectively compared with those of planar case. The larger pattern area of

SGT(vertical) is due to the larger pattern area for wirings between NMOS and

PMOS. This feature is the same as 2-input and 3-input NAND gates.

（Ｂ）

(A)

（Ｃ）

Figure 4: Designed pattern of 4-input NAND gates of 8F, (A)planar, (B)SGT(vertical) and

(C)SGT(horizontal).

Next, inverter, 2-, 3- and 4-input NAND gate of various channel width have been

designed. The results of pattern area reduction with SGT(vertical) and

SGT(horizontal) are shown in Fig.5. Except for inverter with channel width of 8F

SGT(horizontal) is smaller than that with SGT(vertical). For the small channel

width case with large number of input the pattern area reduction with

SGT(horizontal) is large compared with SGT(vertical) case.


Channel width

Nor

mal

ized

pat

tern

are

a

vertical

horizontal

(C) Figure 5: Pattern area reduction with SGT(vertical) and SGT(horizontal), (A)inverter, (B)2-input

NAND gate, (C)4-input NAND gate

3 Pattern area reduction dependence on the placement direction

with SGT for system LSI

In this section the placement direction dependence of pattern area with SGT for

two system LSI are described. The pattern area analysis of system LSI for

communication [11] with planar transistor is shown in Table 2(A). Number of input


signal and channel width is used for this analysis. X1 indicates the channel width

of 8F. This pattern area is reduced to 62.99% for SGT(vertical), Table 2(B), and to

58.48% for SGT(horizontal), Table 2(C). This is because almost circuits are

composed with large channel width and large input signal number circuits except

for inverter with small channel width.

Table 2: Pattern area reduction with SGT for system LSI for communication, (A)planar,

(B)SGT(vertical), (C)SGT(horizontal)

×１ ×２ ×３ ×４ ×８ ×１６ ×２０ Sum

1 13.9 3 0.5 1.2 4.6 1.4 1.3 25.9

2 50.7 6 5.9 62.6

3 5.5 1.4 0.7 7.6

4 2.5 2.5

6 0.9 0.9

8 0.4 0.4

Sum 73.9 10.4 0.5 7.8 4.6 1.4 1.3 100

(A)

×１ ×２ ×３ ×４ ×８ ×１６ ×２０ Sum

1 8.28 1.41 0.21 0.48 1.75 0.52 0.47 13.11

2 33.90 3.17 2.63 39.70

3 4.50 0.87 0.35 5.73

4 2.30 2.30

6 1.28 1.28

8 0.88 0.88

Sum 51.14 5.45 0.21 3.46 1.75 0.52 0.47 62.99

(B)

×１ ×２ ×３ ×４ ×８ ×１６ ×２０ Sum

1 8.98 1.41 0.20 0.44 1.58 0.46 0.41 13.49

2 32.10 2.93 2.38 0.00 37.41

3 3.76 0.75 0.31 0.00 4.82

4 1.84 1.84

6 0.65 0.65

8 0.28 0.28

Sum 47.60 5.09 0.20 3.13 1.58 0.46 0.41 58.48

(C)

Another example is shown in Table 3. The pattern area analysis of cell library for

system LSI [12][13] with planar transistor is shown in Table 3 (A). This pattern

area is reduced to 70.29% for SGT(vertical), Table 3(B), and to 59.13% for

SGT(horizontal), Table 3(C). This feature, larger pattern area with SGT(vertical)

compared with SGT(horizontal), is the same as system LSI for communication.

Therefore, the further research about relatively complicated logic circuit is

performed using only SGT(horizontal) with large pattern area reduction effect.


Table 3: Pattern area reduction with SGT for cell library for system LSI, (A)planar,

(B)SGT(vertical), (C)SGT(horizontal)

4 pattern area reduction with SGT for flip-flop, multiplexer and

full adder circuit

Using flip flop, multiplexer and 3 kinds of full adders the pattern area reduction

with SGT(horizontal) is newly estimated. 3 kinds of full adders are as follows,

(1)Full adder with 2 input NAND/NOR gates, (2)Full adder with 3/4 input

NAND/NOR gates, (3)Full adder with composite gate. Fig.6 shows the estimated

results of flip-flop ((A)Circuit diagram, (B)Pattern with planar, (C)Pattern with

SGT(horizontal)). Fig.7, Fig.8, and Fig.9 show the estimated results of multiple-

xer, Full adder with 2 input NAND/NOR gates, and Full adder with 3/4 input

NAND/NOR gates, respectively. Channel width is 8F.

(A)

×1 ×2 ×３ ×４ ×8 ×16 ×20 Sum1 1.64 1.64 1.64 1.64 6.562 26.23 19.67 1.64 1.64 49.183 16.39 9.84 26.234 4.92 4.92 9.846 4.92 3.28 8.208 0.00

Sum 54.10 39.34 1.64 3.28 1.64 0.00 0.00 100.00

(B)

×1 ×2 ×３ ×４ ×8 ×16 ×20 Sum1 0.98 0.77 0.66 0.62 3.032 17.54 10.39 0.79 0.73 29.453 13.41 6.11 19.534 4.52 3.49 8.026 6.99 3.28 10.278 0.00

Sum 43.45 24.05 0.79 1.39 0.62 0.00 0.00 70.29

(C)

×1 ×2 ×３ ×４ ×8 ×16 ×20 Sum1 1.06 0.77 0.60 0.56 2.992 16.61 9.61 0.69 0.66 27.563 11.21 5.27 16.484 3.62 2.90 6.526 3.55 2.03 5.588 0.00

Sum 36.04 20.58 0.69 1.26 0.56 0.00 0.00 59.14


(A)

(B) (C)

Figure 6: Flip flop, (A)Circuit diagram, (B)Pattern with planar, (C)Pattern with SGT(horizontal).

（Ａ）

（Ｂ）（Ｃ） Figure 7: Multiplexer, (A)Circuit diagram, (B)Pattern with planar, (C)Pattern with

SGT(horizontal).


（Ａ）

(B) (C)

Figure 8: Full adder with 2 input NAND/NOR gates, (A)Circuit diagram, (B)Pattern with planar,

(C)Pattern with SGT(horizontal).

(A)

(B) (C) Figure 9: Full adder with 3/4 input NAND/NOR gates, (A)Circuit diagram, (B)Pattern with planar,

(C)Pattern with SGT(horizontal).


Table 4: reduction of pattern area for logic circuit

reductoin rate(%)No. of input ration of wiring （％） vertical length horizontal length pattern area

flip flop 1 40 68 94 65multiplexer ー 54 68 127 86full adder （2-input NAND） 1.5 32 63 109 69full adder（composite） 2 24 64 113 72full adder（3-, 4-input NAND ） 2.3 42 71 108 77

Estimated results of pattern area reduction with SGT(horizontal) is shown in Table

4. Number of input is defined as the average number of input for gates circuit

except for multiplexer. The ratio of wiring is defined as the pattern area of wiring

area. By introducing SGT(horizontal) pattern area of these circuit can be

successfully reduced to 65-86% compared with that with planar transistor. The

vertical length of these circuit can be reduced to 63-71% compared with that with

planar transistor. On the other hand, the horizontal length is enlarged as shown in

the table.

Figure 10: Relation between ratio of wiring and vertical length

Figure 11: Relation between number of input and horizontal length

Ratio of wiring

Norm

aliz

ed v

ert

ical le

ngth

multiplexer

2-input

3,4-input

compositeFlip flop


For the further analysis reduction of vertical length and horizontal length are

investigated as shown in Fig.10 and Fig.11. Except for multiplexer which can not

define the number of input normalized vertical length is strongly in proportion to

ratio of wiring. With increasing ratio of wiring normalized vertical length

increases. In the case of ratio of wiring is 100% pattern area reduction with

SGT(horizontal) cannot be considered. On the other hand in the case of ratio of

wiring is 0% pattern area can be successfully reduced to 50% with

SGT(horizontal).

The normalized horizontal length is almost independent to number of input. In the

case of large number of input, full adder case, the value is about 110% which is

10% larger than compared with planar case.

5 Conclusion

The analysis of pattern area reduction with SGT for inverter, NAND gates, and

system LSI focusing in the placement direction of SGT has been described.

Except for inverter with small channel width the pattern area of these circuits with

SGT featured by the horizontal placement are smaller (4.5%-11.2% for system

LSI) than that with SGT featured by vertical placement. And also flip-flop and

multiplexer is firstly designed with SGT. The reduction rate of pattern area to

planar transistor case of these circuits is 65-86%. These values are almost the

same as previously presented full adder case. SGT with horizontal placement is

promising candidates for realizing high packing density logic circuit and system

LSI.

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Received: April 13, 2015; Published: June 19, 2015

http://dx.doi.org/10.1109/4.753680

analysis of pattern area reduction for logic circuit and...

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