Microelectronics Reliability 51 (2011) 2053–2058

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Microelectronics Reliability

journal homepage: www.elsevier .com/locate /microrel

Analytical threshold voltage model for cylindrical surrounding-gate MOSFETwith electrically induced source/drain extensions

Cong Li a,⇑, Yiqi Zhuang a, Ru Han b, Gang Jin a, Junlin Bao a

a Key Laboratory for Wide Band-Gap Semiconductor Materials and Devices of Ministry of Education, School of Microelectronics, Xidian University, Xi’an 710071, Chinab Aviation Microelectronics Center, Northwestern Polytechnic University, Xi’an 710072, China

a r t i c l e i n f o

Article history:Received 20 January 2011Received in revised form 18 April 2011Accepted 18 April 2011Available online 18 May 2011

0026-2714/$ - see front matter � 2011 Elsevier Ltd. Adoi:10.1016/j.microrel.2011.04.017

⇑ Corresponding author. Tel.: +86 29 8820 1983 801E-mail address: cong.li@mail.xidian.edu.cn (C. Li).

a b s t r a c t

Physics-based analytical threshold voltage model for cylindrical surrounding-gate MOSFET with electri-cally induced source/drain extensions is presented. The effect of inversion carriers on the channel’spotential is considered in presented model. Using this analytical model, the characteristics of EJ-CSGare investigated in terms of surface potential and electric field distribution, threshold voltage roll-off,and DIBL. Results show that the application of electrically induced S/D extensions to the cylindrical sur-rounding-gate MOSFET will successfully suppress the hot-carrier effects, threshold voltage roll-off, andDIBL. It is also revealed that a moderate side-gate bias voltage, a small gate oxide thickness, and a smallsilicon channel radius are needed to improve device characteristics. The derived analytical model is ver-ified by its good agreement with the three-dimensional numerical device simulator ISE.

� 2011 Elsevier Ltd. All rights reserved.

1. Introduction

As semiconductor devices are scaled down to the nanoscaleregime, short-channel effects (SCEs) such as threshold voltageroll-off, drain induced barrier lowering (DIBL) and hot-carrier ef-fects (HCEs) impose a physical limit on the ultimate performanceof traditional planar MOSFETs [1]. To overcome these shortcom-ings, various alternative structures have been proposed in recentyears. Among them, cylindrical surrounding-gate (CSG) MOSFETis considered to be the most promising device structure for its bestcontrol of SCEs [2–9]. However, even for CSG MOSFET, SCEs cannotbe neglected when channel-lengths below 100 nm [2].

An ultra shallow extended source/drain (S/D) extension is a veryeffective method to suppress SCEs in MOSFETs. However, it is verydifficult to form shallow junctions by conventional fabricationtechnique. It has been reported that SCEs can be suppressed byusing an inversion layer as an ultra shallow extended S/D [10–16]. This kind of device is known as electrically induced shallowjunction (EJ) MOSFET.

To incorporate the advantages of both CSG and EJ structures,recently, a new structure called cylindrical surrounding-gate MOS-FET with electrically induced S/D extensions (EJ-CSG MOSFET) hasbeen proposed by Li et al. [17]. In their work, the characteristics ofEJ-CSG MOSFET were investigated merely by using TCAD tool. How-ever, to better understand the device physics as well as faster inves-tigate device performances of EJ-CSG MOSFET, a two-dimensional

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(2D) analytical threshold voltage model for EJ-CSG MOSFET isrequired.

Although several analytical models [6,7,18] have been proposedfor modeling CSG MOSFET with more than one channel region,both of those models neglect the effect of the charge carriers onthe potential of channel. This may be a valid assumption for deviceunder weak inversion condition. But for EJ-CSG MOSFET, side-gateregions work in moderate inversion condition, the effect of inver-sion carriers on the channel’s potential should not be neglected.

In this paper, we report for the first time, an analytical thresholdvoltage model for EJ-CSG MOSFET by solving the 2D Poisson’sequation with three continuous region’s boundary conditions.Moreover, to accurately predict the characteristics of EJ-CSG MOS-FET, the effect of inversion carriers on the channel’s potential isconsidered in our model. Using this model, the 2D potential profilecan be calculated, which can be used to explain the unique attri-butes of EJ-CSG structure in suppressing the SCEs. The effects ofvarying the device parameters (such as gate oxide thickness andradius of channel) can be easily investigated using the analyticalthreshold voltage model proposed in this paper as well. The accu-racy of the analytical model is verified by the three-dimensional(3D) numerical device simulator ISE.

2. Model derivation

The cross-sectional view of EJ-CSG MOSFET is shown in Fig. 1 Asshown in the figures, the extremely shallow S/D junction is real-ized with a tripe-gate structure consisting of one main-gate (withgate length L2) and two side-gates (with gate length L1 and L3,respectively). The two side-gates are biased independently of

Fig. 1. Cross-section view of EJ-CSG MOSFET.

2054 C. Li et al. / Microelectronics Reliability 51 (2011) 2053–2058

the main-gate to induce two inversion layers which work as thevirtual source and drain.

For the symmetry of the structure, the electrostatic potentialand the electric field have no variation with angular in plane ofthe radial direction, hence a 2D analysis is sufficient (only channelradius direction r and channel-length direction z are employed). Itwas further found that when L1 = L2 = L3, the device can be oper-ated in optimal condition [12–14]. Unless otherwise stated, thisoptimal configuration is applied in whole paper.

The thickness of diffusion barriers (td) is so small that can be ne-glected in model derivation, therefore the silicon channel can bedivided into three parts. The surface potential is derived by solvingthe Poisson’s equation in those regions with continuity boundaryconditions [15]. Then, the electrostatic potential /(r,z) in three re-gions of silicon channel can be written as

1r@

@rr@

@r/jðr; zÞ

� �þ @2

@z2 /jðr; zÞ ¼qesi

Na þ njðr; zÞ� �

; j ¼ 1;2;3

ð1Þ

where q is the electron charge, esi is the dielectric constant of siliconchannel, Na is the uniform channel doping concentration, and nj(r,z)is mobile charge density of region j. Since applying rigorous methodto solve the above equations is too difficult, for presenting a simplemodel, following assumptions is adopted:

1. Main-gate region works in weak inversion regime then surfacemobile charge density is neglected, i.e. n2(r = R,z) = 0.

2. Side-gate regions work in moderate inversion regime then sur-face mobile charge density is only dependent on the surfacepotential, i.e. njðr ¼ R; zÞ ¼ c/ðjÞs ðzÞ; j ¼ 1;3, where c is a fittingparameter, /ðjÞs ðzÞ ¼ /jðr ¼ R; zÞ is the surface potential of regionj.

3. Influence of the fixed oxide charges on the electrostatics poten-tial of the channel is neglected.

4. The potential profile in the radial direction can be expressed asa parabolic function

/jðr; zÞ ¼ cðjÞ0 ðzÞ þ cðjÞ1 ðzÞr þ cðjÞ2 ðzÞr2; j ¼ 1;2;3 ð2Þ

where the coefficients cðjÞ0 ðzÞ, cðjÞ1 ðzÞ, and cðjÞ2 ðzÞ are functions of z only.

In EJ-CSG MOSFET, the electric field in the center of the siliconchannel is zero by symmetry

@/jðr; zÞ@r

����r¼0¼ 0 ¼ cðjÞ1 ðzÞ j ¼ 1;2;3 ð3Þ

Electric flux at the interface between oxide and silicon channel iscontinuous

@/jðr; zÞ@r

����r¼R

¼ eox

esit0oxV ðjÞgs � /MS � /ðjÞs ðzÞ� �

¼ 2cðjÞ2 ðzÞR; j ¼ 1;2;3

ð4Þ

where eox is the dielectric constant of gate oxide,t0ox ¼ R lnð1þ tox=RÞ is called equivalent gate oxide thickness [19],V ð1Þgs ¼ V ð3Þgs ¼ VSG is the side-gate bias voltage, and V ð2Þgs ¼ VMG is themain-gate bias voltage. /MS is the work function difference.

From (1)–(4), we can obtain the differential equation of the sur-face potential as

d2/ðjÞs ðzÞdz2 � k2

j /ðjÞs ðzÞ ¼ bj; j ¼ 1;2;3 ð5Þ

where

k1 ¼ k3 ¼ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi2eox

esiRt0ox

þ qcesi

s; ð6Þ

k2 ¼ffiffiffiffiffiffiffiffiffiffiffiffiffiffi2eox

esiRt0ox

s; ð7Þ

bj ¼qNa

esi�

2eox V ðjÞgs � /MS

� �esiRt0ox

j ¼ 1;2;3 ð8Þ

(5) presents three second-order differential equations with constantcoefficients, thus the general solution for the surface potential is

/ðjÞs ðzÞ ¼ Aj expðkjzÞ þ Bj expð�kjzÞ þ rj; j ¼ 1;2;3 ð9Þ

where

rj ¼ �bj

k2j

j ¼ 1;2;3 ð10Þ

The coefficients A1, A2, A3, B1, B2, and B3 are determined by the fol-lowing boundary conditions:

1. The surface potential at the source end is

/ð1Þs ðz ¼ 0Þ ¼ Vbi: ð11Þ

2. The surface potential at the drain end is

/ð3Þs ðz ¼ L1 þ L2 þ L3Þ ¼ Vbi þ Vds: ð12Þ

3. The surface potential at the interface of the three regions iscontinuous:

/ð1Þs ðz ¼ L1Þ ¼ /ð2Þs ðz ¼ L1Þ; ð13Þ/ð2Þs ðz ¼ L1 þ L2Þ ¼ /ð3Þs ðz ¼ L1 þ L2Þ: ð14Þ

4. The electric flux at the interface of the three regions iscontinuous:

d/ð1Þs ðzÞdz

�����z¼L1

¼ d/ð2Þs ðzÞdz

�����z¼L1

; ð15Þ

d/ð2Þs ðzÞdz

�����z¼L1þL2

¼ d/ð3Þs ðzÞdz

�����z¼L1þL2

: ð16Þ

Using the boundary condition (11)–(16), the resultant expres-sion of coefficients A1, A2, A3, B1, B2, and B3 can be obtained as

A2 ¼

T3T2 expð�k2L2Þ þ k1T1ðVbi þ Vds � r1Þ

�T3T1 � k1T2ðVbi � r1Þ expð�k2L2Þ

" #

T21 expðk2L2Þ � T2

2 expð�k2L2Þ;

ð17Þ

0 30 60 90 120 150−10

−8

−6

−4

−2

0

2

4

6

8

10

Channel length position, z (nm)

Cha

nnel

rad

ius

posi

tion,

r (

nm)

0.80V

0.66V

0.60V

0.54V

0.45V

0.26V

0.23V

0.23V

0.26V

Solid line: Model Dash line: ISE

0.21V

0.22V

0.45V

0.54V

0.60V

0.66V

0.84V

1.25V

Fig. 2. Two-dimensional analytical potential contours of EJ-CSG MOSFET. Thesimulated device parameters are Vds = 0.5 V, VMG = 0.1 V, VSG = 0.5 V, R = 10 nm,tox = 5 nm, L1 = L2 = L3 = 50 nm.

C. Li et al. / Microelectronics Reliability 51 (2011) 2053–2058 2055

B2 ¼k1ðVbi � r1Þ � T3 � A2T2

T1; ð18Þ

A1 ¼A2ðk1 þ k2Þ þ B2ðk1 � k2Þ þ k1ðr2 � r1Þ

2k1 expðk1L1Þ; ð19Þ

B1 ¼A2ðk1 � k2Þ þ B2ðk1 þ k2Þ þ k1ðr2 � r1Þ

2k1 expð�k1L1Þ; ð20Þ

A3 ¼

A2ðk1 þ k2Þ expðk2L2Þ þ k1ðr2 � r1ÞþB2ðk1 � k2Þ expð�k2L2Þ

� �2k1

;ð21Þ

B3 ¼

A2ðk1 � k2Þ expðk2L2Þ þ k1ðr2 � r1ÞþB2ðk1 þ k2Þ expð�k2L2Þ

� �2k1

;ð22Þ

where T1 = k1cosh(k1L1) + k2sinh(k1L1), T2 = k1cosh(k1L1)� k2sinh(k1L1),and T3 = k1(r2 � r1)cosh(k1L1).

By differentiating /s(z) with respect to z, the surface electricfield in the z direction is given as follows

EjðzÞ ¼ kjAj expðkjzÞ � kjBj expð�kjzÞ j ¼ 1;2;3 ð23Þ

For EJ-CSG MOSFET, the minimum surface potential lies in themain-gate region, it implies that the threshold behavior is mainlycontrolled by the main-gate. By differentiating /ð2Þs ðzÞ with respectto z, and equating it to zero, the position zmin of /ð2Þs can be obtained.Substituting zmin for z in /ð2Þs , /s,min can be obtained as

/s;min ¼ 2ffiffiffiffiffiffiffiffiffiffiA2B2

p� b2

k22

: ð24Þ

Threshold voltage is an very important parameter for MOSFET. Con-sidering the non-ideal effects of realistic devices, there are so manymethods to determine threshold voltage [20,21]. Though for un-doped MOSFET, the ‘‘/s,min = 2/F’’ method is inaccurate, while forlightly doped MOSFET, the ‘‘/s,min = 2/F’’ method is the most effec-tive way to obtain analytical expression of threshold voltage [5–9,15,22–24]. So in this paper the threshold voltage is defined as

/s;min ¼ 2/F for VMG ¼ V th: ð25Þ

Substituting (25) into (24) and solving for VMG, the threshold volt-age can be obtained as

V th ¼�x2 þ

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffix2

2 � 4x1x3

q2x1

þ /MS þqNaRt0ox

2eox; ð26Þ

with

x1 ¼ 4Q 1P1 � 1; ð27Þx2 ¼ 4ðQ2P1 þ Q 1P2 þ /FÞ; ð28Þx3 ¼ 4 Q 2P2 � /2

F

�; ð29Þ

where

Q 1 ¼k1 coshðk1L1Þ T2 expð�k2L2Þ � T1½ �

T21 expðk2L2Þ � T2

2 expð�k2L2Þ; ð30Þ

Q 2 ¼k1T1ðVbi þ Vds � r1Þ � k1T2ðVbi � r1Þ expð�k2T2Þ

T21 expðk2L2Þ � T2

2 expð�k2L2Þ� r1Q 1; ð31Þ

P1 ¼�k1 coshðk1L1Þ � T2Q 1

T1; ð32Þ

P2 ¼k1 coshðk1L1Þ � T2Q1 þ k1ðVbi � r1Þ

T1: ð33Þ

3. Simulation results and discussion

Using derived analytical models, the performance of EJ-CSGMOSFET is examined in terms of surface electrostatics potential,electric field distribution, threshold voltage roll-off and DIBL. Thesimulated data of conventional CSG MOSFET is also included forcomparison. To verify the analytical model, the three-dimensionalnumerical device simulator ISE is employed to simulate the devicecharacteristics. To extract the threshold voltage from the simulateddata using ISE, commonly used maximum transconductance meth-od is adopted in data analysis tool. Unless otherwise stated, drainand source doping concentration Nd = 5 � 1019 cm�3, silicon chan-nel doping concentration Na = 1016 cm�3, gate length L1 = L2 =L3 = 50 nm, silicon channel radius R = 10 nm, gate oxide thicknesstox = 5 nm, the work functions of gate is 4.9 V, and fitting parame-ter c is chosen to be 2.0 � 1018(V cm3)�1. For ISE simulation, thethickness of diffusion barrier td is fixed at 2 nm.

Fig. 2 shows the 2D analytical potential contours of EJ-CSGMOSFET. It is evident that the potential contours of region 2 havethe tendency to bent vertically, which implies that the electricfields from main-gate can easily penetrate into the channel andcontrol the threshold behavior (main-gate is the so-called controlgate) [25,26]. In contrast, the potential contours of region 3 areprone to bent horizontally. It indicates that most of the lateralelectrical field induced by drain voltage is completely absorbedin region 3, leading to the effective suppression of DIBL.

In short-channel devices, electric field peak near the drain endcauses carrier heating that result in the hot-electron effect therebydegrading the hot-carrier reliability of the device [24]. The surfacehorizontal electric field of EJ-CSG MOSFET is shown in Fig. 3. It isfound that the presence of the extremely shallow inversion layersunder the side-gates reduces the peak electric field of main-gateconsiderably, which implies that EJ-CSG MOSFET exhibits furthersuppression of HCEs than CSG MOSFET.

The most significant phenomenon that clarifies the SCEs isthreshold voltage roll-off. Fig. 4 shows the threshold voltage roll-off of EJ-CSG MOSFET versus the main-gate length compared withCSG MOSFET. It can be observed that EJ-CSG MOSFET exhibits alower threshold voltage roll-off than CSG MOSFET. This unique fea-ture of EJ-CSG MOSFET structure is an added advantage when thedevice dimensions are continuously shrinking.

Fig. 3. Longitudinal electric field along the channel toward the drain end. Thesimulated device parameters are Vds = 1 V, VMG = 0.1 V, R = 10 nm, tox = 5 nm,L1 = L2 = L3 = 50 nm.

Fig. 4. Threshold voltage roll-off versus main-gate length. The simulated deviceparameters are Vds = 0.05 V, R = 10 nm, tox = 5 nm.

Fig. 5. Threshold voltage roll-off versus the main-gate length with different siliconradii. The simulated device parameters are Vds = 0.05 V, tox = 5 nm.

Fig. 6. Threshold voltage roll-off versus the main-gate length with different gateoxide thickness. The simulated device parameters are Vds = 0.05 V, R = 10 nm.

Fig. 7. DIBL variations versus the main-gate length for EJ-CSG MOSFET and CSGMOSFET. The simulated device parameters are R = 10 nm, tox = 5 nm.

2056 C. Li et al. / Microelectronics Reliability 51 (2011) 2053–2058

Fig. 5 shows that the threshold voltage roll-off for EJ-CSG MOS-FET against main-gate length with various radius of the siliconchannel. It is revealed that a small radius of the silicon channelleads to less threshold roll-off. However, when the radius of the sil-icon channel is less than 5 nm, the quantum effects that causes dif-ferent device characteristics will become important [27]. In thispaper, we are only evaluating devices with a silicon channel radiuslarger than 5 nm. Therefore, quantum effects can be neglected.

It is shown in Fig. 6 that the dependence of the thresholdvoltage roll-off on the main-gate length for different gate oxidethickness tox. The plot indicates that a larger gate oxide thick-ness will induce a greater threshold voltage roll-off. The gategradually loses control of the channel as the gate oxide thicknesssteadily increases. This is because a large oxide thickness will re-sist the vertical electric field from the gate into the channel,resulting in the degradation of threshold behavior. Therefore,to suppress the threshold voltage roll-off, thin gate oxide ispreferred.

Fig. 8. Surface potential profiles in the channel of the EJ-CSG MOSFET for differentside-gate biases. The simulated device parameters are Vds = 1 V, VMG = 0.2 V,R = 10 nm, tox = 5 nm.

C. Li et al. / Microelectronics Reliability 51 (2011) 2053–2058 2057

DIBL variations of EJ-CSG MOSFET and CSG MOSFET versus themain-gate length are presented in Fig. 7. DIBL can be expressedas DVth/DVds, where DV th ¼ V thjVds¼0:05 V � V thjVds¼2 V. It is clear fromthe figure that with the electrical induced source/drain extension,EJ-CSG MOSFET structure effectively screens the main-gate regionfrom the drain bias variations. Hence accounts for much bettersuppression of DIBL than CSG MOSFET structure.

Figs. 3, 4, and 7 also shows the influence of side-gate bias(VSG) on electric field, threshold voltage roll-off and DIBL. It isdemonstrated that lower VSG improves electric field, thresholdvoltage roll-off and DIBL. To explain this, Fig. 8 shows the depen-dence of surface potential on side-gate bias. It can be seen fromfigure that when the side-gate bias is 0 V, the surface potentialin the virtual source and drain are lower than that in main-gateregion, and there are not enough carriers in the virtual sourceand drain. As the side-gate bias increasing, the potential and car-rier concentration in the virtual source and drain will alsoincreasing. When side-gate bias increases to above 0.5 V, the car-rier concentration in virtual source and drain are sufficient forthe inversion layers to function as the virtual source and drain.However, if the side-gate bias is too large, the position of mini-mum surface potential for main-gate region is pulled up, whichresulting in poor immunity to SCEs.

Figs. 2–8 show that the analytical model is in good agreementwith 3D numerical device simulator ISE.

4. Conclusions

Based on solving 2D Poisson’s equation in cylindrical coordi-nates, analytical surface potential and threshold voltage modelsfor a cylindrical surrounding-gate MOSFET with electrically in-duced source/drain extensions (EJ-CSG MOSFET) is developed.To accurately predict potential distribution under side-gate re-gions, the effect of inversion carriers on the channel’s potentialis considered in this analytical model. Using this analyticalmodel, the characteristics of EJ-CSG are investigated in termsof surface potential and electric field distribution, threshold volt-age roll-off, and DIBL. It is shown that EJ-CSG MOSFET exhibitsbetter performance in suppression of threshold voltage roll-off,DIBL and HCEs. It is also revealed that a moderate side-gate biasvoltage, a small gate oxide thickness and a small silicon channelradius are needed to improve threshold voltage characteristics.

The results obtained from the models agree well with the simu-lated results obtained using ISE. This paper not only provides anefficient tool for design and characterization of the EJ-CSG MOS-FET, but also gives the physical insight into the device physics ofthe EJ-CSG MOSFET.

Acknowledgements

This work was supported by the National Nature Science Foun-dation of China (Grant No. 61076101). The authors would like tothank Li Zhang for helpful discussions.

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