anand institute of higher technology · 2014-07-24 · 1 cmageshkumar_ap_aiht cs2071_computer...

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CMageshKumar_AP_AIHT CS2071_Computer Architecture

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ANAND INSTITUTE OF HIGHER TECHNOLOGY Chennai-603 103

DEPARTMENT OF ELECTRONICS AND INSTRUMENTATION ENGINEERING

CS2071 COMPUTER ARCHITECTURE

2 Marks and 16 Marks Question Bank

Faculty Name: C.MAGESHKUMAR

YEAR / SEMESTER: IV / VII EIE A & B

UNIT I – INSTRUCTION SET ARCHITECTURE

Introduction to computer architecture - Review of digital design – Instructions and addressing –procedures and data –

assembly language programs – instruction set variations

UNIT II – ARITHMETIC LOGIC UNIT

Number representation – design of adders – design of simple ALUs – design of Multipliers and dividers – design of

floating point arithmetic unit

UNIT III DATA PATH AND CONTROL

Instruction execution steps – control unit synthesis – microprogramming – pipelining – pipeline performance

UNIT IV – MEMORY SYSTEM

Main Memory concepts – types of memory – cache memory organization – secondary storage –virtual memory – paging

UNIT V – I/O AND INTERFACES

I/O devices – I/O programming – polling – interrupts – DMA – buses – links – interfacing – context switching – threads

and multithreading

TEXT BOOKS

1. B. Parhami, “Computer Architecture”, Oxford University Press, 2005.

2. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, “Computer Organization”, Fifth Edition, Tata McGraw Hill, 2002

NOTE: PLEASE REFER THE TEXT BOOKS FOR PERFECTNESS OF THE ANSWERS.

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ANAND INSTITUTE OF HIGHER TECHNOLOGY Chennai-603 103 DEPARTMENT OF ELECTRONICS AND INSTRUMENTATION ENGINEERING

CS2071 COMPUTER ARCHITECTURE – Question Bank

Faculty: C.MAGESHKUMAR Date: 15.07.2013

UNIT I – INSTRUCTION SET ARCHITECTURE CLASS: FINAL EIE A&B

PART A – (2 Marks)

1. Define Computer Architecture.

Computer Architecture is an area of study that deals with the computer at the interface between hardware and

software.

Computer Architecture deals with the structure and behavior of a computer including the information formats.

Computer Architecture encompasses a set of ideas that are applicable to design or understand any computer

virtually from tiniest embedded microprocessors to most powerful supercomputers

2. List out the reasons to study computer architecture.

The purposes of studying architecture are

To gain knowledge about designing / building a new computer

To gain knowledge about designing / building a new version of computer

To improve software performance

To find solution with embedded computer system

To purchase a new computer

3. What is computer organization?

Computer organization deals with operational units and interconnections that realize computer architectural

specifications.

Architectural specifications refers to control signal, interface between computers, interface between CPU,

memory, input/output peripherals.

Microarchitecture, also known as Computer organization is a lower level, a detailed description of the system

that is sufficient for completely describing the operation of all parts of the computing system, and how they are

inter-connected and inter-operate in order to implement the ISA.

4. Define abstraction:

Abstraction is a process by which data and program are defined with a representation similar in form to its

meaning.

5. Define word

In computer architecture, word can be defined as a 32-bit data element stored in a register or memory location

with an address.

A word is a unit of data of a defined bit length (32 bit in miniMIPS) that can be addressed and moved between

storage and the computer processor.

6. Define word length

Word length is defined as the total number of bits used to represent. In general 1 word equals 32 bits.

Usually, the defined bit length of a word is equivalent to the width of the computer's data bus so that a word can

be moved in a single operation from storage to a processor register.

For any computer architecture with an eight-bit byte, the word will be some multiple of eight bits.

7. Define addressing modes. (EIE Nov’11)

Addressing mode is the method by which location of an operand is specified within an instruction.

The way in which the location of an operand is specified in an instruction.

A method used to specify where operands are to be found and where result must go.

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8. What are the addressing modes in MiniMIPS?

MiniMIPS uses six addressing modes as follows:

1. Implied addressing mode

2. Immediate addressing mode

3. Register addressing mode

4. Base addressing

5. PC-Relative addressing.

6. Pseudo direct addressing.

9. Give an example each of zero-address, one-address, two-address, and three address instructions.

The examples are as follows:

1. zero-address instruction – syscall –(control transfer)

2. One –address instruction-jump instructions

Syntax: j verify

where verify-holds the address of a procedure

3. Two –address instructions -mult, div, addi

Syntax: mult $s0,$s1

4. Three address instructions – add,sub,and,or

Syntax: add $t0, $s0,$s1

10. What is operand? (CS May’11)

In computer programming languages, the definitions of operator and operand are almost the same.

In computing, an operand is the part of a computer instruction which specifies what data is to be manipulated or

operated on, whilst at the same time representing the data itself.

In assembly language, an operand is a value (an argument) on which the instruction, named by mnemonic,

operates. The operand may be a processor register, a memory address, a literal constant, or a label.

11. What is an opcode? How many bits are needed to specify 32 distinct operations? (CS May’11)

An opcode (operational code) is a binary code or bit pattern that defines an operation.

An opcode (operation code) is the portion of a machine language instruction that specifies the operation to

be performed.

Example: opcode for Addition operation is 32 100010 in binary

5 bits are needed to specify an opcode in 32 bit instruction,distinct operations

12. What is a Procedure?

A procedure is a subprogram that when called or initiated performs a specific task, leading to one or more results,

based on the input parameters (arguments) with which it is provided and returns to the point of call.

Instruction: jal proc

Opcode for jal instruction = 3 (000011)

13. What are the functions of program counter (PC)?

To monitor the sequence of instruction execution

To store the address of next instruction to be executed

14. What is the difference between Pseudoinstructions & Macroinstructions?

Pseudoinstructions are incorporated in the design of assembler and are thus fixed for the user but macros are user

defined.

Pseudo instructions looks exactly like an instruction, but macro looks more like a procedure in a high level

language.

15. Write down the instructions to push a value onto stack.

A new data in register $t4 can be pushed onto stack by the following statements:

addi $sp, $sp,-4

sw $t4,0($sp)

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16. Write down the instructions to pop a value from the stack.

The top element from the stack is copied into register $t5 by the following instructions:

lw $t5, 0($sp)

addi $

17. What is the function of linker?

Ensuring correct interpretation (resolution) of labels in all modules

Determining the placement of text and data segments in memory

Evaluating all data addresses and instruction labels.

Forming an executable program with no unresolved references.

18. What is the function of loader?

Determining the memory needs of the program from its header.

Copying text and data from the executable program file into memory.

Modifying / shifting addresses, where needed during copying.

Placing program parameters onto stack.

Initializing all machine registers, including stack pointer

Jumping to a startup routine that calls the main routine.

19. What are the instruction set attributes?

1. Consistency

2. Orthogonality

3. Transparency

4. Ease of learning

5. Extensibility

6. Efficiency

20. What are the features of RISC architecture?

Small set of instructions, each of which can be executed in approximately same amount of time.

Load/Store architecture

Limited addressing modes that eliminate or speed up address calculations.

Simple, uniform instruction formats that facilitate extraction/decoding of various fields and allow overlap

between opcode interpretation and register readout.

21. What are the advantages of CISC architecture?

Economy in the number of instructions used translates to smaller storage space requirements, fewer memory

accesses and more effective use of cache space.

Closer correspondence between machine instructions and operations commonly found in high level languages

facilitate program compilation, understanding, troubleshooting and modification.

22.List out the methods used to improve system performance.

The methods used to improve system performance are

1. Processor clock

2. Basic Performance Equation

3. Pipelining

4. Clock rate

5. Instruction set

6. Compiler

23. What is Byte Addressability?

Byte Addressability is used for assigning successive memory address to successive memory location. This type of

assigning is used in modern computers.

One byte=8 bits.

Ex:32bits Address:0,4,8....

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24. What is meant by Bid-Endian and Little Endian?

1. The name big-Endian is used when lower byte addresses are used for the most significant bytes (the left

most bytes) of the word. (most significant byte has lowest address)

2. The name little-Endian is used when lower byte addresses are used for the less significant bytes (the right

most bytes) of the word. (Least significant byte has lowest address)

25. What are the steps in transforming an assembly language program to an executable program residing in memory?

26. What are the available instruction formats in miniMIPS?

1. Register (R)

2. Immediate (I)

3. Jump (J)

Note: for q. no. 27, 28, and 29

Give the number of fields,

Give the number of bits in each field and its usuage

27. Write notes on register instruction format.

Example: ADD $t0,$s0,$s1 - t0=s0+s1

28. Write notes on immediate instruction format.

Example: ADD $t0,$s0,91 - t0=s0+91

5 bits 5 bits

31 25 20 15 0

Opcode Source register 1

Source register 2

op rs rt

R 6 bits 5 bits

rd

5 bits

sh

6 bits

10 5 fn

Destination register

Shift amount

Opcode extension

Linker Loader

Executable machine language program

Memory content

Library routines (machine language)

Co

mp

iler

Asse

mb

ler

Inte

rpre

ter

temp=v[i] v[i]=v[i+1] v[i+1]=temp

Swap v[i] and v[i+1]

add $2,$5,$5 add $2,$2,$2 add $2,$4,$2 lw $15,0($2) lw $16,4($2) sw $16,0($2) sw $15,4($2) jr $31

00a51020 00421020 00821020 8c620000 8cf20004 acf20000 ac620004 03e00008

Very high-level language objectives or tasks

High-level language statements

Assembly language instructions, mnemonic

Machine language instructions, binary (hex)

One task = many statements

One statement = several instructions

Mostly one-to-one

More abstract, machine-independent; easier to write, read, debug, or maintain

More concrete, machine-specific, error-prone; harder to write, read, debug, or maintain

Immediate operand or address offset

31 25 20 15 0

Opcode Destination or data

Source or base

op rs rt operand / offset

I 5 bits 6 bits 16 bits 5 bits

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29. Write notes on Jump instruction format.

Example: J EIE - goto memory location named “EIE”

30. Short notes on Pseudoinstructions.

Psudoinstructions allow us to formulate computations and decisions in alternative forms that are not directly

supported by hardware .

MiniMIPS assembler takes care of translating these alternative forms to basic form that is supported by existing

hardware instruction (hardware supported instruction).

Pseudoinstruction are predefined, fixed, and look like machine instructions

31. Short notes on Macroinstructions.

A macroinstructions (macro) is a mechanism to give a name to an often-used sequence of instructions (shorthand

notation) to avoid having a specify sequence in full each time.

Macros are user-defined and resemble procedures (have arguments – input parameters)

32. How is a macro different from a procedure?

Control is transferred to and returns from a procedure

After a macro has been replaced, no trace of it remains.

33. What are the different data types?

In miniMIPS, there are 3 datasize as follows,

1. Byte –8 bits

2. Word – 4 bytes (32 bits)

3. Double word – 8 bytes (64 bits)

Example:

Type 8-bit number Value 32-bit version of the number

Unsigned 0010 1011 43 0000 0000 0000 0000 0000 0000 0010 1011

Unsigned 1010 1011 171 0000 0000 0000 0000 0000 0000 1010 1011

Signed 0010 1011 +43 0000 0000 0000 0000 0000 0000 0010 1011

Signed 1010 1011 –85 1111 1111 1111 1111 1111 1111 1010 1011

34. Define Instruction set/ Define Instruction.

Instruction is a word/ language easily interpreted by machine/hardware

Instructions are the language of the machine

An instruction set, or instruction set architecture (ISA), is the part of the computer architecture related to

programming, including the native data types, instructions, registers, addressing modes, memory

architecture, interrupt and exception handling, and external I/O.

An ISA includes a specification of the set of opcodes (machine language), and the native commands

implemented by a particular processor.

S.no. Data types Datasize

1 Signed integer byte word -

2 Unsigned integer byte word -

3 Floating point number - word doubleword

4 Bit string byte word doubleword

0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0

31 0

Opcode

op jump target address

J

Memory word address (byte address divided by 4)

26 bits

25

6 bits

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35. Classify instruction sets.

A complex instruction set computer (CISC) has many specialized instructions, which may only be rarely

used in practical programs.

A reduced instruction set computer (RISC) simplifies the processor by only implementing instructions that

are frequently used in programs; unusual operations are implemented as subroutines, where the extra processor

execution time is offset by their rare use.

Theoretically important types are the minimal instruction set computer (MISC) and the one instruction set

computer (IISC) but these are not implemented in commercial processors.

Another variation is the very long instruction word (VLIW) where the processor receives many instructions

encoded and retrieved in one instruction word.

36. Classify instruction types.

Computer must have instructions capable of performing four types of operations

1. Data transfer between memory and processor

2. Arithmetic and logic operations

3. Program sequencing and control

4. Input / output transfer

37. Draw the flow of instruction cycle. (EIE Nov’11)

38. What are the Digital Computer Subsystems? or What are the major components of computer architecture? (EIE Dec 2012)

39. Define stack and stack pointer.

Stack is a list of data element usually words or bytes with accessing restriction that the data elements can

be added or removed at only one end of the list only.

Stack pointer is a register used to hold the address of the stack.

Stack pointer is denoted by $SP in MIPS register

Memory

Link Input/Output

To/from network

Processor

Control

Datapath

Input

Output

CPU I/O

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40. Brief note on MIPS registers.

In MIPS, the operands must be registers.

• 32 registers are provided

• each register stores a 32-bit value

• compilers associate variables with registers

• registers are referred to by names such as $s0 and $t1

• we use the “s” registers for values that correspond to variables in our programs

• we use the “t” registers for temporary values

For example, consider this example from the text:

f = (g + h) - (i + j);

We choose registers to store the values of our variables: f in $s0, g in $s1, h in $s2, i in $s3, and j in $s4.

We’ll also need to store temporary values, which we will store in $t0 and $t1.

The MIPS code:

add $t0, $s1, $s2

add $t1, $s3, $s4

sub $s0, $t0, $t1

41. Short notes on Jump Instruction.

Jump instruction causes the program execution to proceed to the location whose address is provided instead of

continuing with next instruction in sequence.

Example: j eie

Jump instruction follows jump (J) instruction format

42. What is assembly language?

Assembly language is a low level language in which there is a very strong one-to-one correspondence between

language and computer architecture’s machine code instruction.

Example: add $to, $s8, $s5

addi $t1, $s7, 43

43. Mention the advantage of assembly language.

Extreme efficiency

An assembly language program uses up much less memory

Runs much faster.

44. How is a floating number represented? Give one example.

In computing, floating point describes a method of representing an approximation of a real number in a

way that can support a wide range of values. The numbers are, in general, represented approximately to a

fixed number of significant digits (the mantissa) and scaled using an exponent. The base for the scaling is

normally 2, 10 or 16.

The typical number that can be represented exactly is of the form:

Significant digits × baseexponent

Example: 152853.5047 = 1.528535047×105

0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0

31 0

Opcode

op jump target address

J

Memory word address (byte address divided by 4)

26 bits

25

6 bits

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PART B

1. Discuss about instructions formats, instruction and addressing modes (16). (EIE Dec 2011)

2. What are the types of basic instruction formats? Explain each type with an example. (CS Nov’10)

3. Explain the Data transfer, Logic and Program Control Instructions with examples? (16) (EIE Dec’ 2009)

4. Define addressing mode and describe in detail the different addressing mode with an example(8).(May’08)

5. Describe the addressing modes and instructions designed for control flow (10)

6. Explain the following: (EIE Dec 2011, EEE Dec 2010)

(i) Procedures and data. (8)

(ii) Instruction set. (8)

7. What is the difference between register addressing and direct addressing? Is it possible to combine register addressing

and directing addressing? Explain.

8. What are the steps in transforming an assembly language program to an executable program residing in memory?

Explain in detail.

9. List the various addressing modes with example. Give the importance of each in detail. (EIE Dec 2012)

10. How do you classify the instruction set of a processor? Explain usage of each classification with a suitable example.

(EIE Dec 2012)

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ANAND INSTITUTE OF HIGHER TECHNOLOGYChennai-603 103 DEPARTMENT OF ELECTRONICS AND INSTRUMENTATION ENGINEERING


Faculty Name: C.MAGESHKUMAR Date: 15.07.2013

UNIT II – ARITHMETIC LOGIC UNIT CLASS: FINAL EIE A&B


1. Draw a half adder circuit. (EIE Dec 2012)

2. Write the logic equations of a binary half adder. (CS May’11)

4. State the purpose of binary adder. (EIE Nov’11)

A device that could add two binary bits together. Such a device is known as a half-adder. In this sense, digital

arithmetic circuits aren't much different from analog arithmetic (operational amplifier) circuits: they do exactly what

they're wired to do, no more and no less. We are not, however, restricted to designing digital computer circuits in this

manner. It is possible to embed the mathematical "rules" for any arithmetic operation in the form of digital data

rather than in hard-wired connections between gates. The result is unparalleled flexibility in operation, giving rise to

a whole new kind of digital device: the programmable computer.

5. Write down the equation for carry generate and propagate.

The auxiliary binary signal carry generate (gi) as being 1 for the positions at which carry is generated and 0

elsewhere. gi is the logical and of xi and yi.

The auxiliary binary signal carry propagate (pi) is defined as being 1 iff digit position i propagates an

incoming carry.

Carry generate equation: gi=xi. yi

propagate equation: pi=xi xor yi

6. Define a multiplier. (EIE Nov’11)

A binary multiplier is an electronic circuit used in digital electronics, such as a computer, to multiply

two binary numbers.

It is built using binary adders. A variety of computer arithmetic techniques can be used to implement

a digital multiplier. Most techniques involve computing a set of partial products, and then summing

the partial products together.

In binary encoding each long number is multiplied by one digit (either 0 or 1), and that is much

easier than in decimal, as the product by 0 or 1 is just 0 or the same number.

Therefore, the multiplication of two binary numbers comes down to calculating partial products

(which are 0 or the first number), shifting them left, and then adding them together

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7. What is a carry look-ahead adder? (ECE Nov’11)

A carry-lookahead adder (CLA) is a type of adder used in digital logic. A carry-lookahead adder improves

speed by reducing the amount of time required to determine carry bits.

It can be contrasted with the simpler, but usually slower, ripple carry adder for which the carry bit is

calculated alongside the sum bit, and each bit must wait until the previous carry has been calculated to begin

calculating its own result and carry bits (see adder for detail on ripple carry adders).

The carry-lookahead adder calculates one or more carry bits before the sum, which reduces the wait time to

calculate the result of the larger value bits.

The Kogge-Stone adder and Brent-Kung adder are examples of this type of adder.

8. What is meant by underflow and overflow? (ECE Nov’11)

Overflow:

In the single precision, if the number requires a exponent greater then +127 or in a double precision,

if the number requires an exponent form the overflow occurs.

Underflow:

In a single precision ,if the number requires an exponent less than -26 or in a double presition,if the

number requires an exponent less than -1022 to represent its normalized form the underflow occurs.

9. Define priority encoder. (EC Nov’11)

A priority encoder is a circuit or algorithm that compresses multiple binary inputs into a smaller number of

outputs. The output of a priority encoder is the binary representation of the ordinal number starting from zero

of the most significant input bit.

They are often used to control interrupt requests by acting on the highest priority.

If two or more inputs are given at the same time, the input having the highest priority will take precedence.

An example of a single bit 4 to 2 encoder is shown, where highest-priority inputs are to the left and "x"

indicates an irrelevant value - i.e. any input value there yields the same output since it is superseded by

higher-priority input. The output V indicates if the input is valid.

10. Draw the full adder circuit using two half adders.

11. List out rules for Booth recoded multiplier?

1. Start from LSB check each bit one by one.

2. Change the first one as -1.

3. Skip all succeeding ones (record them as zero‟s) until you see a zero, Change this zero as one.

12. List out the rules for mul /div of floating point number?

Multiply rule:

1. Add the exponent and subtract 127,

2. Multiply the mantissa and determine the sign of the result.

http://en.wikipedia.org/wiki/Electronic_circuit

http://en.wikipedia.org/wiki/Algorithm

http://en.wikipedia.org/wiki/Binary_code

http://en.wikipedia.org/wiki/Interrupt_request

http://en.wiktionary.org/wiki/precedence

http://en.wikipedia.org/wiki/Encoder

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3. Normalise the resulting value, if necessary.

Divide rule:

1. Subtract the exponents and add 127,

2. Divide the mantissa and determine the sign of the result,

3. Normalise the resulting value, if necessary.

13. What is the principle of booth multiplication? PLEASE REFER Xerox, class notes, BOOK

Booth multiplication is nothing but addition of properly shifted multiplicand patterns. It is carried out by

following steps:

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14. List the two techniques used for speeding up the multiplication process:

The two techniques used for spreading up the multiplication process are

1)Bit pair recording or modified Booth algorithm

2)Carry save addition of summands.

15. Define n-bit ripple-carry adder.

A cascaded connection of n full adder blocks can be used to add two n-bit numbers. Since the carries must

propagate or ripple, through the cascade, the configuration is called n b-bit ripple carry adder.

16. List out the rules for add/sub of floating point number?

1. Choose the number with the smaller exponent and shift its mantissa right a number of steps equal to the

difference in exponents.

2. Set the exponent of the result equal to the larger exponent.

3. Perform addition /subtraction on the mantissa and determine the sign of the result.

4. Normalize the resulting value, if necessary.

17. Short notes on counter.

18. Short notes on increamenter.

19. Write down the equation for design of fast adders

20. What are the logic and shift operation instruction in ALU.

21. What is shift-add multiplication?

22. Significance of hardware multiplier.

23. Programmed multiplication?

24. What is shift-subtract division?

25. Significance of hardware dividers.

26. Programmed Division.

27. What is called rounding?

28. Draw distribution of floating point numbers on real line.

29. What are the 3 directed rounding modes?

30. Give an example for floating point addition.

31. Give an example for floating point multiplication.

32. Give an example for floating point division.

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Part B

1. Explain floating point adder unit and explain the process addition with a flow chart. (16) (EIE dec 2012)

2. A) starting from truth table explain how to construct a full added (8) (EIE dec 2012)

B) What is ripple carry added? Mention the disadvantage and explain how it is resolved.(8)

3. Design a 4 bit Carry look ahead adder and explain its operation with an example. (EIE dec 2012, EIE dec 2011)

4. Explain 2’s complement multiplier with a neat block diagram. (16) (EC Nov’11)

5. Explain floating point adder pipeline with neat block diagram. (16) (EIE dec 2011, EC Nov’11)

6. Write notes on the following: (CS Nov’10)

a) Fixed and Floating point representation,

b) 2's compliment addition and subtraction, and

c) Decimal fixed-point representation.

7. Draw the block diagram of a 4 bit register level magnitude comparator and explain. (EC Nov’11)

8. Design a binary multiplier using sequential adder. Explain its operation.(CS Nov’10)

9. Draw the circuit for integer division and explain.(CS Nov’10)

10. What is a priority encoder? Design a 16-bit priority encoder using two copies of an 8-bit priority encoder. (6)

11. What are floating point instructions. Explain in detail.

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UNIT III DATA PATH AND CONTROL CLASS: FINAL EIE A&B


1. What are the advantages of pipelining? (EIE Dec 2012)

To increase the performance of instruction execution

Data forwarding

Branch prediction

2. State the function of control unit. (EIE Nov’11)

The control unit coordinates the components of a computer system. It fetches the code of all of the

instructions in the program. It directs the operation of the other units by providing timing and control

signals.

All computer resources are managed by the CU. It directs the flow of data between the Central Processing

Unit (CPU) and the other devices.

The control unit is the circuitry that controls the flow of data through the processor, and coordinates the

activities of the other units within it.

The control unit receives external instructions or commands which it converts into a sequence of control

signals that the control unit applies to the data path to implement a sequence of register-transfer level

operations.

3. What is pipelining. (EIE Nov’11)

Pipelining is an implementation technique where multiple instructions are overlapped in execution. The

computer pipeline is divided in stages.

Each stage completes a part of an instruction in parallel. The stages are connected one to the next to form a

pipe - instructions enter at one end, progress through the stages, and exit at the other end.

Pipelining does not decrease the time for individual instruction execution. Instead, it increases instruction

throughput.

The throughput of the instruction pipeline is determined by how often an instruction exits the pipeline.

4. What is microinstruction and what factors determines the length of the microinstructions? (ECE Nov’11)

A single instruction in microcode. It is the most elementary instruction in the computer, such as moving the

contents of a register to the arithmetic logic unit (ALU).

It takes several microinstructions to carry out one complex machine instruction (CISC).

Also called a "micro-op" or "µop," microinstructions differ within the same computer family and even the

same vendor.

For example, although all are x86 chips, the microcode for Intel's Pentium 4, Pentium M and AMD's Athlon

are not the same

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5. Differentiate between hardwired and micro-programmed control unit. (ECE Nov’11)

Hardwired control is a control mechanism to generate control signals by using appropriate finite state

machine.

Microprogrammed control is a control mechanism to generate control signals by using a memory called

control storage (CS), which contains the control signals.

Although microprogrammed control seems to be advantageous to CISC machines, since CISC requires

systematic development of sophisticated control signals, there is no intrinsic difference between these 2

control mechanism.

The pair of "microinstruction-register" and "control storage address register" can be regarded as a "state

register" for the hardwired control.

6. Define Pipeline Hazards?

The pipeline architectures works smoothly as long as it is able to take up new task in every machine cycle. In

practice there are situation when the next instruction can be executed in the following machine cycle. These events

called as pipeline hazards.

7. What are the major hazards occur in pipelining? or What are the major hurdle occur in pipelining?

Types of Hazards:

a) Structural Hazards (Resource Bound)

b) Control Hazards ( Pipelining Bubbles)

c) Data Hazards ( Data dependencies)

8. What is Structural Hazards:

During the pipelining, the overlapped execution of instructions requires pipelining of functional units and

duplication of resources to allow all possible combinations of instructions in the pipeline. If some combination of

instructions cannot be accommodated because of a resource conflict, the machine is said to have a structural hazard.

This type of hazards occurs when two activities require the same resource simultaneously.

9. What is Control Hazard:

This type of hazard is caused by uncertainty of execution path, branch taken or not taken.

It is a hazard that arises when an attempt is made to make a decision before condition is evaluated.It results when

we branch to a new location in the program, invalidating everything we have loaded in our pipeline.

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10. What is Data Hazards:

Data hazards occur when the pipeline changes the order of read/write accesses to operands so that the order

differs from the order seen by sequentially executing instructions on the unpipelined machine. Data hazards are also

known as data dependency. Data dependency is the condition in which the outcome of the current operation is

dependent on the outcome of a previous instruction that has not yet been executed to completion because of the

effect of the pipeline.

11. What is pipelining?

A pipelining may be visualized as a collection of segments called pipe stages through which binary information

flows. Each segment performs partial processing as dictated by the task. The result obtained in each segment is

transferred to the next segment in the pipeline. The final result is obtained after the data passes through all the

segments.

12. Explain latency and throughput.

Latency : Each Instruction takes certain amount of time to complete. This is called as latency. It is the time

differences when an instruction is issued and when it is completed.

Throughput : The number of instructions completed in a given time is called Throughput.

13. What are the major characteristics of a pipeline?

1. Pipelining cannot be implemented in a single task. As it works by splitting multiple task into a number of

subtask and operating on them simultaneously.

2. The speedup or efficicenty is achieved by using the pipelining depends on the number of pipe stages and

the number of available task that can be subdivide.

14. what is instruction pipeline?

The type of pipeline which works by partitioning the instruction execution.

15. What are the various stages in a pipeling execution.

Instruction Fetch

Instruction Decode

Operand fetch

Opcode Execution

Write back

16. What is superscalar processor?

Super scalar processor exploits parallelism which has Multiple E_ Unit each of which is pipelined and it

constitutes independent Instruction pipeline.

The processor has PCU designed to fetch and decode several instructions concurrently which is issued to

pipeline E_Units that Executes several instruction is the same.

17. What do you mean by out-of order execution? Is it Desirable?

In a pipelined processor with several instructions is process concurrently it is Possible for instruction to

finish out of sequence, one instruction finishes before Another which is issued earlier. as for as main computation is

concerned no Hazards will happen but if an interrupts occurs it creates the problem.

17


18. What are Hazards?

A hazard is also called as hurdle .The situation that prevents the next instruction in the instruction stream

from executing during its designated Clock cycle. Stall is introduced by hazard. (Ideal stage)

19. List out Various branching technique used in micro program control unit?

a) Bit-Oring

b) Using Conditional Variable

c) Wide Branch Addressing

20. Compare hardwired control unit and microprogrammed control unit

hardwired control unit microprogrammed control unit

Attitude Hardwired Control Micro Programmed control

Speed Fast Slow

Control function Implemented in hardware

Implemented is software

Flexibility

Not flexible, to accommodated new

system specifications or new

instructions.

More flexible, to accommodate new system

specifications or new instructions redesign is required.

Ability to handle

large complex

instruction set

difficult Easier

Ability to

support.

Very difficult Easy

Design process Somewhat complicated Orderly and Systematic

Instruction size Usually under 100 instructions Usually over 100 instructions.

Chip area

Efficiency

Uses least area Uses more Area

Applications Mostly RISI Micro processor Mainframes, Some Micro Processors

21. What is micro programming and micro programmed control unit?

Microprogramming is a method of control unit design in which the control unit selection and sequencing

information are stored in ROM and RAM‟s called control store or control memory.Micro programmed control unit

is a general approach used for implementation of control unit. Here control signals are generated by a program

similar to machine language programs

22. What is meant by hardwired control?

It is the one that contains control units that use fixed logic circuits to interpret instructions and generate

control signals from them. Here, the fixed logic circuit block includes combinational circuit that generates the

required control outputs for decoding and encoding functions.

23. What is the necessity of grouping signals?

It is used to reduce the number of the bits in the microinstruction.

It is used to overcome the drawback of assigning individual bits to each control signal results in long

microinstructions, because the number of the required signals is usually large,moreoveronly a few bits are used in

any given instruction.

18


24. List the techniques used for grouping of the control signals?

a) Vertical organization

b) Horizontal organization

25. Define Job Sequencing.

It is a process of scheduling task that are awaiting initiation in order to avoid collision and achieve high

throughput.

26. Write control signals for storing a word in memory.

R1out ,

MARin R2out ,

MDRin ,write

MDRout E ,

WMFC

27. What are the problems faced in Instruction Pipeline.

1. Resources Confilicts

2. Data Dependency

3. Branch Difficulties

28. What is Register Renaming?

If a temporary register assumes the role of the permanent register whose data it is holding and is given the

same name is called as the Register Renaming

29. How data hazard can be prevented in pipelining?

Data hazards in the instruction pipelining can prevented by the following techniques.

Operand Forwarding

Software Approach

30. Explain the various approaches used to deal with Conditional pipelining?

* A condition branch instruction introduces the added hazard caused by the dependency of branch condition

on result of a preceding instruction.

* Branching instruction represent about 20 percent of the dynamic interaction count of most programs.

* The dynamic count is the number of instruction execution, taking into account the that same program

instruction are executed many times because of loops. These branching junctions can le handled by following

ways,

1. Delayed branch.

2. Branch prediction.

3. Dynamic branch prediction

31. What are the five categories of instruction? Page no.245

32. What the common execution sequence of R-format ALU instructions? Page no.245

33. What are the blocks associated with single cycle data-path? Page no.251

34. Draw the instruction decoder of single cycle datapath. Page no.252

35. Performance of single cycle datapath. Page no.253

36. Short notes on multicycle implementation.

37. What are the blocks associated with multicycle datapath? Page no.262

19


38. Control state machine? Page no.264

39. Draw the instruction decoders of multicycle MicroMIPS. Page no.265

40. Performance of multicycle design.

41. What is microprogramming?

42. What are microinstruction and microorder?

43. Give the format of microinstruction.

44. What are the strategies to achieve greater performance? Page no.278

45. What are the factors that degrade the instruction execution throughput? Page no.280

46. What are the 2 types of data dependency for MicroMIPS pipeline? Page no.281

47. What do you mean by bubble insertion? Page no.281

48. What is control dependency? Page no.282

49. Write down the equation of throughput increase with dependencies. Page no.285

50. What are the 5 pipeline stages? Page no.286

51. Data forwarding? Page no.300

52. Branch prediction? Page no.304

53. Draw the hardware elements for branch prediction scheme. Page no.305

54. What are the 2 forms of hardware implementation of instruction retirement and commit. Page no.310

20


Part B

1. Draw schematic diagram of micro programmed control unit and explain its functioning. Compare it with

hardwired control unit (EIE dec 2012) (EC Nov’11)

2. List out all pipeline hazards. Explain any one hazard with suitable example (EIE dec 2012)

3. Explain the following: (EIE dec 2011)

i. Control unit synthesis. (8)

ii. Microprogramming. (8)

4. Discuss the instruction execution steps with suitable illustrations. (16) (EIE dec 2011)

5. Describe various factors that reduce the performance of pipelined CPU and the mechanisms used to overcome

it.

6. Design a micro programmed control unit of non-pipelined general purpose computers.

7. Discuss the data and control path methods in pipelining.

8. Explain micro programmed control unit. What are the advantages and disadvantages of it.

9. Design a 4-stage instruction pipeline and show how its performance is improved over sequential execution.

10. (i) Describe the role of cache memory in pipelined system. (8)

11. (ii) Discuss the influence of pipelining on instruction set design. (8)

12. Write short notes on: Data Forwarding and Branch Prediction (16)

21


ANAND INSTITUTE OF HIGHER TECHNOLOGY Chennai-603 103 DEPARTMENT OF ELECTRONICS AND INSTRUMENTATION ENGINEERING


Faculty: C.MAGESHKUMAR Date: 15.07.2013

UNIT IV – MEMORY SYSTEM CLASS: FINAL EIE A&B


1. List any three characteristics of memory device. (EIE dec 2012)

volatility,

mutability,

Storage capacity (S).

Cost

Access time (accessibility)

Access modes (addressability.)

2. Compare main memory and secondary memory. (EIE dec 2012)

Main memory

Memory is that part of the computer, which holds data and instructions for processing. Logically, it is an

integral component of the CPU, but physically it is a separate part placed on the computer's motherboard.

Memory stores program instructions or data for only as long as the program they pertain to is in

operation. The CPU accesses the main memory in a random manner, that is, the CPU can access any

location of this memory to either read information from it or store information in it.

The primary memory is of two types: random access memory (RAM) and read only memory (ROM).

Secondary memory

Secondary memory is a non-volatile form of memory that is connected to the motherboard, but is not part

of it.

Secondary memory is slower than primary memory because it is located further away from the CPU.

There are many forms of secondary memory that can be used for long term storage, backup or transfer of

data including:

Hard Drives (direct access) Hard Drives are the most common form of secondary memory and are used

to locally store and copy data.

Tapes (sequential access) Tapes are used in the industry to backup very large amounts of data

CD (direct access) CDs are used to Transfer music, data and are used sometimes for the backup of files.

Flash Memory (direct access) Flash Memory which includes SSDs, SD Cards, USB Sticks, which are

used to transfer data form one computer to another, or store files on Cameras or MP3 Players.

3. What is cache memory? (EIE Nov’11)

The small and fast RAM units are called as caches. When the execution of an instruction calls for data

located in the main memory, the data are fetched and a copy is placed in the cache. Later if the same data

is required it is read directly from the cache.

Memory word are stored in cache data memory and are grouped into small pages called cache blocks or

line. The contents of the cache’s data memory are thus copies of a set of main memory blocks.

22


4. What is byte addressable memory? (EIE Nov’11)

The assignment of successive addresses to successive byte locations in the memory is called byte

addressable memory.

5. Compare SRAM with DRAM. (Nov’11)

SRAM is static while DRAM is dynamic

SRAM is faster compared to DRAM

SRAM consumes less power than DRAM

SRAM uses more transistors per bit of memory compared to DRAM

SRAM is more expensive than DRAM

Cheaper DRAM is used in main memory while SRAM is commonly used in cache memory

6. Give the features of ROM cell. (May’08)

Read-only memory (ROM) is a class of storage medium used in computers and other electronic devices.

Data stored in ROM cannot be modified, or can be modified only slowly or with difficulty, so it is mainly

used to distribute firmware

ROM refers only to mask ROM (the oldest type of solid state ROM), which is fabricated with the desired

data permanently stored in it, and thus can never be modified.

Despite the simplicity, speed and economies of scale of mask ROM, field-programmability often make

reprogrammable memories more flexible and inexpensive

7. What is memory system?

Every Computer contains several types of devices to store the instructions and data for its operation. These

storage devices plus the algorithm implements by hardware and software needed to manage the stored information

from the memory system of computer.

8. Give the classification of memory

a. CPU Register

b. Main memory

c. Secondary Memory

d. Cache.

9. Define Static Memories and Dynamic Memories.

Memories that consist of circuits‟ capable of retaining their state as long as power is applied are known‟s

static memories. In Dynamic Memories such cells do not retain their state indefinitely.

10. What is read access time?

A basic performance measure is the average time to read a fixed amount of information for instance, one

word from the memory. This parameter is called the read access time.

11. Define RAM

Basically they are array of storage cells (location) that can be accessed in any order and access time is

independent of the location being accessed, the memory is termed as random access memory.

12. What is ROM?

Memories whose content cannot be altered online if they can be altered at all are read only memories.

23


13. What are PROMs?

Semiconductor ROMs whose contents can be changed offline-with some difficulties is called PROMs.

A programmable combinational part can do the job of many gates or gate networks.

To avoid having to use large number of small-scale integrated circuits for implementing Boolean

function of several variables.

Programmed by cutting existing connections (fuses) or establishing new connections (antifuses)

14. What is SRAM AND DRAM?

SRAM: Static randam access memory. It tends to be faster. They require no refreshing

DRAM: Dynamic random access memory. Data is stored in the form of charges. So continuous refreshing is needed.

15. What is volatile memory?

A memory is volatile if the loss of power destroys the stored information. Information can be stored indefinitely in a

volatile memory by providing battery backup or other means to maintain a continuous supply of power.

17. What is flash memory?

A recent semiconductor technology called flash memory of a same non-volatility as a PROM, but it can be

done a bit at a time.

18. Mention two system organizations for caches.

Two system organizations for caches are a. look aside and b. look through

19. What is RAMBUS memory?

The key feature of Rambus technology is a fast signaling method used to transfer information between chip using

narrow bus.

21. Give the difference between EEPROM and Flash memory?

The primary difference between EEPROM and flash memory is that flash restricts writes to multiple

kilobytes blocks, increasing the memory capacity per chip by reducing area of control.

22. Differences between cache memory and virtual memery

1. In caches, replacement is primarily controlled by the hardware. In VM, replacement is primarily controlled

by the OS.

2. The Number of bits in the address determines the size of VM, where as cache size is independent of the

address size.

3. But there is only one class of cache.

23. Uses of Virtual Memory.

Protection: VM is often used to protect one program from others in the system

Base and Bounds: this method allows relocation. User processes cannot be allowed to change these registers,

but the OS must be able to do so on a process switch.

24. Interleaved Memory.

Banks of memory are often one word wide , so bus width need not be changed to access memory. However

several independent areas of memory can be accessed simultaneously by using interleaved memory.

24


25. What is write back protocol?

In this scheme, only the block in cache is modified. The main memory when the block must be replaces in

the cache. This requires the use of a dirty bit to keep track of blocks, that have been modified.

26. What is the maximum size of the memory that can be used in a 16-bit computer and 32 bit computer?

The maximum size of the memory that can be used in a 16-bit computer is 2 16=64K memory locations.

The maximum size of the memory that can be used in a 32-bit computer is 2 32=4 G memory locations.

27. Define memory access time?

The time required to access one word is called the memory access time. (Or) It is the time that elapses

between the initiation of an operation and the completion of that operation.

28. Define memory cycle time?

It is the minimum time delay required between the initiations of two successive memory operations.

Eg. The time between two successive read operations.

29. When is a memory unit called as RAM?

A memory unit is called as RAM if any location can be accessed for a read or write operation in some fixed

amount of time that is independent of the location’s address.

30. What is MMU?

MMU is the Memory Management Unit. It is a special memory control circuit used for implementing the

mapping of the virtual address space onto the physical memory.

32. Define memory and memory cell.

Memory refers to a physical device used to store programs or data on a temporary or permanent basis for use

in a computer or other electronic device.

A memory cell is capable of storing one bit of information. It is usually organized in the form of an array.

Other important questions:

1. Give the features of a ROM cell (APRIL/MAY 2008)

2. Define Locality of Reference. (NOV/DEC 2009)&(APRIL/ MAY 2008)

3. What is Translation Look aside Buffer? (MAY/JUNE 2006)

4. Define memory access time.

5. Define memory cycle time.

6. Define data transfer rate.

7. Define Cache memory.

8. Define Virtual Memory.

9. What are the advantages of SRAM?

10. Define Asynchronous DRAMS.

11. Define Synchronous DRAMS.

12. Define Memory latency & memory bandwidth.

13. Draw the structure of Memory hierarchy.

14. What is replacement algorithm?

15. What is write-back (or) copy-back protocol?

16. What is mapping & when do you apply the mapping techniques?

17. What is hit rate & miss rate?

25


PART B – (16 Marks)

1. Explain about Static & Dynamic memory systems and ROM technologies. (NOV/DEC 2007)

2. What is mapping? Explain various mechanisms of mapping main memory address into cache memory addresses.

(MAY 2008) (MAY/JUNE 2006)

3. Explain the performance factors in memory. (MAY/JUNE 2006)

4. Explain the concept of memory hierarchy (NOV/DEC 2007)&( NOV/DEC 2006)

5. Discuss different page replacement policies in virtual memory system. (MAY 2006)

6. Describe the working principle of a typical magnetic disk.(APRIL 2008)

7. How a virtual address gets translated into a physical address? Explain in detail. Explain the use of TLB.

(APRIL/MAY 2008)&( NOV/DEC 2006) & (MAY/JUNE 2007)

8. What is virtual memory? How is it implemented? (NOV/DEC 2007)

9. Discuss the various memory types and mention their advantages (NOV/DEC 2009)

10. Explain the operation of Associative cache memories. (NOV/DEC 2009)

11. List cache memory organization and explain in detail with suitable diagrams and compare it with other

organization (EIE dec 2012)

12. With neat sketch explain virtual memory management techniques. (EIE dec 2012)

13. Describe cache memory in detail. (16) (EC Nov’11) (NOV/DEC 2006)

14. (i) Describe the organization of typical RAM chip.(6)

(ii).What is virtual memory? Explain how the logical address is translated into physical address in the virtual

memory with a neat diagram (10). (MAY/JUNE 2007) (MAY 2008)

15. Explain paging in detail. (EIE dec 2009, may 2010)

16. Define Cache Mapping Functions. Explain different types of mapping functions in cache memory. (MAY 2009)

17. What are the different secondary storage devices? Elaborate on any one of these devices.(8)

18. Discuss the following

i. Interleaving (5)

ii. Hit rate and Miss penalty (6)

iii. Pre-fetching (5)

26


.




UNIT V – I/O AND INTERFACES CLASS: FINAL EIE A&B


1. What is need for interfacing? (EIE dec 2012)

Hardware interfaces exist in computing systems between many of the components such as the various buses,

storage devices, other I/O devices, etc. A hardware interface is described by the mechanical, electrical and logical signals

at the interface and the protocol for sequencing them (sometimes called signaling).

A standard interface, such as SCSI, decouples the design and introduction of computing hardware, such as I/O

devices, from the design and introduction of other components of a computing system, thereby allowing users and

manufacturers great flexibility in the implementation of computing systems.

Hardware interfaces can be parallel where performance is important or serial where distance is important.

2.Define polling. (EIE Nov’11)

Polling, or polled operation, in computer science, refers to actively sampling the status of an external device by a

client program as a synchronous activity. Polling is most often used in terms of input/output (I/O), and is also referred to

as polled I/O or software-driven I/O.

Polling is sometimes used synonymously with busy-wait polling (busy waiting). In this situation, when an I/O

operation is required, the computer does nothing other than check the status of the I/O device until it is ready, at which

point the device is accessed.

In other words, the computer waits until the device is ready. Polling also refers to the situation where a device is

repeatedly checked for readiness, and if it is not, the computer returns to a different task. Although not as wasteful of CPU

cycles as busy waiting, this is generally not as efficient as the alternative to polling, interrupt-driven I/O.

3. What is an interrupt ? (refer book for proper defn.) (EIE dec 12)(EIE Nov’11)

An interrupt is an event that causes the execution of one program to be suspended and another program to be executed.

4. What are the types of interrupts? (EIE dec 2012)

Internal interrupts

External interrupts

Maskable interrupts

Non-maskable interrupts

5.What are the uses of interrupts?

• Recovery from errors

• Debugging

• Communication between programs

• Use of interrupts in operating system

27


6. Define vectored interrupts.

In order to reduce the overhead involved in the polling process, a device requesting an interrupt may identify itself

directly to the CPU. Then, the CPU can immediately start executing the corresponding interrupt-service routine. The term

vectored interrupts refers to all interrupt-handling schemes base on this approach.

7. What is the need for reduced instruction chip?

1. Relatively few instruction types and addressing modes.

2. Fixed and easily decoded instruction formats.

3. Fast single-cycle instruction execution.

4. Hardwired rather than microprogrammed control.

8. Mention the group of lines in the system bus?

*Address lines

*Data lines

*Control lines

9. What is bus master and slave master?

Input output operations involve data transfers between IO device and memory.In all the preceding operations

memory is passive or slave device with respect to system bus transactions.Where as the cpu can control the system bus,i.e

serve as a bus master.

10. What is the use of IO controller?

The magnetic disks and other secondary memory need to be connected to the system bus via interfacecircuits

called Io controllers.

That performs series to parallel and parallel to series format conversions and other control functions.It can

interface many IO device to system bus.

11. Differentiate synchronous and asynchronous communication?

In synchronous communication each item is transferred during the time slot know to both the source and

destination.Data transfer is slow.

In asynchronous communication data transfer is faster and can be used for long distance communication.Each

item being transferred is accompanied by the control signals.

12.What is strobe signal?

The data ready/request signals are used to load data from the source unit to the bus of from the bus to the

destination unit.such control signals are called strobe signals.

13.What is bus arbitration?

The possibility exists that several master or slave units connected to a shared bus will request access to the bus at

the same time.

A selection mechanism called bus arbitration is therefore required to enable the current master which will still

refer to a bus controller to decide among such competing request.

14.Mention the types of bus arbitration?

*Daisy chaining

*Polling

*Independent requesting

28


15.What is IO control method?

It refers the data transfer between the IO device and the memory or between the IO device and the cpu.eg.testing

the ststus of device and to determine if they are required service by the cpu.

16 .What is DMA?

The CPU and IO controller interact only when the cpu yield the control of the memory bus to the IO controller in response

to the request from the latter.This level of IO control is called direct memory access and IO device interface control circuit

is called DMA controller.

17.What are the advantage and disadvantages of bus?

ADV:

1.Low cost

2.Versatility.

DIS-ADV:

1.It creates a communication bottleneck

2.Limiting the maximum I/O throughput and bandwidth limitation.

18.What are the types of buses?

Processor memory bus

I/O Buses

19.what are the i/o data transfer method using memory busses

Three methods used for data transfer between IO devices and CPU

1. program i/o or polling

2.interrupt driven i/o

3.direct memory access

20. How the interrupt is handled during exception?

* CPU identifies source of interrupt

* CPU obtains memory address of interrupt handles

* HYPERLINK "http://www.indiastudychannel.com/resources/12626-CS--Computer-Architecture-Two-

marks.aspx" \t "_top"pc and other CPU status information are saved

* PC is loaded with address of interrupt handler and handling program to handle it.

23. What is interrupt latency?

Saving register also increases the delay between the time and interrupt request is received and state of execution of the

interrupt service routine. This delay is called interrupt Latency.

24. Define Centralized Arbitration.

It means that all devices waiting to use the bus have no equal responsibility in carrying out the arbitration process.

25. Define Distributed Arbitration.

It means that all devices waiting to use the bus have equal responsibility in carrying out the arbitration process without

using central arbiter.

26. Define Bus Master.

The device that is allowed to initiate data transfers on the bus at any given time.

29


21. Difference between asynchronous bus and synchronous bus.

Synchronous bus and Asynchronous:

1. Synchronous bus on other hand contains synchronous clock that is used to validate each and every signal. It

is also synchronizing clock that is used to validate each and every signal. when it is specified clock speed is set

for all time.

2 .Synchronous buses are affected noise only when clock signal occurs. Asynchronous buses can mistake

noise pulses at any time for valid handshake signal.

3. A master that receives the bus grant signal and it requesting the bus must not propagate it on down the

deisgn chain. The system control which receives the bus grant signal in VME bus .The other name for

Synchronous is VME bus.

4. Synchronous bus designers must control with meta stability when attempting different clock signal

Frequencies. Asynchronous bus designer must deal with events that like synchronously.

5. Synchronous bus of meta stability arises in any flip flop. when time will be violated. It must contend with

meta stability when events that drive bus transaction.

6. Synchronous flipflop can range from nanoseconds to microseconds its range is from 20-45 nanoseconds.

When flip flop experiences effects can occur in downstream circurity unless proper design technique which are

used.

27. What are the roles of I/O controller? Pg. no. 394

28. Define keyboard and keypads, touchpad. Pg. no. 395

29. What do you mean by ergonomic keyboards? Pg. no. 395

30. What do you mean by contact bounce effect? Pg. no. 396

31. Define refresh rate.

32. List out the commonly used sensors and their applications. Pg. no. 404

33. What are the various inputs/outputs other than programs and data? Pg. no. 411

34. What is benchmark?

35. What are the types of benchmark? Pg. no. 405

36. What are i/o performance measure parameters? Pg. no. 405

37. What are the types of interrupt?

38. What are the steps followed in servicing an interrupt request? Pg. no. 418

39. What are the four registers available in DMA controller? Pg. no. 419

40. List out the problems that are to be considered in DMA addressing. Pg. no. 421

41. What is access latency in I/O operation? Pg. no. 422

42. What is data transfer rate in I/O operation? Pg. no. 422

43. What is response time in I/O operation? Pg. no. 422

44. What is throughput in I/O operation? Pg. no. 422

45. What is intra-system link? Pg. no. 429

46. What is inter-system link? Pg. no. 430

47. What are the common three types of interconnection schemes? Pg. no. 431

48. What are the characteristics of interconnecting structures? Pg. no. 431

49. What do mean by legacy buses? Pg. no. 434

50. What do mean by standard buses? Pg. no. 434

51. What do mean by proprietary buses? Pg. no. 434

52. What are the most common bus specifications? Pg. no. 434

53. What are the parameters by which bus performance (bandwidth) can be increased? Pg. no. 439

54. What are the factors that affect the robustness of a bus? Pg. no. 440

55. List out few interfacing standards. Pg. no. 440

56. What is I/O abstraction? Pg. no. 450

57. What are the types of I/O abstraction? Pg. no. 450

30


58. What are exceptions and traps? Pg. no. 452

60. What is context switching? Pg. no. 458

61. what do you mean by multiprogramming or multitasking? Pg. no. 458

62. What is threading and multithreading? Pg. no. 460

Part B

1. Give the need for DMA transfer. What are different modes of DMA transfer? Explain the sequence of operation

required for a DMA transfer? (EIE dec 2012), (EIE dec 2012)

2. Write short notes on: multithreading (8) and context switching (8) (EIE dec 2012), (EIE dec 2011)

3. Explain the use of DMA controllers in a computer system with a neat diagram(8) (EC Nov’11)

4. Describe vectored interrupt scheme with a neat block diagram.(8) (EC Nov’11)

5. Explain how I/O devices can be interfaced with a block diagram.(8) (CS Nov’10)

6. How do you connect multiple I/O devices to a processor using interrupts? Explain with suitable diagrams

7. Explain Handshake protocol. Depict clearly how it controls data transfer during an input operation.

8. Describe the hardware mechanism for handling multiple interrupt requests.(8)

9. What are handshaking signals? Explain the handshake control of data transfer during input and output operation.(8)

10. Explain different types of bus arbitration scheme. (8)

11. What is mean by bus arbitration? Describe bus arbitration daisy chaining and polling schemes for bus arbitration in

detail. (10)

anand institute of higher technology · 2014-07-24 · 1 cmageshkumar_ap_aiht cs2071_computer...

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