1

EE241 - Spring 2007Advanced Digital Integrated Circuits

TuTh 3:30-5pm531 Cory

2

Practical InformationInstructor:

Borivoje Nikolić570 Cory Hall , 3-9297, bora@eecsOffice hours: M 10:30am-12pm

Reader: TBA

Admin: Rosita Alvarez-Croft253 Cory Hall, 3-4976, rosita@eecs

Class Web pagehttp://bwrc.eecs.berkeley.edu/classes/icdesign/ee241_s07

2

3

Class TopicsThis course aims to convey a knowledge of advanced concepts of circuit design for digital LSI and VLSI components in state of the art MOS technologies.

Emphasis is on the circuit design, and optimization for both high performance high speed and low power for use in applications such as microprocessors, signal and multimedia processors, communications, memory and periphery. Special attention will devoted to the most important challenges facing digital circuit designers today and in the coming decade, being the impact of scaling, deep sub-micron effects, variability, interconnect, signal integrity, power distribution and consumption, and timing.

4

EECS141 vs. EECS241EECS 141:

Basic transistor and circuit modelsBasic circuit design stylesFirst experiences with design – creating a solution given a number of specs

EECS 241:Transistor models of varying accuracyDesign under constraints: power-constrained, flexible, robust,…Learning more advanced techniques Study the challenges facing design in the coming yearsCreating new solutions to challenging design problems

3

5

EECS141 vs. EECS241EECS141

0.25μm CMOSUnified transistor modelBasic circuit design techniquesWell defined design projectCadence/HspiceFocus on principles

EECS241Mostly 45nm CMOSDifferent modelsAdvanced circuit techniquesOpen design/research projectAny tool that does the jobFocus on principles

6

Special Focus in Spring 2007

Current technology issuesPower and performance optimizationProcess variationsRobust designPerformance and power limitsTiming strategiesSRAM

4

7

Class TopicsFundamentals - Technology and modeling – Scaling and limits of scaling (1.5 weeks) Design for deep-submicron CMOS (2.5 weeks)

Static CMOS, transistor sizing, high-speed CMOS design styles, dynamic logic Design techniques for power and performance (2.5 weeks)

analysis of power consumption sources power minimization at the technology, circuit, and architecture level

Arithmetic circuits – adders, multipliers (2 weeks) Driving interconnect, high-speed signaling (2 weeks) Timing (2 weeks)

Timing analysis, flip-flop/latch design, clock skew, clocking strategies, self-timed design, clock generation and distribution, phase-locked loops

Memory design (2 week)

8

Class Organization5 (+/-) assignments1 term-long design project

Phase 1: Proposal (by ISSCC)Phase 2: Study (report by week 8)Phase 3: Design (presentation and report by final week)Report and presentations last week of classes

Final exam (in-class)

5

9

Class MaterialBaseline: “Digital Integrated Circuits - A Design Perspective”, 2nd ed. by J. M. Rabaey, A. Chandrakasan, B. NikolićOther reference books:

“Design of High-Performance Microprocessor Circuits,” edited by A. Chandrakasan, W. Bowhill, F. Fox“Low-Power Electronics Design,” C. Piguet, Ed.“CMOS VLSI Design,” 3rd ed, N.Weste, D. Harris“Aqnalysis and Design of Digital ICs,” 3rd ed, D.A. Hodges, H.G. Jackson, R.A. Saleh“High-Speed CMOS Design Styles, by K. Bernstein, et al.“Leakage in Nanometer CMOS Technologies,” by Narendra and Chandrakasan, Ed.“Digital Systems Engineering” by W. Dally

10

Class MaterialList of background material available on web-siteSelected papers will be made available on web-site

Linked from IEEE Xplore and other resourcesNeed to be on campus to access, or use library proxy, library VPN (check http://library.berkeley.edu)

Class-notes on web-site

6

11

SourcesIEEE Journal of Solid-State Circuits (JSSC)IEEE International Solid-State Circuits Conference (ISSCC)Symposium on VLSI Circuits (VLSI)Other conferences and journals

12

Project TopicsVariability studiesRobust designPower-performance tradeoffsLeakage suppressionSRAM design

7

13

Tools

HSPICEYou need an account on cory.eecs

Predictive sub-100nm models (former BPTM)http://www.eas.asu.edu/~ptm/

0.18 /0.13/0.09 μm CMOS device modelsOther tools, schematic or layout editors are optionalCadence, Synopsys, available on quasar.eecs

More information on the web-site.

14

EE290C This SemesterAdvanced topics IC course, taught by Prof. Kuroda (Keio University)1 unitAccelerated pace, February 15-March 20

8

EE241 - Spring 2007Advanced Digital Integrated Circuits

Lecture 1: IntroductionTrends and Challenges in

Digital Integrated Circuit Design

16

Suggested ReadingInternational Technology Roadmap (http://public.itrs.net) Bowhill, Chapter 1 – Impact of physical technology on architecture (J.H. Edmondson),Bowhill, Chapter 2 – CMOS scaling and issues in sub-0.25μm systems (Y. Taur)Baseline: Rabaey et al, Chapter 3.Selected papers from the web:

G.E. Moore, No exponential is forever: but "Forever" can be delayed! Proc. ISSCC’03, Feb 2003. T.-C. Chen, Where CMOS is going: trendy hype vs. real technology. Proc. ISSCC’06, Feb 2006.

S. Chou, Innovation and Integration in the Nanoelectronics Era, Proc. ISSCC’05, Feb. 2005.S. Borkar, “Design challenges of technology scaling,” IEEE Micro, vol.19, no.4, p.23-29, July-Aug. 1999.

The contributions to this lecture by a number of people (J. Rabaey, P. Gelsinger, S, Borkar, etc) are greatly appreciated.

9

17

Moore’s Law

In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 12 months.

He made a prediction that semiconductor technology will double its effectiveness every 18 months“The complexity for minimum component costs has increased at a rate of roughly a factor of two per year. Certainly over the short term, this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years. That means by 1975, the number of components per integrated circuit for minimum cost will be 65,000.”Gordon Moore, Cramming more Components onto Integrated Circuits, (1965).

18

Moore’s Law - 1965““Reduced cost is one of the big Reduced cost is one of the big attractions of integrated attractions of integrated electronics, and the cost electronics, and the cost advantage continues to increase advantage continues to increase as the technology evolves as the technology evolves toward the production of larger toward the production of larger and larger circuit functions on a and larger circuit functions on a single semiconductor substrate.single semiconductor substrate.””Electronics, Volume 38, Electronics, Volume 38, Number 8, April 19, 1965Number 8, April 19, 1965

19601960 19651965 19701970 19751975 19801980 19851985 19901990 19951995 20002000 20052005 20102010

TransistorsTransistorsPer DiePer Die

101088

101077

101066

101055

101044

101033

101022

101011

101000

101099

10101010

Source: IntelSource: Intel

1965 Data (Moore)1965 Data (Moore)

Graph from S.Chou, ISSCC’2005

10

19

Moore’s Law - 2005

40044004

80808080 808680868028680286

386386™™ ProcessorProcessor486486™™ ProcessorProcessor

PentiumPentium®® ProcessorProcessorPentiumPentium®® II ProcessorII Processor

PentiumPentium®® III ProcessorIII ProcessorPentiumPentium®® 4 Processor4 Processor

ItaniumItanium™™ ProcessorProcessor

TransistorsTransistorsPer DiePer Die

101088

101077

101066

101055

101044

101033

101022

101011

101000

101099

10101010

80088008

ItaniumItanium™™ 22 ProcessorProcessor

1K1K4K4K

64K64K256K256K

1M1M

16M16M4M4M

64M64M256M256M

512M512M1G1G 2G2G

128M128M

16K16K

1965 Data (Moore)1965 Data (Moore)

MicroprocessorMicroprocessorMemoryMemory

19601960 19651965 19701970 19751975 19801980 19851985 19901990 19951995 20002000 20052005 20102010

Source: IntelSource: IntelGraph from S.Chou, ISSCC’2005

20

Moore’s law and cost

11

21

Molecular Electronics

Progress in Nano-Technology

Carbon Nanotubes

Silicon Nanowires

Nanomechanics

Spintronic Storage

Millipede

Spintronic device

T.C. Chen, Where Si-CMOS is going: Trendy Hype vs. Real Technology, ISSCC’06

22

Technology Strategy / Roadmap 2000 2005 2010 2015 2020 2025 2030

Plan B: Plan B: SubsytemSubsytem IntegrationIntegration

R D

Plan C: Post Si CMOS Options Plan C: Post Si CMOS Options

R R&D

Plan Q:Plan Q:

R D

Quantum ComputingQuantum Computing

Plan A: Extending Si CMOSPlan A: Extending Si CMOS

R D

T.C. Chen, Where Si-CMOS is going: Trendy Hype vs. Real Technology, ISSCC’06

12

23

Technology EvolutionInternational Technology Roadmap for Semiconductors - 2003 data

2232456590Dram ½ pitch [nm]8800M4400M2200M1100M550MMPU transistors/chip14-1812-1612-1611-1510-14Wiring levels

913182537High-perf. physical gate [nm]

‘Low-power’ power [W]Low-power VDD [V]

Cost-perf. power [W]High-perf. power [W]

Local clock [GHz]High-perf. VDD [V]

Year 20162013201020072004

0.80.91.01.11.24023159.34.2

3.03.02.82.52.20.50.60.70.80.915813812010484288250220190160

24

ITRS Acceleration Continues

13

25

Printed vs. Physical Gate

ITRS’2003

26

Printed vs. Physical Gate

MicronMicron

1000010000

10001000

100100

1010

1010

11

0.10.1

0.010.01

NanoNano--metermeter

NanotechnologyNanotechnology(< 100nm)(< 100nm)

130nm130nm

90nm90nm

70nm70nm50nm50nm

Gate LengthGate Length 65nm65nm

35nm35nm

19701970 19801980 19901990 20002000 20102010 20202020

45nm45nm32nm32nm

22nm22nm

25nm25nm18nm18nm

12nm12nm

0.7X every 2 years

Nominal feature sizeNominal feature size

Source: IntelGraph from S.Chou, ISSCC’2005