anu mehra ppt - 2

© Digital Integrated Circuits2nd Inverter

Low Power VLSI Low Power VLSI DesignDesign

The InverterThe Inverter

Dr Anu Mehra


The CMOS Inverter: A First GlanceThe CMOS Inverter: A First Glance

V in Vout

CL

VDD


CMOS InverterCMOS Inverter

Polysilicon

In Out

VDD

GND

PMOS 2

Metal 1

NMOS

OutIn

VDD

PMOS

NMOS

Contacts

N Well


Two InvertersTwo Inverters

Connect in Metal

Share power and ground

Abut cells

VDD


CMOS InverterCMOS InverterFirst-Order DC AnalysisFirst-Order DC Analysis

VOL = 0VOH = VDD

VM = f(Rn, Rp)

VDD VDD

Vin 5 VDD Vin 5 0

VoutVout

Rn

Rp


CMOS Inverter: Transient ResponseCMOS Inverter: Transient Response

tpHL = f(Ron.CL)

= 0.69 RonCL

VoutVout

Rn

Rp

VDDVDD

Vin 5 VDDVin 5 0

(a) Low-to-high (b) High-to-low

CLCL


Voltage TransferVoltage TransferCharacteristicCharacteristic


PMOS Load LinesPMOS Load Lines

VDSp

IDp

VGSp=-2.5

VGSp=-1VDSp

IDnVin=0

Vin=1.5

Vout

IDnVin=0

Vin=1.5

Vin = VDD+VGSpIDn = - IDp

Vout = VDD+VDSp

Vout

IDnVin = VDD+VGSpIDn = - IDp

Vout = VDD+VDSp


CMOS Inverter Load CharacteristicsCMOS Inverter Load Characteristics

IDn

Vout

Vin = 2.5

Vin = 2

Vin = 1.5

Vin = 0

Vin = 0.5

Vin = 1

NMOS

Vin = 0

Vin = 0.5

Vin = 1Vin = 1.5

Vin = 2

Vin = 2.5

Vin = 1Vin = 1.5

PMOS


CMOS Inverter VTCCMOS Inverter VTC

Vout

Vin0.5 1 1.5 2 2 .5

0.5

11.

52

2.5

NMOS resPMOS off

NMOS satPMOS sat

NMOS offPMOS res

NMOS satPMOS res

NMOS resPMOS sat


Switching Threshold as a function Switching Threshold as a function of Transistor Ratioof Transistor Ratio

100

101

0.8

0.9

1

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

MV

(V

)

Wp

/Wn


Determining VDetermining VIHIH and V and VILIL

VOH

VOL

Vin

Vout

VM

VIL VIH

A simplified approach


Inverter GainInverter Gain

0 0.5 1 1.5 2 2.5-18

-16

-14

-12

-10

-8

-6

-4

-2

0

Vin

(V)

gain


Simulated VTCSimulated VTC

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5

Vin

(V)

Vou

t(V)


Propagation DelayPropagation Delay


CMOS Inverter Propagation DelayCMOS Inverter Propagation DelayApproach 1Approach 1

dt

dVCI L

VDD

Vout

Vin = VDD

CLIav

tpHL = CL Vswing/2

Iav

∆t=CL∆V/IDS

Iav is average charging

current and ∆V is VDD/2


CMOS Inverter Propagation DelayCMOS Inverter Propagation DelayApproach 2Approach 2

VDD

Vout

Vin = VDD

Ron

CL

tpHL = f(Ron.CL)

= 0.69 RonCL

t

Vout

VDD

RonCL

1

0.5

ln(0.5)

0.36


0 0.5 1 1.5 2 2.5

x 10-10

-0.5

0

0.5

1

1.5

2

2.5

3

t (sec)

Vou

t(V)

Transient ResponseTransient Response

tp = 0.69 CL (Reqn+Reqp)/2

tpLHtpHL


Delay as a function of VDelay as a function of VDDDD

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.41

1.5

2

2.5

3

3.5

4

4.5

5

5.5

VDD

(V)

t p(nor

mal

ized

)


The Transistor as a SwitchThe Transistor as a Switch

0.5 1 1.5 2 2.50

1

2

3

4

5

6

7x 10

5

VDD

(V)

Req

(O

hm)


Design for Performance (minimum Design for Performance (minimum delay)delay)

Keep capacitances small –keep drain diffusion area small so less overlap

Increase transistor sizes watch out for self-loading!

Increase VDD –however increasing voltage beyond a level leads to reliability concern


To MAKE A SYMMETRIC INVERTER To MAKE A SYMMETRIC INVERTER tpHL=tpLHtpHL=tpLH

Reqn= 13kΩ and Reqp= 31kΩ (for 0.25µm technology)

RN= Reqn(L/W)n

RP=Reqp(L/W)p

tpLH=ln(2)RPCL

tnHL=ln(2)RNCL


In order to make

tpHL=tpLH

pn W

L

W

L

31

13

np L

W

L

W

38.2


To minimize total delayTo minimize total delay

Total delay =tpHL+tpLH Approximate load Capacitance CL= (Cdp1+Cdn1)+(Cgp2+Cgn2)+CW Let β =(W/L)p/(W/L)n Then Cdp1= βCdn1 and Cgp2=βCgn2 Total delay=tp


tp=0.69((1+β)(Cdn1+Cgn2)+CW

(Reqn+Reqp/β) tp=0.69((1+β)(Cdn1+Cgn2)+CW

Reqn(1+r/β) To minimize delay

0tp

211(

CgnCdn

Cwropt


For 0.25 technology

58.1 r


1 1.5 2 2.5 3 3.5 4 4.5 53

3.5

4

4.5

5x 10

-11

t p(sec

)

NMOS/PMOS ratioNMOS/PMOS ratio

tpLH tpHL

tp = Wp/Wn

anu mehra ppt - 2

Education

v dsp v

v ihand v il

v il v ih

v swing

glance v

v dd c

r n r p v dd v dd v

function of v dd