Ph.: (+1) 213 425 4957 Anurag Goyal goyala@usc.edu

linkedin.com/in/agoyal92 EDUCATION

Master of Science in Electrical Engineering CGPA: 3.7/4.0 Aug 2015 – May 2017 University of Southern California, Los Angeles, CA

Coursework: VLSI System Design, Network Processor Design and Programming, Diagnosis and Design

of Reliable Digital Systems

B.Tech in Electronics and Communication Engineering CGPA: 8.85/10 July 2010 – June 2014 National Institute of Technology, Kurukshetra, India

Coursework: VHDL and Digital Design, Object Oriented Programming, Data Structures, Analog Electronics, Digital Circuits & Systems, Digital Signal Processing

TECHNICAL SKILLS

Languages: C, C++, SystemC, Verilog, Perl, Linux, R

Tools: Cadence Virtuoso, Model Sim, NCsim, Xilinx ISE, Lattice Diamond, MATLAB, Cadence

Encounter, Synopsys PrimeTime, Synopsys Design Compiler, HSPICE

Misc. Skills: Static Timing Analysis, Power Optimization, DRC, RTL design, Digital Logic, SOC, Place and

Route, RC extraction

WORK EXPERIENCE

Hardware Engineering Intern June 2016 – Present Signal Laboratories, Menlo Park, CA

Designing a 32k point Fast Fourier Transform module in fixed point format on Lattice FPGA.

Implemented the bit accurate model of the same in C and SystemC.

Assistant Manager June 2014 – June 2015 Reliance Jio Infocomm Limited, Navi Mumbai, India

Monitored customer end devices used for LTE, FTTX and Wi-Fi networks.

Analysed LTE Call Flow for solving 4G network issues.

Research Intern for ‘Collision Detection in Automated Vehicles’ June 2013 – Aug 2013

Technical University of Ilmenau, Germany

Created a database for verifying collision detection in potential evasive trajectories which made the

whole process faster by more than 500%.

The MATLAB codes are still used by the Professor’s research group.

Research Intern for ‘Transistors as Amplifiers: Some Design Considerations’ June 2012 – July 2012 Defence Research and Development Organisation, Delhi, India

Designed a high frequency Surface Acoustic Wave (SAW) Oscillator.

ACADEMIC PROJECT EXPERIENCE

Semi-custom layout design of a dual clock FIFO, CAM, LIFO Sep 2016

Implemented the RTL design for the above modules in Verilog.

Completed the place and route using ‘Encounter’ and Static Timing Analysis using ‘PrimeTime’

Software Controlled Multi-Threaded Custom Network FPGA Processor May 2016

Designed a network router on the NetFPGA to encrypt the incoming packets and to reroute them

accordingly.

Design and Implementation of a Pipelined Network Processor on NetFPGA Virtex II Pro Feb 2016

Implemented a 5-stage Pipeline processor and designed its custom ISA based on MIPS ISA.

Created a compiler to translate C code to machine code and executed it on the network processor.

AWARDS

DAAD Working Internship in Science and Engineering (WISE) scholarship.