“fpga implementation of cryptographic algorithms...

© 2013, IJARCSSE All Rights Reserved Page | 112

Volume 3, Issue 5, May 2013 ISSN: 2277 128X

International Journal of Advanced Research in Computer Science and Software Engineering Research Paper Available online at: www.ijarcsse.com

“FPGA Implementation of Cryptographic Algorithms using

Multi-Encryption Technique” Rashi Kohli

[1] Manoj Kumar

[2]

Student Assistant Professor

Computer Science and Engineering Computer Science and Engineering

Amity University Amity University

India. India.

Abstract— As internet is in enormous demand and it acts as a repository for the data and knowledge, there is

unremitting demand for real time implementation of cryptographic algorithms so that one can secure its data over this

decentralized network and help in preserving the security of the system. The Importance of IT- security is booming up

in terms of securing the data and for secure communication system. Applications in electronic industry are pacing up

at a good speed. So the requirement is securing these applications through encryption and decryption mechanisms in

the cryptographic algorithms. This paper provides proposed pipelined implementation of X-Tea, Rc-6 and a novel

approach of multi-encryption technique which uses these two algorithms in terms of memory/area chip, operations

used, encryption time etc. to achieve optimization.

Keywords— Cryptography, Optimization, VLSI, security, multi-encryption, RFID

I. INTRODUCTION

In today’s era implementing cryptographic algorithms using hardware description language that utilizes complex operations and approach is a difficult task. Security attacks are increasing since data is paramount, and the main task is

securing the data that will keep on increasing simultaneously maintain the resource consumption and providing the

approach that will lead to optimization since utilizing number of resources undoubtedly will be a costly affair. Different

Software implementations of cryptographic algorithms are available. In this paper a novel approach of multi-encryption

technique within the algorithms and between the algorithms is used. X-tea and Rc-6 will be used and its results will be

compared with the individual pipelined approach of these algorithms. Concept of pipeline is similar to water pipe. The

advantage of using pipelined approach will help in achieving optimization i.e. firstly it will reduce in the critical path

secondly since Rc-6 utilizes different algorithms for encryption and decryption we have to provide a method by which can

reduce the memory space i.e. an approach which will describe encryption and decryption unit simultaneously so as to

reduce the memory/area chip size. Other advantages of pipelined approach take account of reduction in the power

consumption, increasing the throughput of the system, increasing the clock speed etc. The magnificence of this pipelined approach is that new information can instigate its processing while the preceding information is still performing its task,

this will have slight delay towards encryption-decryption time but it will significantly save the resource consumption and

therefore in turn the cost. Now a day’s many encryption algorithms are available but all these are used to provide single

encryption round, this paper uses the proposed approach of multi-encryption technique i.e. encryption of encryption on

field Programmable Gate Arrays (FPGA) using reconfigurable computing. This approach will make the system more

secure from different type of attacks which happened in the past. [1, 11, 12, 23]

II. RELATED WORK

Till now, different approaches have been proposed highlighting the importance of security in the cryptology which is the

science of securing particular application from unauthorized access or from getting hacked. Various researchers provides

efficient software implementation in securing software applications, but there is limited amount of hardware

implementation of the cryptographic algorithms and the hardware implementations which are available follows a single encryption technique and the importance of resource consumption getting neglected while we are securing the

application. Developing the hardware platform using the cryptographic algorithms is not an easy task; rather it is a

tedious task. So to provide the security and achieving optimization in terms of resource consumption, we have chosen

AES, Rc-6 & X-tea. [1][2][3][17].For achieving the security of the large applications, we can use advance encryption

algorithm, since it provides significant level of security. But during the research process, we found that in order to

provide optimal level of resource utilization, we have to focus on different parameters i.e. simplicity, security, and

operations involved. AES although is very efficient and standalone algorithm which provides a great amount of security

but it uses hefty S-box which imparts non linearity and it is the only component which is used for security, it provides

great level of security but it increases the complexity of the system, it is the hindrance in achieving the optimization and

disadvantageous for embedded systems applications. We selected X-tea which is a light weight cryptographic

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Kohli et al., International Journal of Advanced Research in Computer Science and Software Engineering 3(5),

May - 2013, pp. 112-120


algorithms, and which can effectively used for small applications since it is known for its simplicity and less code coverage area and this algorithm can be embedded with other algorithms of same domain sue to its small size features.

Some of the limitations which were encountered during the research process are, firstly neglecting the process of

efficient resource consumption and its management while securing the applications, secondly single round of encryption,

which can be attacked or leaked by unauthorized parties. Earlier cryptographic algorithms i.e. DES, 3DES, which were

subjected to differential attacks were proven insecure. Other algorithms such as AES which is secure but it increases the

complexity since it is SP-base network. On the other hand software implementation of block cipher algorithms usually

require large look up tables which is one of the disadvantage, since it refers to the increase in the code

complexity.[9][10][13]

III. X-TEA BLOCK CIPHER APPROACH

X-tea is a light weight cryptographic algorithm, which is specifically known for its simplicity & small code size. Since it is known for its small code size that means it can be very beneficial in designing small applications, pervasive computing,

ubiquitous computing, RFID technology and it can act as a module in embedded-base applications. [14][15] .Before X-tea

was introduced, TEA algorithm was there but due to different attacks it was proven inadequate from the point of security

since it contained two major weaknesses, that weakness was resolved in the key scheduling part of X-tea. X-tea is feistel

base iterative block cipher algorithm which usually operates on 64-Bit block cipher and the key depends upon the design

requirements it can be 62 bit key, 64 bit key or 128 bit key. But here we have modified the existing approach using

pipelining mechanism to reduce the memory/area on system chip size simultaneously increasing the encryption time and

reducing the critical path time.[5][6][7][8] This approach is shown below in the figure 1

Figure 1: Proposed x-tea approach

In this approach the adder function is used for encrypting the data while. Subtractor function is used for decrypting the data

depending upon the input as plain text or cipher text respectively.

The functions which are used over here are

1. Funct (Q) = (q<<4 xor q>>5) + q

2. Funct (v) = sum(0) + key(sum) Where: sum (0) = delta value = 09E3779B9

The delta value in the existing approach is fixed to 09E3779B9 but here in our approach we can make it user defined i.e.

delta value along with the key value makes the security component stronger. Some of the other changes that were

incorporated were in the operations, earlier basic ripple adder was used but in our approach Kogge stone adder will be used in encryption process following the pipelining approach. The Kogge stone adder is known for its faster approach which is

implemented here in the form of black level and gray level; this will improve the encryption time and will increase the

security feature as well. The approach follows the mealy FSM concept which depends on the current input values and the

current state. This feature will improve the collision between the data, which was there in earlier approaches. The concept of

finite state machine is described above in the figure 2. The states S5-S9 indicates the decryption unit and states S10-S14

indicates the encryption process states. [1][2][4][16][18]


May - 2013, pp. 112-120


Figure 2: State Chart Process of Proposed X-tea approach

IV. RC-6 BLOCK CIPHER APPROACH

Rc-6 is one of the finalist candidate of AES contest, different survey provide that this algorithm provides better results in

comparison with AES when resource consumption is one of the major factors, But there is still a disadvantage that it uses

different structure for encryption and decryption, thus it will acquire more space and it will be hindrance in achieving

optimization but our approach will follow the pipelining mechanism where same structure will provide encryption and

decryption. And since just like X-tea algorithm approach this is also based on feistel base structure rather than SP networks the only basic difference is in the terms of block size, key size & its functionality. The Rc-6 algorithm usually operates on

128 bit block and key size which we have utilized is 128 bit but it can be expandable up to 256 bit key size depending upon

the number of rounds. [12,20,21,22].

The total number of rounds for which it will be iterated will be 20 rounds since 128 bit key is used. The key size therefore

depends on the number of rounds which can be calculated using the function i.e. F(y) = r (2y+1) mod 2w it specifies the

function used and the block size which will be used. The architecture of Rc-6 is described below

Figure 3: Rc-6 process flow


May - 2013, pp. 112-120


V. FPGA MULTI-ENCRYPTION TECHNIQUE Different literature survey and researchers highlighted the importance of single encryption cryptographic algorithm, but

network is expanding day by data, and there is great demand of Big Data, so securing such data is tedious task and requires

strong encryption technique. So the technique employed here uses intra multi-encryption technique between X-tea and Rc-

6, which will be implemented on the FPGA platform using verilog as hardware description language, and the device which

is employed is Spartan 3E and Virtex. The working principle for FPGA implementation of multi-encryption technique is

explained below in figure 3; the algorithm 1 used here is X-tea and algorithm 2 is Rc-6, during the analysis of

cryptographic algorithm we found that Rc-6 and x-tea both operate using feistel base architecture, secondly while

designing this multi-encryption technique, we formulated individually the process of X-tea and Rc-6 and found that both

are compatible for the technique.AES cannot be used in this approach since it uses hefty S-box for security and it is not

compatible because it is not based on feistel base architecture.[1][2]

Figure 4: FPGA multi-encryption Technique

A. Proposed Multi-encryption Algorithm

Algorithm: Multi-Encryption(X-tea &RC-6): Finding the Encrypted Data & providing hardware platform design based

on cryptographic algorithm

INPUTS:

X₁, X₂ , Input Bits from X-tea_func,

Delta_val, key₁, key₂, key₃, key₄, // security input components//

Add_func

Sl, clk, reset

OUTPUT:

Encrypted data ( Out₁, Out₂, Out₃, Out₄) Digital Hardware Design of X-tea, Rc-6 & Multi-Encryption Approach

METHOD:

//Multi-Encryption Approach using X-tea &RC-6)//

X-tea_func a1(.out(w1),.x(x1),.delta(delta),.key1(key1),.key2(key2).sl(sl),.rst(rst),.clk(clk));

X-tea_func a2(.out(w2),.x(x2),.delta(delta),.key1(key3),.key2(key4).sl(sl),.rst(rst),.clk(clk));

Rc6_func a3(.a(w3),.b(w4),.c(w5),.d(w6),.A_out(out1),.B_out(out2).C_out(out3),.D_out(out4),.clk(clk),.add(add));

//Multi-Encryption Approach using X-tea &RC-6)//

PROCEDURE 1: // X-tea- Pipelined Approach//

X-tea_func (Out, S1, Delta_val, key₁, key₂, Q, Z)

1. For each Plaintext Bits X₁ ∈ X¡

2. For each Ciphertext Bit Out₁ ∈ Out¡

3. If (s1=1^S=0)

4. //splitter// assign out₁=in[31:0]; assign out₂=in[63:32];s

5. While(z>= 32) do {

6. For each X¡, Out¡ (Out¡[1] = ((in<<4)^in<<5) + in))

7. For each X¡, Out¡ (Out¡[2]= Delta_val +( key₁,+ key₂)) 8. P= Out¡[1]⊕ Out¡[2] 9. }

10. Else Exit

11. If Q∈ X¡ then Call KSP_func

12. Else Subtract ( Q= Q-{X¡})

13. Exit


May - 2013, pp. 112-120


PROCEDURE 2: // Rc-6 Pipelined Approach// Rc6_func (M_out,N_out,O_out,P_out,m,n,o,p,add,clk);

//ENCRYPTION ROUTINE_Rc_6//

1. DEFINE parameter r=20;

2. for(i=1;i<=r; i=i+1)

3. begin

4. t=n_mul << log_n;

5. u=p_mul << log_p;

6. m_int =((m_int^t) << u)+s[2*i];

7. o_int =((o_int^u) << t)+s[2*i+1];

8. {m_int,n_int,o_int,p_int}={n_int,o_int,p_int,m_int;

9. End

//DECRYPTION ROUTINE_Rc_6//

1. for(j=1;j<=r; j=j+1)

2. begin

3. {M_int,N_int,O_int,P_int}={P_int,M_int,N_int,O_int};

4. U=p_mull << logg_p;

5. T=n_mull << logg_n;

6. O_int = ((O_int-s[2*j+1])>> T)^U;

7. M_int = ((M_int-s[2*j]) >> U)^T;

8. End

PROCEDURE 3: // KSP_func//Kogge stone adder design

KSP_func (x, y, sum, Cin, Cout) // here Gray cells used without group propagate and group generate//

1. Begin

2. Defining Levels(n): = 8 i.e. // Number of levels used here is n=4

// LEVEL 1 //

3. Define Black Cell Level (1A-7A) =G_Z[0-6], P_Z[1-7], G_Z[1-7], P_Z[0-6], G_A[1-7], P_A[1-7]

4. Define Gray Cell Level (OA)= Cin, P_Z[0], G_Z[0], G_A[0]

// LEVEL 2 //

5. Define Gray Cell Level (1B)= cin, P_A[1], G_A[1], G_B[1]

6. Define Gray Cell Level (2B)= G_A[0], P_A[2], G_A[2], G_B[2]

7. Define Black Cell Level (3B-7B) = G_A[1-5], P_A[3-7], G_A[3-7], P_A[1-5], G_B[3-7], P_B[3-7]

// LEVEL 3 //

8. Define Gray Cell Level(3C) =cin, P_B[3], G_B[3], G_C[3] 9. Define Gray Cell level(4C-6C)(G_A[0-2], P_B[4-6], G_B[4-6], G_C[4-6]

10. Define Black Cell Level(7C) G_B[3], P_B[7], G_B[7], P_B[3], G_C[7], P_C[7]

// LEVEL 4 //

11. Define Gray Cell level (7D)=cin, P_C[7], G_C[7], Cout

The proposed algorithm is divided into certain set of inputs and respective outputs, Further it provides the details in the

form of three procedures. The procedure 1 provides the step by step approach in the creation 0f proposed pipelined

approach of x-tea, where the concept of FSM has been used, as described earlier, this procedure calls another

procedure_3 within its process which defines the process of Kogge stone adder which is the fastest adder used in the

process, it is designed into two different levels i.e. black level and gray level, each having its specific task respectively.

After designing the proposed modified approach of X-tea, another component i.e. Rc-6 is described in the procedure 2,

which says that output from the two modules of X-tea each of 32 bit, making it 128 bit (Since input for Rc-6 is 128 bit) is fetched as an input to Rc-6 module, This linking of two different approaches of cryptographic algorithm making it

more secure and powerful over an FPGA platform using HDL i.e. verilog as hardware description language is called

multi-encryption technique.

VI. HARDWARE ENVIRONMENT

Since we are concentrating on the hardware implementation of the proposed approach using cryptographic algorithms i.e.

X-tea and Rc-6, so the hardware platform which can be used comes in two flavours i.e. FPGA or ASIC, selection of such

platform depends on the application, designer of the particular application and its constraints. FPGA refers to Field

Programmable Gate Arrays which consist of collection of CLB’s which incorporates different operations and logic

depending upon the algorithm used .ASIC which refers to the application specific integrated circuits, this is usually used

when we have pre determined and specific task since it cannot be customized further and require proper training before handling such task. The following Table 1 will provide the generalized comparative analysis of both the hardware

environment; the parameters which will be focused are their purpose, cost factor, reusable component factor, flexibility and

their advantages& limitations


May - 2013, pp. 112-120


Table 1: Comparative Analysis of FPGA &ASIC

S.No. Parameters FPGA ASIC

1. Purpose Used for General

Purpose

Used for Application specific

needs of designer

2. Reusable Factor Provides reprogrammable

computing and can be

modified.

Design for specific need of

customer and it can’t be modified

or reprogrammed.

3. Cost Factor Cheaper, used for testing Expensive since it is application

specific

4. Flexibility Highly Flexible Low Flexibility

5. Advantages

1.Applicability on low

volume production

circuits,

2.Better & faster time to market

3.Simpler design cycle

4.Used for smaller

applications

5. No-upfront non-recurring

expenses

1.Applicability on high

volume production circuits

2.Low power requirements

3.Lower unit costs 4.Used for large design

applications

5. Full custom capability.

6. Disadvantages 1.Little more power

consumption

2. Limited Design Size

1.Development time is much

more than FPGA

2.Expensive design affair

3. Design Issues.

VII. RESULTS & DISCUSSIONS

The performance of the approach used is determined on XILINX platform using verilog as hardware description language. Optimization is achieved in terms of effective resource utilization in terms of LUT’s, no of input-output bonds, no of

registers used etc. Along with that hardware platform is designed with the optimized multi-encryption technique

A. RESULT OF EXECUTION TEST

In this paper, the results of cryptographic algorithms i.e. AES , proposed pipelined approach, Rc-6 approach and Multi-

encryption technique has been verified and compared with each other based on the parameters like no of registers used, no

of IOB’s, LUT’s etc. These parameters corresponds how effectively number of resources can be utilized and managed, the

below table verifies the analysis. The table below clearly specifies the comparative analysis of the algorithms used; from

the table we can evidently notice the different parameters, to achieve optimization the utilization of look up tables (LUT)

should be minimum, and it is clearly visible that LUT utilization is maximum in AES i.e. 447% and minimum in proposed

X-tea pipelined approach i.e. 1%. Similarly other parameters and corresponding values are described .It can be analysed from the table that significant of optimization can be achieved via X-tea and Multi-encryption technique (X-tea and Rc-6). .

Figure 5: Resource Utilization values


May - 2013, pp. 112-120


B. RESULT OF SIMULATION(WAVEFORMS) The waveform analysis of multi-encryption technique as well as individual components i.e. X-tea and Rc-6 is shown in the

following figures. These waveforms verify the simulation as well behaviour level of the approach designed. This simulation

can be done over ModelSim simulator or it can be effectively performed within Xilinx ISE suite.

Figure 6: X-tea (Pipelined approach) waveform Analysis

Figure 7: Rc-6 waveform Analysis

Figure 8: Multi-encryption waveform (I) Analysis

Figure 9: Multi-encryption waveform (II) Analysis


May - 2013, pp. 112-120


C. HARDWARE PLATFORM DESIGN IMPLEMENTATION The Xilinx Plan Ahead tool is embedded within the Xilinx ISE suite; it provides the post synthesis analysis and generates

the hardware platform in terms of either floor planning or Input-Output planning. After performing the syntax checking and

RTL or technology design from the Xilinx ISE suite, the Xilinx plan ahead fetch the code directly. The hardware design of

each of the components and multi-encryption technique is implemented below in the figures 10, 11&12

Figure 10: Hardware Design of Proposed X-tea Approach

Figure 11: Hardware Design of Rc-6 Approach

Figure 12: Hardware Design of Multi-Encryption Approach

VIII. CONCLUSION

This paper provides the hardware design of cryptographic algorithms i.e. X-tea & Rc-6 on FPGA using hardware

description language as verilog via Xilinx Plan Ahead simultaneously it provides verification via simulating on either

ModelSim or Xilinx ISE suite. The approach used in the process of multi-encryption is optimized in terms of resource

consumption. The combined approach is design in such a way that it increases the security level simultaneously it keeps

the check on the resources utilized during the process that the memory/area chip size, encryption time and its simplicity

is not hampered. The paper provides the new algorithm by combining the best of features of X-tea and Rc-6, this may

provide best algorithm with improvised security level and optimization of the resources.

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Rashi Kohli [1]

is an M.Tech student in the Department of Computer science & Engineering, ASET,

Amity University, Uttar Pradesh. She received her B.Tech degree in Information and Technology from

Amity University, India. Her research interests include Cryptography, network security and software

engineering domain.

Mr. Manoj Kumar [2]

is currently working as an Assistant Professor in the Department of Computer

science & Engineering, ASET, Amity University, Uttar Pradesh, India. He has received degrees in M.Sc,

M.Tech & PG Diploma. His research interests include Network Security, Embedded Systems & Algorithm

Design.

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