application of non-linear electronics in digital communication
TRANSCRIPT
Analog Approaches in Digital Receivers
محمدرضا ذهابی
هفته پژوهش و فناوری1387آذر 18
Target of the work Why Analog Realization?
Set of Equations
Circuittopology
Channel Encoder
Demodulation
Digital Source
Modulation
Channel
Filtering
Decoder
Target of the work General Communication System
Outline
• Introduction– Coding– Convolutional Codes
• Codes on Graphs• Analog Implementation• Simulation Results
Decoding on Analog Graph
Introduction Maximum Likelihood Decoding
Invalid CodewordValid CodewordObservation
ML Principle
Ĉ = argmax P(Y|C) c
Ĉ = argmin ||Y-C||² c
Exhaustive search 2k comparisons
Decoding Algorithm~ k
k : information length
Introduction Encoding and Decoding of CC.
Decoding
Encoding
yn2
un
yn1
un
yn2
yn1
Recursive Systematic Encoder Feed Forward Encoder
n-1 n n+1 n+2
Trellis of the code
2m
states
Outline
• Introduction• Codes on Graphs
– Principles of Graph – Log-Likelihood Ratio (LLR)– Operations on LLRs– convolutional code example
• Analog Implementation• Simulation Results
Decoding on Analog Graph
b1
Principles of Graph
b o1 o2
Two obs. for a bit
b2
xor
Decoding form
ulas
1 2 1 2 1 2( 0 | ) (1 )(1 )P b o o PP P P b o1 o2
Pb o
Pb o
Codes on Graphs
Log-Likelihood Ratio (LLR)
Codes on Graphs
Pb oPb o
Lboln
Pb o
expLbo
Pb oexpLboexpLbo
Operations on LLRs
Codes on Graphs
Lbo1o2Lbo1Lbo2
tanh Lbo1o22tanh Lb1o12tanh Lb2o22
b o1 o2
b1
b2
xor b o1 o2
Messages in graphs
Check node
Codes on Graphs
Symbol node
Lbo1o2Lbo1Lbo2
tanh Lbo1o22
tanh Lb1o12tanh Lb2o22
(7,5) convolutional code example
yn
un
Codes on Graphs
IN GD
IN GN
UY X
Outline
• Introduction• Codes on Graphs• Analog Implementation
– Probability to LLR– LLR to Probability– Generic Variable Node– Generic Function Node– Schematic Diagram of Decoder
• Simulation Results
Decoding on Analog Graph
Analog ImplementationProbability to LLR
vo i1lnVT i2
Pb oPb o
Lboln
vo Lbo
VT
i1 Pb oi1i2
i2 Pb oi1i2
Analog ImplementationLLR to Probability
vo Lbo
VT
i1 Pb oi1i2
i2 Pb oi1i2
i1i1i2
expv/VT
i2i1i2
expv/VTexpv/VT
Pb o
expLbo
Pb oexpLboexpLbo
Analog Implementation Generic Symbol node
Tail current
Lbo1o2Lbo1Lbo2
vz=vxvy
Analog Implementation Generic check node
Tail current
tanh Lbo1o22tanh Lb1o12tanh Lb2o22tanh vz 2tanh vx 2tanh
vy 2
Analog Implementation (7,5) RSC schematic diagram
Outline
• Introduction• Codes on Graphs• Analog Implementation• Simulation Results
– Overview and setting up– Time Response– Speed and Performance versus a design parameter– Overall Performance (BER)
Decoding on Analog Graph
Overview and setting up
Simulation Results
Decoder
16
8
8
Channel output
Decoded bits
CMOS model : AMS0.35µm (Sub-threshold)
Power supply : 5 V
Power Consumption : 0.3 mW
Decoder : (7,5)oct RSC or non-RSC Codes
Codeword Length : 16 Code Rate : 0.5
Time response
Simulation Results
Effect of tail current
Simulation Results
0 20 40 6010-3
10-2
10-1
100
10 nA
100 nA
1000 nA
Time (µS)
BER
Tail current: 10 nA
Simulation Results Bit-Error-Rate and benchmark
Conclusions and PerspectiveDecoding on Analog Graph
• No need for input ADC• No clock input• Parallel structure• Soft input (gain +3dB gain)• Soft and hard outputs• Very small transistor count
Conclusions and Perspective
• Using current to represent the LLR may reduce the complexity of the summation blocks used in variable nodes.
• Designing competitive analog topologies for realization of graph’s nodes that cope with low consumption requirements.
• Finding other applications suitable for analog implementation. For example the issue of synchronization in MIMO receivers is under investigation.
• Systematic modeling of analog decoders that incorporates transient, mismatching and other secondary effects.
• Extending the idea to non-binary cases such as joint channel equalization and decoding problem.
Decoding on Analog Graph
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Analog Approaches in Digital Receivers