approved american national standard · 2016-10-26 · ansi/vita 65-2010 (r2012) page 2 of 555...

VITA

PO Box 19658, Fountain Hills, AZ 85269 PH: 480-837-7486

Email: [email protected] URL: http://www.vita.com

Approved American National Standard

ANSI/VITA 65-2010 (R2012) OpenVPX™ System Specification

Abstract The OpenVPX System Specification was created to bring versatile system architectural solutions to the VPX market. Based on the extremely flexible VPX family of standards, the OpenVPX standard uses module mechanical, connectors, thermal, communications protocols, utility, and power definitions provided by specific VPX standards and then describes a series of standard profiles that define slots, backplanes, modules, and Standard Development Chassis.

Approved February 2012 American National Standards Institute, Inc.

ANSI/VITA 65-2010 (R2012) of 555 February 2012

American National Standard

Approval of an American National Standard requires verification by ANSI that the requirements for due process, consensus, and other criteria for approval have been met by the standards developer. Consensus is established when, in the judgment of the ANSI Board of Standards Review, substantial agreement has been reached by directly and materially affected interests. Substantial agreement means much more than a simple majority, but not necessarily unanimity. Consensus requires that all views and objections be considered, and that a concerted effort be made toward their resolution. The use of American National Standards is completely voluntary; their existence does not in any respect preclude anyone, whether he has approved the standards or not, from manufacturing, marketing, purchasing, or using products, processes, or procedures not conforming to the standards. The American National Standards Institute does not develop standards and will in no circumstances give an interpretation of any American National Standard. Moreover, no person shall have the right or authority to issue an interpretation of an American National Standard in the name of the American National Standard Institute. Requests for interpretations should be addressed to the secretariat or sponsor whose name appears on the title page of this standard. CAUTION NOTICE: This American National Standard may be revised or withdrawn at any time. The procedures of the American National Standards Institute require that action be taken periodically to reaffirm, revise, or withdraw this standard. Purchases of American National Standards may receive current information on all standards by calling or writing the American National Standards Institute.

Published by VMEbus International Trade Association (VITA) PO Box 19658, Fountain Hills, AZ 85269 Copyright © 2012 by VMEbus International Trade Association All rights reserved. Permission of the publisher is required to reproduce this document or any part of it. Printed in the United States of America - R1.1 ISBN 1-885731-58-2


Table of Contents

1 INTRODUCTION ....................................................................................................................................... 29

1.1 OPENVPX KEY ELEMENT DESCRIPTIONS ................................................................................................................ 30 1.1.1 Backplane Profiles ................................................................................................................................ 30 1.1.2 Slot Profiles .......................................................................................................................................... 30 1.1.3 Standard Development Chassis Profiles ............................................................................................... 30 1.1.4 Module Profiles ................................................................................................................................... 31

1.2 OPENVPX DOCUMENT STRUCTURE DESCRIPTION .................................................................................................... 31 1.3 TERMINOLOGY .................................................................................................................................................. 36

1.3.1 Specification Key Words ....................................................................................................................... 36 1.3.2 Glossary ............................................................................................................................................... 38 1.3.3 Profile Names – Use and Construction ................................................................................................. 45 1.3.4 Backplane Profile Topologies ............................................................................................................... 50

1.4 ADDING NEW PROFILES TO THIS STANDARD ........................................................................................................... 56 1.5 REFERENCES ..................................................................................................................................................... 56

1.5.1 VITA Standards..................................................................................................................................... 57 1.5.2 Other Standards ................................................................................................................................... 58

1.6 ORDER OF PRECEDENCE ...................................................................................................................................... 58

2 OPENVPX COMPLIANCE ........................................................................................................................... 59

2.1 COMPLIANCE .................................................................................................................................................... 59 2.1.1 Statement of Compliance ..................................................................................................................... 59 2.1.2 Verification Method Notation .............................................................................................................. 60 2.1.3 Compatibility ........................................................................................................................................ 60

2.2 METHODS ........................................................................................................................................................ 60 2.2.1 Inspection ............................................................................................................................................. 61 2.2.2 Demonstration ..................................................................................................................................... 61 2.2.3 Analysis ................................................................................................................................................ 61 2.2.4 Test ...................................................................................................................................................... 62

3 UTILITY PLANE ......................................................................................................................................... 63

3.1 MAXIMUM NUMBER OF SLOTS ............................................................................................................................ 63 3.2 POWER DISTRIBUTION ........................................................................................................................................ 63

3.2.1 Power Distribution Profiles for 5V and 12V primary power input modules ......................................... 63 3.2.2 Source of VBAT ..................................................................................................................................... 64 3.2.3 Safety Ground ...................................................................................................................................... 64 3.2.4 Inrush (Surge) Current .......................................................................................................................... 64

3.3 ELECTRICAL STANDARDS FOR DRIVERS AND RECEIVERS .............................................................................................. 64 3.3.1 Low Current Open-Drain Electrical Characteristics .............................................................................. 65 3.3.2 Lower Current Open-Drain Electrical Characteristics ........................................................................... 66 3.3.3 High Current Open-Drain Electrical Characteristics ............................................................................. 67

3.4 SYSTEM CONTROL SIGNALS ................................................................................................................................. 68 3.4.1 System Controller (SYS_CON) ............................................................................................................... 68 3.4.2 System Reset (SYSRESET*) ................................................................................................................... 69 3.4.3 Module Maskable Reset (MaskableReset*) ......................................................................................... 70 3.4.4 Non-Volatile Memory Read Only (NVMRO) ......................................................................................... 71 3.4.5 System Management Buses (SM[3..0]) ................................................................................................ 72 3.4.6 Geographic Address Field..................................................................................................................... 73


3.4.7 JTAG Port ............................................................................................................................................. 73 3.4.8 User I/O ................................................................................................................................................ 73 3.4.9 Auxiliary Resets (AXreset*) .................................................................................................................. 74

3.5 SYSTEM REFERENCE CLOCKS ................................................................................................................................ 74 3.5.1 REF_CLK+/- Reference Clock ................................................................................................................ 74 3.5.2 AUX_CLK+/- Reference Clock ............................................................................................................... 75 3.5.3 P1-REF_CLK-SE ..................................................................................................................................... 76

3.6 BUSSED GPIO (GDISCRETE1) .............................................................................................................................. 77 3.7 OPENVPX VITA 46.0 CONNECTOR P0/J0 AND P1/J1 CONNECTOR PIN ASSIGNMENTS ................................................. 78

4 MECHANICAL – GENERAL SPECIFICATIONS ............................................................................................... 82

4.1 SLOT PITCH ...................................................................................................................................................... 82 4.2 CONNECTOR FAMILY .......................................................................................................................................... 83 4.3 KEYING ............................................................................................................................................................ 83 4.4 RTM CONNECTORS ........................................................................................................................................... 84

5 PROTOCOL SPECIFIC ................................................................................................................................ 85

5.1 ETHERNET ........................................................................................................................................................ 85 5.1.1 1000BASE-BX ....................................................................................................................................... 85 5.1.2 1000BASE-KX ........................................................................................................................................ 85 5.1.3 1000BASE-T .......................................................................................................................................... 85 5.1.4 10GBASE-BX4 ....................................................................................................................................... 86 5.1.5 10GBASE-KX4 ....................................................................................................................................... 86 5.1.6 10GBASE-T ........................................................................................................................................... 86

5.2 SERIAL RAPIDIO® (SRIO) .................................................................................................................................... 86 5.3 PCI-EXPRESS® (PCIE®) ..................................................................................................................................... 87

5.3.1 PCIe Gen 2 Common Reference Clock Implemented as REF_CLK on P0/J0 .......................................... 88 5.3.2 PCIe Gen 2 Common Reference Clock Implemented on Other Than REF_CLK pins on P0/J0 ............... 88

5.4 INFINIBAND® (IB) .............................................................................................................................................. 92

6 COMMON TO 6U AND 3U — SLOT PROFILES ............................................................................................ 93

6.1 ORDER OF PRECEDENCE ...................................................................................................................................... 93 6.2 COMMON REQUIREMENTS FOR ALL SLOT PROFILES ................................................................................................. 93

6.2.1 Reserved pins ....................................................................................................................................... 93 6.2.2 Which lanes, ports and pins are used (unused = reserved) .................................................................. 94 6.2.3 Plug-In Module Compatibility with Multiple Slot Profiles .................................................................... 94 6.2.4 Assigning Lanes Into Ports ................................................................................................................... 94

6.3 COMMON REQUIREMENTS FOR SLOT PROFILES USING VITA 46.0 CONNECTORS. .......................................................... 99 6.3.1 Pin Assignment Tables for Differential Connectors .............................................................................. 99 6.3.2 Pin Assignment Tables for Single-Ended Connectors ......................................................................... 103 6.3.3 User Defined ...................................................................................................................................... 103

6.4 COMMON REQUIREMENTS FOR SLOT PROFILES USING VITA 46.0 AND VITA 67 CONNECTORS ..................................... 109 6.4.1 Pin Assignment Tables for VITA 46.0 Differential Connectors ........................................................... 109 6.4.2 Pin Assignment Tables for Single-Ended Connectors ......................................................................... 109 6.4.3 User Defined ...................................................................................................................................... 110

7 COMMON TO 6U AND 3U — BACKPLANE PROFILES ................................................................................ 111

7.1 ORDER OF PRECEDENCE .................................................................................................................................... 111 7.2 INTERCONNECTING SLOTS WITH PIPES ................................................................................................................. 111

7.2.1 Slot Profiles Labeled as Lanes ............................................................................................................ 112 7.2.2 Slot Profiles Labeled as Thin Pipe Pairs A thru D ................................................................................ 112

7.3 PORT JUMBLING .............................................................................................................................................. 113 7.4 BACKPLANE CHANNEL GBAUD RATE .................................................................................................................... 113


7.5 SYSTEM MANAGEMENT .................................................................................................................................... 113

8 COMMON TO 6U AND 3U — MODULE PROFILES ..................................................................................... 114

8.1 ORDER OF PRECEDENCE .................................................................................................................................... 114 8.2 6U AND 3U MODULE COOLING TYPES ................................................................................................................ 114

8.2.1 6U and 3U VITA 48.1 Air-Cooled Modules ......................................................................................... 114 8.2.2 6U and 3U VITA 48.2 Conduction-Cooled Modules ............................................................................ 116

8.3 USER DEFINED PINS ......................................................................................................................................... 117 8.4 UNUSED PORTS AND LANES ............................................................................................................................... 117 8.5 PLUG-IN MODULE COMPLIANCE WITH MULTIPLE MODULE PROFILES ........................................................................ 117

9 COMMON TO 6U AND 3U — STANDARD DEVELOPMENT CHASSIS PROFILES ........................................... 118

9.1 ORDER OF PRECEDENCE .................................................................................................................................... 118 9.2 6U AND 3U VITA 48.1 AIR-COOLED STANDARD DEVELOPMENT CHASSIS ................................................................. 118 9.3 6U AND 3U VITA 48.2 CONDUCTION-COOLED CHASSIS ........................................................................................ 119

10 6U SLOT PROFILES .................................................................................................................................. 121

10.1 6U SLOT PROFILES COMMON SECTION ................................................................................................................ 121 10.2 6U PAYLOAD SLOT PROFILES USING VITA 46.0 CONNECTORS ................................................................................ 121

10.2.1 Payload Slot Profile SLT6-PAY-4F1Q2U2T-10.2.1 ............................................................................... 122 10.2.2 Payload Slot Profile SLT6-PAY-4F2T-10.2.2 ........................................................................................ 127 10.2.3 Payload Slot Profile SLT6-PAY-8F-10.2.3 ............................................................................................ 131 10.2.4 Payload Slot Profile SLT6-PAY-4F16U-10.2.4 ..................................................................................... 136 10.2.5 Payload Slot Profile SLT6-PAY-2F2U2T-10.2.5 ................................................................................... 140 10.2.6 Payload Slot Profile SLT6-PAY-4F1Q2U2T-10.2.6 ............................................................................... 144 10.2.7 Payload Slot Profile SLT6-PAY-4F2Q2U2T-10.2.7 ............................................................................... 149

10.3 6U PERIPHERAL SLOT PROFILES USING VITA 46.0 CONNECTORS ............................................................................. 154 10.3.1 Peripheral Slot Profile SLT6-PER-4F-10.3.1 ........................................................................................ 155 10.3.2 Peripheral Slot Profile SLT6-PER-2F-10.3.2 ........................................................................................ 159 10.3.3 Peripheral Slot Profile SLT6-PER-4U-10.3.3 ........................................................................................ 163 10.3.4 Peripheral Slot Profile SLT6-PER-1F-10.3.4 ........................................................................................ 167 10.3.5 Peripheral Slot Profile SLT6-PER-1Q-10.3.5 ........................................................................................ 171

10.4 6U SWITCH SLOT PROFILES USING VITA 46.0 CONNECTORS .................................................................................. 176 10.4.1 Switch Slot Profile SLT6-SWH-20U19F-10.4.1 .................................................................................... 177 10.4.2 Switch Slot Profile SLT6-SWH-16U20F-10.4.2 .................................................................................... 183 10.4.3 Switch Slot Profile SLT6-SWH-24F-10.4.3 ........................................................................................... 189 10.4.4 Switch Slot Profile SLT6-SWH-4F24T-10.4.4 ....................................................................................... 194 10.4.5 Switch Slot Profile SLT6-SWH-16U16F-10.4.5 .................................................................................... 199

10.5 6U MISCELLANEOUS SLOT PROFILES USING VITA 46.0 CONNECTORS ...................................................................... 205 10.5.1 VME Bridge Slot Profile SLT6-BRG-4F1V2T-10.5.1 ............................................................................. 206 10.5.2 VME Bridge Slot Profile SLT6-BRG-4F1V-10.5.2 ................................................................................. 211

11 6U BACKPLANE PROFILES ....................................................................................................................... 216

11.1 6U BACKPLANE PROFILES COMMON SECTION ....................................................................................................... 221 11.2 6U BACKPLANE PROFILES USING VITA 46.0 CONNECTORS ..................................................................................... 221

11.2.1 Common Section for 6U Backplanes Using VITA 46.0 Connectors ..................................................... 221 11.2.2 16-Slot — BKP6-CEN16-11.2.2-n (14 Payload + 2 Switch) ................................................................. 224 11.2.3 20-Slot — BKP6-CEN20-11.2.3-n (18 Payload + 2 Switch) ................................................................. 230 11.2.4 10-Slot — BKP6-CEN10-11.2.4-n (9 Payload + 1 Switch) ................................................................... 236 11.2.5 5-Slot — BKP6-CEN05-11.2.5-n (4 Payload + 1 Switch) ..................................................................... 242 11.2.6 10-Slot — BKP6-CEN10-11.2.6-n (8 Payload + 2 Switch) ................................................................... 249 11.2.7 10-Slot — BKP6-CEN10-11.2.7-n (8 Payload + 2 Switch) ................................................................... 255 11.2.8 6-Slot — BKP6-CEN06-11.2.8-n (5 Payload + 1 Switch) ..................................................................... 259


11.2.9 12-Slot — BKP6-CEN12-11.2.9-n (10 Payload + 2 Switch) ................................................................. 263 11.2.10 6-Slot — BKP6-DIS06-11.2.10-n (5 Payload + 1 Switch) ..................................................................... 267 11.2.11 17-Slot — BKP6-HYB17-11.2.11-n (12 Payload + 3 VME + 2 Switch) ............................................... 271 11.2.12 8-Slot — BKP6-HYB08-11.2.12-n (1 Payload + 3 Peripheral + 1 VME Bridge + 3 VME) ..................... 276 11.2.13 9-Slot — BKP6-CEN09-11.2.13-n (1 Payload + 8 Peripheral) ............................................................. 280 11.2.14 6-Slot — BKP6-CEN06-11.2.14-n (1 Payload + 5 Peripheral) ............................................................. 283 11.2.15 6-Slot — BKP6-DIS06-11.2.15-n (5 Payload + 1 Switch) ..................................................................... 287 11.2.16 5-Slot — BKP6-DIS05-11.2.16-n (5 Payload) ...................................................................................... 291 11.2.17 16-Slot — BKP6-CEN16-11.2.17-n (14 Payload + 2 Switch) ............................................................... 294 11.2.18 6-Slot — BKP6-DIS06-11.2.18-n (6 Payload) ...................................................................................... 301 11.2.19 9-Slot — BKP6-DIS09-11.2.19-n (9 payload) ...................................................................................... 306 11.2.20 7-Slot — BKP6-HYB07-11.2.20-n (3 Payload + 2 VME Bridge + 2 VME) ............................................. 311

12 6U MODULE PROFILES ............................................................................................................................ 315

12.1 6U MODULE PROFILES COMMON SECTION .......................................................................................................... 315 12.1.1 6U Module Cooling Types .................................................................................................................. 315 12.1.2 Power voltages and System Management ........................................................................................ 315

12.2 6U PAYLOAD MODULE PROFILES USING VITA 46.0 CONNECTORS ........................................................................... 317 12.2.1 Payload Module Profiles MOD6-PAY-4F1Q2U2T-12.2.1-n ................................................................. 317 12.2.2 Payload Module Profiles MOD6-PAY-4F2T-12.2.2-n .......................................................................... 319 12.2.3 Payload Module Profiles MOD6-PAY-8F-12.2.3-n .............................................................................. 320 12.2.4 Payload Module Profiles MOD6-PAY-4F16U-12.2.4-n ....................................................................... 321 12.2.5 Payload Module Profiles MOD6-PAY-2F2U2T-12.2.5-n ..................................................................... 322 12.2.6 Payload Module Profiles MOD6-PAY-4F1Q2U2T-12.2.6-n ................................................................. 323 12.2.7 Payload Module Profiles MOD6-PAY-4F2Q2U2T-12.2.7-n ................................................................. 325

12.3 6U PERIPHERAL MODULE PROFILES USING VITA 46.0 CONNECTORS ....................................................................... 327 12.3.1 Peripheral Module Profiles MOD6-PER-4F-12.3.1-n ......................................................................... 327 12.3.2 Peripheral Module Profiles MOD6-PER-2F-12.3.2-n .......................................................................... 328 12.3.3 Peripheral Module Profiles MOD6-PER-4U-12.3.3-n .......................................................................... 329 12.3.4 Peripheral Module Profiles MOD6-PER-1F-12.3.4-n .......................................................................... 330 12.3.5 Module Profiles MOD6-PER-1Q-12.3.5-n ........................................................................................... 331

12.4 6U SWITCH MODULE PROFILES USING VITA 46.0 CONNECTORS ............................................................................. 332 12.4.1 Switch Module Profiles MOD6-SWH-20U19F-12.4.1-n ...................................................................... 332 12.4.2 Switch Module Profiles MOD6-SWH-16U20F-12.4.2-n ...................................................................... 334 12.4.3 Switch Module Profiles MOD6-SWH-24F-12.4.3-n ............................................................................. 336 12.4.4 Switch Module Profiles MOD6-SWH-4F24T-12.4.4-n ......................................................................... 337 12.4.5 Module Profiles MOD6-SWH-16U16F-12.4.5-n ................................................................................. 338

12.5 6U MISCELLANEOUS MODULE PROFILES USING VITA 46.0 CONNECTORS ................................................................. 339 12.5.1 Bridge Module Profiles MOD6-BRG-4F1V2T-12.5.1-n ........................................................................ 339 12.5.2 Bridge Module Profiles MOD6-BRG-4F1V-12.5.2-n............................................................................ 341

13 6U STANDARD DEVELOPMENT CHASSIS PROFILES................................................................................... 342

13.1 6U STANDARD DEVELOPMENT CHASSIS PROFILES COMMON SECTION ....................................................................... 342 13.1.1 6U VITA 48.1 Air-Cooled Standard Development Chassis .................................................................. 342 13.1.2 6U VITA 48.2 Conduction-Cooled Standard Development Chassis..................................................... 342

13.2 6U STANDARD DEVELOPMENT CHASSIS PROFILE DEFINITIONS ................................................................................. 342

14 3U SLOT PROFILES .................................................................................................................................. 345

14.1 3U SLOT PROFILES COMMON SECTION ................................................................................................................ 345 14.2 3U PAYLOAD SLOT PROFILES USING VITA 46.0 CONNECTORS ................................................................................ 345

14.2.1 Payload Slot Profile SLT3-PAY-2F1F2U-14.2.1 ................................................................................... 346 14.2.2 Payload Slot Profile SLT3-PAY-1F2F2U-14.2.2 ................................................................................... 349 14.2.3 Payload Slot Profile SLT3-PAY-2F2U-14.2.3 ....................................................................................... 352


14.2.4 Payload Slot Profile SLT3-PAY-1F1F2U-14.2.4 ................................................................................... 355 14.2.5 Payload Slot Profile SLT3-PAY-2F2T-14.2.5 ........................................................................................ 358 14.2.6 Payload Slot Profile SLT3-PAY-1D-14.2.6 ........................................................................................... 361 14.2.7 Payload Slot Profile SLT3-PAY-2F-14.2.7 ............................................................................................ 363 14.2.8 Payload Slot Profile SLT3-PAY-1F4U-14.2.8 ....................................................................................... 365 14.2.9 Payload Slot Profile SLT3-PAY-8U-14.2.9 ........................................................................................... 367 14.2.10 Payload Slot Profile SLT3-PAY-1F1U-14.2.10 ..................................................................................... 369 14.2.11 Payload Slot Profile SLT3-PAY-2F4F2U-14.2.11 ................................................................................. 372 14.2.12 Payload Slot Profile SLT3-PAY-1F2U-14.2.12 ..................................................................................... 376 14.2.13 Payload Slot Profile SLT3-PAY-3F2U-14.2.13 ..................................................................................... 379

14.3 PERIPHERAL SLOT PROFILES USING VITA 46.0 CONNECTORS .................................................................................. 382 14.3.1 Peripheral Slot Profile SLT3-PER-2F-14.3.1 ........................................................................................ 382 14.3.2 Peripheral Slot Profile SLT3-PER-1F-14.3.2 ........................................................................................ 384 14.3.3 Peripheral Slot Profile SLT3-PER-1U-14.3.3 ........................................................................................ 386

14.4 SWITCH SLOT PROFILES USING VITA 46.0 CONNECTORS ........................................................................................ 388 14.4.1 Switch Slot Profile SLT3-SWH-6F6U-14.4.1 ........................................................................................ 388 14.4.2 Switch Slot Profile SLT3-SWH-8F-14.4.2 ............................................................................................. 392 14.4.3 Switch Slot Profile SLT3-SWH-2F24U-14.4.3 ...................................................................................... 395 14.4.4 Switch Slot Profile SLT3-SWH-4F-14.4.4 ............................................................................................. 399 14.4.5 Switch Slot Profile SLT3-SWH-2F8U-14.4.5 ........................................................................................ 401 14.4.6 Switch Slot Profile SLT3-SWH-16T-14.4.6 ........................................................................................... 404 14.4.7 Switch Slot Profile SLT3-SWH-1F14T-14.4.7 ....................................................................................... 407 14.4.8 Switch Slot Profile SLT3-SWH-2F12T-14.4.8 ....................................................................................... 410 14.4.9 Switch Slot Profile SLT3-SWH-6F8U-14.4.9 ........................................................................................ 413

14.5 3U MISCELLANEOUS SLOT PROFILES USING VITA 46.0 CONNECTORS ...................................................................... 416 14.5.1 Storage Slot Profile SLT3-STO-2U-14.5.1 ............................................................................................ 417

14.6 3U PAYLOAD SLOT PROFILES USING VITA 46.0 AND 67 CONNECTORS...................................................................... 420 14.6.1 Payload Slot Profile SLT3-PAY-1F1F2U4R-14.6.1 ............................................................................... 420 14.6.2 Payload Slot Profile SLT3-PAY-4F4R-14.6.2 ........................................................................................ 424

15 3U BACKPLANE PROFILES ....................................................................................................................... 427

15.1 3U BACKPLANE PROFILES COMMON SECTION ....................................................................................................... 432 15.2 3U BACKPLANE PROFILES USING VITA 46.0 CONNECTORS ..................................................................................... 432

15.2.1 Common Section for 3U Backplanes Using VITA 46.0 Connectors ..................................................... 432 15.2.2 6-Slot — BKP3-CEN06-15.2.2-n (5 Payloads + 1 Switch) .................................................................... 435 15.2.3 7-Slot — BKP3-CEN07-15.2.3-n (6 Payloads + 1 Switch) .................................................................... 441 15.2.4 10-Slot — BKP3-CEN10-15.2.4-n (8 Payload + 2 Switch) ................................................................... 445 15.2.5 10-Slot - BKP3-CEN10-15.2.5-n (8 Payload + 2 Switch) ...................................................................... 450 15.2.6 12-Slot — BKP3-CEN12-15.2.6-n (10 Payloads + 2 Switch) ............................................................... 456 15.2.7 6-Slot — BKP3-DIS06-15.2.7-n (5 Payload + 1 Switch) ....................................................................... 461 15.2.8 2-Slot — BKP3-DIS02-15.2.8-n (1 Payload + 1 Peripheral) ................................................................. 466 15.2.9 3-Slot — BKP3-CEN03-15.2.9-n (1 Payload + 2 Peripheral) ................................................................ 469 15.2.10 6-Slot — BKP3-CEN06-15.2.10-n (1 Payload + 5 Peripheral) .............................................................. 472 15.2.11 9-Slot — BKP3-CEN09-15.2.11-n (1 Payload + 8 Peripheral) .............................................................. 475 15.2.12 6-Slot — BKP3-CEN06-15.2.12-n (1 Payload + 4 Peripheral + 1 Switch) ............................................ 478 15.2.13 5-Slot — BKP3-DIS05-15.2.13-n (3 Payload + 2 Peripheral) ............................................................... 481 15.2.14 6-Slot — BKP3-DIS06-15.2.14-n (5 Payload + 1 Switch) ..................................................................... 484 15.2.15 8-Slot — BKP3-CEN08-15.2.15-n (6 Payloads + 2 integrated Switches) ............................................. 488 15.2.16 8-Slot — BKP3-CEN08-15.2.16-n (6 Payloads + 2 segregated Switches) ............................................ 493 15.2.17 9-Slot — BKP3-CEN09-15.2.17-n (8 Payload + 1 Switch) ................................................................... 498

15.3 3U BACKPLANE PROFILES USING VITA 46.0 AND 67 CONNECTORS .......................................................................... 504 15.3.1 Common Section for 3U Backplanes Using VITA 46.0 and VITA 67 Connectors ................................. 504 15.3.2 5-Slot — BKP3-DIS05-15.3.2-n (2 Payload + 3 Payload with RF Cavities) .......................................... 505


15.3.3 5-Slot — BKP3-CEN05-15.3.3-n (2 Payload + 2 Payload with RF Cavities and 1 Switch).................... 508

16 3U MODULE PROFILES ............................................................................................................................ 513

16.1 3U MODULE PROFILES COMMON SECTION .......................................................................................................... 513 16.1.1 Module Cooling Types ........................................................................................................................ 513 16.1.2 Power voltages and System Management ........................................................................................ 513

16.2 3U PAYLOAD MODULE PROFILES USING VITA 46.0 CONNECTORS ........................................................................... 514 16.2.1 Payload Module Profiles MOD3-PAY-2F1F2U-16.2.1-n ..................................................................... 514 16.2.2 Payload Module Profiles MOD3-PAY-1F2F2U-16.2.2-n ..................................................................... 516 16.2.3 Payload Module Profiles MOD3-PAY-2F2U-16.2.3-n ......................................................................... 518 16.2.4 Payload Module Profiles MOD3-PAY-1F1F2U-16.2.4-n ..................................................................... 520 16.2.5 Payload Module Profiles MOD3-PAY-2F2T-16.2.5-n .......................................................................... 522 16.2.6 Payload Module Profiles MOD3-PAY-1D-16.2.6-n ............................................................................. 523 16.2.7 Payload Module Profiles MOD3-PAY-2F-16.2.7-n .............................................................................. 524 16.2.8 Payload Module Profiles MOD3-PAY-1F4U-16.2.8-n ......................................................................... 525 16.2.9 Payload Module Profiles MOD3-PAY-8U-16.2.9-n ............................................................................. 526 16.2.10 Payload Module Profiles MOD3-PAY-2F4F2U-16.2.10-n ................................................................... 527 16.2.11 Payload Module Profiles MOD3-PAY-1F2U-16.2.11-n ....................................................................... 529 16.2.12 Payload Module Profiles MOD3-PAY-3F2U-16.2.12-n ....................................................................... 530

16.3 3U PERIPHERAL MODULE PROFILES USING VITA 46.0 CONNECTORS ....................................................................... 531 16.3.1 Peripheral Module Profiles MOD3-PER-2F-16.3.1-n .......................................................................... 531 16.3.2 Peripheral Module Profiles MOD3-PER-1F-16.3.2-n .......................................................................... 532 16.3.3 Peripheral Module Profiles MOD3-PER-1U-16.3.3-n .......................................................................... 533

16.4 3U SWITCH MODULE PROFILES USING VITA 46.0 CONNECTORS ............................................................................. 534 16.4.1 Switch Module Profiles MOD3-SWH-6F6U-16.4.1-n .......................................................................... 534 16.4.2 Switch Module Profiles MOD3-SWH-8F-16.4.2-n ............................................................................... 536 16.4.3 Switch Module Profiles MOD3-SWH-2F24U-16.4.3-n ........................................................................ 537 16.4.4 Switch Module Profiles MOD3-SWH-1F4U-16.4.4-n .......................................................................... 538 16.4.5 Switch Module Profiles MOD3-SWH-4F-16.4.5-n ............................................................................... 539 16.4.6 Switch Module Profiles MOD3-SWH-2F8U-16.4.6-n .......................................................................... 540 16.4.7 Switch Module Profiles MOD3-SWH-16T-16.4.7-n............................................................................. 542 16.4.8 Switch Module Profiles MOD3-SWH-1F14T-16.4.8-n ......................................................................... 543 16.4.9 Switch Module Profiles MOD3-SWH-2F12T-16.4.9-n ......................................................................... 544 16.4.10 Switch Module Profiles MOD3-SWH-6F8U-16.4.10-n ........................................................................ 545

16.5 3U MISCELLANEOUS MODULE PROFILES USING VITA 46.0 CONNECTORS ................................................................. 547 16.5.1 Storage Module Profiles MOD3-STO-2U-16.5.1-n ............................................................................. 547

16.6 3U PAYLOAD MODULE PROFILES USING VITA 46.0 AND 67 CONNECTORS ................................................................ 548 16.6.1 Payload Module Profiles MOD3-PAY-1F1F2U4R-16.6.1-n ................................................................. 548 16.6.2 Payload Module Profiles MOD3-PAY-4F4R-16.6.2-n .......................................................................... 550

17 3U STANDARD DEVELOPMENT CHASSIS PROFILES................................................................................... 551

17.1 3U STANDARD DEVELOPMENT CHASSIS PROFILES COMMON SECTION ....................................................................... 551 17.1.1 3U VITA 48.1 Air-Cooled Standard Development Chassis .................................................................. 551 17.1.2 3U VITA 48.2 Conduction-Cooled Standard Development Chassis..................................................... 551

17.2 3U STANDARD DEVELOPMENT CHASSIS PROFILE DEFINITIONS ................................................................................. 551

18 6U/3U HYBRID BACKPLANE PROFILES ..................................................................................................... 554

19 6U/3U HYBRID STANDARD DEVELOPMENT CHASSIS PROFILES ................................................................ 555


List of Figures

Figure 1-1 System Interoperability Diagram with interface content ............................................ 29 Figure 1.2-1 Profile Tree Structure ............................................................................................... 32 Figure 1.2-2 Protocol Specific Structure ...................................................................................... 32 Figure 1.2-3 Slot Profile Structure ................................................................................................ 33 Figure 1.2-4 Backplane Profile Structure ..................................................................................... 34 Figure 1.2-5 Module Profile Structure .......................................................................................... 35 Figure 1.2-6 Standard Development Chassis Profile Structure .................................................... 36 Figure 1.3.3.1-1 Slot Profile Name Construct .............................................................................. 46 Figure 1.3.3.2-1 Backplane Profile Name Construct .................................................................... 47 Figure 1.3.3.3-1 Module Profile Name Construct ........................................................................ 48 Figure 1.3.4-1 Example of Single-Star Topology ......................................................................... 50 Figure 1.3.4-2 Example of Dual-Star Topology using two Switch Slots ..................................... 51 Figure 1.3.4-4 Example of Extended-Star Topology .................................................................... 52 Figure 1.3.4-5 Example of Full Mesh Topology .......................................................................... 53 Figure 1.3.4-6 Example of Partial Mesh Topology ...................................................................... 53 Figure 1.3.4-7 Examples of Daisy-Chain Topologies .................................................................. 54 Figure 1.3.4-8 Examples of Ring Topologies ............................................................................... 54 Figure 4-1 Backplane with pitch of 1.00 inch populated with 0.80, 0.85 and 1.00 in. pitch Plug-In

Modules ......................................................................................................... 83 Figure 5.3.2-1 Example of Multiple Separate PCIe Domains ...................................................... 89 Figure 5.3.2.1-1 Backplane clock source ...................................................................................... 90 Figure 5.3.2.2-1 Root Complex in one slot sourcing clock for other slot(s) ................................ 91 Figure 6.3-1 Even Differential Plug-In Module Wafer to Backplane Pin Mappings ................. 100 Figure 6.3-2 Odd Differential Plug-In Module Wafer to Backplane Pin Mappings .................. 101 Figure 8.2.1-1 P-Q curve example .............................................................................................. 115 Figure 9.2-1 Airflow direction .................................................................................................... 119 Figure 10.2.1-1 Payload Slot Profile SLT6-PAY-4F1Q2U2T-10.2.1 ........................................ 122 Figure 10.2.2-1 Payload Slot Profile SLT6-PAY-4F2T-10.2.2 .................................................. 127 Figure 10.2.3-1 Payload Slot Profile SLT6-PAY-8F-10.2.3 ...................................................... 131 Figure 10.2.4-1 Payload Slot Profile SLT6-PAY-4F16U-10.2.4 ............................................... 136 Figure 10.2.5-1 Payload Slot Profile SLT6-PAY-2F2U2T-10.2.5 ............................................. 140 Figure 10.2.6-1 Payload Slot Profile SLT6-PAY-4F1Q2U2T-10.2.6 ........................................ 144 Figure 10.2.7-1 Payload Slot Profile SLT6-PAY-4F2Q2U2T-10.2.7 ........................................ 149 Figure 10.3.1-1 Peripheral Slot Profile SLT6-PER-4F-10.3.1 ................................................... 155 Figure 10.3.2-1 Peripheral Slot Profile SLT6-PER-2F-10.3.2 ................................................... 159 Figure 10.3.3-1 Peripheral Slot Profile SLT6-PER-4U-10.3.3 ................................................... 163 Figure 10.3.4-1 Peripheral Slot Profile SLT6-PER-1F-10.3.4 ................................................... 167


Figure 10.3.5-1 Peripheral Slot Profile SLT6-PER-1Q-10.3.5 ................................................... 171 Figure 10.4.1-1 Switch Slot Profile SLT6-SWH-20U19F-10.4.1 .............................................. 177 Figure 10.4.2-1 Switch Slot Profile SLT6-SWH-16U20F-10.4.2 .............................................. 183 Figure 10.4.3-1 Switch Slot Profile SLT6-SWH-24F-10.4.3 ..................................................... 189 Figure 10.4.4-1 Switch Slot Profile SLT6-SWH-4F24T-10.4.4 ................................................. 194 Figure 10.4.5-1 Switch Slot Profile SLT6-SWH-16U16F-10.4.5 .............................................. 199 Figure 10.5.1-1 VME Bridge Slot Profile SLT6-BRG-4F1V2T-10.5.1 ..................................... 206 Figure 10.5.2-1 Payload Slot Profile SLT6-BRG-4F1V-10.5.2 ................................................. 211 Figure 11.2.2-1 Topology of BKP6-CEN16-11.2.2-n ................................................................ 224 Figure 11.2.2-2 Expansion Plane Lanes of BKP6-CEN16-11.2.2-n .......................................... 225 Figure 11.2.3-1 Topology of BKP6-CEN20-11.2.3-n ................................................................ 230 Figure 11.2.3-2 Expansion Plane Lanes of BKP6-CEN20-11.2.3-n .......................................... 231 Figure 11.2.4-1 Topology of BKP6-CEN10-11.2.4-n ............................................................... 236 Figure 11.2.4-2 Expansion Plane Lanes of BKP6-CEN10-11.2.4-n .......................................... 237 Figure 11.2.5-1 Topology of BKP6-CEN05-11.2.5-n ................................................................ 242 Figure 11.2.5-2 Expansion Plane Lanes of BKP6-CEN05-11.2.5-n .......................................... 243 Figure 11.2.6-1 Topology of BKP6-CEN10-11.2.6-n ................................................................ 249 Figure 11.2.6-2 Expansion Plane Lanes of BKP6-CEN10-11.2.6-n .......................................... 250 Figure 11.2.7-1 Topology of BKP6-CEN10-11.2.7-n ................................................................ 255 Figure 11.2.8-1 Topology of BKP6-CEN06-11.2.8-n ................................................................ 259 Figure 11.2.9-1 Topology of BKP6-CEN12-11.2.9-n ................................................................ 263 Figure 11.2.10-1 Topology of BKP6-DIS06-11.2.10-n .............................................................. 267 Figure 11.2.11-1 Topology of BKP6-HYB17-11.2.11-n ............................................................ 271 Figure 11.2.12-1 Topology of BKP6-HYB08-11.2.12-n ............................................................ 276 Figure 11.2.13-1 Topology of BKP6-CEN09-11.2.13-n ............................................................ 280 Figure 11.2.14-1 Topology of BKP06-CEN06-11.2.14-n .......................................................... 283 Figure 11.2.15-1 Topology of BKP6-DIS06-11.2.15-n .............................................................. 287 Figure 11.2.16-1 Topology of BKP6-DIS05-11.2.16-n .............................................................. 291 Figure 11.2.17-1 Topology of BKP6-CEN16-11.2.17-n ............................................................ 294 Figure 11.2.17-2 Expansion Plane Lanes of BKP6-CEN16-11.2.17-n ...................................... 295 Figure 11.2.18-1 Topology of BKP6-DIS06-11.2.18-n .............................................................. 301 Figure 11.2.18-2 Expansion Plane Lanes of BKP6-DIS06-11.2.18-n ........................................ 302 Figure 11.2.19-1 Topology of BKP6-DIS09-11.2.19-n .............................................................. 306 Figure 11.2.20-1 Topology of BKP6-HYB07-11.2.20-n ............................................................ 311 Figure 13.2-1 6U Standard Development Chassis Profile Name Construct ............................... 343 Figure 14.2.1-1 Payload Slot Profile SLT3-PAY-2F1F2U-14.2.1 ............................................. 346 Figure 14.2.2-1 Payload Slot Profile SLT3-PAY-1F2F2U-14.2.2 ............................................. 349 Figure 14.2.3-1 Payload Slot Profile SLT3-PAY-2F2U-14.2.3 ................................................. 352 Figure 14.2.4-1 Payload Slot Profile SLT3-PAY-1F1F2U-14.2.4 ............................................. 355 Figure 14.2.5-1 Payload Slot Profile SLT3-PAY-2F2T-14.2.5 .................................................. 358 Figure 14.2.6-1 Payload Slot Profile SLT3-PAY-1D-14.2.6...................................................... 361


Figure 14.2.7-1 Payload Slot Profile SLT3-PAY-2F-14.2.7 ...................................................... 363 Figure 14.2.8-1 Payload Slot Profile SLT3-PAY-1F4U-14.2.8 ................................................. 365 Figure 14.2.9-1 Payload Slot Profile SLT3-PAY-8U-14.2.9...................................................... 367 Figure 14.2.10-1 Payload Slot Profile SLT3-PAY-1F1U-14.2.10 ............................................. 369 Figure 14.2.11-1 Payload Slot Profile SLT3-PAY-2F4F2U-14.2.11 ......................................... 372 Figure 14.2.12-1 Payload Slot Profile SLT3-PAY-1F2U-14.2.12 ............................................. 376 Figure 14.2.13-1 Payload Slot Profile SLT3-PAY-3F2U-14.2.13 ............................................. 379 Figure 14.3.1-1 Peripheral Slot Profile SLT3-PER-2F-14.3.1 ................................................... 382 Figure 14.3.2-1 Peripheral Slot Profile SLT3-PER-1F-14.3.2 ................................................... 384 Figure 14.3.3-1 Peripheral Slot Profile SLT3-PER-1U-14.3.3 ................................................... 386 Figure 14.4.1-1 Switch Slot Profile SLT3-SWH-6F6U-14.4.1 .................................................. 388 Figure 14.4.2-1 Switch Slot Profile SLT3-SWH-8F-14.4.2 ....................................................... 392 Figure 14.4.3-1 Switch Slot Profile SLT3-SWH-2F24U-14.4.3 ................................................ 395 Figure 14.4.4-1 Switch Slot Profile SLT3-SWH-4F-14.4.4 ....................................................... 399 Figure 14.4.5-1 Switch Slot Profile SLT3-SWH-2F8U-14.4.5 .................................................. 401 Figure 14.4.6-1 Switch Slot Profile SLT3-SWH-16T-14.4.6 ..................................................... 404 Figure 14.4.7-1 Switch Slot Profile SLT3-SWH-1F14T-14.4.7 ................................................. 407 Figure 14.4.8-1 Switch Slot Profile SLT3-SWH-2F12T-14.4.8 ................................................. 410 Figure 14.4.9-1 Switch Slot Profile SLT3-SWH-6F8U-14.4.9 .................................................. 413 Figure 14.5.1-1 Storage Slot Profile SLT3-STO-2U-14.5.1 ....................................................... 417 Figure 14.6.1-1 Payload Slot Profile SLT3-PAY-1F1F2U4R-14.6.1 ........................................ 420 Figure 14.6.2-1 Payload Slot Profile SLT3-PAY-4F4R-14.6.2.................................................. 424 Figure 15.2.2-1 Topology of BKP3-CEN06-15.2.2-n ................................................................ 435 Figure 15.2.2-2 Expansion Plane Lanes of BKP3-CEN06-15.2.2-n .......................................... 436 Figure 15.2.3-1 Topology of BKP3-CEN07-15.2.3-n ................................................................ 441 Figure 15.2.4-1 Topology of BKP3-CEN10-15.2.4-n ................................................................ 445 Figure 15.2.4-2 Expansion Plane Lanes of BKP3-CEN10-15.2.4-n .......................................... 446 Figure 15.2.5-1 Topology of BKP3-CEN10-15.2.5-n ................................................................ 450 Figure 15.2.5-2 Expansion Plane Lanes of BKP3-CEN10-15.2.5-n .......................................... 451 Figure 15.2.6-1 Topology of BKP3-CEN12-15.2.6-n ................................................................ 456 Figure 15.2.7-1 Topology of BKP3-DIS06-15.2.7-n .................................................................. 461 Figure 15.2.8-1 Topology of 2 Slot - BKP3-DIS02-15.2.8-n ..................................................... 466 Figure 15.2.9-1 Topology of BKP3-CEN03-15.2.9-n ................................................................ 469 Figure 15.2.10-1 Topology of BKP3-CEN06-15.2.10-n ............................................................ 472 Figure 15.2.11-1 Topology of BKP3-CEN09-15.2.11-n ............................................................ 475 Figure 15.2.12-1 Topology of BKP3-CEN06-15.2.12-n ............................................................ 478 Figure 15.2.13-1 Topology of 5 Slot - BKP3-DIS05-15.2.13-n ................................................. 481 Figure 15.2.14-1 Topology of BKP3-DIS06-15.2.14-n .............................................................. 484 Figure 15.2.15-1 Topology of BKP3-CEN08-15.2.15-n ............................................................ 488 Figure 15.2.16-1 Topology of BKP3-CEN08-15.2.16-n ............................................................ 493 Figure 15.2.17-1 Topology of BKP3-CEN09-15.2.17-n ............................................................ 498


Figure 15.2.17-2 Expansion Plane Lanes of BKP3-CEN09-15.2.17-n ...................................... 499 Figure 15.3.2-1 Topology of BKP3-DIS05-15.3.2-n .................................................................. 505 Figure 15.3.3-1 Topology of BKP3-CEN05-15.3.3-n ................................................................ 508 Figure 15.3.3-2 Expansion Plane Lanes of BKP3-CEN05-15.3.3-n .......................................... 509 Figure 17.2-1 3U Standard Development Chassis Profile Name Construct .............................. 552


List of Tables

Table 1.1-1 OpenVPX Profile Relationships ................................................................................ 31 Table 1.3.2-1 Glossary .................................................................................................................. 38 Table 3.7-1 Utility Plane Signals on P0 ........................................................................................ 79 Table 3.7-2 Utility Plane Signals on J0 ........................................................................................ 79 Table 3.7-3 Utility Plane Signals on P1 ........................................................................................ 80 Table 3.7-4 Utility Plane Signals on J1 ........................................................................................ 80 Table 3.7-5 P0 and P1 Contact Assignments ................................................................................ 81 Table 6.2.4.1-1 Repartitioning of a Data Plane FP into TPs, or UTPs ........................................ 95 Table 6.2.4.1-2 Repartitioning of 2 Data Plane FPs into a DFP, TPs, or UTPs ........................... 95 Table 6.2.4.2-1 Expansion Plane Assignment of 4 Lanes to Pipes .............................................. 96 Table 6.2.4.2-2 Expansion Plane Assignment of 8 Lanes to Pipes ............................................... 97 Table 6.2.4.2-3 Expansion Plane Assignment of 16 Lanes to Pipes ............................................ 98 Table 6.3.1-1 Connector Example Plug-In Module Only — Differential .................................. 102 Table 6.3.1-2 Connector Example Backplane Only — Differential ........................................... 102 Table 6.3.1-3 Connector Example Combined Plug-In Module & Backplane — Differential ... 103 Table 6.3.3.1-1 User Defined pins for Pn & Jn — Differential Connectors ............................... 105 Table 6.3.3.1-2 User Defined pins for Pn – Differential Connector ........................................... 106 Table 6.3.3.1-3 User Defined pins for Pn – Single-Ended Connector ........................................ 106 Table 6.3.3.1-4 User Defined pins for Jn – Single-Ended Only ................................................. 107 Table 6.3.3.1-5 User Defined pins for Jn – Universal Ground Pattern ....................................... 107 Table 6.3.3.2-1 Suggested Thin Pipe on Single-Ended .............................................................. 108 Table 10.2.1-1 Payload Slot Profile SLT6-PAY-4F1Q2U2T-10.2.1 — P1 & J1 ...................... 124 Table 10.2.1-2 Payload Slot Profile SLT6-PAY-4F1Q2U2T-10.2.1 — P2 & J2 ...................... 124 Table 10.2.1-3 Payload Slot Profile SLT6-PAY-4F1Q2U2T-10.2.1 — P3 & J3 ...................... 125 Table 10.2.1-4 Payload Slot Profile SLT6-PAY-4F1Q2U2T-10.2.1 — P4 & J4 ...................... 125 Table 10.2.1-5 Payload Slot Profile SLT6-PAY-4F1Q2U2T-10.2.1 — P5 & J5 ...................... 126 Table 10.2.1-6 Payload Slot Profile SLT6-PAY-4F1Q2U2T-10.2.1 — P6 & J6 ...................... 126 Table 10.2.2-1 Payload Slot Profile SLT6-PAY-4F2T-10.2.2 — P1 & J1 ................................ 129 Table 10.2.2-2 Payload Slot Profile SLT6-PAY-4F2T-10.2.2 — P2 & J2 ................................ 129 Table 10.2.2-3 Payload Slot Profile SLT6-PAY-4F2T-10.2.2 — P3 & J3 ................................ 129 Table 10.2.2-4 Payload Slot Profile SLT6-PAY-4F2T-10.2.2 — P4 & J4 ................................ 130 Table 10.2.2-5 Payload Slot Profile SLT6-PAY-4F2T-10.2.2 — P5 & J5 ................................ 130 Table 10.2.2-6 Payload Slot Profile SLT6-PAY-4F2T-10.2.2 — P6 & J6 ................................ 130 Table 10.2.3-1 Payload Slot Profile SLT6-PAY-8F-10.2.3 — P1 & J1 ..................................... 133 Table 10.2.3-2 Payload Slot Profile SLT6-PAY-8F-10.2.3 — P2 & J2 ..................................... 133 Table 10.2.3-3 Payload Slot Profile SLT6-PAY-8F-10.2.3 — P3 & J3 ..................................... 134 Table 10.2.3-4 Payload Slot Profile SLT6-PAY-8F-10.2.3 — P4 & J4 ..................................... 134


Table 10.2.3-5 Payload Slot Profile SLT6-PAY-8F-10.2.3 — P5 & J5 ..................................... 134 Table 10.2.3-6 Payload Slot Profile SLT6-PAY-8F-10.2.3 — P6 & J6 ..................................... 135 Table 10.2.4-1 Payload Slot Profile SLT6-PAY-4F16U-10.2.4 — P1& J1 ............................... 138 Table 10.2.4-2 Payload Slot Profile SLT6-PAY-4F16U-10.2.4 — P2 & J2 .............................. 138 Table 10.2.4-3 Payload Slot Profile SLT6-PAY-4F16U-10.2.4 — P3 & J3 .............................. 139 Table 10.2.4-4 Payload Slot Profile SLT6-PAY-4F16U-10.2.4 — P4 & J4 .............................. 139 Table 10.2.4-5 Payload Slot Profile SLT6-PAY-4F16U-10.2.4 — P5 & J5 .............................. 139 Table 10.2.4-6 Payload Slot Profile SLT6-PAY-4F16U-10.2.4 — P6 & J6 .............................. 139 Table 10.2.5-1 Payload Slot Profile SLT6-PAY-2F2U2T-10.2.5 — P1 & J1 ........................... 142 Table 10.2.5-2 Payload Slot Profile SLT6-PAY-2F2U2T-10.2.5 — P2 & J2 ........................... 142 Table 10.2.5-3 Payload Slot Profile SLT6-PAY-2F2U2T-10.2.5 — P3 & J3 ........................... 142 Table 10.2.5-4 Payload Slot Profile SLT6-PAY-2F2U2T-10.2.5 — P4 & J4 ........................... 143 Table 10.2.5-5 Payload Slot Profile SLT6-PAY-2F2U2T-10.2.5 — P5 & J5 ........................... 143 Table 10.2.5-6 Payload Slot Profile SLT6-PAY-2F2U2T-10.2.5 — P6 & J6 ........................... 143 Table 10.2.6-1 Payload Slot Profile SLT6-PAY-4F1Q2U2T-10.2.6 — P1 & J1 ...................... 147 Table 10.2.6-2 Payload Slot Profile SLT6-PAY-4F1Q2U2T-10.2.6 — P2 & J2 ...................... 147 Table 10.2.6-3 Payload Slot Profile SLT6-PAY-4F1Q2U2T-10.2.6 — P3 & J3 ...................... 147 Table 10.2.6-4 Payload Slot Profile SLT6-PAY-4F1Q2U2T-10.2.6 — P4 & J4 ...................... 148 Table 10.2.6-5 Payload Slot Profile SLT6-PAY-4F1Q2U2T-10.2.6 — P5 & J5 ...................... 148 Table 10.2.6-6 Payload Slot Profile SLT6-PAY-4F1Q2U2T-10.2.6 — P6 & J6 ...................... 148 Table 10.2.7-1 Payload Slot Profile SLT6-PAY-4F2Q2U2T-10.2.7 — P1 & J1 ...................... 152 Table 10.2.7-2 Payload Slot Profile SLT6-PAY-4F2Q2U2T-10.2.7 — P2 & J2 ...................... 152 Table 10.2.7-3 Payload Slot Profile SLT6-PAY-4F2Q2U2T-10.2.7 — P3 & J3 ...................... 152 Table 10.2.7-4 Payload Slot Profile SLT6-PAY-4F2Q2U2T-10.2.7 — P4 & J4 ...................... 152 Table 10.2.7-5 Payload Slot Profile SLT6-PAY-4F2Q2U2T-10.2.1 — P5 & J5 ...................... 153 Table 10.2.7-6 Payload Slot Profile SLT6-PAY-4F2Q2U2T-10.2.7 — P6 & J6 ...................... 153 Table 10.3.1-1 Peripheral Slot Profile SLT6-PER-4F-10.3.1 — P1 & J1 .................................. 156 Table 10.3.1-2 Peripheral Slot Profile SLT6-PER-4F-10.3.1 — P2 & J2 .................................. 157 Table 10.3.1-3 Peripheral Slot Profile SLT6-PER-4F-10.3.1 — P3 & J3 .................................. 157 Table 10.3.1-4 Peripheral Slot Profile SLT6-PER-4F-10.3.1 — P4 & J4 .................................. 157 Table 10.3.1-5 Peripheral Slot Profile SLT6-PER-4F-10.3.1 — P5 & J5 .................................. 157 Table 10.3.1-6 Peripheral Slot Profile SLT6-PER-4F-10.3.1 — P6 & J6 ................................. 158 Table 10.3.2-1 Peripheral Slot Profile SLT6-PER-2F-10.3.2 — P1& J1 ................................... 161 Table 10.3.2-2 Peripheral Slot Profile SLT6-PER-2F-10.3.2 — P2 & J2 .................................. 161 Table 10.3.2-3 Peripheral Slot Profile SLT6-PER-2F-10.3.2 — P3 & J3 .................................. 162 Table 10.3.2-4 Peripheral Slot Profile SLT6-PER-2F-10.3.2 — P4 & J4 .................................. 162 Table 10.3.2-5 Peripheral Slot Profile SLT6-PER-2F-10.3.2 — P5 & J5 .................................. 162 Table 10.3.2-6 Peripheral Slot Profile SLT6-PER-2F-10.3.2 — P6 & J6 .................................. 162 Table 10.3.3-1 Peripheral Slot Profile SLT6-PER-4U-10.3.3 — P1& J1 .................................. 165 Table 10.3.3-2 Peripheral Slot Profile SLT6-PER-4U-10.3.3 — P2 & J2 ................................. 165 Table 10.3.3-3 Peripheral Slot Profile SLT6-PER-4U-10.3.3 — P3 & J3 ................................. 165


Table 10.3.3-4 Peripheral Slot Profile SLT6-PER-4U-10.3.3 — P4 & J4 ................................. 166 Table 10.3.3-5 Peripheral Slot Profile SLT6-PER-4U-10.3.3 — P5 & J5 ................................. 166 Table 10.3.3-6 Peripheral Slot Profile SLT6-PER-4U-10.3.3 — P6 & J6 ................................. 166 Table 10.3.4-1 Peripheral Slot Profile SLT6-PER-1F-10.3.4 — P1& J1 ................................... 169 Table 10.3.4-2 Peripheral Slot Profile SLT6-PER-1F-10.3.4 — P2 & J2 .................................. 169 Table 10.3.4-3 Peripheral Slot Profile SLT6-PER-1F-10.3.4 — P3 & J3 .................................. 170 Table 10.3.4-4 Peripheral Slot Profile SLT6-PER-1F-10.3.4 — P4 & J4 .................................. 170 Table 10.3.4-5 Peripheral Slot Profile SLT6-PER-1F-10.3.4 — P5 & J5 .................................. 170 Table 10.3.4-6 Peripheral Slot Profile SLT6-PER-1F-10.3.4 — P6 & J6 .................................. 170 Table 10.3.5-1 Peripheral Slot Profile SLT6-PER-1Q-10.3.5 — P1& J1 .................................. 173 Table 10.3.5-2 Peripheral Slot Profile SLT6-PER-1Q-10.3.5 — P2 & J2 ................................. 174 Table 10.3.5-3 Peripheral Slot Profile SLT6-PER-1Q-10.3.5 — P3 & J3 ................................. 175 Table 10.3.5-4 Peripheral Slot Profile SLT6-PER-1Q-10.3.5 — P4 & J4 ................................. 175 Table 10.3.5-5 Peripheral Slot Profile SLT6-PER-1Q-10.3.5 — P5 & J5 ................................. 175 Table 10.3.5-6 Peripheral Slot Profile SLT6-PER-1Q-10.3.5 — P6 & J6 ................................. 175 Table 10.4.1-1 Switch Slot Profile SLT6-SWH-20U19F-10.4.1 — P1 & J1 ............................. 180 Table 10.4.1-2 Switch Slot Profile SLT6-SWH-20U19F-10.4.1 — P2 & J2 ............................. 180 Table 10.4.1-3 Switch Slot Profile SLT6-SWH-20U19F-10.4.1 — P3 & J3 ............................. 181 Table 10.4.1-4 Switch Slot Profile SLT6-SWH-20U19F-10.4.1 — P4 & J4 ............................. 181 Table 10.4.1-5 Switch Slot Profile SLT6-SWH-20U19F-10.4.1 — P5 & J5 ............................. 182 Table 10.4.1-6 Switch Slot Profile SLT6-SWH-20U19F-10.4.1 — P6 & J6 ............................. 182 Table 10.4.2-1 Switch Slot Profile SLT6-SWH-16U20F-10.4.2 — P1 & J1 ............................. 186 Table 10.4.2-2 Switch Slot Profile SLT6-SWH-16U20F-10.4.2 — P2 & J2 ............................. 186 Table 10.4.2-3 Switch Slot Profile SLT6-SWH-16U20F-10.4.2 — P3 & J3 ............................. 187 Table 10.4.2-4 Switch Slot Profile SLT6-SWH-16U20F-10.4.2 — P4 & J4 ............................. 187 Table 10.4.2-5 Switch Slot Profile SLT6-SWH-16U20F-10.4.2 — P5 & J5 ............................. 188 Table 10.4.2-6 Switch Slot Profile SLT6-SWH-16U20F-10.4.2 — P6 & J6 ............................. 188 Table 10.4.3-1 Switch Slot Profile SLT6-SWH-24F-10.4.3 — P1 & J1.................................... 191 Table 10.4.3-2 Switch Slot Profile SLT6-SWH-24F-10.4.3 — P2 & J2.................................... 191 Table 10.4.3-3 Switch Slot Profile SLT6-SWH-24F-10.4.3 — P3 & J3.................................... 192 Table 10.4.3-4 Switch Slot Profile SLT6-SWH-24F-10.4.3 — P4 & J4.................................... 192 Table 10.4.3-5 Switch Slot Profile SLT6-SWH-24F-10.4.3 — P5 & J5.................................... 193 Table 10.4.3-6 Switch Slot Profile SLT6-SWH-24F-10.4.3 — P6 & J6.................................... 193 Table 10.4.4-1 Switch Slot Profile SLT6-SWH-4F24T-10.4.4 — P1 & J1 ............................... 196 Table 10.4.4-2 Switch Slot Profile SLT6-SWH-4F24T-10.4.4 — P2 & J2 ............................... 196 Table 10.4.4-3 Switch Slot Profile SLT6-SWH-4F24T-10.4.4 — P3 & J3 ............................... 197 Table 10.4.4-4 Switch Slot Profile SLT6-SWH-4F24T-10.4.4 — P4 & J4 ............................... 197 Table 10.4.4-5 Switch Slot Profile SLT6-SWH-4F24T-10.4.4 — P5 & J5 ............................... 198 Table 10.4.4-6 Switch Slot Profile SLT6-SWH-4F24T-10.4.4 — P6 & J6 ............................... 198 Table 10.4.5-1 Switch Slot Profile SLT6-SWH-16U16F-10.4.5 — P1 & J1 ............................. 202 Table 10.4.5-2 Switch Slot Profile SLT6-SWH-16U16F-10.4.5 — P2 & J2 ............................. 202


Table 10.4.5-3 Switch Slot Profile SLT6-SWH-16U16F-10.4.5— P3 & J3 .............................. 203 Table 10.4.5-4 Switch Slot Profile SLT6-SWH-16U16F-10.4.5— P4 & J4 .............................. 203 Table 10.4.5-5 Switch Slot Profile SLT6-SWH-16U16F-10.4.5— P5 & J5 .............................. 204 Table 10.4.5-6 Switch Slot Profile SLT6-SWH-16U16F-10.4.5— P6 & J6 .............................. 204 Table 10.5.1-1 VME Bridge Slot Profile SLT6-BRG-4F1V2T-10.5.1 — P1 & J1 ................... 208 Table 10.5.1-2 VME Bridge Slot Profile SLT6-BRG-4F1V2T-10.5.1 — P2 & J2 ................... 208 Table 10.5.1-3 VME Bridge Slot Profile SLT6-BRG-4F1V2T-10.5.1 — P3 & J3 ................... 209 Table 10.5.1-4 VME Bridge Slot Profile SLT6-BRG-4F1V2T-10.5.1 — P4 & J4 ................... 209 Table 10.5.1-5 VME Bridge Slot Profile SLT6-BRG-4F1V2T-10.5.1 — P5 & J5 ................... 210 Table 10.5.1-6 VME Bridge Slot Profile SLT6-BRG-4F1V2T-10.5.1 — P6 & J6 ................... 210 Table 10.5.2-1 VME Bridge Slot Profile SLT6-BRG-4F1V-10.5.2 — P1& J1 ......................... 213 Table 10.5.2-2 VME Bridge Slot Profile SLT6-BRG-4F1V-10.5.2 — P2 & J2 ........................ 213 Table 10.5.2-3 VME Bridge Slot Profile SLT6-BRG-4F1V-10.5.2 — P3 & J3 ........................ 214 Table 10.5.2-4 VME Bridge Slot Profile SLT6-BRG-4F1V-10.5.2 — P4 & J4 ........................ 214 Table 10.5.2-5 VME Bridge Slot Profile SLT6-BRG-4F1V-10.5.2 — P5 & J5 ........................ 215 Table 10.5.2-6 VME Bridge Slot Profile SLT6-BRG-4F1V-10.5.2 — P6 & J6 ........................ 215 Table 11-1 Summary of 6U Backplane Profiles Using VITA 46.0 Connectors ......................... 217 Table 11-2 Matching Module Profiles to Backplane Profiles Using VITA 46.0 Connectors .... 220 Table 11.2.2-1 Backplane Profiles BKP6-CEN16-11.2.2-n ....................................................... 225 Table 11.2.3-1 Backplane Profiles BKP6-CEN20-11.2.3-n ....................................................... 231 Table 11.2.4-1 Backplane Profiles BKP6-CEN10-11.2.4-n ....................................................... 237 Table 11.2.5-1 Backplane Profiles BKP6-CEN05-11.2.5-n ....................................................... 244 Table 11.2.6-1 Backplane Profiles BKP6-CEN10-11.2.6-n ....................................................... 250 Table 11.2.7-1 Backplane Profiles BKP6-CEN10-11.2.7-n ....................................................... 256 Table 11.2.8-1 Backplane Profiles BKP6-CEN06-11.2.8-n ....................................................... 260 Table 11.2.9-1 Backplane Profiles BKP6-CEN12-11.2.9-n ....................................................... 264 Table 11.2.10-1 Backplane Profiles BKP6-DIS06-11.2.10-n ..................................................... 268 Table 11.2.10-2 Data Plane Connection BKP6-DIS06-11.2.10-n .............................................. 270 Table 11.2.11-1 Backplane Profiles BKP6-HYB17-11.2.11-n ................................................... 272 Table 11.2.11-2 Data Plane Connection BKP6-HYB17-11.2.11-n ............................................ 274 Table 11.2.12-1 Backplane Profiles BKP6-HYB08-11.2.12-n ................................................... 277 Table 11.2.13-1 Backplane Profiles BKP6-CEN09-11.2.13-n ................................................... 281 Table 11.2.14-1 Backplane Profiles BKP6-CEN06-11.2.14-n ................................................... 284 Table 11.2.15-1 Backplane Profiles BKP6-DIS06-11.2.15-n ..................................................... 288 Table 11.2.15-2 Data Plane Connection BKP6-DIS06-11.2.15-n .............................................. 289 Table 11.2.16-1 Backplane Profiles BKP6-DIS05-11.2.16-n ..................................................... 292 Table 11.2.16-2 Data Plane Connection BKP6-DIS06-11.2.16-n .............................................. 293 Table 11.2.17-1 Backplane Profiles BKP6-CEN16-11.2.17-n ................................................... 295 Table 11.2.18-1 Backplane Profiles BKP6-DIS06-11.2.18-n ..................................................... 302 Table 11.2.18-2 Data Plane Connection BKP6-DIS06-11.2.18-n .............................................. 303 Table 11.2.19-1 Backplane Profiles BKP6-DIS09-11.2.19-n ..................................................... 307


Table 11.2.19.3-1 Control Plane Connection BKP6-DIS09-11.2.19-n ...................................... 309 Table 11.2.19.4-1 Data Plane Connection BKP6-DIS09-11.2.19-n ........................................... 310 Table 11.2.20-1 Backplane Profiles BKP6-HYB07-11.2.20-n ................................................... 312 Table 11.2.20.5-1 Data Plane Connection BKP6-HYB07-11.2.20-n ......................................... 314 Table 12.2.1-1 Module Profiles MOD6-PAY-4F1Q2U2T-12.2.1-n .......................................... 317 Table 12.2.2-1 Module Profiles MOD6-PAY-4F2T-12.2.2-n .................................................... 319 Table 12.2.3-1 Module Profiles MOD6-PAY-8F-12.2.3-n ........................................................ 320 Table 12.2.4-1 Module Profiles MOD6-PAY-4F16U-12.2.4-n ................................................. 321 Table 12.2.5-1 Module Profiles MOD6-PAY-2F2U2T-12.2.5-n ............................................... 322 Table 12.2.6-1 Module Profiles MOD6-PAY-4F1Q2U2T-12.2.6-n .......................................... 324 Table 12.2.7-1 Module Profiles MOD6-PAY-4F2Q2U2T-12.2.7-n .......................................... 326 Table 12.3.1-1 Module Profiles MOD6-PER-4F-12.3.1-n ......................................................... 327 Table 12.3.2-1 Module Profiles MOD6-PER-2F-12.3.2-n ......................................................... 328 Table 12.3.3-1 Module Profiles MOD6-PER-4U-12.3.3-n ........................................................ 329 Table 12.3.4-1 Module Profiles MOD6-PER-1F-12.3.4-n ......................................................... 330 Table 12.3.5-1 Module Profiles MOD6-PER-1Q-12.3.5-n ........................................................ 331 Table 12.4.1-1 Module Profiles MOD6-SWH-20U19F-12.4.1-n ............................................... 333 Table 12.4.2-1 Module Profiles MOD6-SWH-16U20F-12.4.2-n ............................................... 335 Table 12.4.3-1 Module Profiles MOD6-SWH-24F-12.4.3-n ..................................................... 336 Table 12.4.4-1 Module Profiles MOD6-SWH-4F24T-12.4.4-n ................................................. 337 Table 12.4.5-1 Module Profiles MOD6-SWH-16F16U-12.4.5-n ............................................... 338 Table 12.5.1-1 Module Profiles MOD6-BRG-4F1V2T-12.5.1-n ............................................... 340 Table 12.5.2-1 Module Profiles MOD6-BRG-4F1V-12.5.2-n ................................................... 341 Table 13.2-1 6U Standard Development Chassis Backplane Power Options .......................... 344 Table 14.2.1-1 Payload Slot Profile SLT3-PAY-2F1F2U-14.2.1 — P1 & J1............................ 348 Table 14.2.1-2 Payload Slot Profile SLT3-PAY-2F1F2U-14.2.1 — P2 & J2............................ 348 Table 14.2.2-1 Payload Slot Profile SLT3-PAY-1F2F2U-14.2.2 — P1 & J1............................ 351 Table 14.2.2-2 Payload Slot Profile SLT3-PAY-1F2F2U-14.2.2 — P2 & J2............................ 351 Table 14.2.3-1 Payload Slot Profile SLT3-PAY-2F2U-14.2.3 — P1 & J1 ................................ 354 Table 14.2.3-2 Payload Slot Profile SLT3-PAY-2F2U-14.2.3 — P2 & J2 ................................ 354 Table 14.2.4-1 Payload Slot Profile SLT3-PAY-1F1F2U-14.2.4 — P1 & J1............................ 357 Table 14.2.4-2 Payload Slot Profile SLT3-PAY-1F1F2U-14.2.4 — P2 & J2............................ 357 Table 14.2.5-1 Payload Slot Profile SLT3-PAY-2F2T-14.2.5 — P1 & J1 ................................ 360 Table 14.2.5-2 Payload Slot Profile SLT3-PAY-2F2T-14.2.5 — P2 & J2 ................................ 360 Table 14.2.6-1 Payload Slot Profile SLT3-PAY-1D-14.2.6 — P1 & J1 .................................... 362 Table 14.2.6-2 Payload Slot Profile SLT3-PAY-1D-14.2.6 — P2 & J2 .................................... 362 Table 14.2.7-1 Payload Slot Profile SLT3-PAY-2F-14.2.7 — P1 & J1 ..................................... 364 Table 14.2.7-2 Payload Slot Profile SLT3-PAY-1D-14.2.7 — P2 & J2 .................................... 364 Table 14.2.8-1 Payload Slot Profile SLT3-PAY-1F4U-14.2.8 — P1 & J1 ................................ 366 Table 14.2.8-2 Payload Slot Profile SLT3-PAY-1F4U-14.2.8 — P2 & J2 ................................ 366 Table 14.2.9-1 Payload Slot Profile SLT3-PAY-8U-14.2.9 — P1 & J1 .................................... 368


Table 14.2.9-2 Payload Slot Profile SLT3-PAY-8U-14.2.9 — P2 & J2 .................................... 368 Table 14.2.10-1 Payload Slot Profile SLT3-PAY-1F1U-14.2.10 — P1 & J1 ............................ 371 Table 14.2.10-2 Payload Slot Profile SLT3-PAY-1F1U-14.2.10 — P2 & J2 ............................ 371 Table 14.2.11-1 Payload Slot Profile SLT3-PAY-2F4F2U-14.2.11 — P1 & J1 ........................ 374 Table 14.2.11-2 Payload Slot Profile SLT3-PAY-2F4F2U-14.2.11 — P2 & J2 ........................ 375 Table 14.2.12-1 Payload Slot Profile SLT3-PAY-1F2U-14.2.12— P1 & J1 ............................. 378 Table 14.2.12-2 Payload Slot Profile SLT3-PAY-1F2U-14.2.12— P2 & J2 ............................. 378 Table 14.2.13-1 Payload Slot Profile SLT3-PAY-3F2U-14.2.13 — P1 & J1 ............................ 381 Table 14.2.13-2 Payload Slot Profile SLT3-PAY-3F2U-14.2.13 — P2 & J2 ............................ 381 Table 14.3.1-1 Peripheral Slot Profile SLT3-PER-2F-14.3.1 — P1 & J1 .................................. 383 Table 14.3.1-2 Peripheral Slot Profile SLT3-PER-2F-14.3.1 — P2 & J2 .................................. 383 Table 14.3.2-1 Peripheral Slot Profile SLT3-PER-1F-14.3.2 — P1 & J1 .................................. 385 Table 14.3.2-2 Peripheral Slot Profile SLT3-PER-1F-14.3.2 — P2 & J2 .................................. 385 Table 14.3.3-1 Peripheral Slot Profile SLT3-PER-1U-14.3.3 — P1 & J1 ................................. 387 Table 14.3.3-2 Peripheral Slot Profile SLT3-PER-1U-14.3.3 — P2 & J2 ................................. 387 Table 14.4.1-1 Switch Slot Profile SLT3-SWH-6F6U-14.4.1 — P1 & J1 ................................. 390 Table 14.4.1-2 Switch Slot Profile SLT3-SWH-6F6U-14.4.1 — P2 & J2 ................................. 391 Table 14.4.1-3 User Defined Pins for Thin Pipe — P2 & J2...................................................... 391 Table 14.4.2-1 Switch Slot Profile SLT3-SWH-8F-14.4.2 — P1 & J1...................................... 394 Table 14.4.2-2 Switch Slot Profile SLT3-SWH-8F-14.4.2 — P2 & J2...................................... 394 Table 14.4.3-1 Switch Slot Profile SLT3-SWH-2F24U-14.4.3 — P1 & J1 ............................... 397 Table 14.4.3-2 Switch Slot Profile SLT3-SWH-2F24U-14.4.3 — P2 & J2 ............................... 398 Table 14.4.4-1 Switch Slot Profile SLT3-SWH-4F-14.4.4 — P1 & J1...................................... 400 Table 14.4.4-2 Switch Slot Profile SLT3-SWH-4F-14.4.4 — P2 & J2...................................... 400 Table 14.4.5-1 Switch Slot Profile SLT3-SWH-2F8U-14.4.5 — P1 & J1 ................................. 403 Table 14.4.5-2 Switch Slot Profile SLT3-SWH-2F8U-14.4.5 — P2 & J2 ................................. 403 Table 14.4.6-1 Switch Slot Profile SLT3-SWH-16T-14.4.6 — P1& J1 .................................... 406 Table 14.4.6-2 Switch Slot Profile SLT3-SWH-16T-14.4.6 — P2 & J2 ................................... 406 Table 14.4.7-1 Switch Slot Profile SLT3-SWH-1F14T-14.4.7 — P1& J1 ................................ 409 Table 14.4.7-2 Switch Slot Profile SLT3-SWH-1F14T-14.4.7 — P2 & J2 ............................... 409 Table 14.4.8-1 Switch Slot Profile SLT3-SWH-2F12T-14.4.8 — J1 & P2 .............................. 412 Table 14.4.8-2 Switch Slot Profile SLT3-SWH-2F12T-14.4.8 — P2& J2 ................................ 412 Table 14.4.9-1 Switch Slot Profile SLT3-SWH-6F8U-14.4.9 — P1 & J1 ................................. 415 Table 14.4.9-2 Switch Slot Profile SLT3-SWH-6F8U-14.4.9 — P2 & J2 ................................. 416 Table 14.5.1-1 Storage Slot Profile SLT3-STO-2U-14.5.1 — P1 & J1 ..................................... 419 Table 14.5.1-2 Storage Slot Profile SLT3-STO-2U-14.5.1 — P2 & J2 ..................................... 419 Table 14.6.1-1 Payload Slot Profile SLT3-PAY-1F1F2U4R-14.6.1— P1 & J1 ........................ 422 Table 14.6.1-2 Payload Slot Profile SLT3-PAY-1F1F2U4R-14.6.1— P2 & J2 ........................ 423 Table 14.6.2-1 Payload Slot Profile SLT3-PAY-4F4R-14.6.2— P1 & J1 ................................. 425 Table 14.6.2-2 Payload Slot Profile SLT3-PAY-4F4R-14.6.2— P2 & J2 ................................. 426 Table 15-1 Summary of 3U Backplane Profiles Using VITA 46.0 Connectors ......................... 428


Table 15-2 Matching Module Profiles to Backplane Profiles Using VITA 46.0 Connectors .... 430 Table 15-3 Summary of 3U Backplane Profile Using VITA 46.0 and VITA 67 Connectors ... 431 Table 15-4 Matching Module Profiles to Backplane Profiles Using VITA 46.0 and VITA 67

Connectors ................................................................................................... 431 Table 15.2.2-1 Backplane Profiles BKP3-CEN06-15.2.2-n ....................................................... 436 Table 15.2.2-2 BKP3-CEN06-15.2.2-n Control Plane Port connections ................................... 438 Table 15.2.2-3 BKP3-CEN06-15.2.2-n Data Plane Port connections ........................................ 439 Table 15.2.3-1 Backplane Profiles BKP3-CEN07-15.2.3-n ....................................................... 442 Table 15.2.3-2 BKP3-CEN07-15.2.3-n Control Plane Port connections ................................... 443 Table 15.2.3-3 BKP3-CEN07-15.2.3-n Data Plane Port connections ........................................ 444 Table 15.2.4-1 Backplane Profiles BKP3-CEN10-15.2.4-n ....................................................... 446 Table 15.2.4-2 BKP3-CEN10-15.2.4-n Data Plane Port connections ........................................ 448 Table 15.2.5-1 Backplane Profiles BKP3-CEN10-15.2.5-n ....................................................... 451 Table 15.2.5-2 BKP3-CEN10-15.2.5-n Data Plane Port connections ........................................ 453 Table 15.2.6-1 Backplane Profiles BKP3-CEN12-15.2.6-n ....................................................... 457 Table 15.2.6-2 BKP3-CEN12-15.2.6-n Control Plane Port connections ................................... 459 Table 15.2.6-3 BKP3-CEN12-15.2.6-n Data Plane Port connections ........................................ 460 Table 15.2.7-1 Backplane Profiles BKP3-DIS06-15.2.7-n ......................................................... 462 Table 15.2.7-2 Data Plane Connection BKP3-DIS06-15.2.7-n .................................................. 464 Table 15.2.7-3 Data Plane Connection BKP3-DIS06-15.2.7-n .................................................. 464 Table 15.2.8-1 Backplane Profiles BKP3-DIS02-15.2.8-n ......................................................... 467 Table 15.2.9-1 Backplane Profiles BKP3-CEN03-15.2.9-n ....................................................... 470 Table 15.2.10-1 Backplane Profiles BKP3-CEN06-15.2.10-n ................................................... 473 Table 15.2.11-1 Backplane Profiles BKP3-CEN09-15.2.11-n ................................................... 476 Table 15.2.12-1 Backplane Profiles BKP3-CEN06-15.2.12-n ................................................... 479 Table 15.2.13-1 Backplane Profiles BKP3-DIS05-15.2.13-n ..................................................... 482 Table 15.2.14-1 Backplane Profiles BKP3-DIS06-15.2.14-n ..................................................... 485 Table 15.2.14-2 Data Plane Connection BKP3-DIS06-15.2.14-n .............................................. 486 Table 15.2.14-3 Data Plane Connection BKP3-DIS06-15.2.14-n .............................................. 486 Table 15.2.15-1 Backplane Profiles BKP3-CEN08-15.2.15-n ................................................... 489 Table 15.2.15-2 BKP3-CEN08-15.2.15-n Control Plane Port connections ............................... 490 Table 15.2.15-3 BKP3-CEN08-15.2.15-n Data Plane Port connections .................................... 491 Table 15.2.16-1 Backplane Profiles BKP3-CEN08-15.2.16-n ................................................... 494 Table 15.2.16-2 BKP3-CEN08-15.2.16-n Control Plane Port connections ............................... 496 Table 15.2.16-3 BKP3-CEN08-15.2.16-n Data Plane Port connections .................................... 497 Table 15.2.17-1 Backplane Profiles BKP3-CEN09-15.2.17-n ................................................... 499 Table 15.2.17-2 BKP3-CEN09-15.2.17-n Control Plane Port connections ............................... 501 Table 15.2.17-3 BKP3-CEN09-15.2.17-n Data Plane Port connections .................................... 502 Table 15.2.17-4 BKP3-CEN09-15.2.17-n Data Plane Port connections .................................... 502 Table 15.3.2-1 Backplane Profiles BKP3-DIS05-15.3.2-n ......................................................... 506 Table 15.3.2-2 Data Plane Connection BKP3-DIS05-15.3.2-n .................................................. 507


Table 15.3.3-1 Backplane Profiles BKP3-CEN05-15.3.3-n ....................................................... 509 Table 15.3.3-2 BKP3-CEN05-15.3.3-n Control Plane Port connections ................................... 511 Table 15.3.3-3 BKP3-CEN05-15.3.3-n Data Plane Port connections ........................................ 512 Table 16.2.1-1 Module Profiles MOD3-PAY-2F1F2U-16.2.1-n ............................................... 515 Table 16.2.2-1 Module Profiles MOD3-PAY-1F2F2U-16.2.2-n ............................................... 517 Table 16.2.3-1 Module Profiles MOD3-PAY-2F2U-16.2.3-n ................................................... 519 Table 16.2.4-1 Module Profiles MOD3-PAY-1F1F2U-16.2.4-n ............................................... 521 Table 16.2.5-1 Module Profiles MOD3-PAY-2F2T-16.2.5-n .................................................... 522 Table 16.2.6-1 Module Profiles MOD3-PAY-1D-16.2.6-n ........................................................ 523 Table 16.2.7-1 Module Profiles MOD3-PAY-2F-16.2.7-n ........................................................ 524 Table 16.2.8-1 Module Profiles MOD3-PAY-1F4U-16.2.8-n ................................................... 525 Table 16.2.9-1 Module Profiles MOD3-PAY-8U-16.2.9-n ........................................................ 526 Table 16.2.10-1 Module Profiles MOD3-PAY-2F4F2U-16.2.10-n ........................................... 528 Table 16.2.11-1 Module Profiles MOD3-PAY-1F2U-16.2.11-n ............................................... 529 Table 16.2.12-1 Module Profiles MOD3-PAY-3F2U-16.2.12-n ............................................... 530 Table 16.3.1-1 Module Profiles MOD3-PER-2F-16.3.1-n ......................................................... 531 Table 16.3.2-1 Module Profiles MOD3-PER-1F-16.3.2-n ......................................................... 532 Table 16.3.3-1 Module Profiles MOD3-PER-1U-16.3.3-n ........................................................ 533 Table 16.4.1-1 Module Profiles MOD3-SWH-6F6U-16.4.1-n ................................................... 535 Table 16.4.2-1 Module Profiles MOD3-SWH-8F-16.4.2-n ....................................................... 536 Table 16.4.3-1 Module Profiles MOD3-SWH-2F24U-16.4.3-n ................................................. 537 Table 16.4.4-1 Module Profiles MOD3-SWH-1F4U-16.4.4-n ................................................... 538 Table 16.4.5-1 Module Profiles MOD3-SWH-4F-16.4.5-n ....................................................... 539 Table 16.4.6-1 Module Profiles MOD3-SWH-2F8U-16.4.6-n ................................................... 541 Table 16.4.7-1 Module Profiles MOD3-SWH-16T-16.4.7-n ..................................................... 542 Table 16.4.8-1 Module Profiles MOD3-SWH-1F14T-16.4.8-n ................................................. 543 Table 16.4.9-1 Module Profiles MOD3-SWH-2F12T-16.4.9-n ................................................. 544 Table 16.4.10-1 Module Profiles MOD3-SWH-6F8U-16.4.10-n ............................................... 546 Table 16.5.1-1 Module Profiles MOD3-STO-2U-16.5.1-n ........................................................ 547 Table 16.6.1-1 Module Profiles MOD3-PAY-1F1F2U4R-16.6.1-n........................................... 549 Table 16.6.2-1 Module Profiles MOD3-PAY-4F4R-16.6.2-n .................................................... 550 Table 17.2-1 3U Standard Development Chassis Backplane Power Options .......................... 553


Acknowledgements

For those who contributed to the first version of this specification, see the Acknowledgements Section of [VITA 65-2010].

The VITA 65 Technical Working Group is indebted to the following individual(s) and would like to recognize their contribution to the successful completion of this, the second version of the VITA 65 Specification:

• To the Working Group Members and their respective companies without their commitment and dedication this body of work could not have been completed.

• To Pete Jha, who was the VITA 65 Technical Working Group Chair through much of the process of creating this specification.

• To John Rynearson for his invaluable guidance during the VSO and ANSI Ratification process.

• To the following individuals who wrote content that was incorporated into this version of the specification – in alphabetical order:

o Steve Edwards of Curtiss-Wright Controls Embedded Computing o Bob Ford of The Boeing Company o Jim Goldenberg of General Electric o Paul Mesibov of PENTEK o Mike Munroe of Elma Bustronic Corp. o Greg Rocco of Mercury Computer Systems o David Slaton of General Electric o Serge Tissot of Kontron

Greg Rocco Mercury Computer Systems VITA 65 Technical Working Group Chair and Lead Editor Feb. 28, 2012


VITA 65 Working Group Members Who Contributed to this Standard

Name Company

David Hinkle Elma Electronic, Inc.

Chris Eckert General Electric

Steve Edwards Curtiss-Wright Controls Embedded Computing

Fred Fons Foxconn Electronics

Robert Ford The Boeing Company

Scott Goedeke Northrop Grumman

Jim Goldenberg General Electric

Jay Grandin Annapolis Micro Systems, Inc.

Paul Griffith Concurrent Technologies

Val Gueorguiev

Pete Jha Curtiss-Wright Controls Embedded Computing

Paul Mesibov PENTEK INC

Michael Munroe Elma Bustronic Corp.

Greg Rocco Mercury Computer Systems

John Rynearson VITA

Pat Shaw General Dynamics Canada

Andrew Shieh CSPI

David Slaton General Electric

Bob Sullivan Curtiss-Wright Controls Embedded Computing

Michael Thompson Pentair

Kevin Thorson Lockheed Martin

Serge Tissot Kontron Modular Computers S.A.S

Dan Toohey Mercury Computer Systems

Ben Winder Curtiss-Wright Controls Embedded Computing


Lead Editor

The lead editor for the creation of this document was:

Greg Rocco Mercury Computer Systems, Inc. 199 Riverneck Road Chelmsford, MA 01824-2820 direct: 978-967-1346 switchboard: 978-256-1300 email: [email protected]

Comments, Correction, and/or Additions

Anyone wishing to provide comments, corrections and/or additions to this standard please direct them to the VITA Technical Director:

John Rynearson, Technical Director VITA PO Box 19658 Fountain Hills, AZ 85269 Ph: 480 837 7486 Email: [email protected]

VSO and Other Standards

Should anyone want information on other ANSI/VITA standards, the VME Handbook, or general information on the embedded market, please contact the VITA office at the address, telephone number, or URL shown on the front cover.

mailto:[email protected]


Changes from [VITA 65-2010]

The change bars in this document show changes from [VITA 65-2010], with the exception of very minor changes such as formatting and punctuation.

This section does not highlight all changes. Here are examples of changes that are not specifically listed in this section:

• Formatting changes are not listed (these are also not indicated by change bars).

• Minor changes to informative text are not listed.

• There were several places where there were minor problems with Section headers, table titles or figure titles, these are not listed. For example Figure 10.3.1-1, had been labeled as a “Payload Slot Profile” but the title of the Section it is labeled “Peripheral Slot Profile”.

With Sections that were re-written, in order to keep the reference numbers, for the requirements, in the new version of this document, unique from the numbers used to reference requirements in the previous version, the sequence numbers in sections that are re-written start with a sequence number that is larger than the largest number in the previous version of the section. Here is the section that was re-written:

• Section 5.3 — This section was re-written. The Working Group decided that the PCIe topology information that was included in [VITA 65-2010] was confusing. We decided to make the issues of PCIe topology, that were being covered in Section 5.3 of [VITA 65-2010], beyond the scope of this document. Also, the re-write allows for a Common Reference Clock whereas [VITA 65-2010] did not.

Some errors with [VITA 65-2010] were found. With the exception of the re-write of Section 5.3, requirements that were deleted, that had other requirements following them, in the same section, were left in place, with “***Deleted***”, inserted at the beginning of the requirement. This preserves requirement number, so the numbering of other requirements does not change and to makes it clear that the requirement was deleted, in case it was referenced by an external document. The text of the deleted requirement is struck through. Here is a list of corrections and other changes:

• Updated Section 1.2 to reflect sections that were added to accommodate new protocols and connector types.

• With Section 1.3.2, the following terms were added to the Glossary:

o IB (InfiniBand) o PCIe Common Reference clock o TFP (Triple Fat Pipe)

• With Section 1.3.2, the following terms were removed from the Glossary:

o System Root Complex


• With Section 1.3.2, there were some changes to existing items in the Glossary, as indicated by change bars.

• Updated Section 1.3.3, to reflect the construction of Profile names including VITA 67 connectors.

• Section 1.3.4 (Backplane Profile Topologies) added text and figures to better defined the terminology used to refer to topologies.

• Section 1.4 was re-written to not refer to the VITA internal documentation concerning the maintenance of VITA 65.

• Section 1.5 gives the references. In [VITA 65-2010] the revision of references was not included. Now it is. In addition to adding revisions to references, text was added to the introduction of Section 1.5 to explain that references might be out of date.

• Observation 2.1.1-1 was deleted. This was mentioning a template for compliance that has not been implemented.

• Rules, associated with resistance value, were re-worded to make it so that a resistance, within a tolerance range is required, as opposed to requiring a particular value and tolerance of a resistor. For example instead of saying “a 4.7 Kohm +/- 5% resistor” is required, we say a “resistance of 4.7 Kohm +/- 5%” is required. These changes did not change the resistance value that was required to meet the requirement. Here is a list of the Rules changed in this way: Rule 3.4.3-3, Rule 3.4.4-2, Rule 3.4.4-3, Rule 3.6-2, and Rule 3.6-4.

• It was felt that Recommendation 3.4.3-1 was not clear and was not adding enough value, so it was deleted.

• With Permission 5.1.2-2, Observation 5.1.2-1, and Observation 5.1.2-2; changed “1000BASE-KX4” to “10GBASE-KX4”. The “1000BASE-KX4” was there in error.

• There was redundancy between Rule 7.4-1 and Rule 7.4-2. Deleted Rule 7.4-2 and reworded Rule 7.4-1.

• The beginnings of the Backplane Profiles Sections; Sections 11 and 15 were reorganized and additional tables were added to the start of Section 15, to account for the addition of Profiles that include other than VITA 46.0 connectors.

• With Rule 11.2.1.2.4-6 and Rule 15.2.1.2.4-6 there is a note saying the physical slot numbers can be different from the ones in this document. To make it more clear changed “the Slot numbers in this document” to “the logical Slot numbers in this document”.

• Rule 11.2.2.3-4 was changed to correct a signal name from “CSutp16” to “CPutp16”.

• The following Observations were changed to make them consistent with the re-write of Section 5.3: Observation 11.2.2.4-1, Observation 11.2.3.4-1, Observation 11.2.4.4-1, Observation 11.2.5.4-1, Observation 11.2.6.4-1, Observation 11.2.7.4-1, Observation 11.2.8.4-1, Observation 11.2.9.4-1,


• The following is a list of Rules that were deleted because they were requiring baud rates for the Control Plane, when the associated Backplane Profile did not route the Control Plane, in the backplane: Rule 11.2.7.3-2, Rule 11.2.9.3-2, Rule 11.2.11.4-5, Rule 11.2.15.3-3, Rule 15.2.7.3-3, Rule 15.2.14.3-4.

• With Permission 11.2.12.1-1, changed “Modules can be used” to “Modules may be used”.

• Figure 11.2.11-1 was changed to add the Management Plane and make the way groups of slots are labeled (e.g. Payload Slots vs. Bridge Slots) and the headings of the columns of Table 11.2.11-1 were changed to be consistent with the updated figure.

• Of the Module Profile Sections that were present in [VITA 65-2010], the following InfiniBand Module Profiles were added:

o MOD6-PAY-4F1Q2U2T-12.2.1-13 o MOD6-SWH-16U20F-12.4.2-10

• Rule 14.4.1.3-1 Had been worded saying that there were five Fat Pipes on P1/J1 and half of P2/J2, but there is only 1 of these 5 Fat Pipes on P2/J2, so fixed wording.

• Sections 15.2.7.4 and 15.2.14.4 were changed to allow another option for which Data Plane ports connect to which, adding Table 15.2.7-3 and Table 15.2.14-3.

• Fixed numbering with following with Observation 15.2.8.1-1 (was 15.2.8-1).

• Fixed numbering with Observation 15.2.9.1-1 (was 15.2.9-1), changed: “have an adverse affect on RTM” to “have an adverse effect on RTM”.

• Permission 15.2.10.1-1 was a duplicate, so it was deleted. This was the only requirement in Section 15.2.10.1, but left the section so number of subsequent sections would not be effected.

• There were two rules numbered Rule 15.2.12.3-3, fixed the second one to be Rule 15.2.12.3-4.

• With Rule 15.2.12.3-3, Rule 15.2.13.1-1, and Rule 15.2.13.1-2 changed the verification method from “VM=T,I” to “VM=I”.

• The Backplane Profile of Section 15.2.13 was missing a Utility Plane section. It was added to the end as Section 15.2.13.5.

• Several 3U Module Profile Sections had the Port Names for the Expansion Plane incorrect in the column headings of Module Profile tables. The Expansion Plane Port names were deleted, for consistency with the 6U Module Profile Sections. This problem was fixed in the following: Table 16.2.1-1, Table 16.2.2-1, and Table 16.2.4-1.

• With Table 16.4.8-1, the profile names were incorrect, changed “2F12T” to “1F14T”.

Section 1.2 gives an overview other structure and explains that this document is structured in a way to allow new content to be added without disturbing existing content. Here is a list of new sections:

• Section 3.4.9 Auxiliary Resets (AXreset*)


• Section 5.4 InfiniBand® (IB)

• Section 6.4 Common Requirements for Slot Profiles Using VITA 46.0 and VITA 67 connectors

• Section 10.2.5 Payload Slot Profile SLT6-PAY-2F2U2T-10.2.5

• Section 10.2.6 Payload Slot Profile SLT6-PAY-4F1Q2U2T-10.2.6

• Section 10.2.7 Payload Slot Profile SLT6-PAY-4F2Q2U2T-10.2.7

• Section 10.3.5 Peripheral Slot Profile SLT6-PER-1Q-10.3.5

• Section 10.4.5 Switch Slot Profile SLT6-SWH-16U16F-10.4.5

• Section 11.2.17 16-Slot — BKP6-CEN16-11.2.17-n (14 Payload + 2 Switch)

• Section 11.2.18 6-Slot — BKP6-DIS06-11.2.18-n (6 Payload)

• Section 11.2.19 9-Slot — BKP6-DIS09-11.2.19-n (9 payload)

• Section 11.2.20 7-Slot — BKP6-HYB07-11.2.20-n (3 Payload + 2 VME Bridge + 2 VME)

• Section 12.2.5 Payload Module Profiles MOD6-PAY-2F2U2T-12.2.5-n

• Section 12.2.6 Payload Module Profiles MOD6-PAY-4F1Q2U2T-12.2.6-n

• Section 12.2.7 Payload Module Profiles MOD6-PAY-4F2Q2U2T-12.2.7-n

• Section 12.3.5 Module Profiles MOD6-PER-1Q-12.3.5-n

• Section 12.4.5 Module Profiles MOD6-SWH-16U16F-12.4.5-n

• Section 14.2.11 Payload Slot Profile SLT3-PAY-2F4F2U-14.2.11

• Section 14.2.12 Payload Slot Profile SLT3-PAY-1F2U-14.2.12

• Section 14.2.13 Payload Slot Profile SLT3-PAY-3F2U-14.2.13

• Section 14.4.9 Switch Slot Profile SLT3-SWH-6F8U-14.4.9

• Section 14.6 3U Payload Slot Profiles Using VITA 46.0 and 67 connectors

• Section 14.6.1 Payload Slot Profile SLT3-PAY-1F1F2U4R-14.6.1

• Section 14.6.2 Payload Slot Profile SLT3-PAY-4F4R-14.6.2

• Section 15.2.15 8-Slot — BKP3-CEN08-15.2.15-n (6 Payloads + 2 integrated Switches)

• Section 15.2.16 8-Slot — BKP3-CEN08-15.2.16-n (6 Payloads + 2 segregated Switches)

• Section 15.2.17 9-Slot — BKP3-CEN09-15.2.17-n (8 Payload + 1 Switch)

• Section 15.3 3U Backplane Profiles Using VITA 46.0 and 67 connectors— new section

• Section 15.3.1 Common Section for 3U Backplanes Using VITA 46.0 and VITA 67 Connectors


• Section 15.3.2 5-Slot — BKP3-DIS05-15.3.2-n (2 Payload + 3 Payload with RF Cavities)

• Section 15.3.3 5-Slot — BKP3-CEN05-15.3.3-n (2 Payload + 2 Payload with RF Cavities and 1 Switch)

• Section 16.2.10 Payload Module Profiles MOD3-PAY-2F4F2U-16.2.10-n

• Section 16.2.11 Payload Module Profiles MOD3-PAY-1F2U-16.2.11-n

• Section 16.2.12 Payload Module Profiles MOD3-PAY-3F2U-16.2.12-n

• Section 16.4.10 Switch Module Profiles MOD3-SWH-6F8U-16.4.10-n

• Section 16.6 3U Payload Module Profiles Using VITA 46.0 and 67 connectors

• Section 16.6.1 Payload Module Profiles MOD3-PAY-1F1F2U4R-16.6.1-n

• Section 16.6.2 Payload Module Profiles MOD3-PAY-4F4R-16.6.2-n


1 Introduction The OpenVPX System Specification was created to bring versatile system architectural solutions to the VPX market. Based on the extremely flexible VPX family of standards, the OpenVPX standard uses module mechanical, connectors, thermal, communications protocols, utility, and power definitions provided by specific VPX standards and then describes a series of standard profiles that define slots, backplanes, modules, and Standard Development Chassis.

Interoperability is at the core of the OpenVPX philosophy. Figure 1-1 illustrates all interoperable VPX system interfaces. The OpenVPX Standard defines the allowable combinations of interfaces between the Module, Backplane and Chassis.

The OpenVPX standard acknowledges, but does not define the interfaces between the Application and the Module or Chassis (Grayed out text and lines).

Figure 1-1 System Interoperability Diagram with interface content

• Utility Signals • Sys Management • Power

• Height • Mechanical

• Pitch

• Other Functions • Functional API • Sys Management API

Enclosure: • Mechanical • Thermal • Power

Module

Application

Backplane / Slots

• Communication Protocol • Pin assignments • Utility Signals

• Sys Management • Power

• Connector

Chassis • Slot Thermal • Slot Mechanical

• Pitch • Height


1.1 OpenVPX Key Element Descriptions

Note: This section uses terms that are defined in the glossary. For the glossary see Section 1.3.2.

1.1.1 Backplane Profiles

At the center of each OpenVPX architectural definition is the Backplane Profile. This profile contains two important elements: a backplane topology for each communication plane and a slot interconnection definition for each slot type used. Backplane Profiles are summarized according to key characteristics at the beginning of the 6U and 3U Backplane Profile sections to aid the user in finding a desired architecture. All references contained in the Backplane Profile are hyperlinked for ease of access. Compatible Module Profiles with backplane referenced Slot Profiles are summarized at the beginning of the Module Profile section.

Each Backplane Profile references a Slot Profile for each slot position on the backplane and then defines how each pipe in each slot is interconnected and each pipe’s electrical performance. The Backplane Profiles defined in the OpenVPX standard are specifically targeted for use in Standard Development Chassis Profiles, however, their end use is not restricted. The Backplane Profile defines which pins or set of pins are routed in the backplane, and which pins are available on RTM (Rear Transition Module) connectors on the rear of the backplane. The Backplane Profile also defines allowed slot-to-slot pitch.

1.1.2 Slot Profiles

Slot Profiles define the connector type and how each pin, or pair of pins, is allocated. Single pins are generally allocated to the utility plane for power, grounds, system discrete signals, and system management. Differential pin/pairs are generally allocated for the three communication Planes called Control, Data, and Expansion. Differential paired pins are grouped together to form “pipes”. The definition of Planes, Pipes, and Profiles can be found in the Glossary. Finally, Slot Profiles also determine which pins are user defined. Slot Profiles are categorized as either Payload or Switch. Payload Slots are further divided into sub-categories such as, but not limited to, Peripheral, Storage, and Bridge.

1.1.3 Standard Development Chassis Profiles

Within the context of OpenVPX, a Standard Development Chassis is targeted for Plug-In module system integration and test. OpenVPX defines three variants of Standard Development Chassis: small, medium, and large. The Standard Development Chassis Profiles also allow for 6U or 3U height and forced air or conduction-cooled modules. All Chassis Profiles assume the use of Rear Transition Modules for access to the majority of user defined pins.


1.1.4 Module Profiles

The Module Profile defines what communication protocol can be used on each pipe as defined in a corresponding Slot Profile, connector type, module height (6U/3U), and cooling method (forced air/conduction).

Table 1.1-1 summarizes the content of each profile and their relationship to each other.

Table 1.1-1 OpenVPX Profile Relationships

Module Profile Slot Profile Backplane Profile Chassis Profile

Communication Protocols Communication Plane Topology Backplane

Profile Slot Profile Compatibility Pin-Allocation Definition

Slot Profiles

Utility Signals

Connector Type Connector Type Height Height Height Height

Cooling Cooling Pitch Compatibility Pitch Pitch

1.2 OpenVPX Document Structure Description

The purpose of this section is to explain the document structure, in order to assist the reader in navigating the document.

The OpenVPX document structure is best described as a hierarchical descending tree, illustrated in Figure 1.2-1 through Figure 1.2-6. Generally, OpenVPX sections 5 and on are designed to accept new content, in the form of new sub-sections, as new serial technologies, new slot, backplane and module definitions emerge from the VPX market.


Figure 1.2-1 Profile Tree Structure

Figure 1.2-2 Protocol Specific Structure

Backplane Profile

Slot Profiles

Chassis Profile

Module Profiles

Slot Profiles

Module Profiles

Section 5.1: Ethernet

Section 5.1.1: 1000BASE-BX

Section 5: Protocol Specific

Section 5.1.2: 1000BASE-KX

Section 5.1.n: Other Ethernet

standards

Section 5.2: Serial Rapid I/O

Section 5.3: PCI-Express

Section 5.4: InfiniBand® (IB)


Figure 1.2-3 Slot Profile Structure

Slot Profile 1

Slot Profile 2

Slot Profile n

Sections 10.2 – 10.5: VITA 46.0 Connector

Based 6U Slot Profiles

Section 6: Common Requirements 6U/3U Slot Profiles

Section 10.1: Common Requirements 6U Slot Profiles

Slot Profile 1

Slot Profile 2

Slot Profile n


Based 3U Slot Profiles

Section 14.1: Common Requirements 3U Slot Profiles

Section 6.3: Common Requirements for Slot Profiles using VITA 46.0 Connectors

Section 6.4: Common Requirements for Slot Profiles using VITA 46.0 and VITA 67 Connectors

Slot Profile 1

Slot Profile 2

Slot Profile n

Section 14.6: VITA 46.0 and VITA 67 Connector Based 3U Slot Profiles


Figure 1.2-4 Backplane Profile Structure

Backplane Profile 1

Backplane Profile 2

Backplane Profile n

Section 11.2: VITA 46.0 Connector Based 6U Backplane Profiles

Section 7: Common Requirements 6U/3U

Backplane Profiles

Section 11.1: Common Requirements 6U Backplane Profiles

Backplane Profile 1

Backplane Profile 2

Backplane Profile n

Section 15.2: VITA 46.0 Connector Based 3U Backplane Profiles

Section 15.1: Common Requirements 3U Backplane Profiles

Backplane Profile 1

Backplane Profile 2

Backplane Profile n

Section 15.3: VITA 46.0 and VITA 67 Connector

Based 3U Backplane


Figure 1.2-5 Module Profile Structure

Modules Profile 1

Modules Profile 2

Modules Profile n


Based 6U Module Profiles

Section 8: Common Requirements 6U/3U

Module Profiles

Section 12.1: Common Requirements 6U Module Profiles

Modules Profile 1

Modules Profile 2

Modules Profile n

Sections 16.2 - 16.5: VITA 46.0 Connector


Section 16.1: Common Requirements 3U Module Profiles

Modules Profile 1

Modules Profile 2

Modules Profile n

Sections 16.6: VITA 46.0 and VITA 67 Connector



Figure 1.2-6 Standard Development Chassis Profile Structure

1.3 Terminology

1.3.1 Specification Key Words

To avoid confusion and to make very clear what the requirements for compliance are, many of the paragraphs in this standard are labeled with keywords that indicate the type of information they contain. These keywords are listed below:

• Rule

• Recommendation

• Suggestion

• Permission

• Observation

Any text not labeled with one of these keywords is to be interpreted as descriptive in nature. These will be written in either a descriptive or a narrative style.

Sections 13.2: Based 6U Dev. Chassis Profiles

Section 9: Common Requirements 6U/3U Dev. Chassis Profiles

Section 13.1: Common Requirements 6U Dev

Chassis Profiles

Section 13.1.1: VITA 48.1 Air-Cooled Dev. Chassis

Section 13.1.2: VITA 48.2 Conduction-Cooled Dev.

Chassis

Sections 17.2: Based 3U Dev. Chassis Profiles

Section 17.1: Common Requirements 3U Dev

Chassis Profiles

Section 17.1.1: VITA 48.1 Air-Cooled Dev. Chassis

Section 17.1.2: VITA 48.2 Conduction-Cooled Dev.

Chassis

Section 9.2: 6U/3U VITA 48.1 Air-Cooled Dev. Chassis

Section 9.3: 6U/3U VITA 48.2 Conduction-Cooled Dev. Chassis


Key words are reserved for specific use as defined in subsequent sections.

1.3.1.1 Rule <section>-<number>:

Compliance with Rules is mandatory. Rules always include the term “shall”. Rules are expressed in some combination of text, figures, tables, or drawings. All Rules will be followed to ensure compatibility between board and backplane designs. All Rules use the “shall” or “shall not” words to emphasize the importance of the Rule. The “shall” or “shall not” words are reserved exclusively for stating Rules in this draft standard and are not used for any other purpose.

1.3.1.2 Recommendation <section>-<number>:

Compliance with Recommendations is optional. Recommendations always include the term “should”. Recommendations are used to convey implementation advice based on the community’s collective knowledge base. Wherever a Recommendation appears, designers would be wise to take the advice given. Doing otherwise might result in poor performance or awkward problems. Recommendations found in this standard are based on experience and are provided to designers to speed their traversal of the learning curve. All Recommendations use the “should” or “should not” words to emphasize the importance of the Recommendation. The “should” or “should not” words are reserved exclusively for stating Recommendations in this draft standard and are not used for any other purpose.

1.3.1.3 Suggestion <section>-<number>:

A Suggestion contains advice, which is helpful but not vital. The reader is encouraged to consider the advice before discarding it. Some design decisions that need to be made are difficult until experience has been gained. Suggestions are included to help a designer who has not yet gained this experience.

1.3.1.4 Permission <section>-<number>:

Compliance with Permissions is optional. Permissions always include the term “may”. In some cases, a Rule does not specifically prohibit a certain design approach, but the reader might be left wondering whether that approach might violate the spirit of the Rule or whether it might lead to some subtle problem. Permissions reassure the reader that a certain approach is acceptable and will cause no problems. All Permissions use the “may” words to emphasize the importance of the Permission. The lower-case “may” words are reserved exclusively for stating Permissions in this draft standard and are not used for any other purpose.

1.3.1.5 Observation <section>-<number>:

Observations do not offer any specific advice. They usually follow naturally from what has just been discussed. They spell out the implications of certain Rules and bring attention to things that might otherwise be overlooked. They also give the rationale behind certain Rules so that the reader understands why the Rule must be followed.


1.3.2 Glossary

Table 1.3.2-1 gives terms that are used within the body of the specification. In this context, they have the meanings given in the Table.

Table 1.3.2-1 Glossary Term Definition Backplane Profile See Profile.

Bridge Module See Module.

Bridge Slot See Slot

Bus A multi-drop physical interconnection between three or more entities. Example: The physical interconnection of [VITA 46.0] defines SM[3:0] as going to all slots, hence SM[3:0] is a bus.

Channel A point-to-point physical interconnection between exactly two entities. The width of a Channel can vary across Channel instances. Example: A single 4x Serial RapidIO connection between a given Payload Module slot and a Switch Module slot.

Chassis A physical enclosure that provides module and backplane resources defined by one or more Profiles necessary to implement the logical functionality specified by one or more system implementations.

ChMC Chassis Management Controller. ChMCs are optional System Management components, defined by [VITA 46.11].

Compatibility The ability of an item not meeting all requirements of compliance to interoperate with compliant items, albeit with less capability and without impairing the compliant item’s functionality.

Compliance Conformity in fulfilling Official Requirements.

Conformity The act of verifying the item’s performance against each declared requirement.

Connector A mechanical device used to hold two parts of an electrical or optical circuit together. In OpenVPX, Connectors are used to attach and detach Modules and/or cables to other Modules and/or cables.

Control Plane See Plane.

Data Plane See Plane.


Term Definition DFP Double Fat Pipe. See Pipe.

Double Fat Pipe See Pipe.

Downstream Port See PCIe

Endpoint See PCIe

Expansion Plane See Plane.

Fabric A set of paths used for communication between elements of a system

Fat Pipe See Pipe.

FP Fat Pipe. See Pipe.

IB InfiniBand, See www.infiniband.org for more information.

Interoperability The ability of two or more items that are compliant or compatible to the same set of requirements to function together.

IPMB Intelligent Platform Management Bus, defined by [VITA 46.11].

IPMC Intelligent Platform Management Controller. IPMCs are optional System Management components, defined by [VITA 46.11].

Lane An electrical lane consists of one transmit differential pair and one receive differential pair, point-to-point, crossed connection (transmit connects to receive and receive to transmit).

An optical lane consists of a transmit and receive fiber, point-to-point, crossed connection.

Management Plane See Plane.

http://www.infiniband.org/


Term Definition Module A printed wire assembly which conforms to defined mechanical and

electrical specifications. Preexisting examples of Modules that are applicable to OpenVPX include 3U Plug-In Modules; 6U Plug-In Modules; backplanes, mezzanine Modules such as XMC, PMC, or FMC Modules; and Rear Transition Modules. Additionally, the following Module types are defined by OpenVPX:

Bridge Module: A Plug-In Module in an OpenVPX system that might be required to provide communication paths between multiple Plug-In Modules that support different Plane protocols and/or implementations. When the transfer of information is necessary between Plug-In Modules utilizing dissimilar interfaces for communication, the Bridge Module terminates the Channel and/or Bus from the Plug-In Module(s) communicating via the initial protocol and transmits the information along to the Plug-In Module(s) communicating via the second protocol on a separate Channel or Bus.

Payload Module: A Plug-In Module that provides hardware processing and/or I/O resources required to satisfy the needs of the top-level application. Example: A Payload Module might be an embedded processor or an I/O controller Module.

Peripheral Module: A Plug-In Module such as an I/O device interface that is usually subservient to a Payload Module. Plug-In Module: A Module that is capable of being plugged into a backplane.

Storage Module: A Module providing the functionality of a disk drive. An example is a SATA HDD/SSD (Hard Disk Drive / Solid-State Drive) carrier.

Switch Module: A Plug-In Module in an OpenVPX system that minimally serves the function of aggregating Channels from other Plug-In Modules. These Channels might be physical partitions of logical Planes as defined by a Backplane Profile. This Module terminates the aggregated Channels and provides the necessary switch fabric(s) to transfer data frames from a source Plug-In Module to a terminating Plug-In Module as defined by the assigned Channel protocol. This Module is typically used in systems that implement centralized switch architectures to achieve interconnection of their logical Planes. Distributed switch architectures typically do not include a Switch Module.

Module Profile See Profile.

Non-Transparent Port See PCIe.


Term Definition Official Requirements Those declared by this specification, as applicable to profiles and any

referenced specifications and standards.

Octal Fat Pipe See Pipe.

OFP Octal Fat Pipe. See Pipe.

Payload Module See Module.

Payload Slot See Slot

PCIe® PCI EXPRESS®. See http://www.pcisig.com The following terms are commonly associated with PCIe

Downstream Port: A port facing away from the Root Complex.

Endpoint: A device at an end-node of a PCIe hierarchy. It is analogous to an I/O device in a conventional PCI system. A PCIe device function that has a Type 00h Configuration Space header is an end-node.

Non-Transparent Port: A PCIe port that contains the functionality of a non-transparent PCI bridge. The system behind the port and the PCIe link have separate address spaces. It is used to connect PCIe hierarchies together.

PCIe Common Reference Clock: A clock that is distributed to multiple PCIe end points. In particular the receiver of PCIe lanes uses a Common Clock as opposed to having its own local clock. See Figure 4-49 (Common Refclk Rx Architecture) in [PCIe 2 Base].

Root Complex: The device at the top of a PCIe hierarchy. It is analogous to the host bridge of bus 0 in a conventional PCI system.

Transparent Port: A PCIe port in which the system behind the port and the PCIe link share the same address space.

Upstream Port: A port facing towards the Root Complex.

Peripheral Module See Module.

Peripheral Slot See Slot

http://www.pcisig.com/


Term Definition Pipe A physical aggregation of differential pairs used for a common function

that is characterized in terms of the total number of differential pairs. A Pipe is not characterized by the protocol used on it. The following Pipes are predefined by OpenVPX:

Ultra-Thin Pipe (UTP): A Pipe comprised of two differential pairs. Example: 1000BASE-KX Ethernet, 1x Serial RapidIO, and x1 PCIe interfaces.

Thin Pipe (TP): A Pipe composed of four differential pairs. Example: 1000BASE-T interfaces.

Fat Pipe (FP): A Pipe composed of eight differential pairs. Example: 4x Serial RapidIO, x4 PCIe, and 10GBASE-KX4 interfaces.

Double Fat Pipe (DFP): A Pipe composed of sixteen differential pairs. Example: x8 PCIe interface.

Triple Fat Pipe (TFP): A Pipe composed of twenty-four differential pairs. Example: 12x InfiniBand interface.

Quad Fat Pipe (QFP): A Pipe composed of thirty-two differential pairs. Example: x16 PCIe interface.

Octal Fat Pipe (OFP): A Pipe composed of sixty-four differential pairs. Example: x32 PCIe interface.

Plane A physical and logical interconnection path between elements of a system used for the transfer of information between elements. The following Planes are predefined by OpenVPX:

Control Plane: A Plane that is dedicated to application software control traffic.

Data Plane: A Plane that is used for application and external data traffic.

Expansion Plane: A Plane that is dedicated to communication between a logical controlling system element and a separate, but logically adjunct, system resource.

Management Plane: A Plane that is dedicated to the supervision and management of hardware resources. Functional definitions for this Plane are provided in the [VITA 46.11] specification.

Utility Plane: A Plane that is dedicated to common system services and/or utilities.

Plug-In Module See Module.

Port A physical aggregation of pins for a common I/O function on either a Plug-In Module’s backplane Connectors or a backplane slot’s Connectors.


Term Definition Profile Backplane Profile: A physical definition of a backplane implementation

that includes details such as the number and type of slots that are implemented and the topologies used to interconnect them. Ultimately a Backplane Profile is a description of Channels and Buses that interconnect slots and other physical entities in a backplane.

Standard Development Chassis Profile: A physical definition of a Standard Development Chassis implementation that includes details such as the chassis type, slot count, primary power input, module cooling type, Backplane Profile, and supplied backplane power, that are implemented in the Standard Development Chassis Profile.

Module Profile: A physical mapping of Ports onto a given Module’s backplane Connectors and protocol mapping(s), as appropriate, to the assigned Port(s). This definition provides a first-order check of operating compatibility between Modules and slots as well as between multiple Modules in a Chassis. Module Profiles achieve the physical mapping of ports to backplane connectors by specifying a Slot Profile. Multiple Module Profiles can specify the same Slot Profile.

Slot Profile: A physical mapping of Ports onto a given slot’s backplane connectors. These definitions are often made in terms of Pipes. Slot Profiles also give the mapping of Ports onto Plug-In Module’s backplane connectors. Unlike Module Profiles, a Slot Profile never specifies protocols for any of the defined Ports.

QFP Quad Fat Pipe. See Pipe.

Quad Fat Pipe See Pipe.

PCIe Common Reference Clock

See PCIe

Root Complex See PCIe

RTM Rear Transition Module. A Plug-In Module intended to provide additional I/O breakout options. RTMs are mated to the rear side of a backplane, hence the name.

SAS Serial Attached SCSI (Small Computer System Interface). See http://www.t10.org/

SATA Serial ATA (Advanced Technology Attachment). A serial interface typically used to connect to storage devices. See http://www.sata-io.org

http://www.t10.org/

http://www.sata-io.org/


Term Definition Slot A physical space on a OpenVPX backplane with a defined mechanical

and electrical specification intended to accept a Plug-In module. Preexisting examples of slots that are applicable to OpenVPX include 6U and 3U. Additionally, the following slot types are defined by OpenVPX:

Bridge Slot: A space in an OpenVPX system that will accept a Bridge Module that provides communication paths between multiple Plug-In Modules that support different Plane protocols and/or implementations.

Payload Slot: A space in an OpenVPX system that will accept a Payload Plug-In Module such as, but not limited to, a hardware processing and/or I/O Plug-In Module.

Peripheral Slot: A space in an OpenVPX system that will accept a Peripheral Plug-In Module that is usually subservient to a Payload Module. Storage Slot: A space in an OpenVPX system that will accept a Storage Plug-In Module, such as a module providing the functionality of a disk drive.

Switch Slot: A space in an OpenVPX system that will accept a Switch plug-in Module.

Slot Profile See Profile.

SRIO Serial RapidIO®. See http://www.rapidio.org

Standard Development Chassis

A chassis for use in an controlled environment such as a laboratory or office. The OpenVPX specification defines Standard Development Chassis Profiles to address common engineering development, integration, and test activities. However, there are no restrictions on how any OpenVPX Standard Development Chassis Profile can be used. Note: There may also be development chassis that are beyond the scope of this specification that are for targeted for particular applications.

Storage Module See Module.

Storage Slot See Slot

Switch Module See Module.

Switch Slot See Slot

TFP Triple Fat Pipe. See Pipe

Thin Pipe See Pipe.

http://www.rapidio.org/


Term Definition TP Thin Pipe. See Pipe.

Triple Fat Pipe (TFP) See Pipe

Ultra-Thin Pipe See Pipe.

Upstream Port See PCIe.

User I/O Plug-In Module Ports that are defined by application requirements beyond the Control Plane, Data Plane, Expansion Plane, Management Plane, and Utility Plane physical implementations. User I/O Ports are typically implemented as rear transition area access Ports but might also be implemented as application-specific backplane interconnections between slots and/or other backplane entities.

Utility Plane See Plane.

UTP Ultra-Thin Pipe. See Pipe.

Verification Verification is accomplished by one or more of several accepted methods: Inspection, Demonstration, Analysis, Test.

1.3.3 Profile Names – Use and Construction

This informative section provides a description of Profile Names that are used throughout this document. OpenVPX profiles can be classified into one of three main categories:

• Slot (SLT)

• Backplane (BKP)

• Module (MOD)

Each profile is assigned a unique name as described in the sections below.


1.3.3.1 Slot Profiles

Slot Profiles use the naming format as per Figure 1.3.3.1-1. Note the ‘Fabric Information’ parameter in the SLT profile name is read from J0 to J2 (3U) or J6 (6U) (or equivalent for alternate connectors) as pipes are encountered.

SLTu-WWW-xYxY-z.z.z

Categorization Type

Form Factor

Module Type

Fabric Information

OpenVPX Doc Section

Port Quantity

Port Size

Figure 1.3.3.1-1 Slot Profile Name Construct

The parameters in Figure 1.3.3.1-1 are described below:

SLT Slot Category

u Form-factor {3 | 6}

Where 3 = 3U VPX 6 = 6U VPX

WWW Slot Type {BRG | PAY | PER | STO| SWH}

Where BRG = Bridge card PAY = Payload card PER = Peripheral card STO = Storage card SWH = Switch card

Note: The following pattern “xY” is repeated for each set of pipes defined by the slot profile. Only two example pipes are shown in Figure 1.3.3.1-1, however there can be more or less, depending on the slot definition.

x Port Quantity {1 to n}


Y Port Size {U | T | F | D | Q | O | V } Where U = UTP T = TP F = FP D = DFP Q = QFP O = OFP V = VME R = RF/analog coaxial

z.z.z OpenVPX section number

1.3.3.2 Backplane Profiles

The Backplane Profiles use the naming format as per Figure 1.3.3.2-1.

BKPu-XXXyy-z.z.z-m

Categorization Type

Form Factor

TopologyOpenVPX Doc

sub-sectionConfiguration

Sequence Number

Total Slot

Count

Figure 1.3.3.2-1 Backplane Profile Name Construct

The parameters Figure 1.3.3.2-1 in are described below.

BKP Backplane

u Form-factor {3 | 6 }

Where 3 = 3U VPX 6 = 6U VPX

XXX Topology of Data Plane {CEN | DIS | HYB } (See Section 1.3.4)

Where CEN = Centralized topology DIS = Distributed topology HYB = Hybrid topology


yy Total Slot Count {01 to 20}


m A sequence number assigned each variant of backplane configuration to uniquely identify it within the backplane profile section {1 to n}

1.3.3.3 Module Profiles

Module Profiles use the naming format as per Figure 1.3.3.3-1. Note the ‘Fabric Information’ parameter in the MOD profile name is read from P0 to P2 (3U) or P6 (6U) (or equivalent for alternate connectors) as pipes are encountered.

MODu-WWW-xYxY-z.z.z-m

Categorization Type

Form Factor

Module Type

Fabric Information

OpenVPX Doc Section

Port Quantity

Port Size

ConfigurationSequence Number

Figure 1.3.3.3-1 Module Profile Name Construct

The parameters Figure 1.3.3.3-1 in are described below:

MOD Module

u Form-factor {3 | 6} Where 3 = 3U VPX 6 = 6U VPX

WWW Module Type {BRG | PAY | PER | STO| SWH}

Where BRG = Bridge card PAY = Payload card PER = Peripheral card STO = Storage card SWH = Switch card


Note: The following pattern “xY” is repeated for each set of pipes defined by the module profile. Only two example pipes are shown in Figure 1.3.3.3-1, however there can be more or less, depending on the module definition

x Port Quantity {1 to n} Y Port Size {U | T | F | D | Q | O | V }

Where U = UTP T = TP F = FP D = DFP Q = QFP O = OFP V = VME R = RF/analog coaxial


m A sequence number assigned each variant of module profile configuration

to uniquely identify it within the module profile section {1 to n}


1.3.4 Backplane Profile Topologies

The first part of this section goes through topologies in general (Figure 1.3.4-1 thru Figure 1.3.4-8). Starting with Section 1.3.4.1, the part of the Backplane Profile naming, that reflects topology is explained.

Figure 1.3.4-1 thru Figure 1.3.4-4 give examples of Star Topologies. A Star is where Payload Slots are connected through centralized Switch Slots. Note: For the purpose of the discussion in this Section, a Peripheral Slot is considered a type of Payload Slot.

• A Single Star is where there is a single Switch Slot and every Payload Slot is connected to this Switch Slot. See Figure 1.3.4-1.

• A Dual Star, using two Switch Slots (or Redundant Star), is where there are two Switch Slots and every Payload Slot is connected to both Switch Slots. There are generally links between the Switch Slots as well, but this is not needed to be a Dual Star. See Figure 1.3.4-2.

• A Dual Star, using a single Switch Slot, is where there is a single Switch Slot and every Payload Slot is connected to the Switch Slot with two links (pipes). See Figure 1.3.4-3.

• An Extended Star is a star topology where some or all of the Payload Slots are connected to the Switch Slot through intermediate hops. See Figure 1.3.4-4.

Figure 1.3.4-1 Example of Single-Star Topology


Figure 1.3.4-2 Example of Dual-Star Topology using two Switch Slots

Figure 1.3.4-3 Example of Dual-Star Topology using a Single Switch Slot


Figure 1.3.4-4 Example of Extended-Star Topology


Figure 1.3.4-5 and Figure 1.3.4-6 give examples of Mesh topologies. A Mesh Topology is where Payload Slots are directly connected to other Payload Slots, without the use of a centralized Switch Slot.

• A Full Mesh is a mesh topology in which every Payload Slot is directly connected to every other Payload Slot. See Figure 1.3.4-5.

• A Partially Mesh is a Mesh Topology in which not all Payload Slots are directly connected to each other. In this case they are connected through one or more intermediate Payload Slots. See Figure 1.3.4-6.

Figure 1.3.4-5 Example of Full Mesh Topology

Figure 1.3.4-6 Example of Partial Mesh Topology


Figure 1.3.4-7 gives examples of Daisy-Chain topologies. A Daisy-Chain topology is where slots are connected linearly, so that there is a single path between one end of the chain and the other.

Figure 1.3.4-7 Examples of Daisy-Chain Topologies

Figure 1.3.4-8 gives examples of Ring topologies. A Ring topology is similar to a Daisy-Chain, except that the ends of the chain are connected to each other to form a ring.

Figure 1.3.4-8 Examples of Ring Topologies


Section 1.3.3.2 gives the construction of Backplane Profile names. The Sections that follow define the topology field of the Backplane Profile names in more detail. The topology of the Data Plane is used as the primary differentiator among the topologies of the Backplane Profiles. The topologies are as follows:

1.3.4.1 CEN — Centralized

The topology is a star, with one or more centralized switches. Generally one or more Switch Slots is the center of the star with Payload Slots as the points. For generic topologies, of this type, see Figure 1.3.4-1, Figure 1.3.4-2, Figure 1.3.4-3, and Figure 1.3.4-4. For examples of Backplane Profiles, see:

• 11.2.2 16-Slot — BKP6-CEN16-11.2.2-n (14 Payload + 2 Switch)




• 15.2.12 6-Slot — BKP3-CEN06-15.2.12-n (1 Payload + 4 Peripheral + 1 Switch)

Instead of the center of the star being a Switch Slot, it can also be a Payload Slot. Typically in these cases the Payload Slot is intended for a Plug-In Module, something like an SBC (Single Board Computer) that connects to multiple Peripheral Slots. Such a Plug-In Module at the center of the star might just connect to the points of the star or it might have a Switch that enables peer-to-peer traffic among the points of the star. PCIe is a common protocol for systems based on these types of topologies. Some examples of these are:

• 11.2.13 9-Slot — BKP6-CEN09-11.2.13-n (1 Payload + 8 Peripheral)





1.3.4.2 DIS — Distributed Topology

These are topologies that are intended to be used by Plug-In modules that each contribute to the Switching as opposed to having centralized resources for Switching. These can be mesh, daisy-chain, ring topologies, or some combination. For generic topologies, of this type, see Figure 1.3.4-5, Figure 1.3.4-6, Figure 1.3.4-7, and Figure 1.3.4-8. For examples of Backplane Profiles, see:

• 11.2.10 6-Slot — BKP6-DIS06-11.2.10-n (5 Payload + 1 Switch)

• 11.2.16 5-Slot — BKP6-DIS05-11.2.16-n (5 Payload)

• 15.2.8 2-Slot — BKP3-DIS02-15.2.8-n (1 Payload + 1 Peripheral)

• 15.2.13 5-Slot — BKP3-DIS05-15.2.13-n (3 Payload + 2 Peripheral)

• 15.2.14 6-Slot — BKP3-DIS06-15.2.14-n (5 Payload + 1 Switch)

1.3.4.3 HYB — Hybrid Topology

These are topologies that are a hybrid between a point-to-point switched topology and a bussed topology. The point-to-point switched topology might be either Centralized or Distributed. The bussed might be something like VME bus. Some examples of these are:

• 11.2.11 17-Slot — BKP6-HYB17-11.2.11-n (12 Payload + 3 VME + 2 Switch)

• 11.2.12 8-Slot — BKP6-HYB08-11.2.12-n (1 Payload + 3 Peripheral + 1 VME Bridge + 3 VME)

1.4 Adding New Profiles to this Standard

To add new profiles to this standard, contact the VITA Technical Director, who can put you in touch with the appropriate members of the VITA 65 Working Group. The address for the VITA Technical Director is given in the “Comments, Corrections, and/or Additions” Section in the front matter of this document.

1.5 References

The publications listed in this Section are referenced by this standard. Unless otherwise specified, use the latest revision. In the event that section numbers change, with a revision of a referenced specification, the referenced version can be used to see the intended content to be referenced, then that content can be found in the latest revision.


1.5.1 VITA Standards

The standards, in the following list, that are VITA xx are available from the VMEbus International Trade Association (http://www.vita.com):

[VITA 1.1] ANSI/VITA 1.1-1997 American National Standard for VME64 Extensions

[VITA 46.0] ANSI/VITA 46.0-2007 VPX Baseline Standard

[VITA 46.1] ANSI/VITA 46.1-2007 for VMEbus Signal Mapping on VPX

[VITA 46.3] Currently in draft form, Serial RapidIO® on VPX Fabric Connector; Draft Revision 0.13, Feb. 27, 2012

[VITA 46.4] Currently in draft form, PCI EXPRESS® on VPX Fabric Connector; Draft Revision 0.15, July 21, 2010

[VITA 46.6] VITA Draft Standard for Trial Use, Gigabit Ethernet Control Plane on VPX; Draft Revision 0.7, Sept. 22, 2010, Trial Use expires March 22, 2012

[VITA 46.7] Currently in draft form, Ethernet on VPX Fabric Connector; Draft Revision 0.11, Jan. 31, 2012

[VITA 46.8] VITA Draft Standard for Trial Use, InfiniBand® on the VPX Fabric Connector; Revision 0.11, May 24, 2011, Trial Use expires May 24, 2014

[VITA 46.9] ANSI/VITA 46.9-2010 PMC/XMC Rear I/O Signal Mapping on 3U and 6U VPX Module

[VITA 46.10] ANSI/VITA 46.10-2009, Rear Transition Module on VPX

[VITA 46.11] Currently in draft form, System Management for VPX; Draft Revision 0.6, Jan. 20, 2012

[VITA 48.0] ANSI/VITA 48.0-2010 Mechanical Specifications for Microcomputers Using Ruggedized Enhanced Design Implementation (REDI)

[VITA 48.1] ANSI/VITA 48.1-2010 Mechanical Specifications for Microcomputers Using REDI Air Cooling

[VITA 48.2] ANSI/VITA 48.2-2010 Mechanical Specification for Microcomputers Using REDI Conduction Cooling Applied to VITA VPX

[VITA 65-2010] ANSI/VITA 65-2010, OpenVPX™ System Specification

[VITA 67.0] ANSI/VITA 67.0-2012, Coaxial Interconnect on VPX - Base Standard

[VITA 67.1] Currently in draft form, Coaxial Interconnect on VPX, 3U, 4 Position SMPM Configuration; Draft Revision 1.11, Jan. 10, 2012

[VITA 68] Currently in draft form, VITA 68.0 VPX Compliance Channel; Draft Revision 0.27, Sept 1, 2011

http://www.vita.com/


1.5.2 Other Standards

Other standards referenced by this document:

[ANSI B46.1] ANSI B46.1-2009 Surface Texture, Surface Roughness, Waviness and Lay; http://www.ansi.org/

[IEEE 802.3] IEEE Std 802.3TM-2008 IEEE Standard for Information technology—Telecommunications and information exchange between systems—Local and metropolitan area networks—Specific requirements Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) access method and Physical Layer specifications; http://standards.ieee.org/

[PCIe 2 Base] PCI Express® Base Specification; Rev 2.1, March 4, 2009 http://www.pcisig.com/

[PCIe 2 CEM] PCI Express® Card Electromechanical Specification; Rev 2.0, April 11, 2007 http://www.pcisig.com/

[TIA/EIA 899] TIA/EIA (March 2002) Electrical Characteristics of Multipoint-Low-Voltage Differential Signaling (M-LVDS) Interface Circuits for Multipoint Data Interchange; http://www.tiaonline.org/

1.6 Order of Precedence

Rule 1.6-1: In the event of a conflict between requirements of this standard and any referenced standards or documentation, this standard shall take precedence. [VM = VNR]

http://www.ansi.org/

http://standards.ieee.org/



http://www.tiaonline.org/


2 OpenVPX Compliance

2.1 Compliance

Product compliance is a cornerstone of the OpenVPX system philosophy. A product’s performance must be verified to all requirements listed in applicable profile(s) in order to claim compliance to this specification.

Rule 2.1-1: All requirements listed or referenced in an applicable slot, backplane, module and/or Chassis Profile shall be verified that it meets all requirements listed for a product to claim compliance to the OpenVPX specification. [VM = VNR]

Rule 2.1-2: All procedures used, and results of verification shall be documented and controlled. [VM = VNR]

Permission 2.1-1: A supplier may use a similarity argument to establish conformity for a specific Rule, Recommendation, and Permission if the implementation of the interface or function has previously established conformity with the same Rule, Recommendation, and Permission on a similar item.

2.1.1 Statement of Compliance

Any supplier of a product claiming compliance to this specification must provide, on request, a statement of compliance which clearly indicates the following from applicable profiles:

a) Rules plus verification outcome (Pass/Fail),

b) The state of Recommendations and Permissions (implemented/did not implement), and verification outcome (Pass/Fail).

In the event of a dispute arising between a product’s performance to the specification and the claim of compliance, a user might request evidence of conformity for only those requirements in dispute. The evidence of conformity might contain intellectual property or industrial secrets of a highly proprietary nature, and therefore any user, before executing a request of this nature, needs to verify both Non-Disclosure Agreements, and any contractual restrictions that might exist.

Rule 2.1.1-1: For any product claiming compliance to this specification, the supplier shall provide, on request, a Statement of Compliance. [VM = VNR]


2.1.2 Verification Method Notation

At the end of each Rule and Recommendation in section 3 and on, the verification method is specified and denoted as follows:

[VM = vmlist]

Where:

VM = Verification Method,

vmlist = Verification Method List

The Verification Method List consists of one or more of the following: I (Inspection), D (Demonstration), A (Analysis), T (Test), VNR (Verification Not Required), and are listed in the recommended order. For example:

[VM = I] means Inspection only

[VM = D,A,T] means Demonstration is recommended, Analysis and Test are permitted

[VM = T,D] means Test is recommended, Demonstration is permitted

[VM = VNR] means Verification Not Required.

Each of the four methods of verification are described in section 2.2

2.1.3 Compatibility

Items claiming compatibility will have the characteristic of Interoperability, albeit with less functionality. That is, they might have less or smaller pipes, or operate at slower speeds but will still meet the basic requirements across an interface. A product might also claim compatibility even though an interface is not implemented, for example Module Maskable Reset or Expansion Bus, as long as that item does not impair other items from implementing that functionality.

2.2 Methods

This specification uses up to four methods to establish conformity to each requirement: Inspection, Demonstration, Analysis, and Test. Each are described below. If one or more method is permitted, the supplier’s choice of method will be governed by the applicable section text, under the conditions stated in each Rule, Recommendation, or Permission.

Rule 2.2-1: Conformity shall be conducted using the method and the condition(s) indicated within each Rule, Recommendation, or Permission. [VM = VNR]

Rule 2.2-2: If VM = VNR, no verification shall be required. [VM = VNR]

Permission 2.2-1: When more than one method is indicated the supplier may choose which method best fits their internal processes.


If only one method is listed, it represents the minimum effort required to accomplish verification. Methods are considered in the following order of increasing effort: Inspection, Demonstration, Analysis, Test.

Permission 2.2-2: If only one method is listed, Suppliers may use a method of verification representing a greater level of effort to accomplish verification.

2.2.1 Inspection

The Inspection method primarily uses a static, visual means to establish conformity.

Rule 2.2.1-1: When the verification method specifies the use of Inspection as the method of establishing conformity, the item shall visually display the static characteristic either in physical or drawing form. Drawing forms are any controlled document that defines the product configuration for design, assembly, or test. Product data or marketing sheets are not acceptable drawing forms. [VM = VNR]

2.2.2 Demonstration

The Demonstration method primarily uses a dynamic, visual means of showing functionality to establish conformity. While test equipment might be required as part of the demonstration setup, measurements are typically not required.

Rule 2.2.2-1: When the verification method specifies the use of Demonstration as the method of establishing conformity, the item shall visually display the characteristic dynamic behavior when all necessary input conditions are satisfied. [VM = VNR]

2.2.3 Analysis

The Analysis method primarily uses theoretical means to establish conformity. Analysis input parameters can be based on component datasheet or empirically derived parameters.

Rule 2.2.3-1: When the verification method specifies the use of Analysis as the method of establishing conformity, the item shall be subjected to a generally accepted method of analysis for each specified characteristic. “Generally accepted”, in this context, means in accordance with common design engineering practices. [VM = VNR]

Recommendation 2.2.3-1: The validity of any Analysis increases when accompanied by testing, specifically under limited input conditions, used to validate the analysis results. Suppliers should use limited testing to validate any analysis. [VM = VNR]


2.2.4 Test

The Test method primarily uses physical measurements and test procedures to establish conformity. The Testing method is necessary when inspection, demonstration, and analysis methods are inadequate, not supported by tools, or cost prohibitive.

Rule 2.2.4-1: When the verification method specifies the use of Test as the method of establishing conformity, the item shall be subjected to a test procedure specifying setup, input conditions, and performance measurements recorded, per Rule 2.1-2. [VM = VNR]

Rule 2.2.4-2: All test equipment used in any test setup or measurement shall be calibrated in accordance with accredited standards body processes, e.g. the National Institute of Standards and Technology (NIST). [VM = VNR]

Rule 2.2.4-3: Any Unit-Under-Test (UUT) output to be used as part of a “wrap-around” test (use of UUT outputs as a stimulus to the same UUT’s inputs) shall be first tested and characterized by test equipment meeting Rule 2.2.4-2. [VM = VNR]


3 Utility Plane The Utility Plane (UP) in an OpenVPX backplane includes both common power distribution rails, common control/status signals, and common reference clocks. These definitions extend the fundamental resource definitions provided in Sections 4 and 7 of [VITA 46.0] and define new UP signals, using the same definition constructs as the signals originally defined in [VITA 46.0].

This section provides common definitions for these power rails and signals, while the slot and Backplane Profile definitions in this Design Specification provide detailed application requirements for these resources.

3.1 Maximum Number of Slots

Both Plug-In Modules and RTMs can place loads on the Utility Plane signals. This section gives the maximum number of slots that the Utility Plane is intended to have.

Rule 3.1-1: The backplane shall not have more than 21 slots. [VM = I]

Permission 3.1-1: A backplane with 21 slots may have 21 Plug-In Modules and 21 RTMs plugged in.

3.2 Power Distribution

The fundamental power distribution definitions for OpenVPX are provided in Section 4 of [VITA 46.0]. This section provides additional definitions for 5V and 12V primary power distribution, VBAT, and safety ground on the backplane. Note that OpenVPX systems currently are not defined to utilize the isolated +48V rail defined in [VITA 46.0].

3.2.1 Power Distribution Profiles for 5V and 12V primary power input modules

Recommendation 3.2.1-1: With 12V Primary Power Input Profile for 6U: The Plug-In Modules should use dc/dc converters on the VS1 and VS2 rails, and utilize the VS3, 3.3V_AUX, and 12V_AUX (+-) rails directly for internal circuits and installed mezzanines. [VM = VNR]

Recommendation 3.2.1-2: With 5V Primary Power Input Profile for 6U: The Plug-In Modules should use dc/dc converters on the VS3 rail, and utilize the remaining power rails directly for internal circuits and installed mezzanines. [VM = VNR]




3.2.2 Source of VBAT

VBAT is defined by [VITA 46.0] Section 4.9.2.

Permission 3.2.2-1: A separate dedicated slot may be used to provide VBAT power within the system.

3.2.3 Safety Ground

For background concerning safety ground, see Section 3.1 of [VITA 46.0].

Provisions for tying safety ground to signal ground within a backplane:

Rule 3.2.3-1: The backplane shall provide provisions for tying safety ground to signal ground. [VM = I]

3.2.4 Inrush (Surge) Current

These Recommendations apply at any time when backplane power per Section 3.2.1 is energized, including ramp-up.

Recommendation 3.2.4-1: Any time the backplane power is energized, the ratio of instantaneous current (It) over a module's maximum rated continuous current draw (Im) should not exceed 1.25. [VM = T,D]

Recommendation 3.2.4-2: Any time the backplane power is energized, the module’s ratio (It/Im) should not exceed 1 for more than 20 ms. [VM = T,D]

Recommendation 3.2.4-3: Any time the backplane power is energized, if the module’s ratio (It/Im) has exceeded 1, it should not exceed 1 again for at least 100ms following the up to 20 ms period of Recommendation 3.2.4-2. [VM = T,D]

Permission 3.2.4-1: A module vendor may assume a 20 ms backplane power rise time and a monotonic ramp-up per [VITA 46.0] Recommendation 3-3, when validating the Recommendations in this section.

3.3 Electrical Standards for Drivers and Receivers

This section provides requirements for drivers and receivers that are in addition to those given by Section 4.8.12 of [VITA 46.0]. With the electrical characteristics of this section, the current that


can be sourced or sunk when the board is not driving was decreased, to be more in line with present day components.

3.3.1 Low Current Open-Drain Electrical Characteristics

These electrical characteristics are similar to the Low Current Open Collector Electrical Characteristics of Section 4.8.12.1 of [VITA 46.0]; except the amount of current a Plug-In Module is allowed to source/sink is much lower (when it is not driving), this enables the addition of RTMs without adding too much DC load.

These rules are for OpenVPX signals defined to meet low-current open-drain electrical characteristics. These Rules are for Plug-In Modules and RTMs that are using these signals, that call out this Section’s Electrical Characteristics:

Rule 3.3.1-1: If the Plug-In Module or RTM drives or uses this signal, it shall be designed for 3.3 V signaling, on the associated pin. [VM = A,T]

Rule 3.3.1-2: If the Plug-In Module or RTM drives this signal, it shall drive it as an Open Drain signal with a steady-state driver low output level < 0.6 V while sinking a steady state current of at least 24 ma. [VM = A,T]

Rule 3.3.1-3: If the Plug-In Module or RTM receives this signal, it shall regard an input of < 0.8 V as a low and an input of > 2.0 V as a high. [VM = A,T]

Rule 3.3.1-4: Each Plug-In Module and RTM connected to this shall not load this signal with > 20 picofarads of capacitive load. [VM = A,T]

Rule 3.3.1-5: Each Plug-In Module and RTM connected to this, when not actively driving this signal shall not sink or source > 50 µa, not including pull-up resistors required by this standard. [VM = A,T]

Observation 3.3.1-1: Some CMOS devices have what is referred to a bus-holder or bus-keeper circuit. This circuit provides positive feedback, weakly pulling the input low when the input is low and weakly pulling it high, when the input is high. This circuit is intended to help keep an input in either a high or low state when it is not being driven by anything. It is expected that in order to meet Rule 3.3.1-5, it will be necessary to disable any bus-holder circuit.

Rule 3.3.1-6: Inputs receiving this signal shall operate normally, with slew rates ≥ 3 mV/ns. [VM = A,T]

Observation 3.3.1-2: The Open Drain signals that these electrical characteristics are used for tend to have long RC time constants. For example, a bus with 21 Plug-In Modules and 21 RTMs, each with a capacitance of 20 pF and a backplane of 120 pF, with a pull-up of 390 ohms would have a time constant of 374 ns. As an input passes slowing through the transition region, two different problems can occur: 1) A device can draw too much current. This is mitigated by having the device meet Rule 3.3.1-6. 2) The response to the input can glitch. This is mitigated by digitally filtering the input.


3.3.2 Lower Current Open-Drain Electrical Characteristics

These electrical characteristics are the same as those of Section 3.3.1, except the drive strength is decreased slightly, in order to make it so that more common CPLDs (Complex Programmable Logic Devices) can be used.

These rules are for OpenVPX signals defined to meet lower-current open-drain electrical characteristics. These Rules are for Plug-In Modules and RTMs that are using these signals, that call out this Section’s Electrical Characteristics:










3.3.3 High Current Open-Drain Electrical Characteristics

These electrical characteristics are similar to the High Current Open Collector Electrical Characteristics of Section 4.8.12.2 of [VITA 46.0]; except the amount of current a Plug-In Module is allowed to source/sink is much lower (when it is not driving), this enables the addition of RTMs without adding too much DC load.

These rules are for OpenVPX signals defined to meet high-current open-drain electrical characteristics. These Rules are for Plug-In Modules and RTMs that are using these signals, that call out this Section’s Electrical Characteristics:










3.4 System Control Signals

This section defines the Utility Plane (UP) signals, which provide common control functions to all Plug-In Modules on the P0/J0 and P1/J1 connectors in the VPX chassis. For the Utility Plane pin assignments see Table 3.7-1 thru Table 3.7-5.

Most of the UP control signals, including SYSRESET*, NVMRO, and SYS_CON, are generally defined in the base [VITA 46.0] specification. This section simply provides additional clarifying requirements and definitions for a subset of these signals for OpenVPX applications where appropriate. Contact assignments for these signals are provided in [VITA 46.0], in Table 4-3 (Section 4-6) for the P0 connector and Table 4-6 (Section 4-9) for the P1 connector.

This section also introduces a new UP control signal: Module Maskable Reset, which can optionally be used by a Plug-In Module as a secondary reset input.

3.4.1 System Controller (SYS_CON)

Sections 4.8.3 and 7.3.2 in the [VITA 46.0] specification define a single System Controller (SYS_CON) slot, hardwired in the backplane, and do not provide any significant function definitions or requirements for this slot. This section extends the original definition to optionally support a standby slot, optionally reassign the SYS_CON slot(s) in the backplane, and an indication of the functionality to be provided at the SYS_CON slot.

Rule 3.4.1-1: The OpenVPX backplane shall provide a SYS_CON slot, indicated by grounding the SYS_CON* contact on the J1 connector, as defined in the [VITA 46.0] specification. [VM = I]

Observation 3.4.1-1: Section 7.3.2 of [VITA 46.0] recommends that the hard-wired SYS_CON slot be the leftmost slot (slot address 1) when viewed from the front of the chassis. This specification does not make any Recommendations for placement of the hard-wired SYS_CON slot, leaving that selection to the system architect.

Rule 3.4.1-2: Any Plug-In Module containing resources to drive the following signals shall monitor the SYS_CON* contact and enable the appropriate signal driver(s) when asserted: [VM = I]

• REF_CLK+/- [P0 contacts E8, F8; J0 contacts g8, h8]

Permission 3.4.1-1: System architecture design may require additional backplane signals to be driven by the SYS_CON module.

Recommendation 3.4.1-1: Any Plug-In Module containing resources to drive the backplane signals defined in Rule 3.4.1-2 should provide a mechanism to permit application software or system management to reassign the identity of the SYS_CON module, regardless of the logic level of the backplane SYS_CON* contact, in order to control these signal drivers once the backplane power rails are all at minimum operating voltages as defined in [VITA 46.0], Section 4.8.11. [VM = D]

Permission 3.4.1-2: SYS_CON identity reassignment information may be stored in a non-volatile memory device in order to preserve the assignment through a power cycle.


Observation 3.4.1-2: The above definitions assign a known SYS_CON slot during power initialization on the backplane and then allow controlling software to reassign the SYS_CON function to any appropriate slot in the backplane once the backplane power rails have reached their respective minimum operating voltages. The system architect is responsible for SYS_CON slot reassignment and for addressing failure scenarios with such reassignment.

Observation 3.4.1-3: These definitions also allow controlling software to identify a secondary or standby SYS_CON function in the OpenVPX backplane. If this option is utilized in a given application, software is responsible for coordinating switchover from one SYS_CON module to the other.

3.4.2 System Reset (SYSRESET*)

The System Reset function on VPX backplanes is defined in Sections 4.8.11 and 7.3.9 of the [VITA 46.0] specification, utilizing a common open-drain backplane signal (SYSRESET*) on contact B4 of the P0 connector (contact c4 on backplane connector J0).

The System Reset functional definitions are extended in OpenVPX as follows:

Rule 3.4.2-1: All Plug-In Modules or RTMs (with active logic) in the OpenVPX chassis shall receive the SYSRESET* signal as an input and force all interior logic except System Management resources on the module to a known hardware reset state when the backplane signal is asserted. [VM = D,A,T]

Rule 3.4.2-2: When is used by an RTM, the RTM shall follow the Rules of Section 3.3.3, for interfacing to SYSRESET*. [VM = A,T]

Recommendation 3.4.2-1: Newly designed Plug-In Modules should follow the Rules of Section 3.3.3 (High Current Open-Drain), instead of [VITA 46.0] Section 4.8.12.2. [VM = A,T]

Recommendation 3.4.2-2: Rule 4-48 of [VITA 46.0] imposes a minimum of 10 millisecond on the length of SYSRESET*. The 10 millisecond number is a minimum, the system architect should ensure that the reset length will match all of the plug in modules. [VM = A,T]

3.4.2.1 System Management Resources

The following definitions apply to System Management resources in OpenVPX:

Recommendation 3.4.2.1-1: If a backplane has SM3 thru SM0 available on one or more plug-in module or mezzanine module connectors, the backplane should make SYSRESET* available on these same connectors. [VM = I]

Observation 3.4.2.1-1: Some items that connect to a backplane have the possibility of housing an IPMC. The connection of SYSRESET* to backplane connectors carrying SM3 thru SM0, enable an IPMC, located in a device connected to SM3 thru SM0, to monitor the


state of SYSRESET*, as allowed in [VITA 46.11]. Backplane Profiles have Rules to bring out SM3 to SM0 and SYSRESET* out on connectors (see Rule 11.2.1.2.4-1 and Rule 15.2.1.2.4-1), Recommendation 3.4.2.1-1 is to put SYSRESET* on connectors that might be used for non-VPX modules or mezzanines plugging directly into the backplane.

3.4.3 Module Maskable Reset (MaskableReset*)

MaskableReset* is an optional local reset input to a Plug-In Module provided in addition to the global SYSRESET* described above, and is a new addition to the backplane for OpenVPX systems. This specification provides a general functional description for this input and assigns a backplane pin to the signal. Detailed definitions of the conditions that drive assertion of this signal as well as the expected response to this signal on the Plug-In Module are specific to the functions provided on the module, and are controlled by the system architect and Plug-In Module designer.

Permission 3.4.3-1: A Plug-In Module or RTM deployed in an OpenVPX backplane may include a second reset input from the backplane as a complement to the SYSRESET* input.

Permission 3.4.3-2: The Plug-In Module or RTM designer may tailor the use of this reset input as appropriate for the type of Plug-In Module.

Permission 3.4.3-3: The Plug-In Module may mask this reset input.

Rule 3.4.3-1: Connector P1, contact G15 (backplane connector J1, contact i15) shall be used for MaskableReset*. [VM = I]

Rule 3.4.3-2: Contact J1-i15 shall be marked Reserved on the OpenVPX backplane if not used for MaskableReset*. No other backplane signal is to be assigned to this contact. [VM = I]

Rule 3.4.3-3: If MaskableReset* is used by a Plug-In Module, the Plug-In Module shall provide a resistance of 4.7 Kohm +/- 5% from 3.3V_AUX to MaskableReset*. [VM = I]

Rule 3.4.3-4: If MaskableReset* is used by an RTM, the RTM shall not provide a pull up resistor to 3.3V_AUX, unless the pull-up is of a high enough value to comply with Rule 3.3.2-5. [VM = I]

Observation 3.4.3-1: A 4.75 Kohm, 1% resistor meets the pull-up impedance requirement in Rule 3.4.3-3.

Rule 3.4.3-5: Plug-In Modules and RTMs using the MaskableReset* signal shall follow the Rules of Section 3.3.2 (Lower Current Open-Drain). [VM = A,T]

Rule 3.4.3-6: When driving MaskableReset* to a low, the driver of MaskableReset* signal shall hold it at low for a minimum of 10 milliseconds. [VM = D,A,T]

Rule 3.4.3-7: The MaskableReset* signal shall be held at low for a minimum of 10 microseconds, as measured at a Plug-In Module receiver interface, before the Plug-In Module will consider it to be valid. [VM = D,A,T]


Recommendation 3.4.3-1: ***Deleted***The 10 millisecond number of Rule 3.4.3-6 is the same as give by Rule 4-48 of [VITA 46.0]. The 10 millisecond number is a minimum, the system architect should ensure that the reset length will match all of the plug in modules. [VM = A,T] Note: In March 2011, the editing team decided to delete this recommendation. The number was left so that the next recommendation would not be renumbered.

Recommendation 3.4.3-2: This input should be provided to a Plug-In Module from a Rear Transition Module associated with the Plug-In Module. [VM = VNR]

Permission 3.4.3-4: The input signal from a Rear Transition Module may be bussed across the backplane to other slots if desired by the system architect.

Permission 3.4.3-5: The MaskableReset* input may be driven by another module in the chassis across the backplane.

Permission 3.4.3-6: MaskableReset* may be driven by any method deemed appropriate by the system architect or Plug-In Module designer, including a momentary contact switch, combinatorial logic, or controlling software through a register bit.



Rule 3.4.3.1-1: The reset behavior of IPMC circuitry shall not be affected by the assertion and de-assertion of the OpenVPX defined Module Maskable Reset signal. [VM = D,A,T]

Permission 3.4.3.1-1: IPMCs may monitor the state of the OpenVPX defined Module Maskable Reset signal.

Observation 3.4.3.1-1: IPMCs that observe the state of the OpenVPX defined Module Maskable Reset signal are able to determine when the Module Maskable Reset signal is being continuously asserted.

3.4.4 Non-Volatile Memory Read Only (NVMRO)

This is active high open-drain signal. It is defined in [VITA 46.0], Section 4.8.5, as being optional, to provide a hardware signal to inhibit write operations to non-volatile memory resources in the chassis when asserted. With OpenVPX, the presence of this signal on the backplane is mandatory. Plug-In modules are free to respond to or ignore this signal in a manner appropriate for the applications they are intended for. This signal is assigned to contact A4 on the P0 connector (contact b4 on the backplane J0 connector).

The NVMRO signal definition is extended for OpenVPX systems as follows:

Rule 3.4.4-1: The NVMRO signal as defined in Section 4.8.5 of the [VITA 46.0] specification shall be provided on the OpenVPX backplane. [VM = I]


Rule 3.4.4-2: Backplanes with 13 or more slots shall implement a resistance of 390 ohms +/- 5% from 3.3V_AUX to the bussed NVMRO signal (this replaces the 220-ohm value of [VITA 46.0]). [VM = I]

Rule 3.4.4-3: Backplanes with 12 or fewer slots shall implement a resistance of 220 ohms +/-5% from 3.3V_AUX to the bussed NVMRO signal. [VM = I]

Observation 3.4.4-1: The resistor of Rule 3.4.4-2 is chosen to keep the total current needed to pull NVMRO low, to be less than 24 ma (see Rule 3.3.1-2). This current can be as high as 21 * 600 µa (for Plug-In Modules, Rule 4-50h of [VITA 46.0]) + 21 * 50 µa (for RTMs from Rule 3.3.1-5) + 3.3V/390 ohm (termination resistor) = 22 ma.

Rule 3.4.4-4: When used by an RTM, the RTM shall follow the Rules of Section 3.3.1 (Low Current Open-Drain). [VM = A,T]

Recommendation 3.4.4-1: Newly designed Plug-In Modules should follow the Rules of Section 3.3.1 (Low Current Open-Drain), instead of [VITA 46.0] Section 4.8.12.1. [VM = D]

Permission 3.4.4-1: Any Plug-In Module or RTM may assert this signal.

Recommendation 3.4.4-2: Plug-In Modules and RTMs should be implemented such that if the signal glitches during transitions, it does not create a problem. Requiring the signal to be stable for 400ns after a change, before acting on the new value, would be a way of implementing this. See Observation 3.3.1-2. [VM = A,T]



Recommendation 3.4.4.1-1: If a backplane has SM3 thru SM0 available on one or more plug-in module or mezzanine module connectors, the backplane should make NVMRO available on these same connectors. [VM = I]

Observation 3.4.4.1-1: Some items that connect to a backplane have the possibility of housing an IPMC. The connection of NVMRO to backplane connectors carrying SM3 thru SM0, enable an IPMC, located in a device connected to SM3 thru SM0, to monitor and possibly react to the state of NVMRO. Backplane Profiles have Rules to bring out SM3 to SM0 and NVMRO out on connectors (see Rule 11.2.1.2.3-1 and Rule 15.2.1.2.3-1), Recommendation 3.4.4.1-1 is to put NVMRO on connectors that might be used for non-VPX modules or mezzanines plugging directly into the backplane.

3.4.5 System Management Buses (SM[3..0])

The System Management Buses are identified in [VITA 46.0], Section 4.8.8. Detailed electrical and functional specifications for these buses are provided in [VITA 46.11]. There are no OpenVPX definition extensions for these buses.


Rule 3.4.5-1: OpenVPX Backplane Profiles shall comply with System Management buses electrical specifications as defined in [VITA 46.11]. [VM = T]

Observation 3.4.5-1: Backplane Profiles might make SM(3:0) available to RTMs, if an RTM uses these signals, it is up to the System Integrator to make sure that the signal integrity is going to be OK.

3.4.6 Geographic Address Field

The Geographic Address signals assigned to the P0/J0 connector in [VITA 46.0], Section 4.8.2, are used without modification in OpenVPX.

Rule 3.4.6-1: OpenVPX Backplane Profiles shall comply with the Geographic Address Field assignments and function as defined in [VITA 46.0], Section 4.8.2. [VM = I]

3.4.7 JTAG Port

The JTAG port signal assignments provided on the P0/J0 connector in the [VITA 46.0], Section 4.8.7, are used without modification in OpenVPX.

Rule 3.4.7-1: OpenVPX Backplane Profiles shall comply with the JTAG Port assignments and function as defined in [VITA 46.0], Section 4.8.7. [VM = I]

3.4.8 User I/O

Three single-ended User I/O pin assignments on connector P1/J1 are included in the Utility Plane definition for completeness. P1 connector pins G9, G11, and G13 (backplane connector J1 contacts i9, i11, and i13, respectively) do not have any functional assignment in the [VITA 46.0] specification. These User I/O ports are generally front-to-rear interfaces controlled by the front Plug-In Module and are generally not bussed across the backplane, unless specifically called out by the particular Backplane Profile. Each port function is defined by the front Plug-In Module and associated Rear Transition Module. Some of the Slot Profiles, in Sections 10 and 14 might assign these pins.

Recommendation 3.4.8-1: Connector J1 contacts i9, i11, and i13 in an OpenVPX backplane should be reserved for User I/O signal assignments as defined by the Plug-In Module designer. [VM = I]

Permission 3.4.8-1: A Plug-In Module may assign rear I/O port functions to none, some, or all of these backplane pins.


3.4.9 Auxiliary Resets (AXreset*)

Some systems have groups of boards where there is a desire for one board to reset the others in the same group. The AXreset* signals are intended for this purpose. A typical use is as an Expansion Plane reset, but they can be used for other purposes also. Figure 5.3.2-1 shows an example where a Root Complex might want to reset Plug-In Modules that are in its PCIe Domain.

Plug-In Modules can have more than one AXreset*. These will be numbered AXreset1*, AXreset2*, …. In this section “AXreset*” is intended to refer to all of the AXreset* signals. The assignment of pins for Expansion Plane Reset and other uses of AXreset*, is left to Slot Profiles.

Permission 3.4.9-1: A Plug-In Module or RTM deployed in an OpenVPX backplane may include an AXreset* input from the backplane.

Permission 3.4.9-2: AXreset* may be bussed across multiple slots.

Rule 3.4.9-1: If an AXreset* is used by a Plug-In Module, the Plug-In Module shall provide a resistance of 4.7 Kohm +/- 5% from 3.3V_AUX to AXreset*. [VM = I]

Rule 3.4.9-2: Plug-In Modules and RTMs using the AXreset* signal shall follow the Rules of Section 3.3.2 (Lower Current Open-Drain). [VM = A,T]

Rule 3.4.9-3: If the protocol and Backplane Profile making use of AXreset* do not specify a minimum time for the driving of AXreset*; when driving AXreset* to a low, the driver of AXreset* signal shall hold it at low for a minimum of 10,000 microseconds. [VM = D,A,T]

Rule 3.4.9-4: If the protocol and Backplane Profile making use of AXreset* do not specify a length of time below which a Plug-In Module is to ignore it; a Plug-In Module shall not respond to assertions of AXreset*, less than 10 microseconds in duration, as measured at the Plug-In Module receiver interface. [VM = D,A,T]

3.5 System Reference Clocks

The OpenVPX backplane defines two differential reference clocks to be distributed among all Plug-In Modules on the P0 connector: a 25 MHz clock and a high precision periodic timing pulse. The OpenVPX backplane does not include a single-ended reference clock on the P1/J1 connector, and leaves the pin assigned for that reference clock reserved.

3.5.1 REF_CLK+/- Reference Clock

This section defines a high-precision 25 MHz reference clock on the REF_CLK+/- differential signal pair on the P0/J0 connectors as defined in [VITA 46.0], Section 4.8.4. This reference clock has tight accuracy and stability specifications and is driven differentially on the backplane in order to provide high signal integrity. It is typically used in OpenVPX applications to provide a high-precision hardware timing source for time-based processing tasks. As discussed in Section 3.4.1, REF_CLK is to be driven by the System Controller.


OpenVPX system requirements for the REF_CLK+/- signal are as follows:

Recommendation 3.5.1-1: A 25 MHz clock should be driven on the P0 connector REF_CLK+/- contacts (contacts E8 and F8), as defined in [VITA 46.0], Section 4.6, Table 4-3, adhering to the general electrical characteristics defined for a REF_CLK+/- signal defined in [VITA 46.0], Section 4.8.4 for both the signal driver and signal receivers. [VM = VNR]

Rule 3.5.1-1: If provided, the REF_CLK+/- signal shall meet the following requirements in addition to the [VITA 46.0] requirements: [VM = T,A]

• Duty cycle: minimum 40% and maximum 60% of unit interval in the asserted (logic 1) state

• Center frequency accuracy: +/-50ppm over operating environment conditions

Rule 3.5.1-2: If provided, the REF_CLK+/- signal shall only be driven by the active SYS_CON Plug-In Module. [VM = I]

Rule 3.5.1-3: If REF_CLK+/- is not provided for a given system application, the backplane REF_CLK+/- signal pair on the J0 connector shall be Reserved for all Plug-In Modules and not utilized for any other signal or function. [VM = I]

Permission 3.5.1-1: The REF_CLK+/- signal may be received and utilized by any other Plug-In Module in the OpenVPX backplane.

Observation 3.5.1-1: Backplane Profiles might make REF_CLK+/- available to RTMs, if an RTM uses this signal, it is up to the System Integrator to make sure that the signal integrity is going to be OK.

3.5.2 AUX_CLK+/- Reference Clock

This section defines an optional auxiliary 1 pulse-per-second (1 PPS) timing reference on the P0/J0 connector RES_BUS+/- bussed differential pair on the P0/J0 connector as defined in [VITA 46.0], Section 4.8.6. This reference timing source is defined with relatively tight accuracy and stability specifications and is driven differentially on the backplane in order to provide high signal integrity. This signal is typically used in OpenVPX applications to provide a high-precision hardware timing delimiter for time-based processing tasks. The driver of AUX_CLK is left to the system integrator to work out, depending on the application.

AUX_CLK+/- reference timing pulse definitions are as follows:

Permission 3.5.2-1: A 1 pulse-per-second (1 PPS) periodic reference timing pulse may be provided in the OpenVPX backplane as the auxiliary reference clock (AUX_CLK+/-).

Rule 3.5.2-1: If AUX_CLK+/- is provided on the backplane, it shall be driven as a differential pair on the RES_BUS+/- contacts assigned on the P0 connector (contacts B8 and C8) as defined in [VITA 46.0], Section 4.8.6. [VM = I]


Rule 3.5.2-2: Backplane connector J0 contacts c8 and d8 shall be marked Reserved on the OpenVPX backplane if AUX_CLK+/- is not provided. [VM = I]

Rule 3.5.2-3: The differential termination and trace characteristics defined for the RES_BUS+/- pair in [VITA 46.0], Section 7.3.3 shall be met on OpenVPX backplanes. [VM = I]

Rule 3.5.2-4: A 61.9 +/- 1% Ohm resistive differential termination shall be provided at each end of the backplane trace pair as shown in [VITA 46.0], Figure 7-1. [VM = I]

Observation 3.5.2-1: The backplane trace and termination definitions in Rule 3.5.2-3 and Rule 3.5.2-4 are identical to the backplane trace and termination definitions for REF_CLK+/- as listed in [VITA 46.0], Section 7.3.1, Rule 7-10.

Rule 3.5.2-5: One Plug-In Module shall be assigned by application software or system management as the driver for this signal. [VM = I]

Permission 3.5.2-2: Any Plug-In Module may receive and utilize this signal.

Observation 3.5.2-2: Backplane Profiles might make AUX_CLK+/- available to RTMs, if an RTM uses this signal, it is up to the System Integrator to make sure that the signal integrity is going to be OK.

Rule 3.5.2-6: If provided the AUX_CLK+/- signal shall be driven as a [TIA/EIA 899] Multipoint-Low-Voltage Differential Signaling (M-LVDS) signal with the following electrical characteristics: [VM = T,A]

• Time interval (rising edge to rising edge of the pulse): 1.000s +/- 50ppm

• Duty cycle: minimum 100 microseconds at the active state following the rising edge of the pulse and minimum 100 microseconds at the inactive state preceding the rising edge of the pulse.

Permission 3.5.2-3: The AUX_CLK+/- signal may be phase-aligned with the 25 MHz REF_CLK+/- signal.

Permission 3.5.2-4: The AUX_CLK+/- signal may be driven from a slot other than the SYS_CON slot.

Observation 3.5.2-3: A common AUX_CLK+/- implementation is to derive the reference source signal from a global positioning satellite (GPS) receiver unit implemented as either a Plug-In Module in the OpenVPX chassis or as an adjunct module in the host system. It is noted that a conversion circuit will probably be required to convert the reference pulse to M-LVDS format for transfer across the OpenVPX backplane.

3.5.3 P1-REF_CLK-SE

This reference clock is defined on the P1 connector, contact G7 (J1 connector, contact i7), in [VITA 46.0], Section 4.9, and reserved for future use. It is not used in the OpenVPX environment.


3.6 Bussed GPIO (GDiscrete1)

This section provides a general description plus functional and electrical signal requirements for an optional single-ended general purpose I/O signal (GDiscrete1) using the P1-RES_BUS-SE signal, as defined in [VITA 46.0], Section 4.9.1 with backplane trace geometry as defined in [VITA 46.0], Section 7.3.10. This signal is referenced to the 3.3V_AUX voltage rail through the backplane termination circuit defined by Rule 3.6-2.

GDiscrete1 is an wire-OR (open-drain) single-ended signal bussed among all Plug-In Module slots in the backplane on contact i1 of backplane connector J1. This signal can be used by controlling software to provide a common status or control function to all modules that is unique to the host application.

Rule 3.6-1: An OpenVPX backplane shall provide one single-ended signal bussed among all Plug-In Module slots on backplane connector J1, contact i1, as defined in [VITA 46.0], Section 4.9.1. [VM = I]

Permission 3.6-1: A VPX Plug-In Module or RTM defined for use in an OpenVPX system may provide an interface for this signal, configured as either as an input only port, an output only port, or a bidirectional I/O port.

Rule 3.6-2: The backplane termination for GDiscrete1 shall adhere to the single-ended configuration as defined in [VITA 46.0], Section 7.3.10, Rule 7-21, using a resistance of 470 ohm +/- 5%, to 3.3V_AUX, at each end of the backplane. [VM = I]

Rule 3.6-3: The GDiscrete1 signal interface on a Plug-In Module or RTM shall implement an open-drain circuit meeting the electrical rules for lower-current open-drain interfaces specified in Section 3.3.2. [VM = A,T]

Rule 3.6-4: The GDiscrete1 signal interface on each Plug-In Module shall include a pull-up to 3.3V_AUX with a resistance of 47 Kohm +/- 5%. [VM = I]

Rule 3.6-5: Following a high-to-low transition, GDiscrete1 signal shall be held in the active low state for a minimum of 500 ns before being accepted as a valid logic 0 input at a receiving Plug-In Module. [VM = A,T]

Rule 3.6-6: Following a low-to-high transition, GDiscrete1 signal shall remain in the high state for a minimum of 500 ns before being accepted as a valid logic 1 input at a receiving Plug-In Module. [VM = A,T]

Permission 3.6-2: A Plug-In Module may start driving a GDiscrete1 signal that has already been driven to the active low state by another Plug-In Module. This has the effect of prolonging the active low state of GDiscrete1 at all Plug-In Modules receiving the signal.

Observation 3.6-1: It is the responsibility of the system architect and controlling software to coordinate assertion of GDiscrete1 on the backplane among the Plug-In Modules utilizing the common backplane signal.


3.7 OpenVPX VITA 46.0 Connector P0/J0 and P1/J1 Connector Pin Assignments

The following tables summarize the power and signal assignments on the VITA 46.0 P0 / J0 and P1 / J1 connectors in an OpenVPX backplane.

Rule 3.7-1: All OpenVPX compliant backplanes and Plug-In Modules shall adhere to the power, ground and signal assignments on the P0 and J0 connectors shown in Table 3.7-1 and Table 3.7-2. [VM = I]

Rule 3.7-2: All backplanes and Plug-In Modules shall adhere to the power, ground and signal assignments on the P1 and J1 connectors shown in Table 3.7-3 and Table 3.7-4. [VM = I]

Observation 3.7-1: A summary table of signal assignments on the P0 and P1 connector contacts is provided in Table 3.7-5 for reference. Reserved contacts are not shown in the table.


Table 3.7-1 Utility Plane Signals on P0 Row G Row F Row E Row D Row C Row B Row A

1 Vs1 Vs1 Vs1 No Pad* Vs2 Vs2 Vs2



4 SM2 SM3 GND -12V_Aux GND SYSRESET* NVMRO

5 GAP* GA4* GND 3.3V_Aux GND SM0 SM1

6 GA3* GA2* GND +12V_Aux GND GA1* GA0*

7 TCK GND TDO TDI GND TMS TRST*

8 GND REF_CLK- REF_CLK+ GND AUX_CLK- AUX_CLK+ GND

* See [VITA 46.0] Table 4-4, for the definition of no pad.

Table 3.7-2 Utility Plane Signals on J0 Row i Row h Row g Row f Row e Row d Row c Row b Row a

1 Vs1 Vs1 Vs1 Vs1 No Pad* Vs2 Vs2 Vs2 Vs2



4 GND SM2 SM3 GND -12V_Aux GND SYSRESET* NVMRO GND

5 GND GAP* GA4* GND 3.3V_Aux GND SM0 SM1 GND

6 GND GA3* GA2* GND +12V_Aux GND GA1* GA0* GND

7 TCK GND GND TDO TDI GND GND TMS TRST*

8 GND REF_CLK- REF_CLK+ GND GND AUX_CLK- AUX_CLK+ GND GND

* See [VITA 46.0] Table 4-4, for the definition of no pad.


Table 3.7-3 Utility Plane Signals on P1 Row G Row F Row E Row D Row C Row B Row A

1 GDiscrete1

The pairs on Rows A thru F are assigned by Slot Profiles in Sections 10 and 14.

2 GND

3 P1-VBAT

4 GND

5 SYS_CON*

6 GND

7 Reserved

8 GND

9 UD

UD pins in Row G can be assigned by Slot Profiles in Sections 10 and 14.

10 GND

11 UD

12 GND

13 UD

14 GND

15 MaskableReset*

16 GND

Table 3.7-4 Utility Plane Signals on J1 Row i Row h Row g Row f Row e Row d Row c Row b Row a

1 GDiscrete1

The pairs on Rows a thru h are assigned by Slot Profiles in Sections 10 and 14.

2 GND

3 P1-VBAT

4 GND

5 SYS_CON*

6 GND

7 Reserved

8 GND

9 UD

UD pins in Row i can be assigned by Slot Profiles in Sections 10 and 14.

10 GND

11 UD

12 GND

13 UD

14 GND

15 MaskableReset*

16 GND


Table 3.7-5 P0 and P1 Contact Assignments UP Signal Connector Set Plug-In Module

Px Contact(s) Backplane Jx Contact(s)

AUX_CLK- P0 / J0 C8 d8

AUX_CLK+ P0 / J0 B8 c8

GA0* P0 / J0 A6 b6

GA1* P0 / J0 B6 c6

GA2* P0 / J0 F6 g6

GA3* P0 / J0 G6 h6

GA4* P0 / J0 F5 g5

GAP* P0 / J0 G5 h5

NVMRO P0 / J0 A4 b4

REF_CLK- P0 / J0 F8 h8

REF_CLK+ P0 / J0 E8 g8

SM0 P0 / J0 B5 c5

SM1 P0 / J0 A5 b5

SM2 P0 / J0 G4 h4

SM3 P0 / J0 F4 g4

SYS_RESET* P0 / J0 B4 c4

TCK P0 / J0 G7 i7

TDI P0 / J0 D7 e7

TDO P0 / J0 E7 f7

TMS P0 / J0 B7 b7

TRST* P0 / J0 A7 a7

GDiscrete1 P1 / J1 G1 i1

MaskableReset* P1 / J1 G15 i15

SYS_CON* P1 / J1 G5 i5

UD P1 / J1 G9, G11, G13 i9, i11, i13


4 Mechanical – General Specifications Refer to [VITA 46.0] for general form factor information.

Rule 4-1: Modules and chassis shall comply with the mechanical form factor requirements in [VITA 46.0] and [VITA 48.0]. [VM = I]

4.1 Slot Pitch

Recommendation 4.1-1: Standard Development Chassis should support 1" pitch Plug-In Modules per [VITA 48.0]. [VM = I]

Recommendation 4.1-2: Air-cooled Plug-In Modules that are designed for 0.8” or 0.85” pitch and are intended to be installed in a 1” pitch Standard Development Chassis should be offered in a version with a [VITA 48.1] compliant 1” faceplate. [VM = I]

Permission 4.1-1: Plug-In Modules may be offered in VITA 48 0.8” or 0.85” pitch.

Observation 4.1-1: When 0.8” or 0.85” pitch air-cooled Plug-In Modules are installed in a 1” pitch air-cooled chassis, gaps are created at the faceplates as well as alongside the Plug-In Modules in the air channels; please see detailed figures in [VITA 48.0]. Refer to Figure 4-1 for a high level illustration of the problem.

Recommendation 4.1-3: Air-cooled chassis vendors should offer mini air blocker devices which block the small faceplate gap and the small air gap between Plug-In Modules when using an air-cooled Plug-In Modules designed for 0.8” or 0.85” in a 1” slot; note that these blockers are suitable for Standard Development Chassis lab use only – not for deployment. [VM = VNR]

Recommendation 4.1-4: With air-cooled chassis, air blocking devices should be inserted into otherwise empty chassis slots. [VM = I]


Figure 4-1 Backplane with pitch of 1.00 inch populated with 0.80, 0.85 and 1.00 in. pitch Plug-In Modules

4.2 Connector Family

The OpenVPX specification is versatile and can accommodate different connector types as they are adopted by VITA. The initial release of OpenVPX is structured around the VITA 46.0 connector family. As VITA formally approves new connector types and as they become available, they can be included in future releases of this standard.

4.3 Keying

Keying is defined by [VITA 46.0], and is additionally constrained for OpenVPX as outlined in this section.

Rule 4.3-1: Key position 1 for 6U modules and backplanes shall be set to 315. [VM = I]


4.4 RTM Connectors

In most Standard Development Chassis and some deployed chassis, Rear Transition Modules are used to bring out I/O signals from the modules. In this case, the backplane has RJ0 – RJ6 (6U) or RJ0 – RJ2 (3U) connectors that are pressed into the back side of the same holes which are used for the J0 – J6 (6U) or J0 – J2 (3U) connectors (refer to [VITA 46.10] ). Wherever high-speed signals (typically SERDES type signals) are routed across the backplane, the rear connectors cannot be connected to those signal pins because it would create stubs that would cause signal integrity problems and bit errors.

Rule 4.4-1: Wherever signals (typically SERDES type signals) are routed across the backplane, backplane vendors shall ensure that any rear connectors are not connected to those signal pins. [VM = I]

Observation 4.4-1: This can be accomplished in a number of different ways:

• If the connector vendors offer connectors with the appropriate contacts removed, the backplane vendor can buy RJ connectors with the appropriate pins already depopulated. This is the preferred long term approach for commonly-used Backplane Profiles.

• If the high-speed backplane signals are not routed in the bottom layers, back drilling can be used on selected connector pins of the backplane in order to break the connection to the RJ connector. This adds some cost to the backplane and constrains signal routing.

• The backplane vendor can remove the unwanted contacts out of the RJ connector as needed.

Observation 4.4-2: The availability of Utility Plane Signals on the RJ connectors (for potential use by an RTM) is specified by the Backplane Profile.


5 Protocol Specific OpenVPX Control, Data, and Expansion Planes can accommodate communication protocols adopted by VITA and other standards organizations. As new protocols are approved, they can be incorporated in future releases of this specification. The following sub-sections define the allowed communication protocols for use in OpenVPX systems.

5.1 Ethernet

OpenVPX uses several versions of Ethernet, all of which are defined in VITA 46 dot specifications.

5.1.1 1000BASE-BX

OpenVPX uses 1000BASE-BX as defined in [VITA 46.6].

Rule 5.1.1-1: Plug-In Modules using 1000BASE-BX shall comply with [VITA 46.6], except for pin assignments. [VM = T]

5.1.2 1000BASE-KX

Permission 5.1.2-1: 1000BASE-KX may be used where 1000BASE-BX is called out, provided the 1000BASE-KX interfaces are configured such that their auto-negotiation capability is disabled and their baud rate is fixed at 1.25 Gbaud. See [VITA 46.6].

Permission 5.1.2-2: 1000BASE-KX may be used where 10GBASE-KX4 is called out.

Observation 5.1.2-1: If a 10GBASE-KX4 interface is connected to a 1000BASE-KX, the link will degrade to 1000BASE-KX.

Observation 5.1.2-2: If a 1000BASE-KX is used instead of 10GBASE-KX4, it is up to the system integrator to make sure the link has enough bandwidth to meet the application’s needs.

5.1.3 1000BASE-T

OpenVPX uses 1000BASE-T as defined in [VITA 46.6].

Rule 5.1.3-1: Plug-In Modules using 1000BASE-T shall comply with [VITA 46.6], except for pin assignments. [VM = T]


Rule 5.1.3-2: Plug-In Modules using 1000BASE-T that are plugged into Slots that are wired according to the Rules of Section 7.2.2 shall comply with [IEEE 802.3] Subchapter 40.4.4 (Automatic MDI/MDI-X Configuration). [VM = T]

5.1.4 10GBASE-BX4

OpenVPX uses 10GBASE-BX4 as defined in [VITA 46.7].

Rule 5.1.4-1: Plug-In Modules using 10GBASE-BX4 shall comply with [VITA 46.7], except for pin assignments. [VM = T]

5.1.5 10GBASE-KX4

OpenVPX uses 10GBASE-KX4 as defined in [VITA 46.7].

Rule 5.1.5-1: Plug-In Modules using 10GBASE-KX4 shall comply with [VITA 46.7], except for pin assignments. [VM = T]

5.1.6 10GBASE-T

OpenVPX uses 10GBASE-T as defined by [IEEE 802.3] clause 55.

Rule 5.1.6-1: Plug-In Modules using 10GBASE-T shall comply with clause 55 of [IEEE 802.3]. [VM = T]

5.2 Serial RapidIO® (SRIO)

OpenVPX uses Serial RapidIO as defined in [VITA 46.3].

Rule 5.2-1: Plug-In Modules using Serial RapidIO shall comply with [VITA 46.3], except for pin assignments. [VM = T]


5.3 PCI-EXPRESS® (PCIe®)

OpenVPX uses PCIe as defined in [VITA 46.4]. However, for improved support for various backplane configurations and support of next-generation PCIe (i.e. Gen2 or Gen3), it may be necessary to provide a common reference clock.

For requirements related to System Reset see Section 3.4.2. For requirements related to Auxiliary resets, which can be used as Expansion Plane resets, see Section 3.4.9.

Note: This section was re-written after the release of [VITA 65-2010]. In order to make it so that the requirement numbers in this section are not the same as the requirement numbers from the [VITA 65-2010] version of this section, the sequence numbers of the requirements in this section starts at 10.

Rule 5.3-10: Plug-In Modules using PCI-Express without a common reference clock shall comply with [VITA 46.4], except for the pin assignments. [VM = A, T]

Rule 5.3-11: Plug-In Modules using PCI-Express with a common reference clock shall comply with [VITA 46.4], except for the prohibition against the requirement of a common reference clock in Rule 4-1, and the pin assignments. [VM = A, T]

Observation 5.3-10: It is up to the System Integrator to make sure there is a methodology implemented to provide synchronization among Plug-In Modules, within a PCIe domain. The system needs to be set up so that when the Root Complex goes to enumerate the Plug-In Modules, within its PCIe domain, those Plug-In Modules are up far enough, to be ready for enumeration. A way of implementing the synchronization is to follow Recommendation 4-17 of [VITA 46.0], Recommendation 4-17 is a way to make sure reset is not released before power is stable. It is also necessary to make sure that the leaf Plug-In Modules are ready for enumeration, in less time after reset is released, than when the Root Complex attempts to enumerate the Plug-In Module in question. Notice that a system may have one or more PCIe domains. An example of a system with multiple PCIe domains is depicted in Figure 5.3.2-1.

Rule 5.3-12: If a PCIe Common Reference Clock is present, a PCIe Common Reference Clock Synchronous to the Root Complex shall be driven to each device in a Root Complex’s PCIe hierarchy, in accordance with either the option given in Section 5.3.1 or the option given in Section 5.3.2. [VM = A, T]

Rule 5.3-13: Products that drive a PCIe Common Reference Clock shall drive 100 MHz, as specified in [PCIe 2 CEM]. [VM = A, T]

A variety of methods may be used to drive synchronized clocks to multiple slots. One example is shown in Figure 5.3.2.1-1.

Permission 5.1.6-10: If it is desirable to drive more slots than can be accommodated by the Root Complex, another distribution scheme may be used to drive the reference clock to multiple slots from a central source, such as a Plug-In Module intended for this purpose, or an active backplane.

Recommendation 5.3-10: Downstream devices on a Root Complex’s hierarchy should be designed such that if no PCIe reference clock is present, they are capable of following the


Separate Refclk Architecture as defined in [PCIe 2 Base] (either automatically or through a configuration option). [VM = A, T]

Permission 5.1.6-11: The PCIe clock pairs may be configurable to either drive, receive, or ignore the PCIe reference clock.

Observation 5.3-11: If the PCIe clock is daisy chained where Plug-In Modules receive it and re-drive it to another, resulting clocks may not meet jitter requirements.

Observation 5.3-12: PCIe Reference Clock implemented as REF_CLK +/- on P0/J0 might not be electrically compatible with a PCIe Reference Clock implemented on other pins.

Two different options for driving a common reference clock are through the use of:

• The Utility Plane REF_CLK pins on P0/J0 - Requirements that only apply to this option are in Section 5.3.1.

• Other pins - An example of this is the case when the Common Reference Clock is associated with the Expansion Plane. For examples of Slot Profiles that assign pins for the Expansion Plane, see Sections 10.2.6.4.1 and 10.2.7.4.1. Note: In these Slot Profiles, if the protocol on the Expansion Plane is not PCIe, these pins can be used for a clock that is appropriate for that protocol. The requirements that only apply to this option are in Section 5.3.2.

5.3.1 PCIe Gen 2 Common Reference Clock Implemented as REF_CLK on P0/J0

Permission 5.3.1-1: The REF_CLK +/- on P0/J0 may be used as the PCIe Reference Clock.

Rule 5.3.1-1: If a module uses REF_CLK +/- on P0/J0 as a PCIe reference clock, it shall comply with the electrical characteristics and termination scheme specified in [VITA 46.0] Sections 4.8.4 and 7.3.1. [VM = A,T]

Permission 5.3.1-2: Products that drive REF_CLK +/- on P0/J0 at frequencies other than 25 MHz may include the provision for 25 MHz as an optional frequency.

5.3.2 PCIe Gen 2 Common Reference Clock Implemented on Other Than REF_CLK pins on P0/J0

These requirements are geared toward supporting systems where one slot is a Root Complex and there are one or more Plug-In Modules, with PCIe Endpoints, that are in the same PCIe Domain, such as with Figure 5.3.2-1. Other topologies can also be supported. To distinguish this reference clock from the REF_CLK signals on P0/J0, this section refers to the clock as “PCIe_REF_CLK”.

A typical use for the PCIe Common Reference Clock topologies in this section, is to enable the use of a PCIe Common Reference Clock with the Expansion Plane. For examples of such Backplane Profiles, see the Backplane Profiles BKP6-CEN16-11.2.17-n and BKP6-DIS06-


11.2.18-n. For examples of Module Profiles which include the ability to have a PCIe Reference Clock, on other than P0/J0, see MOD6-PAY-4F1Q2U2T-12.2.6-n and MOD6-PAY-4F2Q2U2T-12.2.7-n.

There are also Backplane Profiles that do not have provisions for a PCIe Common Reference clock, on other than P0/J0. With these there is either no PCIe Common Reference clock or REF_CLK on P0/J0 is used as a PCIe Common Reference Clock. For an example of such a Backplane Profile, see BKP6-CEN16-11.2.2-n.

Rule 5.3.2-1: If a module uses pins other than REF_CLK +/- on P0/J0, as a PCIe reference clock (PCIe_REF_CLK), it shall comply with the electrical and termination scheme specified in [PCIe 2 CEM] Section 2.1 and Table 2-1, with the understanding that "System Board" is to be substituted with "clock source". [VM = A,T]

Plug-In Module with Endpoints

PCIe Domain A PCIe Domain B




Plug-InModule with

Root Complex A

Plug-InModule with

Root Complex B

First PCIe Port

Upstream

First PCIe Port

Upstream

2nd PCIe Port Not used

2nd PCIe Port Downstream

First PCIe Port

Downstream


First PCIe Port

Upstream

First PCIe Port

Upstream


2nd PCIe Port Downstream

First PCIe Port

Downstream


Figure 5.3.2-1 Example of Multiple Separate PCIe Domains

5.3.2.1 REF_CLK Profile 1

This topology allows for PCIe_REF_CLK distribution to multiple slots from a central source clock device located on the backplane, as shown in Figure 5.3.2.1-1.


Central Clock

Source

Dow

nstream

Receiver 1

Dow

nstream

Receiver nR

oot-Com

plex 0

Receiver/

Transmitter

0

REF_CLKn

REF_CLK1

Source Clock orREF_CLK0

PCIe_REF_CLK0 PCIe_REF_CLK1 PCIe_REF_CLKn

VPX Backplane

Figure 5.3.2.1-1 Backplane clock source

Each distributed PCIe_REF_CLK driven from the central source must present a clock at the receiver that matches the requirements expressed in section 2.1 and 4.7 of the [PCIe 2 CEM]. Instead of being bussed from slot-to-slot as anticipated by section 4.8.4 of [VITA 46.0], this profile requires separate clocks to be routed from the central source device to each slot.

The trace length from the central source device to the VPX backplane connector for the destination Plug-In Module, is represented in Figure 2-9 of the [PCIe 2 CEM] as “Motherboard Trace”. The trace length from the receiving VPX module’s connector to the receiver’s termination is represented as “Add-In” in Figure 2-9.

The rules below apply independently for each PCIe domain in the system. Specific pin assignments for PCIe_REF_CLK are designated in the relevant backplane profile.

Rule 5.3.2.1-1: The “Add-In” trace length shall be less than or equal to 3.0”.

Rule 5.3.2.1-2: Modules with downstream devices adhering to this profile shall utilize the PCIe_REF_CLK as an input.

Permission 5.3.2.1-1: Modules with root complexes adhering to this profile may utilize the PCIe_REF_CLK as an input or output.

Permission 5.3.2.1-2: Backplanes adhering to this profile may use the root complex’s PCIe_REF_CLK as an input for synchronization of its central source device.


Rule 5.3.2.1-3: Backplanes adhering to this profile shall route a unique copy of PCIe_REF_CLK to each downstream slot (as opposed to bussing the clock).

Rule 5.3.2.1-4: Backplanes sourcing PCIe_REF_CLK and Plug-In Modules receiving PCIe_REF_CLK, adhering to this profile, shall meet the requirements of [PCIe 2 CEM] section 2.1 and section 4.7, except where superseded herein.

Observation 5.3.2.1-1: If Permission 5.3.2.1-2 is taken advantage of, it is up to the System integrator to make sure that the PCIe_REF_CLK source, on the backplane, still meets the requirements of [PCIe 2 CEM] section 2.1 and section 4.7. An example of a potential problem area is that the jitter of the PCIe_REF_CLK could be increased by using an Plug-In Module to synchronize it.

Permission 5.3.2.1-3: Although this section is written as if there are active components on the backplane, driving the PCIe_REF_CLK, an implementation of the backplane may source the PCIe_REF_CLK from a mezzanine card or other module that plugs into the backplane. In such a case, the path (traces and connectors) from the actual source on the mezzanine, through any connectors to the destination Plug-In Module’s VPX backplane connector, is counted as part of the “Motherboard Trace, as given in Figure 2-9 of the [PCIe 2 CEM].

5.3.2.2 REF_CLK Profile 2

This topology allows for PCIe_REF_CLK distribution from one slot to another and is intended for use in applications where there are multiple root complexes or where a particular slot is designated as the clock source for multiple other slots. An example is shown in Figure 5.3.2.2-1.

PCIe_REF_CLKx PCIe_REF_CLKy

Root Complex

Figure 5.3.2.2-1 Root Complex in one slot sourcing clock for other slot(s)

Using this topology, PCIe_REF_CLK is distributed from one slot via “PCIe_REF_CLKx” and received on another slot via “PCIe_REF_CLKy”. “PCIe_REF_CLKx” and “PCIe_REF_CLKy” might be the same pin (of different slots) or might be different pins. Specific pin assignments for PCIe_REF_CLK are given in relevant Backplane Profiles.


Each distributed PCIe_REF_CLK driven from one slot to another must present a clock at the receiver that matches the requirements of a PCIe Add-In card. These requirements are expressed in section 2.1 and 4.7 of the [PCIe 2 CEM].

The trace length from the source VPX module’s termination to the VPX backplane connector of the receiving device is represented in Figure 2-9 of the [PCIe 2 CEM] as “Motherboard Trace”. The trace length from the receiving VPX module’s connector to the receiver’s termination is represented as “Add-In” in Figure 2-9.

Rule 5.3.2.2-1: The “Add-In” trace length shall be less than or equal to 3.0”.

Rule 5.3.2.2-2: Modules adhering to this profile, with downstream devices shall, utilize the PCIe_REF_CLK as an input.

Rule 5.3.2.2-3: Modules with root complexes adhering to this profile, shall utilize the PCIe_REF_CLK as an output.

Rule 5.3.2.2-4: Backplanes, Plug-In Modules sourcing PCIe_REF_CLK (Root Complexes), and Plug-In Modules receiving PCIe_REF_CLK, adhering to this profile, shall meet the requirements of [PCIe 2 CEM] section 2.1 and section 4.7.

5.4 InfiniBand® (IB)

OpenVPX uses InfiniBand as defined in [VITA 46.8].

Rule 5.4-1: Plug-In Modules using InfiniBand shall comply with [VITA 46.8] unless otherwise stated in this document. [VM = T]


6 Common to 6U and 3U — Slot Profiles OpenVPX uses Slot Profiles to define interoperability and physical characteristics necessary to interface with compatible modules and backplanes. The following sub-sections define common requirements for all OpenVPX Slot Profiles:


This specification identifies several levels of requirements for Slot Profiles.

Rule 6.1-1: Requirements for a specific 6U Slot Profile shall be applied using the following order of precedence: [VM = VNR]

1. Section 10.2 (or higher), connector specific 6U Slot Profiles

2. Section 10.1, 6U Slot Profile Common Section

3. Section 6.3 (or higher), connector specific Common Requirements for Slot Profiles

4. Section 6.2, Common Requirements for all Slot Profiles

Rule 6.1-2: Requirements for a specific 3U Slot Profile shall be applied using the following order of precedence: [VM = VNR]

1. Section 14.2 (or higher), connector specific 3U Slot Profiles

2. Section 14.1, 3U Slot Profile Common Section

3. Section 6.3 (or higher), connector specific Common Requirements for Slot Profiles

4. Section 6.2, Common Requirements for all Slot Profiles

6.2 Common Requirements for All Slot Profiles

6.2.1 Reserved pins

Rule 6.2.1-1: On Plug-In Modules, Pins that are labeled Reserved or RSVD, in the pin assignment tables, shall not connect to anything. [VM = I]

Rule 6.2.1-2: With Backplane Profiles, Pins that are labeled Reserved or RSVD, in the pin assignment tables, shall not connect to anything. [VM = I]


6.2.2 Which lanes, ports and pins are used (unused = reserved)

Rule 6.2.2-1: When only a subset of the lanes are used, it shall be the lower numbered lanes that are the ones used. For example, if a FP is used for x1 PCIe, lane 0 will be the one used. [VM = I]

Rule 6.2.2-2: When only a subset of the ports are used, it shall be the lower numbered ports that are the ones used. [VM = I]

Rule 6.2.2-3: Pins that are assigned by a Slot Profile shall be used for that purpose or left unused (reserved). This includes, but is not limited to, the unused lanes and ports of Rule 6.2.2-1 and Rule 6.2.2-2. [VM = I]

6.2.3 Plug-In Module Compatibility with Multiple Slot Profiles

Note: For requirements related to a Plug-In Module being compliant to multiple Module Profiles, see Section 8.5.

Permission 6.2.3-1: Plug-In Module implementations may be configurable to comply with more than one Slot Profile.

Observation 6.2.3-1: One Slot Profile might be a subset of another, with the exception of the User Defined pins. For example, if two Slot Profiles are the same, except that one has two Fat Pipes and the other has User defined pins in place of one of the Fat Pipes, the one with one Fat Pipe is a subset of the one with two Fat Pipes. In such cases, if a Plug-In Module, with the subset Slot Profile, leaves the User Defined pins that would conflict, as no connects, then the Plug-In Module can be compatible with Backplane Profiles that have either of Slot Profiles.

Observation 6.2.3-2: A Plug-In Module can support the features of more than one Slot Profile, provided that any signal conflicts are limited to pins that are User Defined on all but one of the Slot Profiles. Such pins take on the definition of the Slot Profile in which they are not User Defined.

6.2.4 Assigning Lanes Into Ports

6.2.4.1 Repartitioning of Data Plane Ports

Some of the Slot Profiles include the ability to repartition the Data Plane ports. This Section gives the tables that show how ports might be repartitioned. Slot Profiles that include the ability to repartition the Data Plane ports, might have a Rule, Recommendation, or Suggestion that references a table in this section.


Table 6.2.4.1-1 Repartitioning of a Data Plane FP into TPs, or UTPs

Cou

nt o

f Pi

pes

# of FPs 1

# of TPs

2 1

# of UTPs

2 4

DP0

1

Lane TD/RD0

FP1

TP1

TP1 U

TP1

Lane TD/RD1

UTP

3

Lane TD/RD2

TP2 U

TP1

UTP

2

Lane TD/RD3

UTP

2

UTP

4

Table 6.2.4.1-2 Repartitioning of 2 Data Plane FPs into a DFP, TPs, or UTPs

Cou

nts o

f Pip

es

# of DFP 1

# of FPs

2 1 1 1

# of TPs

2 1 4 2

# of UTPs

2 4 4 8

DP0

1

Lane TD/RD0

DFP

1

FP1

FP1

FP1

FP1

TP1

TP1 U

TP1

Lane TD/RD1 U

TP5

Lane TD/RD2

TP3 U

TP1

UTP

3

Lane TD/RD3

UTP

3

UTP

7

DP0

2

Lane TD/RD0

FP2

TP1

TP1 U

TP1

TP2

TP2 U

TP2

Lane TD/RD1

UTP

3

UTP

6

Lane TD/RD2

TP2 U

TP1

UTP

2

TP4 U

TP2

UTP

4

Lane TD/RD3

UTP

2

UTP

4

UTP

4

UTP

8


6.2.4.2 Partitioning of Expansion Plane Lanes Into Ports

Some of the Slot Profiles have lanes assigned to the Expansion Plane. This Section gives the tables that show how lanes might be assigned to pipes. Slot Profiles that include Expansion Plane lanes, might have a Rule, Recommendation, or Suggestion that references a table in this section.

Table 6.2.4.2-1 Expansion Plane Assignment of 4 Lanes to Pipes

Cou

nt o

f Pi

pes

# of FPs 1

# of TPs

2 1

# of UTPs

2 4

Ass

ignm

ent o

f lan

es

to p

ipes

Lane EP00

FP1

TP1

TP1 U

TP1

Lane EP01

UTP

3

Lane EP02

TP2 U

TP1

UTP

2

Lane EP03

UTP

2

UTP

4


Table 6.2.4.2-2 Expansion Plane Assignment of 8 Lanes to Pipes

Cou

nts o

f Pip

es

# of DFP 1

# of FPs

2 1 1 1

# of TPs

2 1 4 2

# of UTPs

2 4 4 8

Ass

ignm

ent o

f lan

es to

pip

es

Lane EP00

DFP

1

FP1

FP1

FP1

FP1

TP1

TP1 U

TP1

Lane EP01

UTP

5

Lane EP02

TP3 U

TP1

UTP

3

Lane EP03

UTP

3

UTP

7

Lane EP04 FP

2

TP1

TP1 U

TP1

TP2

TP2 U

TP2

Lane EP05

UTP

3

UTP

6

Lane EP06

TP2 U

TP1

UTP

2

TP4 U

TP2

UTP

4

Lane EP07

UTP

2

UTP

4

UTP

4

UTP

8


Table 6.2.4.2-3 Expansion Plane Assignment of 16 Lanes to Pipes C

ount

s of P

ipes

# of QFP 1

# of DFP 2 1 1 1 1 1 1 1

# of FPs

2 1 1 1 4 3 3 2 2 2

# of TPs

2 1 4 2 2 4 2 8 4

# of UTPs

2 4 4 8 4 4 8 8 16

Ass

ignm

ent o

f lan

es to

pip

es

EP00

QFP

1

DFP

1

DFP

1

DFP

1

DFP

1

DFP

1

DFP

1

DFP

1

DFP

1

FP1

FP1

FP1

FP1

FP1

FP1

TP1

TP1 U

TP1

EP01

UTP

9

EP02

TP5 U

TP1

UTP

5

EP03

UTP

5

UTP

13

EP04

FP3

FP3

FP3

TP1

TP1 U

TP1

TP3

TP3 U

TP3

EP05

UTP

5

UTP

11

EP06

TP3 U

TP1

UTP

3

TP7 U

TP3

UTP

7

EP07

UTP

3

UTP

7

UTP

7

UTP

15

EP08

DFP

2

FP1

FP1

FP1

FP1

TP1

TP1 U

TP1

FP2

FP2

FP2

FP2

FP2

FP2

TP2

TP2 U

TP2

EP09

UTP

5

UTP

10

EP10

TP3 U

TP1

UTP

3

TP6 U

TP2

UTP

6

EP11

UTP

3

UTP

7

UTP

6

UTP

14

EP12

FP2

TP1

TP1 U

TP1

TP2

TP2 U

TP2

FP4

TP1 U

TP1

TP2

TP2 U

TP2

TP4

TP4 U

TP4

EP13

UTP

3

UTP

6

UTP

3

UTP

6

UTP

12

EP14

TP2 U

TP1

UTP

1

TP4 U

TP2

UTP

4

TP2 U

TP2

TP4 U

TP2

UTP

4

TP8 U

TP4

UTP

8

EP15

UTP

2

UTP

4

UTP

4

UTP

8

UTP

4

UTP

4

UTP

8

UTP

8

UTP

16


6.3 Common Requirements for Slot Profiles Using VITA 46.0 connectors.

These are requirements for 6U and 3U Slot Profiles using VITA 46.0 connectors. An explanation of how Plug-In Module and Backplane pins, for the differential connectors, are defined, is provided in Section 6.3.1. With [VITA 46.0], for other than P0/J0, the connectors are different on the Plug-In Module side for differential vs. single-ended. The connectors on the backplane side are the same but the grounding pattern is different for differential vs. single-ended.

Rule 6.3-1: Slot Profiles meeting the requirements of this Section shall use the P0 connector on the Plug-In Module and the J0 connector on the backplane as specified by [VITA 46.0]. [VM = I]

Rule 6.3-2: Slot Profiles meeting the requirements of this Section shall use differential connectors, as specified by [VITA 46.0], for the connectors other than P0, on the Plug-In Module side unless specifically specified otherwise. [VM = I]

Rule 6.3-3: Slot Profiles meeting the requirements of this Section shall use the differential ground pattern on the backplane, as specified by [VITA 46.0], for the connectors other than J0, unless specifically specified otherwise. Note: Some examples of where it is specified otherwise are: 1) where the connector is all user defined, see Section 6.3.3 and where a Slot Profile specifies VME, see Section 10.5.1.4 and 10.5.2.3. [VM = I]

6.3.1 Pin Assignment Tables for Differential Connectors

With the VITA 46 connector system, the number of rows in the Plug-In Module connector is different from the number of rows in the backplane connectors. Figure 6.3-1 and Figure 6.3-2 show the mapping of the Plug-In Module connector pins to the backplane connector pins, for differential connectors. Figure 6.3-1 and Figure 6.3-2 are taken from Section 7.6 of [VITA 46.0]. For additional details, see Section 7.6 of [VITA 46.0].

[VITA 46.0] uses separate pin assignment tables for Plug-In Modules (connectors P0 - P6) and backplanes (connectors J0 - J6). For the differential connectors, this document uses tables that combine both the Plug-In Module connector pins and backplane connector pins in a single table. Table 6.3.1-1 is an example of a pin assignment table that is just for the Plug-In Module.

The columns of the tables correspond to rows of the connector and rows of the tables correspond to wafers of the connectors.

Table 6.3.1-2 is an example of a pin assignment table that is just for the backplane connectors. Notice that the backplane connector has two more rows (columns in the table) than the Plug-In Module connectors do. The additional rows enable more ground pins. The additional ground pins are in italics and are named “GND-Jn” instead of “GND”.

Table 6.3.1-3 is an example of the format of the tables used in this document. This table combines both the Plug-In Module and the Backplane tables. The first heading line gives the connector rows that correspond to the Plug-In Module and the second line of the heading gives the connector rows for the backplane connectors.

With Table 6.3.1-3, the ground pins that are in addition to those of Table 6.3.1-1, are indicated by having the signal name in italics and being named “GND-Jn” instead of “GND”.


When the Plug-In Module connector is mapped into the table that combines both; the Plug-In Module connector Rows E and B are each given in two columns, of the table. The backplane connector has more ground connections. When looking at the pin assignments for the Plug-In Module, these extra ground pins are ignored. For example, when looking at the column labeled "Row E Even"; the even entries in the column give the pin assignments for the even wafers of the Plug-In Module connector. When looking at the Plug-In Module pin assignments the ground connections in this column are ignored. The pin assignments for the odd wafers of Plug-In Module connector Row E are given in the column labeled “Row E Odd”.

The coloring of the connector tables (e.g. Table 6.3.1-3) is to help see groupings of pins. There is not particular meaning to particular colors.

Figure 6.3-1 Even Differential Plug-In Module Wafer to Backplane Pin Mappings


Figure 6.3-2 Odd Differential Plug-In Module Wafer to Backplane Pin Mappings


Table 6.3.1-1 Connector Example Plug-In Module Only — Differential Plug-in module P2 Row G Row F Row E Row D Row C Row B Row A

1 SEwafer1 GND LN0-TD- LN0-TD+ GND LN0-RD- LN0-RD+

2 GND LN1-TD- LN1-TD+ GND LN1-RD- LN1-RD+ GND















Table 6.3.1-2 Connector Example Backplane Only — Differential Backplane J2 Row i Row h Row g Row f Row e Row d Row c Row b Row a

1 SEwafer1 GND GND-J2 LN0-TD- LN0-TD+ GND GND-J2 LN0-RD- LN0-RD+

2 GND LN1-TD- LN1-TD+ GND-J2 GND LN1-RD- LN1-RD+ GND-J2 GND
















Table 6.3.1-3 Connector Example Combined Plug-In Module & Backplane — Differential

Plug-in module P2

Row G Row F Row E Row D Row C Row B Row A Even Odd Even Odd

Bplane J2 Row i Row h Row g Row f Row e Row d Row c Row b Row a 1 SEwafer1 GND GND-J2 LN0-TD- LN0-TD+ GND GND-J2 LN0-RD- LN0-RD+
















6.3.2 Pin Assignment Tables for Single-Ended Connectors

This Section is a place holder. Content can be added in the future, if we have Slot Profiles with single-ended connectors. At the time of this writing the only Slot Profiles with single-ended connectors are ones that comply with [VITA 46.1]. In this case P2 is single-ended and all of it is specified by [VITA 46.1], which can be referenced for the P2/J2 pin assignments.

6.3.3 User Defined

For material on User Defined pins, in addition to what is in this Section, see Section 8.3.

Rule 6.3.3-1: In pin assignment tables, pins labeled UD shall be User Defined. [VM = VNR]

6.3.3.1 Entire Connector User Defined

This Section gives requirements for connectors when the entire connector is User Defined pins. This Section covers both differential and single-ended connectors on Plug-In Modules. User Defined pins for Plug-In Modules whose Slot Profiles use differential connectors (Pn) is given by Table 6.3.3.1-1 and Table 6.3.3.1-2. The version of this pin assignment in Table 6.3.3.1-1


gives the backplane connector also (Jn), assuming that the backplane is wired to accept differential connectors only.

Table 6.3.3.1-3 gives the User Defined pins for a Plug-In Module with single-ended connectors. Table 6.3.3.1-4 gives the corresponding backplane connector for Plug-In Modules with single-ended connectors to plug into.

Table 6.3.3.1-5 is a universal pattern that can accept both Plug-In Modules with single-ended and differential connectors. With this pattern the pins that are not grounds for both patterns are passed through to an RTM (Rear Transition Module). It is then up to the RTM to ground the appropriate pins. Which of the pins are grounded by the RTM, will be different for Plug-In Modules with differential connectors vs. single-ended; but with the universal pattern the backplane can be the same for both.

Notice that Rule 6.3-2 says that, unless otherwise specified, Slot Profiles use differential connectors on the Plug-In Module side. Rule 6.3-3 says that the grounding pattern, on the backplane side is for differential connectors, unless otherwise specified. Hence, this is one of those cases that is specifically specified as being different from the standard backplane differential pattern.

General requirements:

Rule 6.3.3.1-1: In Table 6.3.3.1-1 thru Table 6.3.3.1-5 pins labeled UD shall be User Defined. [VM = VNR]

Requirements specific to Plug-In Modules:

Rule 6.3.3.1-2: If Plug-In Module’s Slot Profile has a differential connector (this is the default), where all the signals are User Defined, then the pin assignment for this connector shall be as given in Table 6.3.3.1-1 and Table 6.3.3.1-2 (both tables give the pin assignment for the Plug-In Module). [VM = I]

Rule 6.3.3.1-3: If Plug-In Module’s Slot Profile has a single-ended connector, where all the signals are User Defined, then the pin assignment for this connector shall be as given in Table 6.3.3.1-3. [VM = I]

Requirements specific to backplanes:

Recommendation 6.3.3.1-1: When used in backplanes implementing Rear Transition connectors for I/O, Slot Profiles meeting the requirements of this Section should use the universal connector ground patterns on the backplane, for any connectors which are entirely designated as user defined, as given in Table 6.3.3.1-5, except for ground pins covered by Permission 6.3.3.1-1. [VM = I]

Permission 6.3.3.1-1: For connectors J2-J6 (J2 for 3U) that are entirely used for rear I/O in backplanes utilizing RTM connectors for I/O, Slot Profiles meeting the requirements of this Section may leave any or all of the ground pins uncommitted within the backplane. Since these signal and ground pins all pass through from the front Plug-In Module to the rear RTM module, this would allow the backplane to support either differential or single ended types of user IO, while avoiding ground loops; this may provide some signal integrity advantages in some applications. Note that this does not apply to J1; the J1 ground pins are required in order to provide the required DC power return current for the J0 power pins.


Rule 6.3.3.1-4: Where a Slot Profile defines an entire connector as differential and entirely User Defined, the contacts in that backplane connector segment shall use the signal assignments of Table 6.3.3.1-1, unless Recommendation 6.3.3.1-1 is followed. This requirement applies whether or not there is a RTM connector installed on the rear side behind this slot connector. [VM = I]

Rule 6.3.3.1-5: Where a Slot Profile defines an entire connector as single-ended and entirely User Defined, the contacts in that backplane connector segment shall use the signal assignments of Table 6.3.3.1-4, unless Recommendation 6.3.3.1-1 is followed. This requirement applies whether or not there is a RTM connector installed on the rear side behind this slot connector. [VM = I]

Table 6.3.3.1-1 User Defined pins for Pn & Jn — Differential Connectors Plug-In Mod Pn


Backplane Jn Row i Row h Row g Row f Row e Row d Row c Row b Row a

1

Use

r Def

ined

UD GND GND-J3 UD UD GND GND-J3 UD UD

2 GND UD UD GND-J3 GND UD UD GND-J3 GND

3 UD GND GND-J3 UD UD GND GND-J3 UD UD














Warning: Tables combine Plug-In Module & Backplane pin assignments, see Section 6.3.1.


Table 6.3.3.1-2 User Defined pins for Pn – Differential Connector Plug-in module Pn Row G Row F Row E Row D Row C Row B Row A

1 UD GND UD UD GND UD UD

2 GND UD UD GND UD UD GND















Table 6.3.3.1-3 User Defined pins for Pn – Single-Ended Connector Plug-in module Pn Row G Row F Row E Row D Row C Row B Row A

1 UD UD GND UD GND UD UD

















Table 6.3.3.1-4 User Defined pins for Jn – Single-Ended Only Backplane Jn Row i Row h Row g Row f Row e Row d Row c Row b Row a

1 GND UD UD GND UD GND UD UD GND
















Warning: Table 6.3.3.1-5 is a universal ground pattern that is compatible with either differential or single ended Plug-In Module connectors. This is intended for use only in backplanes where user defined signals are connected to RTMs (Rear Transition Modules).

Table 6.3.3.1-5 User Defined pins for Jn – Universal Ground Pattern Backplane Jn Row i Row h Row g Row f Row e Row d Row c Row b Row a

1 UD UD UD UD UD GND UD UD UD

2 GND UD UD GND UD UD UD UD GND
















6.3.3.2 Thin Pipe on Single-Ended UD pins of Differential Connector

There are 6U and 3U Slot Profiles that have all 8 single-ended pins of a differential connector available as User Defined. With some of these, particularly for Switch Slots, there is a Suggestion or Recommendation to put Thin Pipe on these pins. This Section gives the pipe assignments for when this is done.

With 6U Switch Slot Profiles, it is particularly common for there to be a suggestion or recommendation to put a Thin Pipe on P5/J5 and P6/J6. With 3U Switch Slot Profiles some might suggest or recommend putting a Thin Pipe on the single-ended pins of P2/J2.

Particular Slot Profiles give the actual requirements related to putting a Thin Pipe on the single-ended pins of particular connectors. Slot Profiles making a Suggestion or Recommendation for putting a Thin Pipe on the Single-Ended pins of a differential connector can reference Table 6.3.3.2-1.

Table 6.3.3.2-1 Suggested Thin Pipe on Single-Ended Plug-In Module Pn

Row G Row F Row E Row D Row C Row B Row A

Bplane Jn Row i Row h Row g Row f Row e Row d Row c Row b Row a 1 CPtp01-DA-

2 GND

For these pins see the Particular Slot Profile

3 CPtp01-DA+

4 GND

5 CPtp01-DB-

6 GND

7 CPtp01-DB+

8 GND

9 CPtp01-DC-

10 GND

11 CPtp01-DC+

12 GND

13 CPtp01-DD-

14 GND

15 CPtp01-DD+

16 GND



6.4 Common Requirements for Slot Profiles Using VITA 46.0 and VITA 67 connectors

These are requirements for 6U and 3U Slot Profiles using both VITA 46.0 and VITA 67 connectors. For many of the requirements associated with the VITA 46.0 connectors, this section references Section 6.3. An explanation of how Plug-In Module and Backplane pins, for the VITA 46.0 differential connectors, are defined, is provided in Section 6.3.1. With [VITA 46.0], for other than P0/J0, the connectors are different on the Plug-In Module side for differential vs. single-ended. The connectors on the backplane side are the same but the grounding pattern is different for differential vs. single-ended.

Rule 6.4-1: Slot Profiles meeting the requirements of this Section shall use the P0 connector on the Plug-In Module and the J0 connector on the backplane as specified by [VITA 46.0]. [VM = I]

Rule 6.4-2: Slot Profiles meeting the requirements of this Section shall use differential connectors, as specified by [VITA 46.0], for the connectors other than P0, on the Plug-In Module side unless specifically specified otherwise. [VM = I]

Rule 6.4-3: Slot Profiles meeting the requirements of this Section shall use connectors, as specified by [VITA 46.0], for the connectors other than J0, on the backplane side, except where the individual Slot Profiles specifically call out one of the VITA 67 dot specifications, as specifying the connectors. [VM = I]

Rule 6.4-4: Slot Profiles meeting the requirements of this Section shall use the differential ground pattern on the backplane, as specified by [VITA 46.0], for VITA 46.0 connectors other than J0, unless specifically specified otherwise. [VM = I]

Rule 6.4-5: Unless otherwise specified, Slot Profiles using VITA 67 connectors shall meet the electrical requirements specified in [VITA 67.0] and each specific VITA 67 subsection, that describes a connector modules that is used in the VITA 67 Slot Profile. [VM=I]

6.4.1 Pin Assignment Tables for VITA 46.0 Differential Connectors

Where there is a mix of VITA 46.0 connectors and VITA 67 connectors, the pin tables for the VITA 46.0 differential connectors are the same as is given in Section 6.3.1.

6.4.2 Pin Assignment Tables for Single-Ended Connectors

Where there is a mix of VITA 46.0 connectors and VITA 67 connectors, the pin tables for the VITA 46.0 single-ended connectors are the same as is given in Section 6.3.2.


6.4.3 User Defined

For User Defined pins on VITA 46.0 connectors, including fractions of a VPX connector position, the requirements of Section 6.3.3 apply. 3U Slot Profiles using VITA 67 connectors specified in [VITA 67.1], such as SLT3-PAY-1F1F2U4R-14.6.1 and SLT3-PAY-4F4R-14.6.2, are examples of where half the P2 VITA 46.0 connector position are VITA 46.0 connectors.


7 Common to 6U and 3U — Backplane Profiles OpenVPX uses Backplane Profiles to define interoperability and physical characteristics necessary to interface with compatible Plug-In Modules. The following sub-sections define common requirements for all OpenVPX Backplane Profiles:


This specification identifies several levels of requirements for Backplane Profiles.

Rule 7.1-1: Requirements for a specific 6U Backplane Profile shall be applied using the following order of precedence: [VM = VNR]

1. Section 11.n.2 (or higher), connector specific 6U Backplane Profiles, where n is 2 or greater depending on the connector

2. Section 11.n.1, connector specific 6U Backplane Profile Common Section, where n is 2 or greater depending on the connector

3. Section 11.1, 6U Backplane Profile Common Section

4. Section 7, Common Requirements for all Backplane Profiles

Rule 7.1-2: Requirements for a specific 3U Backplane Profile shall be applied using the following order of precedence: [VM = VNR]

1. Section 15.n.2 (or higher), connector specific 3U Backplane Profiles, where n is 2 or greater depending on the connector

2. Section 15.n.1, connector specific 3U Backplane Profile Common Section, where n is 2 or greater depending on the connector

3. Section 0, 3U Backplane Profile Common Section

4. Section 7, Common Requirements for all Backplane Profiles

7.2 Interconnecting Slots with Pipes

This section gives requirements related to connecting Slots together using pipes. See definition of “pipe” and “lane” in Table 1.3.2-1. Pipes can be wired differently depending on how they are to be used. Also, Slot Profiles label pipes differently depending on usage. This Section has various Subsections that give Rules for connection slots together using different methodologies and taking into account different Slot Profile labeling.


7.2.1 Slot Profiles Labeled as Lanes

This section gives requirements related to pipes between slots, where the pipes are composed of one or more lanes and the Slot Profiles have them labeled as lanes. Backplane Profile Rules that are to be wired as lanes, as defined by these requirements, include the phrase: “complying with the Rules of Section 7.2.1”.

Rule 7.2.1-1: For each lane between a pair of slots, the transmit pair at one end shall connect to the receive pair at the other end; where the name of transmit pairs ends in either “-T” or -Tn” and receive pairs end in “-R” or “-Rn”, where n is the lane number. Note: There is a “+” or “-“ appended to the end of the pair name to identify the individual wires of the pair. [VM = I]

Rule 7.2.1-2: For each differential pair between slots the “+” wire on the transmit side shall connect to the “+” wire on the receive side and the “-” wire on the transmit side shall connect to the “-” wire on the receive side. [VM = I]

Rule 7.2.1-3: For connections with multiple lanes, the lanes shall be numbered 0 thru N-1, where N is the number of lanes. [VM = I]

Rule 7.2.1-4: Lane n at one end of the pipe shall connect to lane n at the other end, where n is between 0 and N-1. [VM = I]

7.2.2 Slot Profiles Labeled as Thin Pipe Pairs A thru D

This section gives requirements related to Thin Pipes between slots, where the pipes are composed of two lanes and the Slot Profiles have them labeled as individual pairs. Backplane Profile Rules that are to be wired as lanes, as defined by these requirements, include the phrase: “complying with the Rules of Section 7.2.2”.

Rule 7.2.2-1: The A pair at both ends of the Thin Pipe shall connect to the B pair at the other end; where the name of the A pair ends in “-DA” and the name of the B pair ends in “-DB”. Note: There is a “+” or “-“ appended to the end of the pair name to identify the individual wires of the pair. [VM = I]

Rule 7.2.2-2: The C pair at both ends of the Thin Pipe shall connect to the D pair at the other end; where the name of the C pair ends in “-DC” and the name of the D pair ends in “-DD”. Note: There is a “+” or “-“ appended to the end of the pair name to identify the individual wires of the pair. [VM = I]

Rule 7.2.2-3: For each differential pair between slots, the “+” wire on one end shall connect to the “+” wire on the other end and the “-” wire on one end shall connect to the “-” wire on the other end. [VM = I]

Observation 7.2.2-1: Plug-In Modules that are using 1000BASE-T connections over Thin Pipes that are wired in accordance to the Rules of this Section need to have Automatic MDI/MDI-X Configuration as required by Rule 5.1.3-2.


Observation 7.2.2-2: Plug-In Modules that are using 1000BASE-T connections over Thin Pipes that do not have Automatic MDI/MDI-X Configuration as required by Rule 5.1.3-2, would need the Thin Pipes wired with pair A connecting to pair A, pair B connecting to pair B etc.

7.3 Port Jumbling

Rule 7.3-1: In cases where it is permitted to jumble the order of which ports are used for particular connections, a table shall be provided that spells out which port in one slot connects to which port in another. [VM = I]

Observation 7.3-1: When ports are jumbled, the rules for the backplane topology might allow which port of a Switch Slot, a particular Payload Slot connects to, to vary in order to make backplane routing easier.

Observation 7.3-2: There can be cases where not all ports are equal. For example, a PCIe Switch Module can have a particular port that is intended to be an upstream port. In such a case, jumbling the ports can create a problem where a special port (e.g. the upstream port) on a Switch Module does not go to the correct Payload Module.

7.4 Backplane Channel Gbaud Rate

[VITA 68] defines the backplane channel characteristics necessary to achieve data baud rates used in this specification.

Rule 7.4-1: Backplane channels shall comply with applicable [VITA 68] compliance channel requirements at all frequencies up to their rated baud rate. [VM = T,A]

Rule 7.4-2: ***Deleted***For each channel baud rate specified in a Backplane Profile, backplanes shall be verified using the applicable section in [VITA 68]. [VM = T,A]

7.5 System Management

Observation 7.5-1: This specification does not mandate the locations of ChMCs within a chassis. ChMC locations shown in Backplane Profile diagrams are suggested, but not required.


8 Common to 6U and 3U — Module Profiles OpenVPX uses Module Profiles to define interoperability and physical characteristics necessary to interface with compatible slots. The following sub-sections define common requirements for all OpenVPX Module Profiles:


This specification identifies several levels of requirements for Module Profiles.

Rule 8.1-1: Requirements for a specific 6U Module Profile shall be applied using the following order of precedence: [VM = VNR]

1. Section 12.2 (or higher), connector specific 6U Module Profiles

2. Section 12.1, 6U Module Profile Common Section

3. Section 8, Common Requirements for all Module Profiles

Rule 8.1-2: Requirements for a specific 3U Module Profile shall be applied using the following order of precedence: [VM = VNR]

1. Section 16.2 (or higher), connector specific 3U Module Profiles

2. Section 16.1, 3U Module Profile Common Section

3. Section 8, Common Requirements for all Module Profiles

8.2 6U and 3U Module Cooling Types

As additional module cooling types mature, they might be added to this specification in future releases. This specification addresses the following module cooling types only:

a) [VITA 48.1] (air cooled)

b) [VITA 48.2] (conduction cooled)

c) [VITA 46.0] (air cooled and conduction cooled)

8.2.1 6U and 3U VITA 48.1 Air-Cooled Modules

Rule 8.2.1-1: If an air-cooled module supplier intends for their modules to function in a Standard Development Chassis as defined in this standard, then they shall validate compatibility with the flow rate and pressure drop constraints defined for the relevant Standard Development Chassis Profile(s). [VM = A,T]

Suggestion 8.2.1-1: It is suggested that module suppliers document a module’s required airflow in CFM at mean sea level (MSL)


Suggestion 8.2.1-2: It is suggested that module suppliers document a module’s slot P-Q curve; this plots pressure drop (in H2O) vs. air flow (CFM) at mean sea level (MSL). Refer to Figure 8.2.1-1 for an example of a module P-Q curve plotted along with 2 fan P-Q curves.

Figure 8.2.1-1 P-Q curve example

Observation 8.2.1-1: Module suppliers do not need to measure P-Q data for more than one module pitch.

Suggestion 8.2.1-3: It is suggested that module suppliers document a module’s slot T-Q curve at mean sea level (MSL); this plots a family of device temperature curves (degrees C) at various ambient temperatures vs. air flow (CFM), ideally plotted along with the P-Q curve and the maximum device temperature rating at mean sea level (MSL).

Observation 8.2.1-2: Required module airflow, module slot P-Q curve, and/or module slot T-Q curve might be restricted information that is available only under NDA (Non-Disclosure Agreement) or PIA (Proprietary Information Agreement) agreement.

Suggestion 8.2.1-4: In order to allow their use in Standard Development Chassis, it is suggested that 6U and 3U air-cooled modules be designed to require ≤15 CFM per slot at a maximum pressure of ≤0.24 in H2O at mean sea level (MSL).

Permission 8.2.1-1: 6U and 3U air-cooled modules may be designed to require >15 CFM per slot at a maximum pressure of >0.24 in H2O, but these modules might not be properly cooled in a Standard Development Chassis.

0

0.2

0.4

0.6

0.8

1

1.2

0 2 4 6 8 10 12 14 16 18 20 22 24Q (CFM) per Slot

P (in

H2O

)

Module P-Q curve

Fan 2 P-Q curve

Fan 1 P-Q curve

Fan 2 Operating Point

Fan 1 Operating Point


Rule 8.2.1-2: 6U and 3U air-cooled plug in modules shall be designed for proper cooling with airflow intake at the P6/J6 end (6U) or P2/J2 end (3U), and air exhaust at the P0/J0 end of the module. Refer to Figure 9.2-1. [VM = I]

8.2.2 6U and 3U VITA 48.2 Conduction-Cooled Modules

Rule 8.2.2-1: If a conduction-cooled module supplier intends for their modules to function in one or more Standard Development Chassis as defined in this standard, then they shall validate compatibility with the slot power dissipation, slot sidewall temperature, and slot sidewall finish boundary conditions defined for the relevant Standard Development Chassis Profile(s). [VM = T,A]

Rule 8.2.2-2: Conduction-cooled modules shall utilize a low profile style injector/ejector as defined in [VITA 48.2]. [VM = I]

Suggestion 8.2.2-1: It is suggested that module suppliers document a module’s maximum card edge operating temperature

Suggestion 8.2.2-2: It is suggested that module suppliers document a module’s maximum chassis sidewall operating temperature, taking into account wedge clamp performance with the wedge clamp supplier’s suggested wedge clamp torque assuming chassis sidewall average surface roughness of Ra125 per [ANSI B46.1]. Note that test methods might be supplier proprietary.

Observation 8.2.2-1: A module’s required maximum chassis sidewall operating temperature might be restricted information that is available only under NDA (Non-Disclosure Agreement) or PIA (Proprietary Information Agreement) agreement

Suggestion 8.2.2-3: In order to allow their use in Standard Development Chassis, it is suggested that 6U and 3U conduction-cooled modules be designed to have a maximum operating temperature of >70°C at the card edge.

Recommendation 8.2.2-1: In order to allow their use in Standard Development Chassis, 6U and 3U conduction-cooled modules should be designed to operate with a maximum operating temperature of 55°C at the chassis sidewall taking into account wedge clamp performance with the wedge clamp supplier’s suggested torque with a chassis sidewall average surface roughness of Ra125 per [ANSI B46.1]. Note that test methods might be supplier proprietary. [VM = T,A]

Permission 8.2.2-1: 6U and 3U conduction-cooled modules may be designed to require <55°C at the chassis sidewall, but these modules might not be properly cooled in a Standard Development Chassis.


8.3 User Defined Pins

The Module Profiles in this Section are generic. The Module Profiles are generally silent concerning User Defined pins. It is expected that Modules that are designed to comply with Module Profiles in this document will implement protocols on many of the User Defined pins.

Recommendation 8.3-1: Plug-In Modules that have PMC and/or XMC sites with rear I/O should use [VITA 46.9] to map that I/O onto the backplane connectors. [VM = I]

8.4 Unused ports and lanes

Permission 8.4-1: Unless otherwise noted in a specific Module Profile, for each pipe with a protocol specified, the Module Profiles given in Sections 12 and 16 have all the lanes used. Plug-In Modules built to comply with these Module Profiles may leave some lanes unused, following the Rules of the Slot Profile for which lanes are used first.

8.5 Plug-In Module Compliance with Multiple Module Profiles

Note: For requirements related to Plug-In Module being compatible with multiple Slot Profiles, see Section 6.2.3.

Permission 8.5-1: Plug-In Module implementations may be configurable to comply with more than one Module Profile.

Observation 8.5-1: A Module can plug into a slot intended for another module provided that any pipes/pins that would conflict are not connected. For example, a Plug-In Module with a Module Profile of MOD6-PER-2F-12.3.2-2 can be used in a slot intended for a Module with a profile of MOD6-PER-4F-12.3.1-3, provided that the user defined pins on P1 are not connected.

Permission 8.5-2: A Plug-In Module may support the features of more than one Module Profile, provided that any signal conflicts are limited to pipes that are User Defined on all but one of the corresponding Module Profiles. Such pipes take on the definition of the Module Profile in which they are not User Defined.


9 Common to 6U and 3U — Standard Development Chassis Profiles

OpenVPX uses Standard Development Chassis Profiles to define interoperability and physical characteristics necessary to interface with compatible backplanes and Plug-In Modules. The following sub-sections define common requirements for all OpenVPX Standard Development Chassis Profiles:


This specification identifies several levels of requirements for Chassis Profiles.

Rule 9.1-1: Requirements for a specific 6U Chassis Profile shall be applied using the following order of precedence: [VM = VNR]

1. Section 13.2 (or higher), 6U Standard Development Chassis Profiles

2. Sections 13.1, for 6U Standard Development Chassis Profile Common Section

3. Section 9, Common Requirements for all Standard Development Chassis Profiles

Rule 9.1-2: Requirements for a specific 3U Chassis Profile shall be applied using the following order of precedence: [VM = VNR]

1. Section 17.2 (or higher), 3U Standard Development Chassis Profiles

2. Sections 17.1, for 3U Standard Development Chassis Profile Common Section

3. Section 9, Common Requirements for all Standard Development Chassis Profiles

9.2 6U and 3U VITA 48.1 Air-Cooled Standard Development Chassis

Rule 9.2-1: Chassis suppliers shall certify a chassis’ compliance with the flow rate and pressure drop constraints defined in the relevant Standard Development Chassis Profile, for all slots in the chassis. [VM = A,T]

Suggestion 9.2-1: It is suggested that chassis suppliers document a chassis’ P-Q curve; this plots pressure drop (in H2O) vs. air flow (CFM) in each slot at mean sea level (MSL).

Observation 9.2-1: Chassis P-Q curves and/or test methods might be restricted information that is available only under NDA (Non-Disclosure Agreement) or PIA (Proprietary Information Agreement) agreement

Rule 9.2-2: 6U and 3U Air-cooled Standard Development Chassis shall be designed to provide ≥18 CFM per slot at a maximum pressure of 0.24 in H2O at 5000 ft altitude. [VM = A,T]


Observation 9.2-2: Note that 18 CFM at 5000 ft is the same mass flow as 15 CFM at MSL, and required flow rate is based on power dissipation of 150W/slot for 6U (75W/slot for 3U).

Rule 9.2-3: Standard 6U air-cooled Standard Development Chassis shall be designed such that airflow intake is at the P6/J6 end (P2/J2 end for 3U), and air exhaust is at the P0/J0 end of the module. Refer to Figure 9.2-1. [VM = A,T]

Figure 9.2-1 Airflow direction

Permission 9.2-1: Customized 6U and 3U air-cooled Standard Development Chassis may be designed such that airflow intake is at the P0/J0 end and air exhaust is at the P6/J6 end (6U) or P2/J2 end (3U) of the module. Refer to Figure 9.2-1.

9.3 6U and 3U VITA 48.2 Conduction-Cooled Chassis

Rule 9.3-1: Chassis suppliers shall certify a chassis’ compliance with the temperature and sidewall finish constraints defined in the relevant Standard Development Chassis Profile, for all slots in the chassis. [VM = A,T]

Rule 9.3-2: Conduction-cooled Standard Development Chassis shall provide low profile style injector/ejector lips as defined in [VITA 48.2]. [VM = A,T]

Rule 9.3-3: Conduction-cooled Standard Development Chassis shall have a sidewall average surface roughness of at most Ra125 per [ANSI B46.1]. [VM = I]


Suggestion 9.3-1: It is suggested that chassis suppliers document a chassis’ sidewall temperature for each slot with each slot dissipating the maximum rated power in each slot at 30°C ambient and mean sea level (MSL).

Suggestion 9.3-2: It is suggested that chassis suppliers document their test method for determining chassis’ sidewall temperatures; it is suggested to include a temperature monitoring position in the center of the wedgelock thermal interface on the sidewall.

Observation 9.3-1: A chassis’ sidewall temperature for each slot might be restricted information that is available only under NDA (Non-Disclosure Agreement) or PIA (Proprietary Information Agreement).


10 6U Slot Profiles The following sub-sections define different variants of 6U height Slot Profiles that are used in OpenVPX Backplane Profiles:

10.1 6U Slot Profiles Common Section

For material common to both 6U and 3U Slot Profiles, see Section 6.

10.2 6U Payload Slot Profiles Using VITA 46.0 Connectors

Rule 10.2-1: The Slot Profiles of Section 10.2 shall comply with the Rules of Section 6.3. [VM = I]


10.2.1 Payload Slot Profile SLT6-PAY-4F1Q2U2T-10.2.1

This Slot Profile is for a Payload Slot. Figure 10.2.1-1 gives an overview of the Slot Profile. Table 10.2.1-1 thru Table 10.2.1-6 give the detailed pin assignments. For Module Profiles using this Slot Profile, see Section 12.2.1.

Data Plane — 4 Fat Pipes

Expansion Plane — 32 pairs

User Defined

User Defined

User Defined

SE

DiffP6/J6

SE

DiffP5/J5

SE

DiffP4/J4

SE

DiffP3/J3

SE

DiffP2/J2

SE Diff

P1/J1

SEP0/J0

Utility PlaneUser Defined

Utility Plane

Key

Key

Key

Control Plane — 2 Thin PipesControl Plane — 2 Ultra-Thin Pipes

Figure 10.2.1-1 Payload Slot Profile SLT6-PAY-4F1Q2U2T-10.2.1


10.2.1.1 Utility Plane — Pins on P0/J0 and SE of P1/J1

See Section 3 for a description of the pins associated with the Utility Plane.

Rule 10.2.1.1-1: The Utility Plane shall be implemented as described in Table 3.7-1 and Table 3.7-2 for P0/J0, and Table 10.2.1-1 for single-ended pins of P1/J1. [VM = I]

10.2.1.2 Control Plane

Rule 10.2.1.2-1: There shall be pins allocated for 2 Control Plane Ultra-Thin Pipes on P4/J4, CPutp01 and CPutp02, as given in Table 10.2.1-4, with usage complying with Section 6.2.2. [VM = I]

Rule 10.2.1.2-2: There shall be pins allocated for 2 Control Plane Thin Pipes on P4/J4, CPtp01 and CPtp02, as given in Table 10.2.1-4, with usage complying with Section 6.2.2. [VM = I]

10.2.1.3 Data Plane

Rule 10.2.1.3-1: There shall be pins allocated for 4 Data Plane Fat Pipes on P1/J1, DP01 – DP04, as given in Table 10.2.1-1, with usage complying with Section 6.2.2. [VM = I]

10.2.1.4 Expansion Plane

Rule 10.2.1.4-1: There shall be pins allocated for 16 lanes of Expansion Plane on P2/J2, EP00 – EP15, as given in Table 10.2.1-2, with usage complying with Section 6.2.2. [VM = I]

Rule 10.2.1.4-2: If the Expansion Plane is broken into pipes, the Expansion Plane lanes shall be assigned to pipes following one of the options given in Table 6.2.4.2-3, with usage complying with Section 6.2.2. [VM = I]

Permission 10.2.1.4-1: Some pipes may be left unused.

Permission 10.2.1.4-2: The 16 lanes of Expansion Plane may be used as 32 pairs.

Observation 10.2.1.4-1: Using the Expansion Plane as pairs is useful if there is more traffic in one direction than the other.

Permission 10.2.1.4-3: When the Expansion Plane is used as pairs, the backplane may still be wired as lanes — with pairs intended for receive and transmit crossed. See Section 7.2.1

10.2.1.5 User Defined

For requirements concerning User Defined pins See Section 6.3.3.

For recommendations for plug-in modules with an XMC or PMC site, see Section 8.3.


Table 10.2.1-1 Payload Slot Profile SLT6-PAY-4F1Q2U2T-10.2.1 — P1 & J1 Plug-In Module P1


Bplane J1 Row i Row h Row g Row f Row e Row d Row c Row b Row a 1

Dat

a Pl

ane

Port

1

GDiscrete1 GND GND-J1 DP01-T0- DP01-T0+ GND GND-J1 DP01-R0- DP01-R0+

2 GND DP01-T1- DP01-T1+ GND-J1 GND DP01-R1- DP01-R1+ GND-J1 GND

3 P1-VBAT GND GND-J1 DP01-T2- DP01-T2+ GND GND-J1 DP01-R2- DP01-R2+


5

Dat

a Pl

ane

Port

2

SYS_CON* GND GND-J1 DP02-T0- DP02-T0+ GND GND-J1 DP02-R0- DP02-R0+


7 Reserved GND GND-J1 DP02-T2- DP02-T2+ GND GND-J1 DP02-R2- DP02-R2+


9

Dat

a Pl

ane

Port

3

UD GND GND-J1 DP03-T0- DP03-T0+ GND GND-J1 DP03-R0- DP03-R0+


11 UD GND GND-J1 DP03-T2- DP03-T2+ GND GND-J1 DP03-R2- DP03-R2+


13

Dat

a Pl

ane

Port

4



15 Maskable Reset* GND GND-J1 DP04-T2- DP04-T2+ GND GND-J1 DP04-R2- DP04-R2+





Backplane J2 Row i Row h Row g Row f Row e Row d Row c Row b Row a 1

X16

usin

g [1

5:0]

x8 u

sing

[7:0

]

x4 u

sing

[3:0

] UD GND GND-J2 EP00-T- EP00-T+ GND GND-J2 EP00-R- EP00-R+

2 GND EP01-T- EP01-T+ GND-J2 GND EP01-R- EP01-R+ GND-J2 GND

3 UD GND GND-J2 EP02-T- EP02-T+ GND GND-J2 EP02-R- EP02-R+


5

x4 u

sing

[7:4





9

x8 u

sing

[15:

8]

x4 u

sing

[11:

8] UD GND GND-J2 EP08-T- EP08-T+ GND GND-J2 EP08-R- EP08-R+




13

x4 u

sing

[15:








Backplane J3 Row i Row h Row g Row f Row e Row d Row c Row b Row a

This connector is all User Defined pins. See Section 6.3.3 for requirements and pin assignments concerning connectors that are all User Defined.


Table 10.2.1-4 Payload Slot Profile SLT6-PAY-4F1Q2U2T-10.2.1 — P4 & J4 Plug-In Mod P4



Use

r Def

ined











11

2 U

TP

UD GND GND-J4 CPutp02-T- CPutp02-T+ GND GND-J4 CPutp02-R- CPutp02-R+

12 GND CPutp01-T- CPutp01-T+ GND-J4 GND CPutp01-R- CPutp01-R+ GND-J4 GND

13

Con

trol

Pla

ne

2 TP

s

UD GND GND-J4 CPtp02-DB- CPtp02-DB+ GND GND-J4 CPtp02-DA- CPtp02-DA+

14 GND CPtp02-DD- CPtp02-DD+ GND-J4 GND CPtp02-DC- CPtp02-DC+ GND-J4 GND

15 UD GND GND-J4 CPtp01-DB- CPtp01-DB+ GND GND-J4 CPtp01-DA- CPtp01-DA+




10.2.2 Payload Slot Profile SLT6-PAY-4F2T-10.2.2



User Defined

User Defined

User Defined

User Defined

SE

DiffP6/J6

SE

DiffP5/J5

SE

DiffP4/J4

SE

DiffP3/J3

SE

DiffP2/J2

SE Diff

P1/J1

SEP0/J0


Utility Plane

Key

Key

Key

Control Plane — 2 Thin Pipes

Figure 10.2.2-1 Payload Slot Profile SLT6-PAY-4F2T-10.2.2




Rule 10.2.2.1-1: The Utility Plane shall be implemented as described in Table 3.7-1 and Table 3.7-2 for P0/J0, and Table 10.2.2-1 for single ended pins of P1/J1. [VM = I]



10.2.2.3 Data Plane






Table 10.2.2-1 Payload Slot Profile SLT6-PAY-4F2T-10.2.2 — P1 & J1 Plug-In Module P1



Dat

a Pl

ane

Port

1





5

Dat

a Pl

ane

Port

2





9

Dat

a Pl

ane

Port

3





13

Dat

a Pl

ane

Port

4















Table 10.2.2-4 Payload Slot Profile SLT6-PAY-4F2T-10.2.2 — P4 & J4 Plug-In Mod P4



Use

r Def

ined













13

Con

trol

Pla

ne

2 TP

s















10.2.3 Payload Slot Profile SLT6-PAY-8F-10.2.3

Slot Profile for a Utility and Data Plane only Payload Slot. Figure 10.2.3-1 gives an overview of this profile. Table 10.2.3-1 thru Table 10.2.3-6 give the details pin assignments. For Module Profiles using this Slot Profile, see Section 12.2.3.


User Defined

User Defined

User Defined

SE

DiffP6

SE

DiffP5

SE

DiffP4

SE

DiffP3

SE

DiffP2

SE Diff

P1

SEP0


Utility Plane

Key

Key

Key

Reserved

Figure 10.2.3-1 Payload Slot Profile SLT6-PAY-8F-10.2.3


10.2.3.1 Utility Plane – Pins on P0/J0 and SE of P1/J1



10.2.3.2 Data Plane

Rule 10.2.3.2-1: There shall be pins allocated for 8 Data Plane Fat Pipes on P1/J1, DP01 – DP08, as given in Table 10.2.3-1 and Table 10.2.3-2, with usage complying with Section 6.2.2. [VM = I]

Recommendation 10.2.3.2-1: When routing more than one protocol within the Data Plane an order of precedence should be followed. [VM = I]

Recommendation 10.2.3.2-2: The following precedence should be followed; starting with Pipes nearest to P0 (DP01) following in order to the last Pipe on P2 (DP08) Peer to Peer protocols, followed by Master / Slave. [VM = I]





Table 10.2.3-1 Payload Slot Profile SLT6-PAY-8F-10.2.3 — P1 & J1 Plug-In Module P1



Dat

a Pl

ane

Port

1





5

Dat

a Pl

ane

Port

2





9

Dat

a Pl

ane

Port

3





13

Dat

a Pl

ane

Port

4









Dat

a Pl

ane

Por

t 5





5

Dat

a Pl

ane

Por

t 6





9

Dat

a Pl

ane

Port

7





13

Dat

a Pl

ane

Port

8











Table 10.2.3-4 Payload Slot Profile SLT6-PAY-8F-10.2.3 — P4 & J4 Plug-In Mod P4



Use

r Def

ined











11

RSV

D

UD GND GND-J4 RSVD RSVD GND GND-J4 RSVD RSVD

12 GND RSVD RSVD GND-J4 GND RSVD RSVD GND-J4 GND

13

Use

r Def

ined











10.2.4 Payload Slot Profile SLT6-PAY-4F16U-10.2.4

Slot Profile for a Utility and Data Plane only Payload Slot. Figure 10.2.4-1 gives an overview of this profile. Table 10.2.4-1 thru Table 10.2.4-6 give the details of pin assignments. For Module Profiles using this Slot Profile, see Section 12.2.4.

Data Plane 4 FP, 16 UTP

User Defined

SE

DiffP6/J6

SE

DiffP5/J5

SE

DiffP4/J4

SE

DiffP3/J3

SE

SE

SEP0/J0

Utility Plane

User Defined

Utility Plane

Key

Key

Key

User Defined

DiffP2/J2

DiffP1/J1

Figure 10.2.4-1 Payload Slot Profile SLT6-PAY-4F16U-10.2.4




Rule 10.2.4.1-1: The Utility Plane shall be implemented as described in Table 3.7-1 and Table 3.7-2 for P0/J0, and Table 10.2.4-1 for single-ended pins of P1/J1. [VM = I, T]

10.2.4.2 Data Plane

Rule 10.2.4.2-1: There shall be pins allocated for 4 Data Plane Fat Pipes on P1/J1, DP01 – DP04, as given in Figure 10.2.4-1 and Table 10.2.4-1, with usage complying with Section 6.2.2. [VM = I]

Rule 10.2.4.2-2: There shall be pins allocated for 16 Data Plane Ultra-Thin Pipes on P2/J2, DP05 – DP20, as given in Figure 10.2.4-1 and Table 10.2.4-2, with usage complying with Section 6.2.2. [VM = I]

Recommendation 10.2.4.2-1: When routing more than one protocol within the Data Plane an order of precedence should be followed. [VM = I]

Recommendation 10.2.4.2-2: The following precedence should be followed; starting with Pipes nearest to P0 of the appropriate size following in order to the last Pipe on P2 Peer to Peer protocols, followed by Master / Slave. [VM = I]





Table 10.2.4-1 Payload Slot Profile SLT6-PAY-4F16U-10.2.4 — P1& J1 Plug-In Module P1



Dat

a Pl

ane

Port

1





5

Dat

a Pl

ane

Port

2





9

Dat

a Pl

ane

Port

3





13

Dat

a Pl

ane

Port

4






Table 10.2.4-2 Payload Slot Profile SLT6-PAY-4F16U-10.2.4 — P2 & J2 Plug-In Module P2



16 U

ltra-

Thin

Pip

es fo

r Dat

a Po

rts

05 th

ru 2

0

UD GND GND-J2 DP05-T- DP05-T+ GND GND-J2 DP05-R- DP05-R+

2 GND DP06-T- DP06-T+ GND-J2 GND DP06-R- DP65-R+ GND-J2 GND

3 UD GND GND-J2 DP07-T- DP07-T+ GND GND-J2 DP07-R- DP07-R+





8 GND DP12-T3- DP12-T+ GND-J2 GND DP12-R- DP12-R+ GND-J2 GND










10.2.5 Payload Slot Profile SLT6-PAY-2F2U2T-10.2.5


Key

User DefinedControl Plane — 2 Ultra-Thin Pipes

User Defined

User Defined


User Defined

Key

SE

DiffP6/J6

SE

DiffP5/J5

SE

DiffP4/J4

SE

DiffP3/J3

SE

DiffP2/J2

SE Diff

P1/J1

SEP0/J0


Utility Plane

Key


Figure 10.2.5-1 Payload Slot Profile SLT6-PAY-2F2U2T-10.2.5








10.2.5.3 Data Plane






Table 10.2.5-1 Payload Slot Profile SLT6-PAY-2F2U2T-10.2.5 — P1 & J1 Plug-In Module P1



Dat

a Pl

ane

Port

1





5

Dat

a Pl

ane

Port

2





9

Use

r Def

ined





13

Use

r Def

ined



15 Maskable Reset* GND GND-J1 UD UD GND GND-J1 UD UD
















The pin assignments for this connector are the same as given in Table 10.2.1-4.













This Slot Profile is for a Payload Slot. Figure 10.2.6-1 gives an overview of the Slot Profile. Table 10.2.6-1 thru Table 10.2.6-6 give the detailed pin assignments. For Module Profiles using this Slot Profile, see Section 12.2.6. This Slot Profile is the same as SLT6-PAY-4F1Q2U2T-10.2.1, except that it adds clocks to the Expansion Plane and auxiliary resets.


User Defined

User Defined

User Defined

SE

DiffP6/J6

SE

DiffP5/J5

SE

DiffP4/J4

SE

DiffP3/J3

SE

DiffP2/J2

SE Diff

P1/J1

SEP0/J0


Utility Plane

Key

Key

Key


2 AXresets

2 EPclocks Expansion Plane —32 pairs as lanes EP15:EP00






10.2.6.1.1 Auxiliary Resets

Rule 10.2.6.1.1-1: There shall be pins allocated for 2 Expansion Plane Resets on P2/J2, AXreset1* and AXreset2*, as given in Table 10.2.6-2, with usage complying with Sections 3.4.9 and 6.2.2. [VM = I]




10.2.6.3 Data Plane










10.2.6.4.1 Expansion Plane Auxiliary Clocks

Rule 10.2.6.4.1-1: There shall be pins allocated for 2 Expansion Plane Clocks on P2/J2, EPclock1 and EPclock2, as given in Table 10.2.6-2, with usage complying with Section 6.2.2. [VM = I]












Bplane J2 Row i Row h Row g Row f Row e Row d Row c Row b Row a 1 AXreset1*

For the assignment of pins on P2 rows A thru F (J2 rows a thru h), see Table 10.2.1-2.

2 GND

3 AXreset2*

4 GND

5 EPclock1-

6 GND

7 EPclock1+

8 GND

9 EPclock2-

10 GND

11 EPclock2+

12 GND

13 UD

14 GND

15 UD

16 GND








This Slot Profile is for a Payload Slot. Figure 10.2.6-1 gives an overview of the Slot Profile. Table 10.2.7-1 thru Table 10.2.7-6 give the detailed pin assignments. For Module Profiles using this Slot Profile, see Section 12.2.7. This Slot Profile is the same as SLT6-PAY-4F1Q2U2T-10.2.6, except that it increases the number of Expansion Plane lanes from 16 to 32.


Expansion Plane —32 pairs as lanes EP15:EP00

User Defined

User Defined

User Defined

SE

DiffP6/J6

SE

DiffP5/J5

SE

DiffP4/J4

SE

DiffP3/J3

DiffP2/J2

SE Diff

P1/J1

SEP0/J0


Utility Plane

Key

Key

Key


Expansion Plane —32 pairs as lanes EP31:EP16

SE

2 AXresets

2 EPclocks






10.2.7.1.1 Expansion Plane Auxiliary Resets

Rule 10.2.7.1.1-1: There shall be pins allocated for 2 Expansion Plane Resets on P2/J2, AXreset1* and AXreset2*, as given in Table 10.2.6-2, with usage complying with Sections 3.4.9 and 6.2.2. [VM = I]




10.2.7.3 Data Plane



Rule 10.2.7.4-1: There shall be pins allocated for 32 lanes of Expansion Plane on P2/J2 and P5/J5, EP00 – EP31, as given in Table 10.2.1-2 and Table 10.2.7-5, with usage complying with Section 6.2.2. [VM = I]

Rule 10.2.7.4-2: If the Expansion Plane lanes EP00 thru EP15 (P2/J2) are broken into pipes, the Expansion Plane lanes shall be assigned to pipes following one of the options given in Table 6.2.4.2-3, with usage complying with Section 6.2.2. [VM = I]

Rule 10.2.7.4-3: If the Expansion Plane lanes EP16 thru EP31 (P5/J5) are broken into pipes, the Expansion Plane lanes shall be assigned to pipes following one of the options given in Table 6.2.4.2-3, with usage complying with Section 6.2.2. With lanes EP16 thru EP31 of this Slot Profile corresponding with lanes EP00 thru EP15 of Table 6.2.4.2-3. [VM = I]


Recommendation 10.2.7.4-1: If some Expansion Plane lanes are left unused, the lanes on P2 should be used first. [VM = I]


Permission 10.2.7.4-2: Some lanes on P5 may be used even if not all the lanes on P2 are used.

Observation 10.2.7.4-1: Module providers should look at which backplanes they want their module to be able to operate in, when considering where to put the lanes. For example if a module has only 12 lanes and the module supplier wants to be able to get an FP to the next lower and the next upper neighboring slots in both BKP-CEN16-11.2.2-n and BKP-CEN16-11.2.17-n then 2 FPs are put on P2 and 1 FP on P5. With 8 lanes on P2 and 4 on P5, mapped as FPs, following Rule 10.2.7.4-2 and Rule 10.2.7.4-3, the following lanes will be used: EP03:EP00, EP11:EP08, and EP19:EP16. With the backplane BKP-CEN16-11.2.2-n, the 2 FPs on P2 will be used and with BKP-CEN16-11.2.17-n, one on P2 and one on P5 will be used.




10.2.7.4.1 Expansion Plane Auxiliary Clocks

Rule 10.2.7.4.1-1: There shall be pins allocated for 2 Expansion Plane Clocks on P2/J2, EPclock1 and EPclock2, as given in Table 10.2.6-2, with usage complying with Section 6.2.2. [VM = I]

Observation 10.2.7.4.1-1: The clocks on P2/J2 are intended for use with the Expansion Plane lanes on both P2/J2 and P5/J5.








X16

usin

g [1

5:0]

x8 u

sing

[7:0

]

x4 u

sing

[3:0





5

x4 u

sing

[7:4





9

x8 u

sing

[15:

8]

x4 u

sing

[11:





13

x4 u

sing

[15:











10.3 6U Peripheral Slot Profiles Using VITA 46.0 Connectors

Rule 10.3-1: The Slot Profiles of this Section shall comply with the Rules of Section 6.3. [VM = I]


10.3.1 Peripheral Slot Profile SLT6-PER-4F-10.3.1

This Slot Profile is for a Peripheral Slot. Figure 10.3.1-1 gives an overview of the Slot Profile. Table 10.3.1-1 thru Table 10.3.1-6 gives the detailed pin assignments. For Module Profiles using this Slot Profile, see Section 12.3.1.


User Defined

User Defined

SE

DiffP6/J6

SE

DiffP5/J5

SE

DiffP4/J4

SE

DiffP3/J3

SE

DiffP2/J2

SE Diff

P1/J1

SEP0/J0


Utility Plane

Key

Key

Key

User Defined

Figure 10.3.1-1 Peripheral Slot Profile SLT6-PER-4F-10.3.1


10.3.1.1 Utility Plane — Pins on P0/J0 and SE of P/J1



10.3.1.2 Data Plane

Rule 10.3.1.2-1: There shall be pins allocated for 4 Data Plane Fat Pipes on P1, DP01 – DP04, as given in Table 10.3.1-1, with usage complying with Section 6.2.2. [VM = I]




Table 10.3.1-1 Peripheral Slot Profile SLT6-PER-4F-10.3.1 — P1 & J1 Plug-In Module P1



Dat

a Pl

ane

Port

1





5

Dat

a Pl

ane

Port

2





9

Dat

a Pl

ane

Port

3





13

Dat

a Pl

ane

Port

4








Slot Profile for a Utility and Data Plane only Peripheral Slot. Figure 10.3.2-1 gives an overview of this profile. Table 10.3.2-1 thru Table 10.3.2-6 give the details pin assignments. For Module Profiles using this Slot Profile, see Section 12.3.2.

User Defined

User Defined

SE

DiffP6/J6

SE

DiffP5/J5

SE

DiffP4/J4

SE

DiffP3/J3

SE

DiffP2/J2

SE Diff

P1/J1

SEP0/J0


Utility Plane

Key

Key

Key

User Defined







10.3.2.2 Data Plane

Rule 10.3.2.2-1: There shall be pins allocated for 2 Data Plane Fat Pipes on P1/J1, DP01 and DP02, as given in Figure 10.3.2-1 and Table 10.3.2-1, with usage complying with Section 6.2.2. [VM = I]





Table 10.3.2-1 Peripheral Slot Profile SLT6-PER-2F-10.3.2 — P1& J1 Plug-In Module P1



Dat

a Pl

ane

Port

1





5

Dat

a Pl

ane

Port

2





9

Use

r Def

ined















10.3.3 Peripheral Slot Profile SLT6-PER-4U-10.3.3


Data Plane — 4 Ultra-Thin Pipes

User DefinedUser Defined

SE

DiffP6/J6

SE

DiffP5/J5

SE

DiffP4/J4

SE

DiffP3/J3

SE

DiffP2/J2

SE Diff

P1/J1

SEP0/J0


Utility Plane

Key

Key

Key

User Defined

Figure 10.3.3-1 Peripheral Slot Profile SLT6-PER-4U-10.3.3




Rule 10.3.3.1-1: The Utility Plane shall be implemented as described in Table 3.7-1 and Table 3.7-2 for P0/J0, and Table 10.3.3-1 for single-ended pins of P1/J1. [VM = I, T]

10.3.3.2 Data Plane

Rule 10.3.3.2-1: There shall be pins allocated for 4 Data Plane Ultra-Thin Pipes on P1/J1, DP01 – DP04, as given in Figure 10.3.3-1 and Table 10.3.3-1, with usage complying with Section 6.2.2. [VM = I, T]





Table 10.3.3-1 Peripheral Slot Profile SLT6-PER-4U-10.3.3 — P1& J1 Plug-In Module P1



Dat

a Pl

ane

Port

1

GDiscrete1 GND GND-J1 DP01-T- DP01-T+ GND GND-J1 DP01-R- DP01-R+


3 P1-VBAT GND GND-J1 DP03-T- DP03-T+ GND GND-J1 DP03-R- DP03-R+


5

Use

r Def

ined

SYS_CON* GND GND-J1 UD UD GND GND-J1 UD UD


7 Reserved GND GND-J1 UD UD GND GND-J1 UD UD











Table 10.3.3-2 Peripheral Slot Profile SLT6-PER-4U-10.3.3 — P2 & J2 Plug-In Module P2











User Defined

User Defined

SE

DiffP6/J6

SE

DiffP5/J5

SE

DiffP4/J4

SE

DiffP3/J3

SE

DiffP2/J2

SE Diff

P1/J1

SEP0/J0

Utility Plane

User Defined

Utility Plane

Key

Key

Key

User Defined

Data Plane — 1 Fat Pipe






10.3.4.2 Data Plane

Rule 10.3.4.2-1: There shall be pins allocated for one Data Plane Fat Pipe on P1/J1, DP01, as given in Figure 10.3.4-1 and Table 10.3.4-1, with usage complying with Section 6.2.2. [VM = I]





Table 10.3.4-1 Peripheral Slot Profile SLT6-PER-1F-10.3.4 — P1& J1 Plug-In Module P1



Dat

a Pl

ane

Port

1





5

Use

r Def

ined



















10.3.5 Peripheral Slot Profile SLT6-PER-1Q-10.3.5

Slot Profile for a Utility and Expansion Plane only Peripheral Slot. Figure 10.3.5-1 gives an overview of this profile. Table 10.3.5-1 thru Table 10.3.5-6 give the details pin assignments. For Module Profiles using this Slot Profile, see Section 12.3.5.

Expansion Plane — 32 pairs

User Defined

User Defined

SE

DiffP6/J6

SE

DiffP5/J5

SE

DiffP4/J4

SE

DiffP3/J3

SE

DiffP2/J2

SE Diff

P1/J1

SEP0/J0


Utility Plane

Key

Key

Key

User Defined

Figure 10.3.5-1 Peripheral Slot Profile SLT6-PER-1Q-10.3.5





10.3.5.2 P1/J1 Pin Assignments

For requirements concerning User Defined pins see Section 6.3.3.







Permission 10.3.5.2-3: When the Expansion Plane is used as pairs, the backplane may still be wired as lanes — with pairs intended for receive and transmit crossed. See Section 7.2.1.





Table 10.3.5-1 Peripheral Slot Profile SLT6-PER-1Q-10.3.5 — P1& J1 Plug-In Module P1


Bplane J1 Row i Row h Row g Row f Row e Row d Row c Row b Row a 1 GDiscrete1

These rows are all User Defined pins. See Section 6.3.3 for requirements and pin assignments concerning connectors that are all User Defined.

2 GND

3 P1-VBAT

4 GND

5 SYS_CON*

6 GND

7 Reserved

8 GND

9 UD

10 GND

11 UD

12 GND

13 UD

14 GND

15 Maskable Reset*

16 GND



Table 10.3.5-2 Peripheral Slot Profile SLT6-PER-1Q-10.3.5 — P2 & J2 Plug-In Module P2



X16

usin

g [1

5:0]

x8 u

sing

[7:0

]

x4 u

sing

[3:0





5

x4 u

sing

[7:4





9

x8 u

sing

[15:

8]

x4 u

sing

[11:





13

x4 u

sing

[15:






10.4 6U Switch Slot Profiles Using VITA 46.0 Connectors



10.4.1 Switch Slot Profile SLT6-SWH-20U19F-10.4.1

This Slot Profile is for a Switch Slot intended to interoperate with the Payload Slot Profile of Section 10.2.1. Figure 10.4.1-1 gives an overview of the Slot Profile. Table 10.4.1-1 thru Table 10.4.1-6 give the detailed pin assignments. For Module Profiles using this Slot Profile, see Section 12.4.1.

SE

DiffP6/J6

Control Plane — 20 Ultra-Thin Pipes

SE

DiffP5/J5

SE

DiffP4/J4

SE

DiffP3/J3

SE

DiffP2/J2


SEP0/J0

User Defined


Utility Plane

Key

Key

Key

User Defined

SE Diff

P1/J1

Figure 10.4.1-1 Switch Slot Profile SLT6-SWH-20U19F-10.4.1




Rule 10.4.1.1-1: The Utility Plane shall be implemented as described in Table 3.7-1, and Table 3.7-2 for P0/J0, and Table 10.4.1-1 for single-ended pins of P1/J1. [VM = I]


Rule 10.4.1.2-1: There shall be pins allocated for 16 Control Plane Ultra-Thin Pipes, for connections to Payload Slots, CPutp01 thru CPutp16, as given in Table 10.4.1-1 and Table 10.4.1-2, with usage complying with Section 6.2.2. [VM = I]

Rule 10.4.1.2-2: There shall be pins allocated for 4 Control Plane Ultra-Thin Pipes, CSutp01 thru CSutp04, as given in Table 10.4.1-1, with usage complying with Section 6.2.2. [VM = I]

Rule 10.4.1.2-3: If there are connections between Switch Slots, they shall use CSutp01 thru CSutp04, starting with CSutp01. [VM = I]

Permission 10.4.1.2-1: Backplane Profiles that require more connections to Payload Slots than the number of Payload Ports available may use CSutp01 thru CSutp04, starting with the highest and working down, for connections to Payload Slots. Note: The use of ports CSutp01 thru CSutp04 for inter-switch starts with the lowest port and works up.

Observation 10.4.1.2-1: Ports used as crossover connections between Switch Slots might have the option of running at a higher signaling rate than ports to Payload Slots and/or might have some protocol properties, which are different, such as Ethernet stacking ports.

10.4.1.3 Data Plane Fat Pipes

Rule 10.4.1.3-1: There shall be pins allocated for 15 Data Plane Fat Pipes, DP01 thru DP15, as given in Table 10.4.1-2 thru Table 10.4.1-5, with usage complying with Section 6.2.2. [VM = I]

Rule 10.4.1.3-2: There shall be pins allocated for 4 Data Plane Fat Pipes, DS01 thru DS04, as given in Table 10.4.1-6, with usage complying with Section 6.2.2. [VM = I]

Rule 10.4.1.3-3: If there are connections between Switch Slots, they shall use DS01 thru DS04, starting with DS01. [VM = I]

Permission 10.4.1.3-1: Backplane Profiles that require more connections to Payload Slots than the number of Payload Ports available may use DS01 thru DS04, starting with the highest and working down, for connections to Payload Slots. Note: The use of DS01 thru DS04 for inter-switch starts with the lowest inter-switch port and works up.

Observation 10.4.1.3-1: Ports intended to be used as crossover connections between Switch Slots might have the option of running at a higher signaling rate than ports to Payload Slots


and/or might have some protocol properties, which are different, such as Ethernet stacking ports.



10.4.1.4.1 Suggested Thin Pipes Intended for External Connections

Suggestion 10.4.1.4.1-1: If external connections to the Switches are required, it is suggested that they be put on the single-ended pins of P5/J5 and P6/J6 as Thin Pipes.

Rule 10.4.1.4.1-1: If Suggestion 10.4.1.4.1-1 is followed, a Thin Pipe, CPtp01, shall be mapped to P5/J5 as given in Table 6.3.3.2-1 and another, CPtp02, to P6/J6 as given in Table 6.3.3.2-1 (except for the name change from CPtp01 to CPtp02). [VM = I]


Table 10.4.1-1 Switch Slot Profile SLT6-SWH-20U19F-10.4.1 — P1 & J1 Plug-In Module P1



CPl

ane

Inte

r-SW

U

TPs

Port

s 1

– 4 GDiscrete1 GND GND-J1 CSutp01-T- CSutp01-T+ GND GND-J1 CSutp01-R- CSutp01-R+

2 GND CSutp02-T- CSutp02-T+ GND-J1 GND CSutp02-R- CSutp02-R+ GND-J1 GND

3 P1-VBAT GND GND-J1 CSutp03-T- CSutp03-T+ GND GND-J1 CSutp03-R- CSutp03-R+


5

Con

trol

Pla

ne P

aylo

ad U

TPs

Port

s 1

– 12

SYS_CON* GND GND-J1 CPutp01-T- CPutp01-T+ GND GND-J1 CPutp01-R- CPutp01-R+


7 Reserved GND GND-J1 CPutp03-T- CPutp03-T+ GND GND-J1 CPutp03-R- CPutp03-R+


9 UD GND GND-J1 CPutp05-T- CPutp05-T+ GND GND-J1 CPutp05-R- CPutp05-R+






15 Maskable Reset* GND GND-J1 CPutp11-T- CPutp11-T+ GND GND-J1 CPutp11-R- CPutp11-R+






CPl

ane

Pay

UTP

s Po

rts

13 –





5

Dat

a Pl

ane

Pay-

load

FP

Port





9

Dat

a Pl

ane

Pay-

load

FP

Port





13

Dat

a Pl

ane

Pay-

load

FP

Port









Dat

a Pl

ane

Pay-

load

FP

Port





5

Dat

a Pl

ane

Pay-

load

FP

Port





9

Dat

a Pl

ane

Pay-

load

FP

Port





13

Dat

a Pl

ane

Pay-

load

FP

Port






Table 10.4.1-4 Switch Slot Profile SLT6-SWH-20U19F-10.4.1 — P4 & J4 Plug-in Module P4



Dat

a Pl

ane

Pay-

load

FP

Port





5

Dat

a Pl

ane

Pay-

load

FP

Port





9

Dat

a Pl

ane

Pay-

load

FP

Port





13

Dat

a Pl

ane

Pay-

load

FP

Port









Dat

a Pl

ane

Pay-

load

FP

Port





5

Dat

a Pl

ane

Pay-

load

FP

Port





9

Dat

a Pl

ane

Pay-

load

FP

Port





13

Dat

a Pl

ane

Pay-

load

FP

Port









Dat

a Pl

ane

Inte

r-

SW F

P Po

rt 4

UD GND GND-J6 DS04-T0- DS04-T0+ GND GND-J6 DS04-R0- DS04-R0+

2 GND DS04-T1- DS04-T1+ GND-J6 GND DS04-R1- DS04-R1+ GND-J6 GND

3 UD GND GND-J6 DS04-T2- DS04-T2+ GND GND-J6 DS04-R2- DS04-R2+


5

Dat

a Pl

ane

Inte

r-

SW F

P Po

rt 3





9

Dat

a Pl

ane

Inte

r-

SW F

P Po

rt 2





13

Dat

a Pl

ane

Inte

r-

SW F

P Po

rt 1







This Slot Profile is for a Switch Slot intended to interoperate with the Payload Slot of Section 10.2.1. Figure 10.4.2-1 gives an overview of the Slot Profile. Table 10.4.2-1 thru Table 10.4.2-6 give the detailed pin assignments. For Module Profiles using this Slot Profile, see Section 12.4.2.


Utility Plane

SE

DiffP6/J6


SE

DiffP5/J5

SE

DiffP4/J4

SE

DiffP3/J3

SE

DiffP2/J2


SEP0/J0

User Defined

Key

User Defined

Key

Key

SE Diff

P1/J1





Rule 10.4.2.1-1: The Utility Plane shall be implemented as described in Table 3.7-1, and Table 3.7-2 for P0/J0, and Table 10.4.2-1 for single-ended pins of P1/J1. [VM = I]


Rule 10.4.2.2-1: There shall be pins allocated for 12 Control Plane Ultra-Thin Pipes, CPutp01 thru CPutp12, as given in Table 10.4.2-1, with usage complying with Section 6.2.2. [VM = I]

Rule 10.4.2.2-2: There shall be pins allocated for 4 Control Plane Ultra-Thin Pipes, CSutp01 thru CSutp04, as given in Table 10.4.2-1, with usage complying with Section 6.2.2. [VM = I]



Observation 10.4.2.2-1: Ports intended to be used as crossover connections between Switch Slots might have the option of running at a higher signaling rate than ports to Payload Slots and/or might have some protocol properties, which are different, such as Ethernet stacking ports.












Suggestion 10.4.2.4.1-1: If external connections to the switch are required, it is suggested that they be put on the single-ended pins of P5/J5 and P6/J6 as Thin Pipes.






CPl

ane

Inte

r-SW

U

TPs

Port

s 1





5

Con

trol

Pla

ne P

aylo

ad U

TPs

Port

s 1

– 12

















Dat

a Pl

ane

FP

Port

16





5

Dat

a Pl

ane

FP

Port

15





9

Dat

a Pl

ane

FP

Port

14





13

Dat

a Pl

ane

FP

Port

13









Dat

a Pl

ane

Pay-

load

FP

Port





5

Dat

a Pl

ane

Pay-

load

FP

Port





9

Dat

a Pl

ane

Pay-

load

FP

Port





13

Dat

a Pl

ane

Pay-

load

FP

Port






Table 10.4.2-4 Switch Slot Profile SLT6-SWH-16U20F-10.4.2 — P4 & J4 Plug-in Module P4



Dat

a Pl

ane

Pay-

load

FP

Port





5

Dat

a Pl

ane

Pay-

load

FP

Port





9

Dat

a Pl

ane

Pay-

load

FP

Port





13

Dat

a Pl

ane

Pay-

load

FP

Port









Dat

a Pl

ane

Pay-

load

FP

Port





5

Dat

a Pl

ane

Pay-

load

FP

Port





9

Dat

a Pl

ane

Pay-

load

FP

Port





13

Dat

a Pl

ane

Pay-

load

FP

Port









Dat

a Pl

ane

Inte

r-

SW F

P Po

rt 4





5

Dat

a Pl

ane

Inte

r-

SW F

P Po

rt 3





9

Dat

a Pl

ane

Inte

r-

SW F

P Po

rt 2





13

Dat

a Pl

ane

Inte

r-

SW F

P Po

rt 1






10.4.3 Switch Slot Profile SLT6-SWH-24F-10.4.3



Utility Plane

SE

DiffP6/J6

SE

DiffP5/J5

SE

DiffP4/J4

SE

DiffP3/J3

SE

DiffP2/J2


SEP0/J0

User Defined

Key

User Defined

Key

Key

SE Diff

P1/J1

Figure 10.4.3-1 Switch Slot Profile SLT6-SWH-24F-10.4.3







Rule 10.4.3.2-2: There shall be pins allocated for 4 Data Plane Fat Pipes, DS01 thru DS04, as given in Table 10.4.3-6 with usage complying with Section 6.2.2. [VM = I]





For requirements concerning User Defined pins See Section 6.3.3. [VM = I]



Rule 10.4.3.3.1-1: If Suggestion 10.4.3.3.1-1 is followed, a Thin Pipe, CPtp01 shall be mapped to P5/J5 as given in Table 6.3.3.2-1 and another, CPtp02, to P6/J6 as given in Table 6.3.3.2-1 (except for the name change from CPtp01 to CPtp02). [VM = I]


Table 10.4.3-1 Switch Slot Profile SLT6-SWH-24F-10.4.3 — P1 & J1 Plug-In Module P2



Dat

a Pl

ane

FP

Port

20





5

Dat

a Pl

ane

FP

Port

19





9

Dat

a Pl

ane

FP

Port

18





13

Dat

a Pl

ane

FP

Port

17









Dat

a Pl

ane

FP

Port

16





5

Dat

a Pl

ane

Pay-

load

FP

Port





9

Dat

a Pl

ane

Pay-

load

FP

Port





13

Dat

a Pl

ane

Pay-

load

FP

Port









Dat

a Pl

ane

Pay-

load

FP

Port





5

Dat

a Pl

ane

Pay-

load

FP

Port





9

Dat

a Pl

ane

Pay-

load

FP

Port





13

Dat

a Pl

ane

Pay-

load

FP

Port






Table 10.4.3-4 Switch Slot Profile SLT6-SWH-24F-10.4.3 — P4 & J4 Plug-in Module P4



Dat

a Pl

ane

Pay-

load

FP

Port





5

Dat

a Pl

ane

Pay-

load

FP

Port





9

Dat

a Pl

ane

Pay-

load

FP

Port





13

Dat

a Pl

ane

Pay-

load

FP

Port









Dat

a Pl

ane

Pay-

load

FP

Port





5

Dat

a Pl

ane

Pay-

load

FP

Port





9

Dat

a Pl

ane

Pay-

load

FP

Port





13

Dat

a Pl

ane

Pay-

load

FP

Port









Dat

a Pl

ane

Inte

r-

SW F

P Po

rt 4





5

Dat

a Pl

ane

Inte

r-

SW F

P Po

rt 3



7 UD CPtp02-DB+ GND GND-J6 DS03-T2- DS03-T2+ GND GND-J6 DS03-R2- DS03-R2+


9

Dat

a Pl

ane

Inte

r-

SW F

P Po

rt 2





13

Dat

a Pl

ane

Inte

r-

SW F

P Po

rt 1






10.4.4 Switch Slot Profile SLT6-SWH-4F24T-10.4.4


Utility Plane

User Defined

Utility Plane

SE

DiffP6/J6

SE

DiffP5/J5

SE

SE

SE


SEP0/J0

User Defined

User Defined

Key

User Defined

Key

Key

SE

Control Plane — 4 Fat Pipes

User Defined

DiffP1/J1

DiffP2/J2

DiffP3/J3

DiffP4/J4

Figure 10.4.4-1 Switch Slot Profile SLT6-SWH-4F24T-10.4.4






10.4.4.2.1 Fat Pipes for External Connections

Rule 10.4.4.2.1-1: There shall be pins allocated for 4 Control Plane Fat Pipes, CP01 thru CP04, as given in Table 10.4.4-1, with usage complying with Section 6.2.2. [VM = I]

10.4.4.2.2 Thin Pipes

Rule 10.4.4.2-1: There shall be pins allocated for 24 Control Plane Thin Pipes, CPtp01 thru CPtp024, as given in Table 10.4.4-2 thru Table 10.4.4-4, with usage complying with Rule 6.2.2-2 and Rule 6.2.2-3. [VM = I]


For requirements concerning User Defined pins See Section 6.3.3. [VM = I]






Table 10.4.4-1 Switch Slot Profile SLT6-SWH-4F24T-10.4.4 — P1 & J1 Plug-In Module P1



Con

trol

Pla

ne

Port

1

GDiscrete1 GND GND-J1 CP01-T0- CP01-T0+ GND GND-J1 CP01-R0- CP01-R0+

2 GND CP01-T1- CP01-T1+ GND-J1 GND CP01-R1- CP01-R1+ GND-J1 GND

3 P1-VBAT GND GND-J1 CP01-T2- CP01-T2+ GND GND-J1 CP01-R2- CP01-R2+


5

Con

trol

Pla

ne

Port

2

SYS_CON* GND GND-J1 CP02-T0- CP02-T0+ GND GND-J1 CP02-R0- CP02-R0+


7 Reserved GND GND-J1 CP02-T2- CP02-T2+ GND GND-J1 CP02-R2- CP02-R2+


9

Con

trol

Pla

ne

Port

3

UD GND GND-J1 CP03-T0- CP03-T0+ GND GND-J1 CP03-R0- CP03-R0+


11 UD GND GND-J1 CP03-T2- CP03-T2+ GND GND-J1 CP03-R2- CP03-R2+


13

Con

trol

Pla

ne

Port

4

UD GND GND-J1 CP04-T0- CP04-T0+ GND GND-J1 CP04-R0- CP04-R0+


15 Maskable Reset* GND GND-J1 CP04-T2- CP04-T2+ GND GND-J1 CP04-R2- CP04-R2+






Con

trol

Pla

ne T

hin

Pipe

s 1

- 8





















Con

trol

Pla

ne T

hin

Pipe

s 9

- 16





















Con

trol

Pla

ne T

hin

Pipe

s 17

- 24

UD GND GND-J4 CPtp17-DB- CPtp17-DB+ GND GND- J4 CPtp17-DA- CPtp17-DA+

2 GND CPtp17-DD- CPtp17-DD+ GND-J3 GND CPtp17-DC- CPtp17-DC+ GND- J4 GND

3 UD GND GND- J4 CPtp18-DB- CPtp18-DB+ GND GND- J4 CPtp18-DA- CPtp18-DA+

4 GND CPtp18-DD- CPtp18-DD+ GND- J4 GND CPtp18-DC- CPtp18-DC+ GND- J4 GND

5 UD GND GND- J4 CPtp19-DB- CPtp19-DB+ GND GND-J3 CPtp19-DA- CPtp19-DA+
















This connector is all User Defined pins. See Section 6.3.3 for requirements and pin assignments concerning connectors that are all User Defined




This connector is all User Defined pins. See Section 6.3.3 for requirements and pin assignments concerning connectors that are all User Defined



This Slot Profile is for a Switch Slot intended to interoperate with the Payload Slot of Section 10.2.1 or to interoperate in a meshed backplane as described in Section 11.2.19. Figure 10.4.5-1 gives an overview of the Slot Profile. Table 10.4.5-1 thru Table 10.4.5-6 give the detailed pin assignments. For Module Profiles using this Slot Profile, see Section 12.4.5.

Control Plane — 16 Ultra-thin Pipes


SE

DiffP6/J6

SE

DiffP5/J5

SE

DiffP4/J4

SE

DiffP3/J3

SE

DiffP2/J2

SE Diff

P1/J1

SEP0/J0


Utility Plane

User Defined

User Defined

Key

Key

Key

User Defined







Rule 10.4.5.2-1: There shall be pins allocated for 12 Control Plane Ultra-Thin Pipes, CPutp01 thru CPutp12, as given in Table 10.4.5-1, with usage complying with Section 6.2.2. [VM = I]

Rule 10.4.5.2-2: There shall be pins allocated for 4 Control Plane Ultra-Thin Pipe, CSutp01 thru CSutp04, as given in Table 10.4.5-1, with usage complying with Section 6.2.2. [VM = I]














CPl

ane

Inte

r-SW

U

TPs

Port

s 1





5

Con

trol

Pla

ne P

aylo

ad U

TPs

Port

s 1

– 12

















Dat

a Pl

ane

Pay-

load

FP

Port





5

Dat

a Pl

ane

Pay-

load

FP

Port





9

Dat

a Pl

ane

Pay-

load

FP

Port





13

Dat

a Pl

ane

Pay-

load

FP

Port






Table 10.4.5-3 Switch Slot Profile SLT6-SWH-16U16F-10.4.5— P3 & J3 Plug-in Module P3



Dat

a Pl

ane

Pay-

load

FP

Port





5

Dat

a Pl

ane

Pay-

load

FP

Port





9

Dat

a Pl

ane

Pay-

load

FP

Port





13

Dat

a Pl

ane

Pay-

load

FP

Port






Table 10.4.5-4 Switch Slot Profile SLT6-SWH-16U16F-10.4.5— P4 & J4 Plug-In Module P4



Dat

a Pl

ane

Pay-

load

FP

Port





5

Dat

a Pl

ane

Pay-

load

FP

Port





9

Dat

a Pl

ane

Pay-

load

FP

Port





13

Dat

a Pl

ane

Pay-

load

FP

Port









Dat

a Pl

ane

Pay-

load

FP

Port





5

Dat

a Pl

ane

Pay-

load

FP

Port


6 GND DS03-T1- DS03-T1+ GND-J5 GND DP03-R1- DP03-R1+ GND-J5 GND



9

Dat

a Pl

ane

Pay-

load

FP

Port





13

Dat

a Pl

ane

Pay-

load

FP

Port











10.5 6U Miscellaneous Slot Profiles Using VITA 46.0 Connectors



10.5.1 VME Bridge Slot Profile SLT6-BRG-4F1V2T-10.5.1

This Slot Profile is for a Payload Slot, which uses the [VITA 46.1] interface. Figure 10.5.1-1 gives an overview of the Slot Profile. Table 10.5.1-1 thru Table 10.5.1-6 give the detailed pin assignments. For Module Profiles using this Slot Profile, see Section 12.5.1.


User Defined

User Defined

VME per VITA 46.1

SE

DiffP6

SE

DiffP5

SE

DiffP4

SE

DiffP3

SEP2

SE Diff

P1

SEP0

Utility Plane

User Defined

Utility Plane

Key

Key

Key

VME per VITA 46.1

User Defined


Figure 10.5.1-1 VME Bridge Slot Profile SLT6-BRG-4F1V2T-10.5.1






Rule 10.5.1.2-1: There shall be pins allocated for 2 Control Plane Thin Pipes, CPtp01 thru CPtp02, as given in Table 10.5.1-4, with usage complying with Section 6.2.2. [VM = I]


Rule 10.5.1.3-1: There shall be pins allocated for 4 Data Plane Fat Pipes, DP01 thru DP04, as given in Table 10.5.1-1, with usage complying with Section 6.2.2. [VM = I]

10.5.1.4 VME connections

Rule 10.5.1.4-1: All Pins assigned as VME shall follow the Rules within [VITA 46.1]. [VM = I]





Table 10.5.1-1 VME Bridge Slot Profile SLT6-BRG-4F1V2T-10.5.1 — P1 & J1 Plug-In Module P1



Dat

a Pl

ane

Port

1



3 P1-VBAT GND GND-J1 DP01-T2- DP01-T2+ GND GND-J1 CP01-R2- DP01-R2+


5

Dat

a Pl

ane

Port

2





9

Dat

a Pl

ane

Port

3





13

Dat

a Pl

ane

Port

4






Table 10.5.1-2 VME Bridge Slot Profile SLT6-BRG-4F1V2T-10.5.1 — P2 & J2

Plug-In Module connector P2 and backplane connector J2

VME uses a single ended connector for P2 / J2. It is completely specified by [VITA 46.1]. See the standard for detail pin assignments.


Table 10.5.1-3 VME Bridge Slot Profile SLT6-BRG-4F1V2T-10.5.1 — P3 & J3 Plug-In Mod P3



Use

r Def

ined

VME GND GND-J3 UD UD GND GND-J3 UD UD


3 VME GND GND-J3 UD UD GND GND-J3 UD UD


















Use

r Def

ined













13

Con

trol

Pla

ne

2 TP

s

VME GND GND-J4 CPtp02-DB- CPtp02-DB+ GND GND-J4 CPtp02-DA- CPtp02-DA+


15 VME GND GND-J4 CPtp01-DB- CPtp01-DB+ GND GND-J4 CPtp01-DA- CPtp01-DA+






Use

r Def

ined




















Bplane J6 Row i Row h Row g Row f Row e Row d Row c Row b Row a



10.5.2 VME Bridge Slot Profile SLT6-BRG-4F1V-10.5.2

Slot Profile is for VME Bridge Slot Profile supporting VITA 46.1 and using Utility and Data Planes. Table 10.5.2-1 through Table 10.5.2-6 give the details pin assignments. For Module Profiles using this Slot Profile, see Section 12.5.2.


User Defined

User Defined

SE

DiffP6/J6

SE

DiffP5/J5

SE

DiffP4/J4

SE

DiffP3/J3

SEP2/J2

SE Diff

P1/J1

SEP0/J0

Utility Plane

User Defined

Utility Plane

Key

Key

Key

Reserved

User Defined

VME per VITA 46.1

VME per VITA 46.1

Figure 10.5.2-1 Payload Slot Profile SLT6-BRG-4F1V-10.5.2





10.5.2.2 Data Plane

Rule 10.5.2.2-1: There shall be pins allocated for 4 Data Plane Fat Pipes, DP01 thru DP04, as given in Table 10.5.2-1, with usage complying with Section 6.2.2. [VM = I]

10.5.2.3 VMEbus

Rule 10.5.2.3-1: All Pins assigned as VME shall follow the Rules within [VITA 46.1]. [VM = I]




10.5.2.5 Other

Rule 10.5.2.5-1: Pins shown in Table 10.2.3-4 as reserved shall not be used. [VM = I]


Table 10.5.2-1 VME Bridge Slot Profile SLT6-BRG-4F1V-10.5.2 — P1& J1 Plug-In Module P1



Dat

a Pl

ane

Port

1





5

Dat

a Pl

ane

Port

2





9

Dat

a Pl

ane

Port

3





13

Dat

a Pl

ane

Port

4






Table 10.5.2-2 VME Bridge Slot Profile SLT6-BRG-4F1V-10.5.2 — P2 & J2

Plug-In Module connector P2 and backplane connector J2

VME uses a single ended connector for P2 / J2. It is completely specified by [VITA 46.1]. See the standard for detail pin assignments.


Table 10.5.2-3 VME Bridge Slot Profile SLT6-BRG-4F1V-10.5.2 — P3 & J3 Plug-In Mod P3



Use

r Def

ined

Sin

gle

Ende

d Pi

ns V

ME





















Use

r Def

ined

Si

ngle

End

ed P

ins

VME











11

RSV

D

VME GND GND-J4 RSVD RSVD GND GND-J4 RSVD RSVD

12 GND RSVD RSVD GND-J4 GND RSVD RSVD GND-J4 GND

13

UD

or

Rec

omm

enda

tion









Use

r Def

ined

Sin

gle

Ende

d Pi

ns V

ME


















Table 10.5.2-6 VME Bridge Slot Profile SLT6-BRG-4F1V-10.5.2 — P6 & J6 Plug-In Module P6





11 6U Backplane Profiles The following sub-sections define different variants of 6U height Backplane Profiles that are used in OpenVPX systems:

Table 11-1 summarizes the key characteristics for each of the Backplane Profiles in the subsections that follow. This table is informative and is provided to simplify the selection of a specific Backplane Profile. The section number, contained at the end of each profile name in the left hand column, is hyperlinked to the associated Backplane Profile for ease of reference. Within each Backplane Profile, the utilized Slot Profiles are also hyperlinked to their respective sections, and within each Slot Profile, a hyperlink is provided to a list of compatible Module Profiles.

For background on how topologies are characterized, see Section 1.3.4.

Table 11-2 gives Module Profiles that can be used with each Backplane Profile. There are some important caveats to using this table:

• It is important to note that these are not the only Module Profiles that can be used with each Backplane. In many cases if some functionality is given up or some restriction is met, other Module Profiles can be used.

• The Backplane Profiles are protocol agnostic. When picking Modules for a particular Backplane Profile it is important to make sure that the Modules are compatible with each other. For example, if a Switch Module is chosen that uses Serial RapidIO for the Data Plane, then the Payload Modules need to use Serial RapidIO for the Data Plane also.

• Backplane Profiles include channel Gbaud rates, for the supported planes; a system integrator needs to make sure the rated Gbaud rates, for the supported planes, are high enough to support the Gbaud rates of the protocols of the modules being used.


Table 11-1 Summary of 6U Backplane Profiles Using VITA 46.0 Connectors

Backplane Profile Name - Section Slot Types Communication Plane Topologies

BKP6-CEN16-11.2.2-n

Payload 14 Control 2 x UTP — Dual Star

Switch 2 Data 4 x FP — Dual Star + Daisy Chain

Expansion 2 x DFP — Daisy Chain

BKP6-CEN20-11.2.3-n




BKP6-CEN10-11.2.4-n





BKP6-CEN05-11.2.5-n Switch 1 Data 4 x FP — Quad Star


BKP6-CEN10-11.2.6-n

Payload 8 Control 2 x UTP – Dual Star

Switch 2 Data 4 x FP — Quad Star


BKP6-CEN10-11.2.7-n

Payload 8 Control 2 x TP — Available to RTMs


Expansion N/A

BKP6-CEN06-11.2.8-n



Expansion N/A


BKP6-CEN12-11.2.9-n Switch 2 Data 4 x FP — Quad Star

Expansion N/A

Payload 5 Control 2 x TP — Dual Star

BKP6-DIS06-11.2.10-n Switch 1 Data 4 x FP — Mesh (5-Slot Cluster)

Expansion N/A



BKP6-HYB17-11.2.11-n


Switch 2 Data 4 x FP — Mesh (3 of 4-Slot Cluster)

VME 3 Expansion N/A

Bridge 4 Parallel 1 x VME

Payload 1 Control N/A

BKP6-HYB08-11.2.12-n Peripheral 3 Data 2 x FP — Dual Star

VME 3 Expansion N/A

Bridge 1 Parallel 1 x VME


BKP6-CEN09-11.2.13-n Peripheral 8 Data 1 x FP — Single Star

Expansion N/A


BKP6-CEN06-11.2.14-n Peripheral 5 Data 2 x FP — Dual Star (1 slot left out)

Expansion N/A


BKP6-DIS06-11.2.15-n Switch 1 Data 4 x FP — Mesh (5-Slot Cluster)

Expansion N/A


BKP6-DIS05-11.2.16-n Data 4 x FP — Mesh (5-Slot Cluster)

Expansion N/A

BKP6-CEN16-11.2.17-n



Expansion 2 x QFP — Daisy Chain


BKP6-DIS06-11.2.18-n Data 4 x FP — Mesh (5-Slot Cluster) with one additional slot

Expansion 2 pairs of slots with QFP

BKP6-DIS09-11.2.19-n

Payload 9 Control 16 x UTP — Mesh (9-Slot Cluster)

Data 16 x FP — Mesh (9-Slot Cluster)

Expansion N/A



BKP6-HYB07-11.2.20-n

Payload 3 Control 2 x TP – Available to RTMs

VME 2 Data 4 x FP — Mesh (5-Slot Cluster)

Bridge 2 Expansion N/A

Parallel VME


Table 11-2 Matching Module Profiles to Backplane Profiles Using VITA 46.0 Connectors

Backplane Profiles Prefix for all names in this column is: BKP6-

Payload Modules Prefix for all names in this column is: MOD6-PAY-

Switch Modules Prefix for all names in this column is: MOD6-SWH-

Peripheral Modules Prefix for all names in this column is: MOD6-PER-

Miscellaneous Modules Prefix for all names in this column is: MOD6-

CEN16-11.2.2-n 4F1Q2U2T-12.2.1-n 20U19F-12.4.1-n

CEN20-11.2.3-n 4F1Q2U2T-12.2.1-n 20U19F-12.4.1-n

CEN10-11.2.4-n 4F1Q2U2T-12.2.1-n 20U19F-12.4.1-n

CEN05-11.2.5-n 4F1Q2U2T-12.2.1-n 16U20F-12.4.2-n

CEN10-11.2.6-n 4F1Q2U2T-12.2.1-n 16U20F-12.4.2-n

CEN10-11.2.7-n 4F2T-12.2.2-n 24F-12.4.3

CEN06-11.2.8-n 4F2T-12.2.2-n 24F-12.4.3

CEN12-11.2.9-n 4F2T-12.2.2-n 24F-12.4.3

DIS06-11.2.10-n 4F2T-12.2.2-n 4F24T-12.4.4

HYB17-11.2.11-n 4F2T-12.2.2-n 4F24T-12.4.4 BRG-4F1V2T-12.5.1-n

HYB08-11.2.12-n 8F-12.2.3-n 2F-12.3.2-n BRG-4F1V-12.5.2-n

CEN09-11.2.13-n 8F-12.2.3-n 2F-12.3.2-n

CEN06-11.2.14-n 8F-12.2.3-n 2F-12.3.2-n

DIS06-11.2.15-n 4F2T-12.2.2-n 4F24T-12.4.4

DIS05-11.2.16-n 4F-12.3.1-n

CEN16-11.2.17-n 4F2Q2U2T-12.2.7 20U19F-12.4.1-n

DIS06-11.2.18-n 4F2Q2U2T-12.2.7

DIS09-11.2.19-n 16U16F-12.4.5-n*

HYB07-11.2.20-n 4F2T-12.2.2-n BRG-4F1V2T-12.5.1-n

* Although this module is a Switch Module, it is being used as a Payload Module, in this particular Backplane Profile.


11.1 6U Backplane Profiles Common Section

For material common to both 6U and 3U Backplane Profiles, see Section 7.

11.2 6U Backplane Profiles Using VITA 46.0 Connectors

11.2.1 Common Section for 6U Backplanes Using VITA 46.0 Connectors

This section is for items that are common to all 6U Backplane Profiles that use VITA 46.0 connectors.

11.2.1.1 RTM connections

RTM connectors are discussed in Section 4.4.

Rule 11.2.1.1-1: Other than the Utility Plane signals covered by Rule 11.2.1.1-2, any signal routed in the backplane shall not be made available on the backplane RTM connectors (RJx) unless a requirement in a Backplane Profile specifically states that the signal is to be available to an RTM. [VM = I]

Recommendation 11.2.1.1-1: Any signal not routed in the backplane should be made available on the backplane RTM connectors (RJx), unless a requirement in a Backplane Profile specifically states otherwise. [VM = I]

Rule 11.2.1.1-2: All Utility Plane signals shall be made available on the backplane RTM connectors (RJx), that is all the signals on P0/J0 (Table 3.7-2) and the single-ended signals on P1/J1 (Table 3.7-4). [VM = I]


11.2.1.2.1 Power Distribution

There are general requirements concerning Power Distribution in Section 3.1.

The following Rules are for Power Distribution signals that are bussed on the backplane:

Rule 11.2.1.2.1-1: Vs1 and Vs2 shall be bussed among all slots in the backplane and be brought out on suitable connectors or connection points. [VM = I]

Recommendation 11.2.1.2.1-1: Vs1 and Vs2 should each be sized to be able to distribute at least 14 A per slot (28 A per slot with both combined). Refer to connector current load limits in [VITA 46.0]. [VM = A]

Rule 11.2.1.2.1-2: Vs3 shall be bussed among all slots in the backplane and be brought out on suitable connectors or connection points. [VM = I]


Recommendation 11.2.1.2.1-2: Vs3 should be sized to be able to distribute at least 22 A per slot. Refer to current load limits in [VITA 46.0]. [VM = A]

Rule 11.2.1.2.1-3: -12V_AUX shall be bussed among all slots in the backplane and be brought out on suitable connectors or connection points. Refer to current load limits in [VITA 46.0]. [VM = I]

Rule 11.2.1.2.1-4: 3.3V_AUX shall be bussed among all slots in the backplane and be brought out on suitable connectors or connection points. Refer to current load limits in [VITA 46.0]. [VM = A]

Rule 11.2.1.2.1-5: +12V_AUX shall be bussed among all slots in the backplane and be brought out on suitable connectors or connection points. Refer to connector current load limits in [VITA 46.0]. [VM = A]

Rule 11.2.1.2.1-6: P1-VBAT shall be bussed among all slots in the backplane and be brought out on suitable connectors or connection points. [VM = I]

11.2.1.2.2 SYS_CON*

There are general requirements concerning SYS_CON* in Section 3.4.1.

Rule 11.2.1.2.2-1: There shall be a method for optionally pulling the SYS_CON* low for all slots, including any Switch Slots. [VM = I]

Rule 11.2.1.2.2-2: SYS_CON* shall be pulled low for one and only one slot. [VM = I]

11.2.1.2.3 NVMRO

Rule 11.2.1.2.3-1: NVMRO shall be bussed among all slots in the backplane and be brought out on suitable connectors or connection points. [VM = I]

Recommendation 11.2.1.2.3-1: The backplane should have a jumper that can be used to ground NVMRO. [VM = I]

Observation 11.2.1.2.3-1: The jumper of Recommendation 11.2.1.2.3-1 can be used to drive NVMRO for cases where there is no other chassis level control, rather than requiring a module to drive it.

11.2.1.2.4 Other Utility Plane Signals

There are general requirements concerning system control signals in Section 3.4 and system clocks in Section 3.5.

The following Rules are for Utility Plane signals that are bussed on the backplane:

Rule 11.2.1.2.4-1: SYSRESET* shall be bussed among all slots in the backplane and be brought out on suitable connectors or connection points. [VM = I]


Rule 11.2.1.2.4-2: SM[3:0] shall each be bussed among all slots in the backplane and be brought out on suitable connectors or connection points. [VM = I]

Rule 11.2.1.2.4-3: REF_CLK-/+ shall be bussed among all slots in the backplane. [VM = I]

Rule 11.2.1.2.4-4: AUX_CLK-/+ shall be bussed among all slots in the backplane. [VM = I]

Rule 11.2.1.2.4-5: GDiscrete1 shall be bussed among all slots in the backplane. [VM = I]

The following Rules are for Utility Plane signals that are not bussed:

Rule 11.2.1.2.4-6: GAP* and GA[4:0] shall be wired to indicate physical slot numbers, with the numbers going from 1 thru N, where N is the number of slots (including both Payload and Switch Slots). Note: The physical slot numbers can be different from the logical Slot numbers in this document. [VM = I]

Rule 11.2.1.2.4-7: P1-G7 / J1-i7 is a reserved signal. It shall not be routed to anything by the backplane. [VM = I]

Rule 11.2.1.2.4-8: The User Defined pins J1-i9, J1-i11, and J1-i13 shall not be bussed unless the particular Backplane Profile specifically calls it out. [VM = I]


11.2.2 16-Slot — BKP6-CEN16-11.2.2-n (14 Payload + 2 Switch)

These Backplane Profiles are intended for a development environment. Some systems might be able to deploy with these backplanes. It is expected that many deployed systems will not use RTMs (Rear Transition Modules); instead the I/O signals that these Backplane Profiles route to RTMs would be routed, via the backplane, to connectors. For more on RTMs, see Section 4.4. Note: It is up to the RTM implementation whether it connects to these signals and what is done with them.

Figure 11.2.2-1 and Figure 11.2.2-2 give an overview of the topology. The dotted lines, from the Switch Slots, are signals that are available to RTMs.

The remainder of this Section gives detail Rules for these Backplane Profiles. Table 11.2.2-1 gives requirements that can vary among the Backplane Profiles of this section, such as channel baud rate and slot pitch. The Slot Profiles include the definition of what connectors are used. The RTM connectors are explicitly specified by this table because they are part of the Backplane Profile that is not specified by the Slot Profiles.

VPX1

VPX2

VPX3

VPX4

VPX5

VPX6

VPX7

VPX10

VPX11

VPX12

VPX13

VPX14

VPX15

VPX16

VPX8

VPX9

Utility PlaneIncludes Power

ManagementPlane (IPMB)

Control Plane(UTP)

Data Plane(FP)

ExpansionPlane(DFP)

Payload Slots Payload SlotsSwitch/

Management

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

ChMCIPMC IPMC IPMC IPMC IPMC IPMC IPMC IPMC IPMC IPMC IPMC IPMC IPMC IPMCChMC

DataSwitch

DataSwitch

ContrlSwitch

ContrlSwitch

Slot numbers are logical, physical slot numbers may be different

TP

FP

UTP

FP

Figure 11.2.2-1 Topology of BKP6-CEN16-11.2.2-n


Expansion Plane lanes Payloadslots of 16-slot backplane(DFP = 8 lanes)

Type A Slot 2

EP(7:0)

EP(15:8)

Type B Slot 1

EP(7:0)

EP(15:8)

Type B Slot 3

EP(7:0)

EP(15:8)

Type ASlot 5

EP(7:0)

EP(15:8)

Type BSlot 4

EP(7:0)

EP(15:8)

Type BSlot 6

EP(7:0)

EP(15:8)

Type C Slot 7

EP(7:0)

EP(15:8)

Type C Slot 10

EP(7:0)

EP(15:8)

Type A Slot 12

EP(7:0)

EP(15:8)

Type BSlot 11

EP(7:0)

EP(15:8)

Type B Slot 13

EP(7:0)

EP(15:8)

Type A Slot 15

EP(7:0)

EP(15:8)

Type BSlot 14

EP(7:0)

EP(15:8)

Type B Slot 16

EP(7:0)

EP(15:8)

Figure 11.2.2-2 Expansion Plane Lanes of BKP6-CEN16-11.2.2-n

Table 11.2.2-1 Backplane Profiles BKP6-CEN16-11.2.2-n

Profile name

Mechanical Slot Profiles and Section Channel Gbaud Rate

Pitch (in)

RTM Conn Payload Switch

Control Plane

Data Plane

Expan- sion

Plane

BKP6-CEN16-11.2.2-1 1.0 VITA 46.10

SLT6-PAY-

4F1Q2U2T-10.2.1

SLT6-SWH-

20U19F-10.4.1

1.25 3.125 5.0

BKP6-CEN16-11.2.2-2 1.0 VITA 46.10

SLT6-PAY-

4F1Q2U2T-10.2.1

SLT6-SWH-

20U19F-10.4.1

1.25 5.0 5.0

BKP6-CEN16-11.2.2-3 1.0 VITA 46.10

SLT6-PAY-

4F1Q2U2T-10.2.1

SLT6-SWH-

20U19F-10.4.1

1.25 6.25 5.0


Permission 11.2.2.1-1: The Slot numbers specified are logical. Physical implementations of this Backplane Profile may change the order of the slots from the numbering used in this document.

Rule 11.2.2.1-1: Slots 1 thru 7 and 10 thru 16 shall be Payload Slots using the Slot Profile specified in Table 11.2.2-1, for the particular Backplane Profile. [VM = I]

Rule 11.2.2.1-2: Slots 8 and 9 shall be Switch Slots using the Slot Profile specified in Table 11.2.2-1, for the particular Backplane Profile. [VM = I]



For requirements concerning the Utility Plane, see 11.2.1.2.

11.2.2.2.1 SYS_CON*

Rule 11.2.2.2.1-1: By default, physical slot 1 shall be the slot that has SYS_CON* pulled low. [VM = I]


Refer to Figure 11.2.2-1.

Rule 11.2.2.3-1: Each Switch Slot shall have its Control Plane inter-switch ports CSutp01 thru CSutp04 connected to the other Switch Slot, complying with the Rules of Section 7.2.1. [VM = I]

Rule 11.2.2.3-2: Each Payload Slot shall have its Control Plane Port CPutp01 connected to Switch Slot 8, one of ports CPutp01 thru CPutp14, complying with the Rules of Section 7.2.1. [VM = I]


Rule 11.2.2.3-4: Each Switch Slot shall have its Control Plane ports CPutp15 and CPutp16 available on RTM connectors on the rear of the backplane. [VM = I]

Observation 11.2.2.3-1: The Switch Slot Profile has the single-ended pins on P5/J5 and P6/J6 as User Defined with a suggested use of Control Plane Thin Pipes. These Thin Pipes are shown in Figure 11.2.2-1, although they are shown connected to the Control Plane, they could be used for something else.

Permission 11.2.2.3-1: With the Switch Slots, which Payload Slot Port connects to which Switch Slot Port may be jumbled. In other words, there is not a requirement to connect particular ports of a Switch Slot to particular Payload Slots.

Observation 11.2.2.3-2: Not requiring particular Payload Slots to connect to particular Switch Slot ports can make backplane routing easier.

Permission 11.2.2.3-2: The ports on the Switch Slots that a particular Payload Slot connects to may be different. For example, slot 2 might connect to Port CPutp05 of one Switch and Port CPutp07 of the other Switch Slot.

Rule 11.2.2.3-5: Each Control Plane channel for a Backplane Profile name listed in Table 11.2.2-1 shall comply with the baud rate specified in the Channel Gbaud Rate column. [VM = T,A]


11.2.2.4 Data Plane


Rule 11.2.2.4-1: Each Switch Slot shall have its Data Plane inter-switch port DS01 thru DS04 connected to the other Switch Slot, complying with the Rules of Section 7.2.1. [VM = I]

Rule 11.2.2.4-2: Each Payload Slot shall have its Data Plane Port DP01 connected to Switch Slot 8, one of ports DP01 thru DP14, complying with the Rules of Section 7.2.1. [VM = I]


Recommendation 11.2.2.4-1: Payload Slot 1 should have its Data Plane Port DP01 connected to DP01 of Switch Slot 8, complying with the Rules of Section 7.2.1. [VM = I]


Observation 11.2.2.4-1: If the Data Plane is to be PCIe, there needs to be a place for a Root Complex. Recommendation 11.2.2.4-1 and Recommendation 11.2.2.4-2 make it so that if a Switch Module puts an upstream port on its DP01, Slot 1 can be a Root Complex, in spite of Permission 11.2.2.4-1 and Permission 11.2.2.4-2.

Rule 11.2.2.4-4: Each Switch Slot shall have its Data Plane port DP15 available on RTM connectors on the rear of the backplane. [VM = I]

Rule 11.2.2.4-5: As shown in Figure 11.2.2-1, with the exception of the first Payload Slot, each slot shall have Data Plane port DP03 connected to DP04 of the next lower numbered Payload Slot, complying with the Rules of Section 7.2.1. [VM = I]

Rule 11.2.2.4-6: As shown in Figure 11.2.2-1, with the exception of the last Payload Slot, each Payload Slot shall have Data Plane Fat Pipe port DP04 connected to DP03 of the next higher numbered Payload Slot, complying with the Rules of Section 7.2.1. [VM = I]

Permission 11.2.2.4-1: With the Switch Slots, which Payload Slot Port connects to which Switch Slot Port may be jumbled, as long as the above Rules are met.


Permission 11.2.2.4-2: The ports on the Switch Slots that a particular Payload Slot connects to may be different. For example, slot 2 might connect to Port DP05 of one Switch Slot and Port DP07 of the other Switch Slot.

Rule 11.2.2.4-7: Each Data Plane channel for a Backplane Profile name listed in Table 11.2.2-1 shall comply with the baud rate specified in the Channel Gbaud Rate column. [VM = T,A]



Figure 11.2.2-2 shows how the Expansion Plane interconnects Payload Slots. With the exception of slots 7 and 10, the slots are in groups of 3, with the center one of each group of 3 being a Type A slot. The slot types are as follows:

• Type A — If some Plug-In Modules have two ports and others only have one, it is intended that the Type A slots be used by the Modules with two ports.

• Type B — If some Plug-In Modules have only one port as opposed to two, it is intended that the Type B slots be used by Modules with a single port. The topology is such that if a Type B slot has a single port Module, the single port connects to a Type A slot. Type B slots can also be used by modules with 2 ports. It is intended that if there is a mix of 2-port and 1-port modules that the 2-port modules go into type A slots first then if there are any leftover 2-port modules they go into Type B or C slots.

• Type C — Type C are slots that did not fit into the pattern of the groups of three. With Type C slots, if a single-port module is put into a Type C slot, it will not have a direct connection to a Type A slot.

For the Rules regarding where the Ports can be, see Section 10.2.1.4. For Rules regarding which ports are used, when only a subset of the ports are used, see Section 6.2.2. The following are Rules for this particular set of Backplane Profiles:

Rule 11.2.2.5-1: Slots 2, 5, 12, and 15 shall be Type A slots. [VM = I]

Rule 11.2.2.5-2: Slots 1, 3, 4, 6, 11, 13, 14, and 16 shall be Type B slots. [VM = I]

Rule 11.2.2.5-3: Slots 7 and 10 shall be Type C slots. [VM = I]

Rule 11.2.2.5-4: Each Type A Slot shall have Expansion Plane Lanes EP(7:0) connected to Lanes EP(7:0) of the next lower Payload Slot, complying with the Rules of Section 7.2.1. [VM = I]

Rule 11.2.2.5-5: Each Type A Slot shall have Expansion Plane Lanes EP(15:8) connected to Lanes EP(7:0) of the next higher Payload Slot, complying with the Rules of Section 7.2.1. [VM = I]

Rule 11.2.2.5-6: Slots 7 and Slot 10 shall connect to each other using Lanes EP(7:0), complying with the Rules of Section 7.2.1. [VM = I]

Rule 11.2.2.5-7: Slots 6 and 7 shall connect to each other using Lanes EP(15:8), complying with the Rules of Section 7.2.1. [VM = I]

Rule 11.2.2.5-8: Slots 10 and 11 shall connect to each other using Lanes EP(15:8). [VM = I]

Suggestion 11.2.2.5-1: It is suggested that Slot 1, Lanes EP(15:8), be made available on RTM connectors on the rear of the backplane.



Rule 11.2.2.5-9: Each Expansion Plane channel for a Backplane Profile name listed in Table 11.2.2-1 shall comply with the baud rate specified in the channel Gbaud rate column. [VM = T,A]


Rule 11.2.2.6-1: The pins of each Slot Profile that are User Defined shall be available on RTM connectors on the rear of the backplane. [VM = I]

Observation 11.2.2.6-1: User Defined pins that are following a suggested use, such as 2 Control Plane Thin Pipes on the single-ended pins of P5/J5 and P6/J6 of Switch Slots, are still User Defined pins and are therefore made available on the rear of the backplane for RTM connections.

11.2.2.7 Slot Pitch

Rule 11.2.2.7-1: Each Backplane Profile shown in Table 11.2.2-1 shall comply with the slot pitch listed in the corresponding slot pitch column. [VM = I]



These Backplane Profiles requires a chassis that is either too large for a 19” rack or is 0.8” pitch. At the time of this writing neither of these is included in the Standard Development Chassis Profiles, in this document.




VPX1

VPX2

VPX3

VPX4

VPX5

VPX6

VPX7

VPX8

VPX9

VPX12

VPX13

VPX14

VPX15

VPX16

VPX17

VPX18

VPX19

VPX20

VPX10

VPX11



Control Plane(UTP)

Data Plane(FP)

ExpansionPlane(DFP)


Management

ContrlPlane

DataPlane

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataSwitch

IPMC ChMCIPMC IPMC IPMC IPMC IPMC IPMC IPMC IPMC IPMC IPMC IPMC IPMC IPMC IPMC IPMC IPMC IPMCChMC

DataSwitch

ContrlSwitch

ContrlSwitch


TP

TP




Type A Slot 2

EP(7:0)

EP(15:8)

Type B Slot 1

EP(7:0)

EP(15:8)

Type BSlot 3

EP(7:0)

EP(15:8)

Type A Slot 5

EP(7:0)

EP(15:8)

Type BSlot 4

EP(7:0)

EP(15:8)

Type B Slot 6

EP(7:0)

EP(15:8)

Type A Slot 8

EP(7:0)

EP(15:8)

Type B Slot 7

EP(7:0)

EP(15:8)

Type BSlot 9

EP(7:0)

EP(15:8)

Type ASlot 13

EP(7:0)

EP(15:8)

Type B Slot 12

EP(7:0)

EP(15:8)

Type B Slot 14

EP(7:0)

EP(15:8)

Type A Slot 16

EP(7:0)

EP(15:8)

Type B Slot 15

EP(7:0)

EP(15:8)

Type B Slot 17

EP(7:0)

EP(15:8)

Type A Slot 19

EP(7:0)

EP(15:8)

Type BSlot 18

EP(7:0)

EP(15:8)

Type BSlot 20

EP(7:0)

EP(15:8)



Profile name


Pitch (in)


Control Plane

Data Plane

Expan- sion

Plane

BKP6-CEN20-11.2.3-1 1.0 VITA 46.10

SLT6-PAY-

4F1Q2U2T-10.2.1

SLT6-SWH-

20U19F-10.4.1

1.25 3.125 5.0

BKP6-CEN20-11.2.3-2 1.0 VITA 46.10

SLT6-PAY-

4F1Q2U2T-10.2.1

SLT6-SWH-

20U19F-10.4.1

1.25 5.0 5.0

BKP6-CEN20-11.2.3-3 1.0 VITA 46.10

SLT6-PAY-

4F1Q2U2T-10.2.1

SLT6-SWH-

20U19F-10.4.1

1.25 6.25 5.0

BKP6-CEN20-11.2.3-4 0.8 VITA 46.10

SLT6-PAY-

4F1Q2U2T-10.2.1

SLT6-SWH-

20U19F-10.4.1

1.25 3.125 5.0

BKP6-CEN20-11.2.3-5 0.8 VITA 46.10

SLT6-PAY-

4F1Q2U2T-10.2.1

SLT6-SWH-

20U19F-10.4.1

1.25 5.0 5.0

BKP6-CEN20-11.2.3-6 0.8 VITA 46.10

SLT6-PAY-

4F1Q2U2T-10.2.1

SLT6-SWH-

20U19F-10.4.1

1.25 6.25 5.0








11.2.3.2.1 SYS_CON*




Rule 11.2.3.3-1: Each Switch Slot shall have its Control Plane inter-switch port CSutp01 thru CSutp02 connected to the other Switch Slot, complying with the Rules of Section 7.2.1. [VM = I]

Rule 11.2.3.3-2: Each Payload Slot shall have its Control Plane Port CPutp01 connected to Switch Slot 10, one of ports CPutp01 thru CPutp16 or CSutp03 thru CSutp04, complying with the Rules of Section 7.2.1. [VM = I]

Rule 11.2.3.3-3: Each Payload Slot shall have its Control Plane Port CPutp02 connected to Switch Slot 11, one of ports CPutp01 thru CPutp16 or CSutp03 thru CSutp04, complying with the Rules of Section 7.2.1. [VM = I]


Permission 11.2.3.3-1: With the Switch Slots, which Payload Slot Port connects to which Switch Slot Port may be “jumbled”. In other words, there is not a requirement to connect particular ports of a Switch Slot to particular Payload Slots.





11.2.3.4 Data Plane


Rule 11.2.3.4-1: Each Switch Slot shall have its Data Plane inter-switch port DS01 connected to the other Switch Slot, complying with the Rules of Section 7.2.1. [VM = I]

Rule 11.2.3.4-2: Each Payload Slot shall have its Data Plane Port DP01 connected to Switch Slot 10, one of DP01 thru DP15 or DS02 thru DS04, complying with the Rules of Section 7.2.1. [VM = I]

Rule 11.2.3.4-3: Each Payload Slot shall have its Data Plane Port DP02 connected Switch Slot 11, one of DP01 thru DP15 or DS02 thru DS04, complying with the Rules of Section 7.2.1. [VM = I]












Figure 11.2.3-2 shows how the Expansion Plane interconnects Payload Slots. The slots are in groups of 3, with the center one of each group of 3 being a Type A Slot. The slot types are as follows:





Rule 11.2.3.5-1: Slots 2, 5, 8, 13, 16, and 19 shall be Type A slots. [VM = I]

Rule 11.2.3.5-2: Slots 1, 3, 4, 6, 7, 9, 12, 14, 15, 17, 18, and 20 shall be Type B slots. [VM = I]



Rule 11.2.3.5-5: Adjacent Type B Slots shall connect to each other using Expansion Plane Lanes EP(15:8), complying with the Rules of Section 7.2.1. [VM = I]

Rule 11.2.3.5-6: Slots 9 and 12 shall connect to each other using Expansion Plane Lanes EP(15:8), complying with the Rules of Section 7.2.1. [VM = I]








11.2.3.7 Slot Pitch





Figure 11.2.4-1 and Figure 11.2.4-2 give an overview of the topology. The dotted lines, from the Switch Slot, are signals that are available to RTMs. This backplane is very much like a smaller version of the 16-slot backplane of Section 11.2.2.

VPX1

VPX2

VPX3

VPX4

VPX5

VPX7

VPX8

VPX9

VPX10

VPX6



Control Plane(UTP)

Data Plane(FP)

ExpansionPlane(DFP)

PayloadSlots

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

DataPlane

DataPlane

DataPlane

DataPlane

ChMCIPMC IPMC IPMC IPMC IPMC IPMC IPMC IPMC IPMC

DataSwitch

ContrlSwitch

Switch/Management

PayloadSlotsSlot numbers

are logical, physical slot numbers may be different

TP

FP

UTP




Type A Slot 2

EP(7:0)

EP(15:8)

Type B Slot 1

EP(7:0)

EP(15:8)

Type BSlot 3

EP(7:0)

EP(15:8)

Type A Slot 5

EP(7:0)

EP(15:8)

Type B Slot 4

EP(7:0)

EP(15:8)

Type B Slot 7

EP(7:0)

EP(15:8)

Type ASlot 9

EP(7:0)

EP(15:8)

Type B Slot 8

EP(7:0)

EP(15:8)

Type B Slot 10

EP(7:0)

EP(15:8)




Profile name


Pitch (in)


Control Plane

Data Plane

Expan- sion

Plane

BKP6-CEN10-11.2.4-1 1.0 VITA 46.10

SLT6-PAY-

4F1Q2U2T-10.2.1

SLT6-SWH-

20U19F-10.4.1

1.25 3.125 5.0

BKP6-CEN10-11.2.4-2 1.0 VITA 46.10

SLT6-PAY-

4F1Q2U2T-10.2.1

SLT6-SWH-

20U19F-10.4.1

1.25 5.0 5.0

BKP6-CEN10-11.2.4-3 1.0 VITA 46.10

SLT6-PAY-

4F1Q2U2T-10.2.1

SLT6-SWH-

20U19F-10.4.1

1.25 6.25 5.0





Rule 11.2.4.1-2: Slot 6 shall be a Switch Slot using the Slot Slots using the Slot Profile specified in Table 11.2.4-1, for the particular Backplane Profile. [VM = I]



11.2.4.2.1 SYS_CON*




Rule 11.2.4.3-1: Each Payload Slot shall have its Control Plane Ports CPutp01 and CPutp02 connected to the Switch Slot, two of ports CPutp01 thru CPutp16 or CSutp03 thru CSutp04, complying with the Rules of Section 7.2.1. [VM = I]

Permission 11.2.4.3-1: With the Switch Slots, which Payload Slot Port connects to which Switch Slot Port may be jumbled.


Rule 11.2.4.3-2: Each Switch Slot shall have its Control Plane inter-switch ports CSutp01 and CSutp02 available on RTM connectors on the rear of the backplane. [VM = I]

Observation 11.2.4.3-2: The inter-switch ports of the Control Plane Switch Slot are run to the RTM because in some cases they might be stacking ports (e.g. Ethernet Switch stacking ports). Given that there are not inter-switch connections, these ports are run to RTM connectors in case stacking ports are to be used for inter-chassis connections.




11.2.4.4 Data Plane


Rule 11.2.4.4-1: Each Payload Slot shall have its Data Plane Ports DP01 and DP02 connected to the Switch Slot, two of DP01 thru DP15 or DS02 thru DS04, complying with the Rules of Section 7.2.1. [VM = I]

Rule 11.2.4.4-2: Payload Slot 1 shall have one of its Data Plane Ports DP01 thru DP02 connected to DP01 of Switch Slot 6, complying with the Rules of Section 7.2.1. [VM = I]

Observation 11.2.4.4-1: If the Data Plane is to be PCIe, there needs to be a place for a Root Complex. Rule 11.2.4.4-2 makes it so that if a Switch Module puts an upstream port on its DP01, Slot 1 can be a Root Complex, in spite of Permission 11.2.4.4-1.



Rule 11.2.4.4-3: Switch Slot Data Plane port DS01 shall be available on RTM connectors on the rear of the backplane. [VM = I]

Observation 11.2.4.4-3: The inter-switch port of the Data Plane Switch Slot is run to the RTM because in some cases it might be stacking ports (e.g. Ethernet Switch stacking ports). Given that there are not inter-switch connections, this port is run to RTM connectors in case stacking ports are to be used for inter-chassis connections.





Figure 11.2.4-2 shows how the Expansion Plane interconnects Payload Slots. The slots are in groups of 3, with the center one of each group of 3 being a Type A slot. The slot types are as follows:






Rule 11.2.4.5-1: Slots 2, 5, and 9 shall be Type A slots. [VM = I]

Rule 11.2.4.5-2: Slots 1, 3, 4, 7, 8, and 10 shall be Type B slots. [VM = I]


Rule 11.2.4.5-4: Each Type A Slot shall have Expansion Plane Lanes EP(15:8) connected to Lanes EP(7:0) of the next higher Payload Slot, complying with the Rules of Section 7.2.1. In the case of Slot 5, the next higher Payload Slot is 7, because Slot 6 is a Switch Slot. [VM = I]

Rule 11.2.4.5-5: Adjacent Type B Slots shall connect to each other using Expansion Plane Lanes EP(15:8), complying with the Rules of Section 7.2.1. [VM = I]








11.2.4.7 Slot Pitch




These Backplane Profiles are intended for a development environment. Some systems might be able to deploy with these backplanes. Figure 11.2.5-1 and Figure 11.2.5-2 give an overview of the topology. The dotted lines, from the Switch Slot, are signals that are available to an RTM (Rear Transition Module).

VPX1

VPX2

VPX3

VPX4

VPX5



Control Plane(UTP)

Data Plane(FP)

ExpansionPlane(DFP)

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

DataPlane

DataPlane

DataPlane

DataPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ChMCIPMC IPMC IPMC IPMC

DataSwitch

ContrlSwitch

Switch/Management

PayloadSlotsSlot numbers

are logical, physical slot numbers may be different

UTP

UTP

TP

FP



Expansion Plane lanes Payload slots of 5-slot backplane(DFP = 8 lanes)

Type ASlot 2

EP(7:0)

EP(15:8)

Type B Slot 1

EP(7:0)

EP(15:8)

Type B Slot 3

EP(7:0)

EP(15:8)

Type C Slot 4

EP(7:0)

EP(15:8)


It is expected that many deployed systems not use RTMs; instead the I/O signals that these Backplane Profiles route to RTMs would be routed, via the backplane, to connectors. For more on RTMs, see Section 4.4. Note: It is up to the RTM implementation whether it connects to these signals and what is done with them.

This backplane has some similarities to the 10-slot backplane of Section 11.2.4 key differences are:

• The number of Payload Slots is reduced from 9 to 4.

• With each Payload Slot, all 4 Data Plane Ports connect to the Switch Slot, instead of just 2.

• The Switch Slot Profile is SLT6-SWH-16U20F-10.4.2 instead of SLT6-SWH-20U19F-10.4.1.




Profile name


Pitch (in)


Control Plane

Data Plane

Expan- sion

Plane

BKP6-CEN05-11.2.5-1 1.0 VITA 46.10

SLT6-PAY-

4F1Q2U2T-10.2.1

SLT6-SWH-

16U20F-10.4.2

1.25 3.125 5.0

BKP6-CEN05-11.2.5-2 1.0 VITA 46.10

SLT6-PAY-

4F1Q2U2T-10.2.1

SLT6-SWH-

16U20F-10.4.2

1.25 5.0 5.0

BKP6-CEN05-11.2.5-3 1.0 VITA 46.10

SLT6-PAY-

4F1Q2U2T-10.2.1

SLT6-SWH-

16U20F-10.4.2

1.25 6.25 5.0



Rule 11.2.5.1-1: Slots 1 thru 4 shall be Payload Slots using the Slot Profile specified in Table 11.2.5-1, for the particular Backplane Profile. [VM = I]

Rule 11.2.5.1-2: Slot 5 shall be a Switch Slot using the Slot Profile specified in Table 11.2.5-1, for the particular Backplane Profile. [VM = I]



11.2.5.2.1 SYS_CON*





Rule 11.2.5.3-1: Each of the Switch Slot ports CPutp01 thru CPutp04 shall connect to each of the Payload Slots using either Payload Slot port CPutp01 or CPutp02 (the Switch Slot connects to the same port on all 4 Payload Slots, using this group of 4 Switch Slot ports), complying with the Rules of Section 7.2.1. [VM = I]

Rule 11.2.5.3-2: Each of the Switch Slot ports CPutp05 thru CPutp08 shall connect to each of the Payload Slots using either Payload Slot port CPutp01 or CPutp02 (the Switch Slot connects to the same port on all 4 Payload Slots, using this group of 4 Switch Slot ports), complying with the Rules of Section 7.2.1. [VM = I]



Rule 11.2.5.3-3: Switch Slot Control Plane ports CSutp01 thru CSutp04 and CPutp09 thru CPutp12 shall be available on RTM connectors on the rear of the backplane. [VM = I]

Observation 11.2.5.3-2: The inter-switch ports are run to the RTM because in some cases they might be stacking ports (e.g. Ethernet Switch stacking ports). Given that there are not inter-switch connections, these ports are run to RTM connectors in case stacking ports are to be used for inter-chassis connections.

Observation 11.2.5.3-3: Other than the lowest 4 ports of the Control Plane Switch Slot, it is the highest numbered ports that are run to the RTM, so that a Switch Module that does not have all the ports populated, can be used.



11.2.5.4 Data Plane


Rule 11.2.5.4-1: Each of the Switch Slot ports DP01 thru DP04 shall connect to each of the 4 Payload Slots using one of Payload Slot Ports DP01 thru DP04 (the Switch Slot connects to the same port on all 4 Payload Slots, using this group of 4 Switch Slot ports), complying with the Rules of Section 7.2.1. [VM = I]









Rule 11.2.5.4-6: Switch Slot Data Plane ports DS01 thru DS04 shall be available on RTM connectors on the rear of the backplane. [VM = I]

Observation 11.2.5.4-3: The inter-switch ports are to the RTM because in some cases they might be stacking ports (e.g. Ethernet Switch stacking ports). Given that there are not inter-switch connections, these ports are run to RTM connectors in case stacking ports are to be used for inter-chassis connections.



Figure 11.2.5-2 shows how the Expansion Plane interconnects Payload Slots. The slots are in a single group of 3 with slot 2 being a Type A slot plus one left over slot. The slot types are as follows:






Rule 11.2.5.5-1: Slot 2 shall be a Type A slot. [VM = I]



Rule 11.2.5.5-4: Slot 3 Expansion Plane Lanes EP(15:8) shall connect to Slot 4 Expansion Plane Lanes EP(7:0), complying with the Rules of Section 7.2.1. [VM = I]








11.2.5.7 Slot Pitch




These Backplane Profiles are intended for a development environment. Some systems might be able to deploy with these backplanes. These backplanes are very similar to the 10-slot backplanes of Section 11.2.4 with the primary exception that this one has dual data and control switches. It is expected that many deployed systems not use RTMs; instead the I/O signals that these Backplanes Profile route to RTMs would be routed, via the backplane, to connectors. For more on RTMs, see Section 4.4. Note: It is up to the RTM implementation whether it connects to these signals and what is done with them.


VPX1

VPX2

VPX3

VPX4

VPX7

VPX8

VPX9

VPX10

VPX5

VPX6

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

DataPlane

DataPlane

DataPlane

DataPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

DataPlane

DataPlane

DataPlane

DataPlane

ChMCIPMC IPMC IPMC IPMC IPMC IPMC IPMC IPMCChMC

DataSwitch

DataSwitch

ContrlSwitch

ContrlSwitch

TP

TP

TP

TP

FP

FP

FP

FP



Control Plane(UTP)

Data Plane(FP)

ExpansionPlane(DFP)


Payloadslots

Switch/Management

Payloadslots




The remainder of this Section gives detail Rules for these Backplane Profiles. Table 11.2.6-1 gives requirements that can vary among the Backplane Profiles of this section, such as channel baud rate and slot pitch.


Profile name


Pitch (in)


Control Plane

Data Plane

Expan- sion

Plane

BKP6-CEN10-11.2.6-1 1.0 VITA 46.10

SLT6-PAY-

4F1Q2U2T-10.2.1

SLT6-SWH-

16U20F-10.4.2

1.25 3.125 5.0

BKP6-CEN10-11.2.6-2 1.0 VITA 46.10

SLT6-PAY-

4F1Q2U2T-10.2.1

SLT6-SWH-

16U20F-10.4.2

1.25 5.0 5.0

BKP6-CEN10-11.2.6-3 1.0 VITA 46.10

SLT6-PAY-

4F1Q2U2T-10.2.1

SLT6-SWH-

16U20F-10.4.2

1.25 6.25 5.0




Rule 11.2.6.1-2: Slot 5 and 6 shall be a Switch Slot using the Slot Profile specified in Table 11.2.6-1, for the particular Backplane Profile. [VM = I]


Type B Slot 4

EP(7:0)

EP(15:8)

Type B Slot 7

EP(7:0)

EP(15:8)

Type A Slot 8

EP(7:0)

EP(15:8)

Type B Slot 2

EP(7:0)

EP(15:8)

Type C Slot 1

EP(7:0)

EP(15:8)

Type A Slot 3

EP(7:0)

EP(15:8)

Type B Slot 9

EP(7:0)

EP(15:8)

Type C Slot 10

EP(7:0)

EP(15:8)




11.2.6.2.1 SYS_CON*









Permission 11.2.6.3-3: Unused Switch Slot ports, CPutp09 thru CPutp12, may either be made available for connection to an RTM or be left as no connects.





11.2.6.4 Data Plane


Rule 11.2.6.4-1: Each Payload Slot shall have its Data Plane Ports DP01 and DP02 connected to Switch Slot 5, to two of the Switch Slot Ports DP01 thru DP16, complying with the Rules of Section 7.2.1. [VM = I]




Observation 11.2.6.4-1: If the Data Plane is to be PCIe, there needs to be a place for a Root Complex. Rule 11.2.6.4-3 and Rule 11.2.6.4-4 make it so that if a Switch Module puts an upstream port on its DP01, Slot 1 can be a Root Complex, in spite of Permission 11.2.6.4-1 and Permission 11.2.6.4-2.


Observation 11.2.6.4-2: Not requiring particular Payload Slots to connect to particular ports of a Switch Slot to particular Payload Slots.


Rule 11.2.6.4-5: Switch Slot Data Plane ports DS01 and DS02 shall be used for inter-switch connections, complying with the Rules of Section 7.2.1. [VM = I]

Rule 11.2.6.4-6: Switch Slot Data Plane ports DS03 and DS04 shall be available on RTM connectors on the rear of the backplane. [VM = I]



Figure 11.2.6-2 shows how the Expansion Plane interconnects Payload Slots. The slots are in groups of 3, with the center one of each group of 3 labeled as a Type A Slot. The slot types are as follows:






Rule 11.2.6.5-1: Slots 3 and 8 shall be Type A slots. [VM = I]

Rule 11.2.6.5-2: Slots 2, 4, 7, and 9 shall be Type B slots. [VM = I]




Rule 11.2.6.5-6: Slots 4 and 7 shall connect to each other using Expansion Plane Lanes EP(15:8), complying with the Rules of Section 7.2.1. [VM = I]










11.2.6.7 Slot Pitch




These Backplane Profiles are intended for a development environment. Some systems might be able to deploy with these backplanes. These backplanes are very similar to the 10-slot backplanes of Section 11.2.6 with the key differentiator that the Control Plane is not wired in theses backplanes. If there is an Control Plane Switch, it is external. It is expected that many deployed systems not use RTMs; instead the I/O signals that this Backplane Profile routes to RTMs would be routed, via the backplane, to connectors. For more on RTMs, see Section 4.4. Note: It is up to the RTM implementation whether it connects to these signals and what is done with them.

Figure 11.2.7-1 gives an overview of the topology. The dotted lines, from the Payload and Switch Slots, are signals that are available to RTMs.

VPX1

VPX2

VPX3

VPX4

VPX7

VPX8

VPX9

VPX10

VPX5

VPX6

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

ChMCIPMC IPMC IPMC IPMC IPMC IPMC IPMC IPMCChMC

DataSwitch

DataSwitch

FP

FP

FP

FP



Control Plane(TP)

Data Plane(FP)


Payloadslots

Switch/Management

Payloadslots

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

20 TPs





Profile name


Pitch (in)

RTM Conn Payload Switch Data Plane

BKP6-CEN10-11.2.7-1 1.0 VITA

46.10 SLT6-PAY-4F2T-

10.2.2 SLT6-SWH-24F-10.4.3 3.125

BKP6-CEN10-11.2.7-2 1.0 VITA


10.2.2 SLT6-SWH-24F-10.4.3 5.0

BKP6-CEN10-11.2.7-3 1.0 VITA


10.2.2 SLT6-SWH-24F-10.4.3 6.25




Rule 11.2.7.1-2: Slot 5 and 6 shall be a Switch Slot using the Slot Profile specified in Table 11.2.7-1, for the particular Backplane Profile. [VM = I]



11.2.7.2.1 SYS_CON*



Refer to Figure 11.2.7-1

Rule 11.2.7.3-1: Each Payload Slot and Switch slot shall have its Control Plane Ports CPtp01 and CPtp02 available on RTM connectors on the rear of the backplane. [VM = I]



Observation 11.2.7.3-2: The Thin Pipes, as shown in Figure 11.2.7-1, depicted by dashed lines are signals available on RTM connectors on the rear of the backplane. These signals and how they are connected externally is beyond the scope of this specification.

Rule 11.2.7.3-2: ***Deleted***This Rule was assigned in error, it does not apply. Each Control Plane channel for a Backplane Profile name listed in Table 11.2.7-1 shall comply with the baud rate specified in the Channel Gbaud Rate column. [VM = T,A]

11.2.7.4 Data Plane





Rule 11.2.7.4-4: Payload Slot 1 shall have one of its Data Plane Port DP03 thru DP04 connected to DP01 of Switch Slot 6, complying with the Rules of Section 7.2.1. [VM = I]



Observation 11.2.7.4-2: Not requiring particular Payload Slots to connect to particular ports of a Switch Slot to particular Payload Slots.


Permission 11.2.7.4-3: Unused Switch Slot ports, DP17 thru DP20, may either be made available for connection to an RTM or be left as no connects.








11.2.7.6 Slot Pitch




These Backplane Profiles are intended for a development environment. It is expected that many deployed systems will not use RTMs (Rear Transition Module); instead the I/O signals that these Backplane Profiles route to RTMs would be routed, via the backplane, to connectors. For more on RTMs, see Section 4.4. Note: It is up to the RTM implementation whether it connects to these signals and what is done with them. Some systems might be able to deploy with these backplanes. These backplanes are very similar to the 10-slot backplanes of Section 11.2.7 with the key differentiator that:

• the second switch slot is replaced with a payload slot;

• the number of Payload Slots is reduced from 8 to 5; and,

• all 4 Payload Slot Fat Pipes, in the Data Plane, are connected to a single switch slot.


VPX1

VPX2

VPX3

VPX4

VPX6



Control Plane(TP)

Data Plane(FP)

DataPlane

DataPlane

DataPlane

DataPlane

IPMC

DataSwitch

Switch/Management

Payloadslots

VPX5

DataPlane

FPFPFPFP

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane 12 TPs

ContrlPlane







Profile name


Pitch (in)


BKP6-CEN06-11.2.8-1 1.0 VITA 46.10

SLT6-PAY-4F2T-

10.2.2

SLT6-SWH-24F-

10.4.3 3.125

BKP6-CEN06-11.2.8-2 1.0 VITA 46.10

SLT6-PAY-4F2T-

10.2.2

SLT6-SWH-24F-

10.4.3 5.0

BKP6-CEN06-11.2.8-3 1.0 VITA 46.10

SLT6-PAY-4F2T-

10.2.2

SLT6-SWH-24F-

10.4.3 6.25







11.2.8.2.1 SYS_CON*








11.2.8.4 Data Plane


Rule 11.2.8.4-1: Each Payload Slot shall have its Data Plane Ports DP01 thru DP04 connected to the Switch Slot, to four of Switch Slot Ports DP01 thru DP20, complying with the Rules of Section 7.2.1. [VM = I]





Rule 11.2.8.4-3: Switch Slot Data Plane ports DS01 thru DS04 shall be available on RTM connectors on the rear of the backplane. [VM = I]

Observation 11.2.8.4-3: The inter-switch ports are to the RTM because in some cases they might be stacking ports (e.g. Ethernet Switch stacking ports). Given that there are not inter-switch connections, these ports are run to RTM connectors in case stacking ports are to be used for inter-chassis connections.






11.2.8.6 Slot Pitch




These Backplane Profiles are intended for a development environment. Some systems might be able to deploy with these backplanes. These backplanes are very similar to the 6-slot backplane of Section 11.2.8 with a mirror image of the configuration between slot 6 and 7 axis and the data switches are connected using 2 Fat Pipes. Figure 11.2.9-1 gives an overview of the topology. The dotted lines, from the Payload and Switch Slots, are signals that are available to RTMs. It is expected that many deployed systems will not use RTMs (Rear Transition Module); instead the I/O signals that these Backplane Profiles route to RTMs would be routed via the backplane, to connectors. For more on RTMs, see Section 4.4. Note: It is up to the RTM implementation whether it connects to these signals and what is done with them.

VPX1

VPX2

VPX3

VPX4

VPX5

VPX8

VPX9

VPX10

VPX11

VPX12

VPX6

VPX7

Payload slots Payload slotsSwitch/

Management

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

ChMCIPMC IPMC IPMC IPMC IPMC IPMC IPMC IPMC IPMC IPMCChMC

DataSwitch

DataSwitch

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

FP

FP

FP

FP




Control Plane(TP)

Data Plane(FP)

ContrlPlane

ContrlPlane 24 TPs





Profile name


Pitch (in)


Data Plane

BKP6-CEN12-11.2.9-1 1.0 VITA

46.10

SLT6-PAY-4F2T-

10.2.2.

SLT6-SWH-24F-

10.4.3 3.125

BKP6-CEN12-11.2.9-2 1.0 VITA

46.10

SLT6-PAY-4F2T-

10.2.2

SLT6-SWH-24F-

10.4.3 5.0

BKP6-CEN12-11.2.9-3 1.0 VITA

46.10

SLT6-PAY-4F2T-

10.2.2

SLT6-SWH-24F-

10.4.3 6.25



Rule 11.2.9.1-1: Slots 1 thru 5 and 8 thru 12 shall be Payload Slots using the Slot Profile specified in Table 11.2.9-1, for the particular Backplane Profile Slot Profile. [VM = I]

Rule 11.2.9.1-2: Slot 6 and 7 shall be a Switch Slot using the Slot Profile specified in Table 11.2.9-1, for the particular Backplane Profile Slot Profile. [VM = I]


For requirements concerning the Utility Plane, see Section 11.2.1.2.

11.2.9.2.1 SYS_CON*









11.2.9.4 Data Plane


Rule 11.2.9.4-1: Each Payload Slot shall have its Data Plane Ports DP01 and DP02 connected to Switch Slot 6, to two of Switch Slot Ports DP01 thru DP20, complying with the Rules of Section 7.2.1. [VM = I]

Rule 11.2.9.4-2: Each Payload Slot shall have its Data Plane Ports DP03 and DP04 connected to Switch Slot 7, to two of Switch Slot Ports DP01 thru DP20, complying with the Rules of Section 7.2.1. [VM = I]














11.2.9.6 Slot Pitch



11.2.10 6-Slot — BKP6-DIS06-11.2.10-n (5 Payload + 1 Switch)

These Backplane Profiles are intended for a development environment. Some systems might be able to deploy with this backplane. It is expected that many deployed systems will not use RTMs (Rear Transition Module); instead the I/O signals that these Backplane Profiles route to RTMs would be routed via the backplane, to connectors. For more on RTMs, see Section 4.4. Note: It is up to the RTM implementation whether it connects to these signals and what is done with them. This backplane contains 5 Payload Slots and 1 Control Plane Switch Slot in a distributed 5-Slot mesh in which each slot is directly connected to every other payload slot. Figure 11.2.10-1 gives an overview of the topology. The dotted lines, from the Switch Slot, are signals that are available to RTMs.

VPX1

VPX2

VPX3

VPX4

VPX6



Control Plane(TP)

Data Plane(FP)

IPMC

Switch/Management

Payloadslots

VPX5

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

FPFPFPFP

TPTP

TPTP

CntrlSwitch

ContrlPlane



DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

Figure 11.2.10-1 Topology of BKP6-DIS06-11.2.10-n


The remainder of this Section gives detailed Rules for these Backplane Profiles. Table 11.2.10-1 gives requirements that can vary among the Backplane Profiles of this section, such as channel baud rate and slot pitch.

Table 11.2.10-1 Backplane Profiles BKP6-DIS06-11.2.10-n

Profile name


Pitch (in)


Control Plane

Data Plane

BKP6-DIS06-11.2.10-1 1.0 VITA

46.10 SLT6-PAY-4F2T-10.2.2

SLT6-SWH-4F24T-10.4.4 1.25 3.125

BKP6-DIS06-11.2.10-2 1.0 VITA

46.10 SLT6-PAY-4F2T-10.2.2

SLT6-SWH-4F24T-10.4.4 1.25 5.0

BKP6-DIS06-11.2.10-3 1.0 VITA

46.10 SLT6-PAY-4F2T-10.2.2

SLT6-SWH-4F24T-10.4.4 1.25 6.25



Rule 11.2.10.1-1: Slots 1 thru 5 shall be Payload Slots using the Slot Profile specified in Table 11.2.10-1, for the particular Backplane Profile Slot Profile. [VM = I]

Rule 11.2.10.1-2: Slot 6 shall be a Switch Slot using the Slot Profile specified in Table 11.2.10-1, for the particular Backplane Profile Slot Profile. [VM = I]



11.2.10.2.1 SYS_CON*





Rule 11.2.10.3-1: Each Payload Slot shall have its Control Plane Ports CPtp01 and CPtp02 connected to the Control Switch, using Switch Ports CPtp5 thru CPtp14, complying with the Rules of Section 7.2.2. [VM = I]

Permission 11.2.10.3-1: With the Switch Slots, which Payload Slot or Switch Slot Port connects to which Switch Port may be jumbled.


Permission 11.2.10.3-2: Unused Switch Slot ports, CPtp15 thru CPtp24, may either be made available for connection to an RTM or be left as no connects.

Rule 11.2.10.3-2: The Control Switch, 4 Thin Pipe Ports, CPtp01 thru CPtp04, shall be available on RTM connectors on the rear of the backplane. [VM = I]

Rule 11.2.10.3-3: The Control Switch, 4 Fat Pipes CP01 thru CP04 shall be available on RTM connectors on the rear of the backplane. [VM = I]

Observation 11.2.10.3-2: CP01 thru CP04 of the Control Switch are intended to be used as stacking ports. Given that there are not inter-switch connections, these ports are run to RTM connectors in case stacking ports are to be used for inter-chassis connections.




11.2.10.4 Data Plane


Table 11.2.10-2 Data Plane Connection BKP6-DIS06-11.2.10-n Slot/

Channel DP01 DP02 DP03 DP04 1

5-Sl

ot M

esh

C

lust

er 1

VPX02-DP01 VPX03-DP01 VPX04-DP01 VPX05-DP01

2 VPX01-DP01 VPX03-DP02 VPX04-DP02 VPX05-DP02




Rule 11.2.10.4-1: Each Payload Slot shall have its Data Plane Ports DP01 thru DP04 connected as described by Table 11.2.10-2, complying with the Rules of Section 7.2.1. [VM = I]





11.2.10.6 Slot Pitch



11.2.11 17-Slot — BKP6-HYB17-11.2.11-n (12 Payload + 3 VME + 2 Switch)

These Backplane Profiles are intended for a development environment. Some systems might be able to deploy with these backplanes. It is expected that many deployed systems will not use RTMs (Rear Transition Module); instead the I/O signals that these Backplane Profiles route to RTMs would be routed via the backplane, to connectors. For more on RTMs, see Section 4.4. Note: It is up to the RTM implementation whether it connects to these signals and what is done with them. This backplane contains a hybrid topology with 3 VME Payload Slots, 12 VPX Payload Slots, and 2 Control Switch Slots. This topology contains three 4-Slot Mesh Clusters.

There are 2 types of VPX Payload Slots. The first uses a VME [VITA 46.1] as an Parallel Bus; while, the second has no Parallel Bus. Figure 11.2.11-1 depicts both types of VPX Payload Slots. The first is represented in Slots 4 thru 7 and the second type in Slots 8 thru 15. In this topology the first cluster within in the 4-Slot Mesh Clusters uses the VME based Parallel BUS; while the other 2 clusters do not.

VME1

VME2

VME3

VPX4

VPX6



Control Plane(TP)

Data Plane(FP)

Switch/Management

PayloadSlots

VPX5

ContrlPlane

CntrlSwitch

ContrlPlane


ChMCIPMC IPMC

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

VPX7

VPX8

VPX9

VPX10

VPX11

VPX12

VPX13

VPX14

VPX15

VPX16

VPX17

CntrlSwitch

IPMC IPMC IPMC IPMC IPMC IPMC IPMC IPMC IPMC IPMC ChMC

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

VMESlots

Expansion Plane(46.1)

VME VME VME VME46.1

VME46.1

VME46.1

VME46.1

BridgeSlots

TP

TP

Figure 11.2.11-1 Topology of BKP6-HYB17-11.2.11-n


The remainder of this Section gives detail Rules for these Backplane Profiles. Table 11.2.11-1 gives requirements that can vary among the Backplane Profiles of this section, such as channel baud rate and slot pitch. Figure 11.2.11-1 gives an overview of the topology. The dotted lines, from the Payload and Switch Slots, are signals that are available to RTMs.

Table 11.2.11-1 Backplane Profiles BKP6-HYB17-11.2.11-n

Profile name

Mechanical VPX Slot Profiles and Section Channel Gbaud

Rate

Pitch (in)

RTM Conn

Bridge Slots 4 - 7

Payload Slots 8 - 15

Switch Slots 16, 17 Data Plane

BKP6-HYB17-11.2.11-1 1.0 VITA

46.10

SLT6-BRG-4F1V2T-

10.5.1

SLT6-PAY-4F2T-10.2.2

SLT6-SWH-4F24T-10.4.4

3.125

BKP6-HYB17-11.2.11-2 1.0 VITA

46.10

SLT6-BRG-4F1V2T-

10.5.1


SLT6-SWH-4F24T-10.4.4

5.0

BKP6-HYB17-11.2.11-3 1.0 VITA

46.10

SLT6-BRG-4F1V2T-

10.5.1


SLT6-SWH-4F24T-10.4.4

6.25

11.2.11.1 VPX Slot Profiles

Rule 11.2.11.1-1: Slots VPX 4 thru VPX 7 shall be Payload Slots using the Slot Profile specified in Table 11.2.11-1, for the particular Backplane Profile. [VM = I]

Rule 11.2.11.1-2: Slots VPX 8 thru VPX 15 shall be Payload Slots using the Slot Profile specified in Table 11.2.11-1, for the particular Backplane Profile. [VM = I]

Rule 11.2.11.1-3: Slot VPX 16 and VPX 17 shall be a Switch Slot using the Slot Profile specified in Table 11.2.11-1, for the particular Backplane Profile. [VM = I]


11.2.11.2 VME Slot Profiles

The intent of this backplane is to allow use of legacy VME Plug-in Modules that might be required because of their unique I/O capabilities.

Rule 11.2.11.2-1: Slots shall comply with [VITA 1.1] specification. [VM = I]


Rule 11.2.11.2-2: Slots VME 1 thru VME 3 slots shall be used by VME Plug-in Modules that can be configured to not provide the VME System Controller Function. [VM = I]

Permission 11.2.11.2-1: Although the backplane is wired for A32:D32 VME Plug-in Modules A24:D16 Plug-in Modules may be used. However care must be taken to insure compatibility is maintained between VME slots.

Observation 11.2.11.2-1: Ethernets on the VME Slots are connected via cables and the pins are beyond the scope of this document.



11.2.11.3.1 SYS_CON*

Rule 11.2.11.3.1-1: By default, the lowest numbered physical VPX slot shall be the slot that has SYS_CON* pulled low. [VM = I]

11.2.11.3.2 VME System Controller Function

Rule 11.2.11.3.2-1: The VME System Controller Function shall be in VPX Payload Slot 4. [VM = I]



Rule 11.2.11.4-1: Each Payload Slot shall have its Control Plane Ports CPtp01 and CPtp02 available on RTM connectors on the rear of the backplane. [VM = I]


Observation 11.2.11.4-2: All Payload Thin Pipes CPtp01, as shown in Figure 11.2.11-1, depicted by dashed lines can be routed to the Control Switch Slot 16 and connected to one of the Switch Slot ports CPtp03 thru CPtp17, using RTMs and external cables, to create half of a dual star topology.

Observation 11.2.11.4-3: All Payload Thin Pipes CPtp02, as shown in Figure 11.2.11-1, depicted by dashed lines can be routed to Control Switch Slot 17 and connected to one of the Switch Slot ports CPtp03 thru CPtp17, using RTMs and external cables, to create half of a dual star topology.

Rule 11.2.11.4-2: The Control Switches shall have Control Plane Ports CPtp01 thru CPtp017 made available on RTM connectors on the rear of the backplane. [VM = I]


Rule 11.2.11.4-3: The Control Switches shall use the lowest 2 Thin Pipes Ports, CPtp01 thru CPtp02, for inter-switch connections. [VM = I]

Permission 11.2.11.4-1: Unused Switch Slot ports, CPtp18 thru CPtp24, may either be made available for connection to an RTM or be left as no connects.

Rule 11.2.11.4-4: The Control Switches, 4 Fat Pipes CP01 thru CP04 shall be available on RTM connectors on the rear of the backplane. . [VM = I]

Observation 11.2.11.4-4: CP01 thru CP04 of the Control Switch are intended to be used as stacking ports. Given that there are not inter-switch connections, these ports are run to RTM connectors in case stacking ports are to be used for inter-chassis connections.




Table 11.2.11-2 Data Plane Connection BKP6-HYB17-11.2.11-n Slot/


4-Sl

ot M

esh

C

lust

er 1





8

4-Sl

ot M

esh

C

lust

er 2





12

4-Sl

ot M

esh

Clu

ster

3









Rule 11.2.11.6-1: The pins of each Slot Profile that are User Defined shall be available on RTM connectors on the rear of the backplane. [VM = I, T]





11.2.12 8-Slot — BKP6-HYB08-11.2.12-n (1 Payload + 3 Peripheral + 1 VME Bridge + 3 VME)

These Backplane Profiles are intended for a development environment. Some systems might be able to deploy with these backplanes. It is expected that many deployed systems will not use RTMs; instead the I/O signals that these Backplane Profiles route to RTMs would be routed, via the backplane, to connectors. For more on RTMs, see Section 4.4. Note: It is up to the RTM implementation whether it connects to these signals and what is done with them. Figure 11.2.12-1 gives an overview of the topology. The intent is to provide a development environment that can be used with legacy VME boards as well as current OpenVPX compatible modules.

The remainder of this Section gives detailed Rules for the these Backplane Profiles. Table 11.2.12-1 gives requirements that are independent of the topology, such as channel baud rate and slot pitch.

VME6

VME7

VPX4

VPX5

VPX2

VPX3

VPX1

DataPlane

DataPlane

DataPlane

DataPlane

DataPlaneData Plane

(FP)

VME SlotsVPX Peripherial Slots

IPMC IPMC IPMC IPMCChMCSystem

ManagementPer VITA 46.11

Utility PlaneIncluding Power

VME BusSlot VPX 5 per VITA 46.1Slots VME 1-3 per VITA 1-1994 (R2002)

VME8

Payload

Slot Bridge

SlotSlot numbers are logical, physical slot numbers may be different




Profile name

Mechanical

VPX Slot Profiles and Section Channel Gbaud Rate VPX 1 VPX 2 - 4 VPX 5

Pitch (in)

RTM Conn Payload Peripheral Bridge Data Plane

BKP6-HYB08-11.2.12-1 1.0 VITA

46.10 SLT6-PAY-8F-

10.2.3 SLT6-PER-2F-10.3.2

SLT6-BRG-4F1V-10.5.2 3.125

BKP6-HYB08-11.2.12-2 1.0 VITA

46.10 SLT6-PAY-8F-

10.2.3 SLT6-PER-2F-10.3.2

SLT6-BRG-4F1V-10.5.2 5.0

BKP6-HYB08-11.2.12-3 1.0 VITA

46.10 SLT6-PAY-8F-

10.2.3 SLT6-PER-2F-10.3.2

SLT6-BRG-4F1V-10.5.2 6.25



Rule 11.2.12.1-1: Slot VPX 1 shall be Payload Slot using the Slot Profile specified in Table 11.2.12-1, for the particular Backplane Profile. [VM = I]

Permission 11.2.12.1-2: A Plug-In Module that complies with a Switch Module Profile may be used in slot VPX 1, provided the pipes that are present are compatible with this Back plane Profile.

Rule 11.2.12.1-2: Slots VPX 2 thru VPX 4 shall be Peripheral Slots using the Slot Profile specified in Table 11.2.12-1, for the particular Backplane Profile. [VM = I]

Rule 11.2.12.1-3: Slots VPX 5 shall be Bridge Slot using the Slot Profile specified in Table 11.2.12-1, for the particular Backplane Profile. [VM = I]



Rule 11.2.12.2-1: Slots shall comply with [VITA 1.1] specification. [VM = I]

Rule 11.2.12.2-2: Slots VME 6 thru VME 8 slots shall be used by VME Plug-in Modules that can be configured to not provide the VME System Controller Function. [VM = I]





Observation 11.2.12.3-1: Some differences between VME based Plug-in Modules and VITA 65 Utility Plane signaling might be observed.

11.2.12.3.1 SYS_CON*

Rule 11.2.12.3.1-1: By default, VPX 1 shall be the slot that has SYS_CON* pulled low. [VM = I]


Observation 11.2.12.3.2-1: With this Backplane Profile, the location of the VME System Controller function is left up to the system integrator. A possible location is on a Plug-In Module in the Bridge Slot but there are other alternatives that might be implemented.


Rule 11.2.12.4-1: Payload Slot VPX 1 ports DP01 and DP02 shall be routed as a single Double Fat Pipe to Peripheral Slot VPX 2 ports DP01 and DP02, complying with the Rules of Section 7.2.1. [VM = I]



Rule 11.2.12.4-4: Payload Slot VPX 1 ports DP07 and DP08 shall be routed as a single Double Fat Pipe to Bridge Slot VPX 5 ports DP01 and DP02, complying with the Rules of Section 7.2.1. [VM = I]

Rule 11.2.12.4-5: The Slot VPX 5 shall use the first two Data Plane Pipe DP01 and DP02 the two remaining Fat Pipes shall be left no connect to the backplane. [VM = I]

Observation 11.2.12.4-1: Routing as Double Fat Pipes, as indicated above, will insure proper wiring for use both by Modules with two Fat Pipes and Modules with a single Dual Fat Pipe.



11.2.13 9-Slot — BKP6-CEN09-11.2.13-n (1 Payload + 8 Peripheral)

These Backplane Profiles are intended for a development environment. Some systems might be able to deploy with these backplanes. It is expected that many deployed systems will not use RTMs; instead the I/O signals that these Backplane Profiles route to RTMs would be routed, via the backplane, to connectors. For more on RTMs, see Section 4.4. Note: It is up to the RTM implementation whether it connects to these signals and what is done with them.

Figure 11.2.13-1 gives an overview of the topology.

The remainder of this Section gives detailed Rules for these Backplane Profiles. Table 11.2.13-1 gives requirements that are independent of the topology, such as channel baud rate and slot pitch. The Slot Profiles include the definition of what connectors are used. The RTM connectors are explicitly specified by this table because they are part of the Backplane Profile that is not specified by the Slot Profiles.

VPX1

VPX2

VPX3

VPX4

VPX5

VPX6

VPX7

VPX8

VPX9



Data Plane(FP)

Peripheral slots

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

IPMC IPMC IPMC IPMC IPMC IPMCChMC IPMC IPMC

Payload





Profile name

Mechanical Slot Profiles and Section Channel

Gbaud Rate VPX 1 VPX 2 - 9

Pitch (in)

RTM Conn Payload Payload or Peripheral Data Plane

BKP6-CEN06-11.2.13-1 1.0 VITA

46.10 SLT6-PAY-8F-10.2.3 SLT6-PER-2F-10.3.2 2.5

BKP6-CEN06-11.2.13-2 1.0 VITA

46.10 SLT6-PAY-8F-10.2.3 SLT6-PER-2F-10.3.2 5.0

BKP6-CEN06-11.2.13-3 1.0 VITA

46.10 SLT6-PAY-8F-10.2.3 SLT6-PER-2F-10.3.2 6.25

Note: This is an 8 Fat Pipe Backplane. With the Slots using SLT6-PER-2F-10.3.2, only the first Fat Pipe will be connected to VPX 1.




Permission 11.2.13.1-2: A Plug-In Module that complies with a Switch Module Profile may be used in slot VPX 1, provided the pipes that are present are compatible with this Backplane Profile.




11.2.13.2.1 SYS_CON*




Rule 11.2.13.3-1: VPX 1 Payload Slot shall have its Data Plane Ports DP01 connected to DP01 Port of Peripheral Slot VPX 2, complying with the Rules of Section 7.2.1. [VM = I]








Rule 11.2.13.3-9: Any other Data Planes not called out here shall be left No Connect. [VM = I]

Rule 11.2.13.3-10: Each Data Plane channel for a Backplane Profile name listed in Table 11.2.13-1 shall comply with the baud rate specified in the Channel Gbaud Rate column. [VM = T]







These Backplane Profiles are intended for a development environment. Some systems might be able to deploy with these backplanes. It is expected that many deployed systems will not use RTMs; instead the I/O signals that these Backplane Profiles route to RTMs would be routed via the backplane, to connectors. For more on RTMs, see Section 4.4. Note: It is up to the RTM implementation whether it connects to these signals and what is done with them.

Figure 11.2.14-1 gives an overview of the topology. The remainder of this Section gives detailed Rules for these Backplane Profiles.


VPX1

VPX2

VPX3

VPX4

VPX5

VPX6



Data Plane(FP)

Peripheral slots

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

IPMC IPMC IPMC IPMC ChMCIPMC

Payload



Table 11.2.14-1 gives requirements that can vary among the Backplane Profiles of this section, such as channel baud rate and slot pitch. The Slot Profiles include the definition of what connectors are used. The RTM connectors are explicitly specified by this table because they are part of the Backplane Profile that is not specified by the Slot Profiles.


Profile name



Pitch (in)


BKP6-CEN06-11.2.14-1 1.0 VITA

46.10 SLT6-PAY-8F-10.2.3 SLT6-PER-2F-10.3.2 2.5

BKP6-CEN06-11.2.14-2 1.0 VITA

46.10 SLT6-PAY-8F-10.2.3 SLT6-PER-2F-10.3.2 5.0

BKP6-CEN06-11.2.14-3 1.0 VITA

46.10 SLT6-PAY-8F-10.2.3 SLT6-PER-2F-10.3.2 6.25






Observation 11.2.14.1-1: Slot VPX 6 is wired only to the Utility Plane and is available for development of System / Chassis Management solutions. No specific Slot Profile was available at the time of this release so a SLT6-PER-2F-10.3.2 Profile is called out with the Data Plane NOT connected on the backplane.

11.2.14.2 Utility Plane



11.2.14.2.1 SYS_CON*







Rule 11.2.14.3-5: Slot 6 shall have its Data Plane ports DP01 and DP02 not routed in the backplane. [VM = I]

Rule 11.2.14.3-6: Slot 6 shall have its Data Plane ports DP01 and DP02 available on RTM connectors on the rear of the backplane. [VM = I]

Observation 11.2.14.3-1: Routing as Double Fat Pipes, as indicated above, will insure proper wiring for use both by Modules with two Fat Pipes and Modules with a single Dual Fat Pipe.

Observation 11.2.14.3-2: Slot 6 is intended for development of chassis management solutions and does not connect the Peripheral Slot Profile Data Plane Ports to the Backplane.

Observation 11.2.14.3-3: With Slot 6, the combination of Rule 11.2.14.3-5 and Rule 11.2.14.4-1 require that all the slot’s pins be available on RTM connectors on the rear of the backplane.

Observation 11.2.14.3-4: It is not necessary that both Data Plane Ports be used on each Peripheral just as it is not necessary that all Slots be filled.




These Backplane Profiles are intended for a development environment. Some systems might be able to deploy with these backplanes. It is expected that many deployed systems will not use RTMs (Rear Transition Module); instead the I/O signals that these Backplane Profiles route to RTMs would be routed, via the backplane, to connectors. For more on RTMs, see Section 4.4. Note: It is up to the RTM implementation whether it connects to these signals and what is done with them. These backplanes contain 5 Payload Slots and 1 Control Plane Switch Slot in a distributed 5-Slot mesh in which each slot is directly connected to every other payload slot. These backplanes are very similar to the 6-Slot backplane of Section 11.2.10 with the key differentiator that the Control Plane signals are made available to the RTM for external cabling. Figure 11.2.15-1 gives an overview of the topology. The dotted lines, from the Payload and Switch Slots, are signals that are available to RTMs.

VPX1

VPX2

VPX3

VPX4

VPX6



Control Plane(TP)

Data Plane(FP)

IPMC

Switch/Management

Payloadslots

VPX5

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

FPFPFPFP

TPTP

TPTP

CntrlSwitch

ContrlPlane



DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

5 TP

5 TP





Profile name


Pitch (in)


Data Plane

BKP6-DIS06-11.2.15-1 1.0 VITA

46.10 SLT6-PAY-4F2T-10.2.2

SLT6-SWH-4F24T-10.4.4 3.125

BKP6-DIS06-11.2.15-2 1.0 VITA

46.10 SLT6-PAY-4F2T-10.2.2

SLT6-SWH-4F24T-10.4.4 5.0

BKP6-DIS06-11.2.15-3 1.0 VITA

46.10 SLT6-PAY-4F2T-10.2.2

SLT6-SWH-4F24T-10.4.4 6.25






11.2.15.2.1 SYS_CON*





Observation 11.2.15.3-1: The Switch Slot Profile has the single-ended pins on P5/J5 and P6/J6 as User Defined with a suggested use of Control Plane Thin Pipes. These Thin Pipes


are shown in Figure 11.2.15-1, although they are shown connected to the Control Plane, they could be used for something else.


Observation 11.2.15.3-3: All Thin Pipes CPtp01 and CPtp02, as shown in Figure 11.2.15-1, depicted by dashed lines can be routed to the Control Switch 6 and connected to two of the Switch Slot ports CPtp05 thru CPtp014 .



Rule 11.2.15.3-4: The Control Switch shall have its 4 Fat Pipe Ports, CP01 thru CP04, available on RTM connectors on the rear of the backplane. [VM = I]

Permission 11.2.15.3-1: Unused Switch Slot ports, CPtp15 thru CPtp24, may either be available for connection to an RTM or be left as no connects.

Observation 11.2.15.3-4: CP01 thru CP04 of the Control Switch are to be used as stacking ports. Given that there are not inter-switch connections, these ports are run to RTM connectors in case stacking ports are to be used for inter-chassis connections.





5-Sl

ot M

esh

C

lust

er 1








11.2.16 5-Slot — BKP6-DIS05-11.2.16-n (5 Payload)

These Backplane Profiles are intended for a development environment. Some systems might be able to deploy with these backplanes. It is expected that many deployed systems will not use RTMs (Rear Transition Module); instead the I/O signals that these Backplane Profiles route to RTMs would be routed, via the backplane, to connectors. For more on RTMs, see Section 4.4. Note: It is up to the RTM implementation whether it connects to these signals and what is done with them. This backplane contains 5 Payload Slots in a distributed 5-Slot mesh, in which each slot is directly connected to every other payload slot. These backplanes are very similar to the 6-Slot backplane of Section 11.2.10 with the key differentiator that there is no Control Plane and the removal of the Switch Slot. Figure 11.2.16-1 gives an overview of the topology.

VPX1

VPX2

VPX3

VPX4



Data Plane(FP)

IPMC

Payloadslots

VPX5


ChMCIPMC IPMC IPMC

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane





Profile name

Mechanical Slot Profiles and

Section Channel

Gbaud Rate

Pitch (in)

RTM Conn Payload

Data Plane

BKP6-DIS05-11.2.16-1 1.0 VITA

46.10 SLT6-PER-4F-

10.3.1 3.125

BKP6-DIS05-11.2.16-2 1.0 VITA

46.10 SLT6-PER-4F-

10.3.1 5.0

BKP6-DIS05-11.2.16-3 1.0 VITA

46.10 SLT6-PER-4F-

10.3.1 6.25



Observation 11.2.16.1-1: Although this SLT6-PER-4F-10.3.1 is a Peripheral Slot in name, the use by this Backplane Profile is more in line with that of a Payload Slot Profile, so the text refers to the slots as Payload Slots.



11.2.16.2.1 SYS_CON*







5-Sl

ot M

esh

C

lust

er 1















Figure 11.2.17-1 and Figure 11.2.17-2 give an overview of the topology. The dotted lines, from the Switch Slots and the two end Payload Slots, are signals that are available to RTMs.


VPX1

VPX2

VPX3

VPX4

VPX5

VPX6

VPX7

VPX10

VPX11

VPX12

VPX13

VPX14

VPX15

VPX16

VPX8

VPX9



Control Plane(UTP)

Data Plane(FP)

ExpansionPlane(QFP)


Management

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

IPMC IPMC IPMC IPMC IPMC IPMC IPMC IPMC IPMC IPMC IPMC IPMC IPMC IPMC

DataSwitch

DataSwitch

ContrlSwitch

ContrlSwitch


TP

FP

UTP

FP

QFP

ChMC ChMC



Expansion Plane lanes Payloadslots of 16-slot backplane(QFP = 16 lanes)EP(15:0) on P2EP(31:16) on P5

Type A Slot 2

EP(15:0)

EP(31:16)

Type B Slot 1

EPclock1

EP(31:16)

AXreset1

EP(15:0)

AXreset2

EPclock2

AXreset1

EPclock1

AXreset2

EPclock2

Type B Slot 3

EPclock1

EP(31:16)

AXreset1

EP(15:0)

AXreset2

EPclock2

Type A Slot 5

EP(15:0)

EP(31:16)

Type B Slot 4

EPclock1

EP(31:16)

AXreset1

EP(15:0)

AXreset2

EPclock2

AXreset1

EPclock1

AXreset2

EPclock2

Type B Slot 6

EPclock1

EP(31:16)

AXreset1

EP(15:0)

AXreset2

EPclock2

Type C Slot 7

Eclock1

EP(31:16)

AXreset1

EP(15:0)

AXreset2

EPclock2

Type A Slot 12

EP(15:0)

EP(31:16)

Type B Slot 11

EPclock1

EP(31:16)

AXreset1

EP(15:0)

AXreset2

EPclock2

AXreset1

EPclock1

AXreset2

EPclock2

Type B Slot 13

EPclock1

EP(31:16)

AXreset1

EP(15:0)

AXreset2

EPclock2

Type A Slot 15

EP(15:0)

EP(31:16)

Type B Slot 14

EPclock1

EP(31:16)

AXreset1

EP(15:0)

AXreset2

EPclock2

AXreset1

EPclock1

AXreset2

EPclock2

Type B Slot 16

EPclock1

EP(31:16)

AXreset1

EP(15:0)

AXreset2

EPclock2

Type C Slot 10

EPclock1

EP(31:16)

AXreset1

EP(15:0)

AXreset2

EPclock2



Profile name


Pitch (in)


Control Plane

Data Plane

Expansion Plane

Lanes Clocks

BKP6-CEN16-11.2.17-1 1.0 VITA

46.10

SLT6-PAY-4F2Q2U2T-

10.2.7

SLT6-SWH-20U19F-10.4.1 1.25 3.125 5.0 1.25

BKP6-CEN16-11.2.17-2 1.0 VITA

46.10

SLT6-PAY-4F2Q2U2T-

10.2.7

SLT6-SWH-20U19F-10.4.1 1.25 5.0 5.0 1.25

BKP6-CEN16-11.2.17-3 1.0 VITA

46.10

SLT6-PAY-4F2Q2U2T-

10.2.7

SLT6-SWH-20U19F-10.4.1 1.25 6.25 5.0 1.25








11.2.17.2.1 SYS_CON*







Rule 11.2.17.3-4: Each Switch Slot shall have its Control Plane ports CPutp15 and CPutp16 available on RTM connectors on the rear of the backplane. [VM = I]


Permission 11.2.17.3-1: With the Switch Slots, which Payload Slot Port connects to which Switch Slot Port may be jumbled. In other words, there is not a requirement to connect particular ports of a Switch Slot to particular Payload Slots.







Rule 11.2.17.4-1: Each Switch Slot shall have its Data Plane inter-switch port DS01 thru DS04 connected to the other Switch Slot, complying with the Rules of Section 7.2.1. [VM = I]






Rule 11.2.17.4-4: Each Switch Slot shall have its Data Plane port DP15 available on RTM connectors on the rear of the backplane. [VM = I]









Figure 11.2.17-2 shows how the Expansion Plane interconnects Payload Slots. With the exception of slots 7 and 10, the slots are in groups of 3, with the center one of each group of 3 being a Type A slot. The slot types are as follows:




For the Rules regarding where the Ports can be, see Section 10.2.7.4. For Rules regarding which port is used, when only a subset of the ports are used, see Section 6.2.2. The following are Rules for this particular set of Backplane Profiles:

Rule 11.2.17.5-1: Slots 2, 5, 12, and 15 shall be Type A slots. [VM = I]

Rule 11.2.17.5-2: Slots 1, 3, 4, 6, 11, 13, 14, and 16 shall be Type B slots. [VM = I]





Rule 11.2.17.5-6: Slots 7 and Slot 10 shall connect to each other using Lanes EP(15:0), complying with the Rules of Section 7.2.1. [VM = I]


Rule 11.2.17.5-8: Slots 10 and 11 shall connect to each other using Lanes EP(31:16). [VM = I]




11.2.17.5.1 Expansion Plane Resets and Clocks


Rule 11.2.17.5.1-1: The rules of Section 5.3.2.2, which apply to Backplanes shall be followed. [VM = I]

Observation 11.2.17.5.1-1: Although the rules of Section 5.3.2.2, are intended to be for PCIe, other protocols can be used.

Rule 11.2.17.5.1-2: Each Type A Slot shall have AXreset1*, EPclock1-, and EPclock1+ connected to AXreset1*, EPclock1-, and EPclock1+, respectively, of the next lower Payload Slot. [VM = I]

Rule 11.2.17.5.1-3: Each Type A Slot shall have AXreset2*, EPclock2-, and EPclock2+ connected to AXreset1*, EPclock1-, and EPclock1+, respectively, of the next higher Payload Slot. [VM = I]

Rule 11.2.17.5-4: Slot 7 AXreset1*, EPclock1-, and EPclock1+ shall connect to slot 10 AXreset1*, EPclock1-, and EPclock1+, respectively. [VM = I]



Suggestion 11.2.17.5.1-1: It is suggested that Slot 1, AXreset2*, EPclock2- and EPclock2+, be made available on RTM connectors on the rear of the backplane.

Suggestion 11.2.17.5.1-2: It is suggested that Slot 16, AXreset2*, EPclock2- and EPclock2+, be made available on RTM connectors on the rear of the backplane.


Rule 11.2.17.5-7: Each Expansion Plane clock for a Backplane Profile name listed in Table 11.2.17-1 shall comply with the baud rate specified in the channel Gbaud rate column. [VM = T,A]







11.2.18 6-Slot — BKP6-DIS06-11.2.18-n (6 Payload)

These Backplane Profiles are intended for a development environment. Some systems might be able to deploy with these backplanes. It is expected that many deployed systems will not use RTMs (Rear Transition Module); instead the I/O signals that these Backplane Profiles route to RTMs would be routed, via the backplane, to connectors. For more on RTMs, see Section 4.4. Note: It is up to the RTM implementation whether it connects to these signals and what is done with them. Figure 11.2.18-1 and Figure 11.2.18-2 give an overview of the topology. The dotted lines, from the Payload Slots, are signals that are available to RTMs.


VPX1

VPX2

VPX3

VPX4

VPX6



Control Plane

Data Plane(FP = 4 lanes)

IPMC

Payloadslots

VPX5


IPMCIPMC IPMC IPMC IPMC

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

Exp. Plane

Exp. Plane

Exp. Plane

Exp. Plane

DataPlane

Expansion Plane (QFP = 16 lanes)

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

TP

TP

ContrlPlane

Exp. Plane

Exp. Plane

FP

QFP



Type A1 Slot 2

EP(15:0)

EP(31:16)

Type B Slot 1

EPclock1

EP(31:16)

Type BSlot 6

EP(15:0)

EP(31:16)

Type B2 Slot 4

EP(15:0)

EP(31:16)

Type B2Slot 3

EP(15:0)

EP(31:16)

Type A1Slot 5

EP(15:0)

EP(31:16)

AXreset1

EP(15:0)

AXreset2

EPclock2

AXreset1

EPclock1

AXreset2

EPclock2

AXreset2

EPclock2

AXreset1

EPclock1

AXreset1

EPclock1EPclock1

AXreset1

AXreset2 AXreset2

EPclock2EPclock2

AXreset2

EPclock2

AXreset1

EPclock1

Expansion Plane lanesPayload Slots of 6-slotbackplane(QFP = 16 lanes)EP(15:0) on P2EP(31:16) on P5

Figure 11.2.18-2 Expansion Plane Lanes of BKP6-DIS06-11.2.18-n


Profile name

Mechanical Slot Profiles and

Section Channel Gbaud Rate

Pitch (in)

RTM Conn Payload

Data Plane

Expansion Plane

Lanes Clocks

BKP6-DIS06-11.2.18-1 1.0 VITA

46.10 SLT6-PAY-

4F2Q2U2T-10.2.7 3.125 5.0 1.25

BKP6-DIS06-11.2.18-2 1.0 VITA

46.10 SLT6-PAY-

4F2Q2U2T-10.2.7 5.0 5.0 1.25

BKP6-DIS06-11.2.18-3 1.0 VITA

46.10 SLT6-PAY-

4F2Q2U2T-10.2.7 6.25 5.0 1.25





11.2.18.2.1 SYS_CON*






Recommendation 11.2.18.3-1: Each Payload Slot should have its Control Plane Ports CPupt01 and CPutp02 made available on RTM connectors on the rear of the backplane. [VM = I]





5-Sl

ot M

esh

C

lust

er 1






Rule 11.2.18.4-1: Each of Payload Slots 1 thru 5 shall have its Data Plane Ports DP01 thru DP04 connected as described by Table 11.2.18-2, complying with the Rules of Section 7.2.1. [VM = I]

Recommendation 11.2.18.4-1: Payload Slot 6 should have its Data Plane Ports DP01 thru DP04 made available on RTM connectors on the rear of the backplane. [VM = I]



Figure 11.2.18-2 shows how the Expansion Plane interconnects Payload Slots. The slots are in groups of 3, with the center one of each group of 3 being a Type A1 slot. The slot types are as follows:

• Type A1 — If some Plug-In Modules have two ports and others only have one, it is intended that the Type A1 slots be used by the Modules with two ports. The difference


between the Type A ports of earlier sections, like Section 11.2.17.5 and this section is that with Type A1, one of the ports is available to an RTM.

• Type B — If some Plug-In Modules have only one port as opposed to two, it is intended that the Type B or B2 slots be used by Modules with a single port. The topology is such that if a Type B slot has a single port Module, the single port connects to a Type A1 slot. Type B slots can also be used by modules with 2 ports. It is intended that if there is a mix of 2-port and 1-port modules that the 2-port modules go into type A1 slots first then if there are any leftover 2-port modules they go into Type B or B2 slots.

• Type B2 — Type B2 slots have all the Expansion Plane lanes available for RTM connections, instead of just the high lanes.

For the Rules regarding where the Ports can be, see Section 10.2.7.4. For Rules regarding which ports are used, when only a subset of the ports are used, see Section 6.2.2.

When the Expansion Plane protocol is PCIe, connections from EP(31:16), AXreset2*, and EPclock2 of slots 3 and 4 can be driven by external devices like PCs, by running a cable from an RTM to a PC. In such a case it is assumed that a Common PCIe Reference Clock would be used between the external PC and the Plug-In Module the PC connects to. Such a PC could be running SSC (Spread Spectrum Clock).

The abundance of Expansion Plane ports available to RTMs makes it possible to set up many different topologies, by using cables among the RTMs.

The following are Rules for this particular set of Backplane Profiles:



Rule 11.2.18.5-3: Slots 1 thru 6 shall make Lanes EP(31:16), available on RTM connectors on the rear of the backplane. [VM = I]

Rule 11.2.18.5-4: Slots 3 and 4 shall make Lanes EP(15:0), available on RTM connectors on the rear of the backplane. [VM = I]


11.2.18.5.1 Expansion Plane Resets and Clocks


Rule 11.2.18.5.1-1: The rules of Section 5.3.2.2, which apply to Backplanes shall be followed. [VM = I]

Observation 11.2.18.5.1-1: Although the rules of Section 5.3.2.2, are intended to be for PCIe, other protocols can be used.


Rule 11.2.18.5.1-2: Slot 1 AXreset1*, EPclock1-, and EPclock1+ shall connect to slot 2 AXreset1, EPclock1-, and EPclock1+, respectively. [VM = I]

Rule 11.2.18.5.1-3: Slot 2 AXreset2*, EPclock2-, and EPclock2+ shall connect to slot 3 AXreset1*, EPclock1-, and EPclock1+, respectively. [VM = I]

Rule 11.2.18.5.1-4: Slots 3 and 4 shall make AXreset2*, EPclock2-, and EPclock2+ available on RTM connectors on the rear of the backplane. [VM = I]



Rule 11.2.18.5.1-7: Slots 1 and 6 shall make AXreset2*, EPclock2-, and EPclock2+ available on RTM connectors on the rear of the backplane. [VM = I]

Rule 11.2.18.5.1-8: Each Expansion Plane clock for a Backplane Profile name listed in Table 11.2.18-1 shall comply with the baud rate specified in the channel Gbaud rate column. [VM = T,A]






11.2.19 9-Slot — BKP6-DIS09-11.2.19-n (9 payload)

These Backplane Profiles are intended for a development environment. Some systems might be able to deploy with this backplane. It is expected that many deployed systems will not use RTMs (Rear Transition Module); instead the I/O signals that these Backplane Profiles route to RTMs would be routed via the backplane, to connectors. For more on RTMs, see Section 4.4. Note: It is up to the RTM implementation whether it connects to these signals and what is done with them. This backplane contains 9 Payload Slots in a redundant distributed 9-Slot mesh in which each slot is directly connected to every other payload slot with 2 Fat Pipe Data Plane connections and 2 Ultra-thin Pipe Control Plane connections. This backplane topology is particularly suitable for compute intensive applications where each card may have multiple FPGAs with processing cores.

VPX1

VPX2

VPX3

VPX4

VPX5

VPX6

VPX7

VPX8

VPX9



Control Plane(UTP) (each line represents two Ultra-thin Pipes for illustration)

Data Plane(FP) (each line represents two Fat Pipes for illustration)

Payload Slots

IPMC IPMC IPMC IPMC IPMC IPMC IPMC


Data Plane

Data Plane

Data Plane

Data Plane

Data Plane

Data Plane

Data Plane

Data Plane

Data Plane

Contrl Plane

Contrl Plane

Contrl Plane

Contrl Plane

Contrl Plane

Contrl Plane

Contrl Plane

Contrl Plane

Contrl Plane

IPMC IPMC



The mesh topology allows any module to pass data on to another module in any order required for the application. In such full mesh implementations, there is typically no need for inter-switch connections to support such functions as fail-over or data coherency. The full mesh also allows cards to be configured to pass data to another slot when some slots may not be populated. Such systems probably do not dynamically change their routing path but are configured for the type of processing and the number of cards in the application. This meshed architecture allows specific data paths to be implemented by processing cards with minimal capability to switch I/O between ports on each card. Figure 11.2.19-1 gives an overview of the topology.



Profile name


Pitch (in)

RTM Conn Payload Slots

Control Plane

Data Plane

BKP6-DIS09-11.2.19-1 1.0 VITA

46.10 SLT6-SWH-16U16F-10.4.5 1.25 3.125

BKP6-DIS09-11.2.19-2 1.0 VITA

46.10 SLT6-SWH-16U16F-10.4.5 1.25 5.0

BKP6-DIS09-11.2.19-3 1.0 VITA

46.10 SLT6-SWH-16U16F-10.4.5 1.25 6.25



Rule 11.2.19.1-1: Slots 1 thru 9 shall be Payload Slots using the Slot Profile specified in Table 11.2.19-1, for the particular Backplane Profile Slot Profile. [VM = I]

11.2.19.2 Utility Plane — Pins on P0/J0 and SE of P1J1


11.2.19.2.1 SYS_CON*




Refer to Figure 11.2.19-1 and Table 11.2.19.3-1.

Rule 11.2.19.3-1: Each Payload Slot shall have its Control Plane Ports CSutp01 thru Csutp04 and CPutp01 thru Cputp12 connected to the Control Plane Ports in the other slots in accordance with Table 11.2.19.3-1 using Rules of Section 7.2.2. [VM = I]

Observation 11.2.19.3-1: The Payload slots have the single-ended pins on P2/J2 thru P6/J6 as User Defined


Observation 11.2.19.3-2: In this backplane CSutp01 thru CSutp04 are routed to payload slots. CSutp01 thru CSutp04 are serving the same function as CPutp01 thru CPutp12.

Rule 11.2.19.3-3: The UTP pairs that connect a pair of ports in one slot, with a pair of ports from another, shall be routed on the backplane, such that the UTP pair can be used as a single TP. [VM = I]


Table 11.2.19.3-1 Control Plane Connection BKP6-DIS09-11.2.19-n Slot/

Channel pairs

CSutp01, CSutp02

CSutp03, CSutp04

CPutp01, CPutp02

CPutp03, CPutp04

CPutp05, CPutp06

CPutp07, CPutp08

CPutp09, CPutp10

CPutp11, CPutp12

1 VPX02-CSutp01, CSutp02

VPX03-CSutp01, CSutp02







2 VPX01-CSutp01, CSutp02


VPX04- CSutp03, CSutp04






3 VPX01- CSutp03, CSutp04


VPX04-CPutp01, CPutp02

VPX05- CPutp01, CPutp02





4 VPX01- CPutp01, CPutp02


















































Rule 11.2.19.4-1: Each Payload Slot shall have its Data Switch Ports DS01 thru DS04 and its Data Plane Ports DP01 thru DP12 connected as described by Table 11.2.19.4-1, complying with the Rules of Section 7.2.1. [VM = I]


Observation 11.2.19.4-1: In this backplane DS01 thru DS04 are routed to payload slots. DS01 thru DS04 are serving the same function as DP01 thru DP12.

Rule 11.2.19.4-3: The FP pairs that connect a pair of ports in one slot, with a pair of ports from another, shall be routed on the backplane, such that the FP pair can be used as a single DFP. [VM = I]


Table 11.2.19.4-1 Data Plane Connection BKP6-DIS09-11.2.19-n Slot/

Channel pairs

DS01, DS02

DS03, DS04

DP01, DP02

DP03, DP04

DP05, DP06

DP07, DP08

DP09, DP10

DP11, DP12

1 VPX02-DS01,DS02

VPX03-DS01,DS02

VPX04-DS01,DS02

VPX05-DS01,DS02

VPX06-DS01,DS02

VPX07-DS01,DS02

VPX08-DS01,DS02

VPX09-DS01,DS02

2 VPX01-DS01,DS02

VPX03-DS03,DS04

VPX04-DS03,DS04

VPX05-DS03,DS04

VPX06-DS03,DS04

VPX07-DS03,DS04

VPX08-DS03,DS04

VPX09-DS03,DS04

3 VPX01-DS03,DS03

VPX02-DS03,DS04

VPX04-DP01,DP02

VPX05-DP01,DP02

VPX06-DP01,DP02

VPX07-DP01,DP02

VPX08-DP01,DP02

VPX09-DP01,DP02

4 VPX01-DP01,DP02

VPX02-DP01,DP02

VPX03-DP01,DP02

VPX05-DP03,DP4

VPX06-DP03,DP4

VPX07-DP03,DP4

VPX08-DP03,DP4

VPX09-DP03,DP4

5 VPX01-DP03,DP04

VPX02-DP03,DP04

VPX03-DP03,DP04

VPX04-DP03,DP04

VPX06-DP05,DP6

VPX07-DP05,DP6

VPX08-DP05,DP6

VPX09-DP05,DP6

6 VPX01-DP05,DP06

VPX02-DP05,DP06

VPX03-DP05,DP06

VPX04-DP05,DP06

VPX05-DP05,DP06

VPX07-DP07,DP08

VPX08-DP07,DP08

VPX09-DP07,DP08

7 VPX01-DP07,DP08

VPX02-DP07,DP08

VPX03-DP07,DP08

VPX04-DP07,DP08

VPX05-DP07,DP08

VPX06-DP07,DP08

VPX08-DP09,DP10

VPX09-DP09,DP10

8 VPX01-DP09,DP10

VPX02-DP09,DP10

VPX03-DP09,DP10

VPX04-DP09,DP10

VPX05-DP09,DP10

VPX06-DP09,DP10

VPX07-DP09,DP10

VPX09-DP11,DP12

9 VPX01-DP11,DP12

VPX02-DP11,DP12

VPX03-DP11,DP12

VPX04-DP11,DP12

VPX05-DP11,DP12

VPX06-DP11,DP12

VPX07-DP11,DP12

VPX08-DP11,DP12



Observation 11.2.19.5-1: User Defined pins that are following a suggested use, such as 2 Control Plane Thin Pipes on the single-ended pins of P5/J5 and P6/J6 of Payload Slots, are still User Defined pins and are therefore made available on the rear of the backplane for RTM connections.




11.2.20 7-Slot — BKP6-HYB07-11.2.20-n (3 Payload + 2 VME Bridge + 2 VME)

These Backplane Profiles are intended for a development environment. Some systems might be able to deploy with these backplanes. It is expected that many deployed systems will not use RTMs; instead the I/O signals that these Backplane Profiles route to RTMs would be routed, via the backplane, to connectors. For more on RTMs, see Section 4.4. Note: It is up to the RTM implementation whether it connects to these signals and what is done with them. Figure 11.2.20-1 gives an overview of the topology. The intent is to provide a development environment that can be used with legacy VME boards as well as current OpenVPX compatible modules.

VME1

VME2

VPX3

VPX5



Control Plane(TP)

Data Plane(FP)

PayloadSlots

VPX4

ContrlPlane

ContrlPlane


IPMC IPMC

DataPlane

DataPlane

DataPlane

DataPlane

ContrlPlane

ContrlPlane

ContrlPlane

VPX6

IPMC IPMC IPMC

DataPlane

VMESlots

Expansion Plane(46.1)

VME7

BridgeSlots

VME VME VME46.1

VME46.1

TP

TP



The remainder of this Section gives detailed Rules for the these Backplane Profiles. Table 11.2.20-1 gives requirements that are independent of the topology, such as channel baud rate and slot pitch.


Profile name

Mechanical

VPX Slot Profiles and Section Channel

Gbaud Rate VPX 1 - 2 VPX 3 - 4 VPX 5 - 7

Pitch (in)

RTM Conn VME64x Bridge Payload Data Plane

BKP6-HYB07-11.2.20-1

1.0 VITA 46.10

VME64x per [VITA 1.1]

SLT6-BRG-4F1V2T-

10.5.1

SLT6-PAY-4F2T-10.2.2 3.125

BKP6-HYB07-11.2.20-2

1.0 VITA 46.10


SLT6-BRG-4F1V2T-

10.5.1

SLT6-PAY-4F2T-10.2.2 5.0

BKP6-HYB07-11.2.20-3

1.0 VITA 46.10


SLT6-BRG-4F1V2T-

10.5.1

SLT6-PAY-4F2T-10.2.2 6.25



Rule 11.2.20.1-1: Slot VPX 5-7 shall be Payload Slot using the Slot Profile specified in Table 11.2.20-1, for the particular Backplane Profile. [VM = I]

Rule 11.2.20.1-2: Slots VPX 3-4 shall be Bridge Slot using the Slot Profile specified in Table 11.2.20-1, for the particular Backplane Profile. [VM = I]




Rule 11.2.20.2-1: Slots VME 1-2 shall comply with [VITA 1.1] specification. [VM = I]

Rule 11.2.20.2-2: Slots VME 1-2 shall be used by VME Plug-in Modules that can be configured to not provide the VME System Controller Function. [VM = I]


Observation 11.2.20.2-1: Ethernets on the VME Slots are connected via cables and the pins are beyond the scope of this document.



Observation 11.2.20.3-1: Some differences between VME based Plug-in Modules and VITA 65 Utility Plane signaling might be observed.

11.2.20.3.1 SYS_CON*

Rule 11.2.20.3.1-1: By default, the lowest numbered physical VPX slot shall be the slot that has SYS_CON* pulled low. [VM = I]


Rule 11.2.20.3.2-1: The VME System Controller Function shall be in VPX Payload Slot 3. [VM = I]








Table 11.2.20.5-1 Data Plane Connection BKP6-HYB07-11.2.20-n Slot/


5-Sl

ot M

esh

C

lust

er






Rule 11.2.20.5-1: Each Payload Slot shall have its Data Plane Ports DP01 thru DP04 connected as described by Table 11.2.20.5-1, complying with the Rules of Section 7.2.1. [VM = I]







12 6U Module Profiles The following sub-sections define different variants of 6U height Module Profiles that are used in OpenVPX systems:

12.1 6U Module Profiles Common Section

For material common to both 6U and 3U Development Module Profiles, see Section 8.

12.1.1 6U Module Cooling Types





12.1.1.1 6U VITA 48.1 Air-Cooled Modules

Suggestion 12.1.1.1-1: In order to allow their use in a Standard Development Chassis, it is suggested that 6U Air-cooled modules designed to require ≤150W per slot.

Permission 12.1.1.1-1: 6U Air-cooled modules may be designed to require >150W per slot, but these modules might not be properly powered in a Standard Development Chassis.

12.1.1.2 6U VITA 48.2 Conduction-Cooled Modules

Recommendation 12.1.1.2-1: In order to allow their use in Standard Development Chassis, 6U conduction-cooled modules should be designed to require ≤150W per slot. [VM = VNR]

Permission 12.1.1.2-1: 6U conduction-cooled modules may be designed to require >150W per slot, but these modules might not be properly powered or cooled in a Standard Development Chassis.

12.1.2 Power voltages and System Management

These Rules apply to all 6U Module Profiles, unless specified otherwise in the specific Module Profile Section:


Rule 12.1.2-1: Vs1 shall be +12.0 VDC per [VITA 46.0]. [VM = I]



Rule 12.1.2-4: If used, SM0 and SM1 shall be implemented in accordance with the requirements of [VITA 46.11]. [VM = D]



12.2 6U Payload Module Profiles Using VITA 46.0 Connectors

12.2.1 Payload Module Profiles MOD6-PAY-4F1Q2U2T-12.2.1-n

Each line of Table 12.2.1-1 is a different Module Profile. The following are Rules that apply to all the Module Profiles of this Section (all lines of the Table):

Rule 12.2.1-1: Plug-In Modules conforming to these profiles shall comply with Slot Profile SLT6-PAY-4F1Q2U2T-10.2.1. [VM = I]

Rule 12.2.1-2: Plug-In Modules conforming to these profiles shall use connectors complying with [VITA 46.0]. [VM = I]

Rule 12.2.1-3: For the applicable Module Profile row in Table 12.2.1-1, the Plug-In Module shall comply with the Plane protocol listed in each corresponding column. [VM = T]

Table 12.2.1-1 Module Profiles MOD6-PAY-4F1Q2U2T-12.2.1-n

Profile name

Data Plane 4 FP

Expansion Plane

Control Plane 2 UTPs

Control Plane 2 TPs

DP01 DP02 DP03 DP04 CPutp01 CPutp02 CPtp01 CPtp02

MOD6-PAY-4F1Q2U2T-12.2.1-1

SRIO 1.3 at 3.125 Gbaud per Section 5.2

PCIe Gen 1 per Section

5.3

1000BASE-BX per Section 5.1.1

1000BASE-T per Section 5.1.3

MOD6-PAY-4F1Q2U2T-12.2.1-2



5.3



MOD6-PAY-4F1Q2U2T-12.2.1-3

PCIe Gen 1 per Section 5.3 PCIe Gen 1 per Section

5.3



MOD6-PAY-4F1Q2U2T-12.2.1-4


5.3



Note: The table is continued on the next page.


Profile name

Data Plane 4 FP

Expansion Plane


Control Plane 2 TPs


MOD6-PAY-4F1Q2U2T-12.2.1-5

10GBASE-BX4 per Section 5.1.4


5.3



MOD6-PAY-4F1Q2U2T-12.2.1-6



5.3



MOD6-PAY-4F1Q2U2T-12.2.1-7

10GBASE-KX4 per Section 5.1.5


5.3



MOD6-PAY-4F1Q2U2T-12.2.1-8



5.3



MOD6-PAY-4F1Q2U2T-12.2.1-9



5.3



MOD6-PAY-4F1Q2U2T-12.2.1-10



5.3



MOD6-PAY-4F1Q2U2T-12.2.1-11



5.3



MOD6-PAY-4F1Q2U2T-12.2.1-12



5.3



MOD6-PAY-4F1Q2U2T-12.2.1-13

InfiniBand DDR per Section 5.4


5.3




12.2.2 Payload Module Profiles MOD6-PAY-4F2T-12.2.2-n


Rule 12.2.2-1: Plug-In Modules conforming to these profiles shall comply with Slot Profile SLT6-PAY-4F2T-10.2.2. [VM = I]



Table 12.2.2-1 Module Profiles MOD6-PAY-4F2T-12.2.2-n

Profile name

Data Plane 4 FP Control Plane 2 TPs

DP01 DP02 DP03 DP04 CPtp01 CPtp02

MOD6-PAY-4F2T-12.2.2-1



MOD6-PAY-4F2T-12.2.2-2

PCIe Gen 1 per Section 5.3 1000BASE-T per Section 5.1.3

MOD6-PAY-4F2T-12.2.2-3

PCIe Gen 2 per Section 5.3 1000BASE-T per Section 5.1.3

MOD6-PAY-4F2T-12.2.2-4

10GBASE-BX4 per Section 5.1.4 1000BASE-T per Section 5.1.3

MOD6-PAY-4F2T-12.2.2-5

10GBASE-KX4 per Section 5.1.5 1000BASE-T per Section 5.1.3

MOD6-PAY-4F2T-12.2.2-6



MOD6-PAY-4F2T-12.2.2-7



MOD6-PAY-4F2T-12.2.2-8



MOD6-PAY-4F2T-12.2.2-9




12.2.3 Payload Module Profiles MOD6-PAY-8F-12.2.3-n


Rule 12.2.3-1: Plug-In Modules conforming to these profiles shall comply with Slot Profile SLT6-PAY-8F-10.2.3 [VM = I]



Permission 12.2.3-1: More than one protocol may exist within the Data Plane Pipes.

Recommendation 12.2.3-1: When routing more than one protocol within the Data Plane an order of precedence should be followed in groups of 4. [VM = I]

Recommendation 12.2.3-2: The following precedence should be followed when more than one protocol is used within the Data Plane; DP1 to DP04 Peer to Peer protocols, and DP05 to DP08 Master / Slave. [VM = I]

Table 12.2.3-1 Module Profiles MOD6-PAY-8F-12.2.3-n

Profile name

Data Plane

Fat Pipes

DP01 – DP04 DP05 – DP08

MOD6-PAY-8F-12.2.3-1 PCIe Gen 1 per Section 5.3 PCIe Gen 1 per Section 5.3

MOD6-PAY-8F-12.2.3-2 PCIe Gen 2 per Section 5.3 PCIe Gen 2 per Section 5.3

MOD6-PAY-8F-12.2.3-3 SRIO 1.3 at 3.125 Gbaud per Section 5.2 PCIe Gen 2 per Section 5.3

MOD6-PAY-8F-12.2.3-4 SRIO 2.0 at 5.0 Gbaud per Section 5.2 PCIe Gen 2 per Section 5.3

MOD6-PAY-8F-12.2.3-5 10GBASE-KX4 per Section 5.1.5



12.2.4 Payload Module Profiles MOD6-PAY-4F16U-12.2.4-n


Rule 12.2.4-1: Plug-In Modules conforming to these profiles shall comply with Slot Profile SLT6-PAY-4F16U-10.2.4. [VM = I]



Permission 12.2.4-1: As shown in the table below, more than one protocol may exist within the Data Plane Pipes.

Recommendation 12.2.4-1: When routing more than one protocol within the Data Plane an order of precedence should be followed. [VM = I]

Recommendation 12.2.4-2: The following precedence should be followed; starting with Pipes nearest to P0 following in order to the last Pipe of the same size Peer to Peer protocols, followed by Master / Slave. [VM = I]

Table 12.2.4-1 Module Profiles MOD6-PAY-4F16U-12.2.4-n

Profile name

Data Plane

Fat Pipes All 16 Ultra-Thin Pipes

DP01-DP02 DP03-DP04 DP05 through DP20

MOD6-PAY-4F16U-12.2.4-1

PCIe Gen 1 per Section 5.3



MOD6-PAY-4F16U-12.2.4-2




MOD6-PAY-4F16U-12.2.4-3




MOD6-PAY-4F16U-12.2.4-4




MOD6-PAY-4F16U-12.2.4-5





12.2.5 Payload Module Profiles MOD6-PAY-2F2U2T-12.2.5-n


Rule 12.2.5-1: Plug-In Modules conforming to these profiles shall comply with Slot Profile SLT6-PAY-2F2U2T-10.2.5. [VM = I]



Table 12.2.5-1 Module Profiles MOD6-PAY-2F2U2T-12.2.5-n

Profile name

Data Plane 2 FP Control Plane 2 UTPs Control Plane 2 TPs

DP01 DP02 CPutp01 CPutp02 CPtp01 CPtp02

MOD6-PAY-2F2U2T-12.2.5-1




MOD6-PAY-2F2U2T-12.2.5-2




MOD6-PAY-2F2U2T-12.2.5-3




MOD6-PAY-2F2U2T-12.2.5-4




MOD6-PAY-2F2U2T-12.2.5-5




MOD6-PAY-2F2U2T-12.2.5-6




MOD6-PAY-2F2U2T-12.2.5-7




MOD6-PAY-2F2U2T-12.2.5-8









Rule 12.2.6-3: If the protocol on the Expansion Plane is PCIe, in accordance with Section 5.3, there is not a PCIe Common Reference clock on P0/J0 and a PCIe Common Reference clock is required, it shall be on the pins EPclock1 and, if two are required, also on EPclock2 (See Section 5.3 for clock characteristics). [VM = I]

Observation 12.2.6-1: If Rule 12.2.6-3 applies, the Rules of 5.3.2 will also apply.

Permission 12.2.6-1: If the Data Plane is PCIe, the EPclocks may be used as a PCIe Common Reference clock for the Data Plane.




Profile name

Data Plane 4 FP

Expansion Plane


Control Plane 2 TPs


MOD6-PAY-4F1Q2U2T-12.2.6-1



5.3



MOD6-PAY-4F1Q2U2T-12.2.6-2



5.3



MOD6-PAY-4F1Q2U2T-12.2.6-3


5.3



MOD6-PAY-4F1Q2U2T-12.2.6-4


5.3



MOD6-PAY-4F1Q2U2T-12.2.6-5



5.3



MOD6-PAY-4F1Q2U2T-12.2.6-6



5.3



MOD6-PAY-4F1Q2U2T-12.2.6-7



5.3



MOD6-PAY-4F1Q2U2T-12.2.6-8



5.3



MOD6-PAY-4F1Q2U2T-12.2.6-9



5.3



MOD6-PAY-4F1Q2U2T-12.2.6-10



5.3



MOD6-PAY-4F1Q2U2T-12.2.6-11



5.3



MOD6-PAY-4F1Q2U2T-12.2.6-12



5.3








Rule 12.2.7-3: If the protocol on the Expansion Plane is PCIe, in accordance with Section 5.3, there is not a PCIe Common Reference clock on P0/J0 and a PCIe Common Reference clock is required, it shall be on the pins EPclock1 and, if two are required, also on EPclock2 (See Section 5.3 for clock characteristics). [VM = I]

Observation 12.2.7-1: If Rule 12.2.7-3 applies, the Rules of 5.3.2 will also apply.

Permission 12.2.7-1: If the Data Plane is PCIe, the EPclocks may be used as a PCIe Common Reference clock for the Data Plane.




Profile name

Data Plane 4 FP

Expansion Plane


Control Plane 2 TPs


MOD6-PAY-4F2Q2U2T-12.2.7-1



5.3



MOD6-PAY-4F2Q2U2T-12.2.7-2



5.3



MOD6-PAY-4F2Q2U2T-12.2.7-3


5.3



MOD6-PAY-4F2Q2U2T-12.2.7-4


5.3



MOD6-PAY-4F2Q2U2T-12.2.7-5



5.3



MOD6-PAY-4F2Q2U2T-12.2.7-6



5.3



MOD6-PAY-4F2Q2U2T-12.2.7-7



5.3



MOD6-PAY-4F2Q2U2T-12.2.7-8



5.3



MOD6-PAY-4F2Q2U2T-12.2.7-9



5.3



MOD6-PAY-4F2Q2U2T-12.2.7-10



5.3



MOD6-PAY-4F2Q2U2T-12.2.7-11



5.3



MOD6-PAY-4F2Q2U2T-12.2.7-12



5.3




12.3 6U Peripheral Module Profiles Using VITA 46.0 Connectors

12.3.1 Peripheral Module Profiles MOD6-PER-4F-12.3.1-n


Rule 12.3.1-1: Plug-In Modules conforming to these profiles shall comply with Slot Profile SLT6-PER-4F-10.3.1. [VM = I]



Table 12.3.1-1 Module Profiles MOD6-PER-4F-12.3.1-n

Profile name

Data Plane 4 FP

DP01 DP02 DP03 DP04

MOD6-PER-4F-12.3.1-1


MOD6-PER-4F-12.3.1-2


MOD6-PER-4F-12.3.1-3


MOD6-PER-4F-12.3.1-4


MOD6-PER-4F-12.3.1-5


MOD6-PER-4F-12.3.1-6


MOD6-PER-4F-12.3.1-7


MOD6-PER-4F-12.3.1-8


MOD6-PER-4F-12.3.1-9












Profile name

Data Plane

DP01 Fat Pipe DP02 Fat Pipe

MOD6-PER-2F-12.3.2-1 PCIe Gen 1 per Section 5.3 PCIe Gen 1 per Section 5.3

MOD6-PER-2F-12.3.2-2 PCIe Gen 2 per Section 5.3 PCIe Gen 2 per Section 5.3

MOD6-PER-2F-12.3.2-3 SRIO 2.0 at 5.0 Gbaud per Section 5.2 PCIe Gen 2 per Section 5.3

MOD6-PER-2F-12.3.2-4 10GBASE-BX4 per Section 5.1.4


MOD6-PER-2F-12.3.2-5 10GBASE-KX4 per Section 5.1.5



12.3.3 Peripheral Module Profiles MOD6-PER-4U-12.3.3-n


Rule 12.3.3-1: Plug-In Modules conforming to these profiles shall comply with Slot Profile SLT6-PER-4U-10.3.3. [VM = I]



Table 12.3.3-1 Module Profiles MOD6-PER-4U-12.3.3-n

Profile name

Data Plane

DP01 – DP04 Ultra-Thin Pipes

MOD6-PER-4U-12.3.3-1 PCIe Gen 1 per Section 5.2

MOD6-PER-4U-12.3.3-2 PCIe Gen 2 per Section 5.2











Profile name

Data Plane

DP01 Fat Pipe

MOD6-PER-1F-12.3.4-1 PCIe Gen 1 per Section 5.3


MOD6-PER-1F-12.3.4-3 SRIO 2.0 at 5.0 Gbaud per Section 5.2




12.3.5 Module Profiles MOD6-PER-1Q-12.3.5-n


Rule 12.3.5-1: Plug-In Modules conforming to these profiles shall comply with Slot Profile SLT6-PER-1Q-10.3.5. [VM = I]



Table 12.3.5-1 Module Profiles MOD6-PER-1Q-12.3.5-n

Profile name Expansion Plane

MOD6-PER-1Q-12.3.5-1 PCIe Gen 1 per Section 5.3

MOD6-PER-1Q-12.3.5-2 PCIe Gen 2 per Section 5.3


12.4 6U Switch Module Profiles using VITA 46.0 Connectors

12.4.1 Switch Module Profiles MOD6-SWH-20U19F-12.4.1-n


Rule 12.4.1-1: Plug-In Modules conforming to these profiles shall comply with Slot Profile SLT6-SWH-20U19F-10.4.1. [VM = I]

Rule 12.4.1-2: Rule 12.4.1-2: Plug-In Modules conforming to these profiles shall use connectors complying with [VITA 46.0]. [VM = I]


Recommendation 12.4.1-1: If Suggestion 10.4.1.4.1-1 is followed, the 2 Thin Pipes (CPtp01 and CPtp02) should be used for either 1000BASE-T or 10GBASE-T. [VM = T]


Table 12.4.1-1 Module Profiles MOD6-SWH-20U19F-12.4.1-n

Profile name

Control Plane 20 UTP Data Plane 19 FP

Inter-Switch or Payload Slots CSutp01 to CSutp04

Payload Slots CPutp01 to CPutp16

Payload Slots DP01 to DP15

Inter-Switch or Payload Slots DS01 to DS04

MOD6-SWH-20U19F-12.4.1-1 1000BASE-BX per Section 5.1.1 SRIO 1.3 at 3.125 Gbaud

per Section 5.2

MOD6-SWH-20U19F-12.4.1-2 1000BASE-BX per Section 5.1.1 PCIe Gen 1 per Section 5.3


MOD6-SWH-20U19F-12.4.1-4 1000BASE-BX per Section 5.1.1 10GBASE-BX4 per Section 5.1.4

MOD6-SWH-20U19F-12.4.1-5 1000BASE-BX per Section 5.1.1 10GBASE-KX4 per Section 5.1.5

MOD6-SWH-20U19F-12.4.1-6 1000BASE-BX per Section 5.1.1 Serial RapidIO 2.0 at 5.0 Gbaud

per Section 5.2


per Section 5.2


per Section 5.2


per Section 5.2


12.4.2 Switch Module Profiles MOD6-SWH-16U20F-12.4.2-n







Table 12.4.2-1 Module Profiles MOD6-SWH-16U20F-12.4.2-n

Profile name

Control Plane 16 UTP Data Plane 20 FP

Inter-Switch CSutp01 to CSutp04

Payload Slots CPutp01 to CPutp12




per Section 5.2



MOD6-SWH-16U20F-12.4.2-4 1000BASE-BX per Section 5.1.1 10GBASE-BX4 per Section 5.1.4

MOD6-SWH-16U20F-12.4.2-5 1000BASE-BX per Section 5.1.1 10GBASE-KX4 per Section 5.1.5


per Section 5.2


per Section 5.2


per Section 5.2


per Section 5.2

MOD6-SWH-16U20F-12.4.2-10 1000BASE-BX per Section 5.1.1



12.4.3 Switch Module Profiles MOD6-SWH-24F-12.4.3-n


Rule 12.4.3-1: Plug-In Modules conforming to these profiles shall be SLT6-SWH-24F-10.4.3. [VM = I]




Table 12.4.3-1 Module Profiles MOD6-SWH-24F-12.4.3-n

Profile name

Data Plane 24 FP



MOD6-SWH-24F-12.4.3-1 Serial RapidIO 1.3 at 3.125 Gbaud per Section 5.2

MOD6-SWH-24F-12.4.3-2 PCIe Gen 1 per Section 5.3

MOD6-SWH-24F-12.4.3-3 PCIe Gen 2 per Section 5.3

MOD6-SWH-24F-12.4.3-4 10GBASE-BX4 per Section 5.1.4

MOD6-SWH-24F-12.4.3-5 10GBASE-KX4 per Section 5.1.5



MOD6-SWH-24F-12.4.3-8 Serial RapidIO 2.1 at 5.0 Gbaud per

Section 5.2



12.4.4 Switch Module Profiles MOD6-SWH-4F24T-12.4.4-n


Rule 12.4.4-1: Plug-In Modules conforming to these profiles shall comply with SLT6-SWH-4F24T-10.4.4. [VM = I]



Table 12.4.4-1 Module Profiles MOD6-SWH-4F24T-12.4.4-n

Profile name

Control Plane 24 TP Control Plane 4 FP

Payload Slots CPtp01 to CPtp24 External CP01 to CP04

MOD6-SWH-4F24T-12.4.4-1 1000BASE-T per Section 5.1.3 10GBASE-BX4 per Section 5.1.4

MOD6-SWH-4F24T-12.4.4-2

1000BASE-T per Section 5.1.3 10GBASE-KX4 per Section 5.1.5


12.4.5 Module Profiles MOD6-SWH-16U16F-12.4.5-n





Table 12.4.5-1 Module Profiles MOD6-SWH-16F16U-12.4.5-n

Profile name

Control Plane 16UTP Data Plane 16FP

Inter-Switch CS01 to CS04 CP01 to CP12 DP01 to DP12

Inter-Switch DS01 to DS04

MOD6-SWH-16U16F-12.4.5-1 1000BASE-BX per Section 5.1.1 PCIe Gen 1 at 2.5 Gbaud

per Section 5.3

MOD6-SWH-16U16F-12.4.5-2 1000BASE-BX per Section 5.1.1 PCIe Gen 2 at 5.0 Gbaud

per Section 5.3

MOD6-SWH-16U16F-12.4.5-3 1000BASE-BX per Section 5.1.1 10GBASE-BX4

per Section 5.1.4

MOD6-SWH-16U16F-12.4.5-4 1000BASE-BX per Section 5.1.1 10GBASE-KX4

per Section 5.1.5


per Section 5.2


per Section 5.2


per Section 5.2


per Section 5.2


per Section 5.2


12.5 6U Miscellaneous Module Profiles using VITA 46.0 Connectors

12.5.1 Bridge Module Profiles MOD6-BRG-4F1V2T-12.5.1-n


Rule 12.5.1-1: Plug-In Modules conforming to these profiles shall comply with Slot Profile SLT6-BRG-4F1V2T-10.5.1. [VM = I]


Rule 12.5.1-3: The Parallel Bus shall comply with VITA 46.1. [VM = T,I]



Table 12.5.1-1 Module Profiles MOD6-BRG-4F1V2T-12.5.1-n

Profile name

Control Plane 2 TP Data Plane 4 FP

CPtp01 CPtp02 Payload Slots DP01 to DP04

MOD6-BRG-4F1V2T-12.5.1-1


Serial RapidIO 1.3 at 3.125 Gbaud per Section 5.2

MOD6-BRG-4F1V2T-12.5.1-2

1000BASE-T per Section 5.1.3 PCIe Gen 1 per Section 5.3

MOD6-BRG-4F1V2T-12.5.1-3

1000BASE-T per Section 5.1.3 PCIe Gen 2 per Section 5.3

MOD6-BRG-4F1V2T-12.5.1-4



MOD6-BRG-4F1V2T-12.5.1-5



MOD6-BRG-4F1V2T-12.5.1-6



MOD6-BRG-4F1V2T-12.5.1-7



MOD6-BRG-4F1V2T-12.5.1-8



MOD6-BRG-4F1V2T-12.5.1-9




12.5.2 Bridge Module Profiles MOD6-BRG-4F1V-12.5.2-n


Rule 12.5.2-1: Plug-in Modules conforming to these profiles shall comply with Slot Profile SLT6-BRG-4F1V-10.5.2. [VM = I]

Rule 12.5.2-2: The Plug-In Modules conforming to these profiles shall use connectors complying with [VITA 46.0]. [VM = I]

Rule 12.5.2-3: The Parallel Bus shall comply with VITA 46.1. [VM = T,I]




Recommendation 12.5.2-2: The following precedence should be followed; starting with Pipes nearest to P0 following in order to the last Pipe on P1 Peer to Peer protocols, followed by Master / Slave. [VM = I]

Table 12.5.2-1 Module Profiles MOD6-BRG-4F1V-12.5.2-n

Module Profile

Data Plane

DP01 – DP02 Fat Pipes DP03 – DP04 Fat Pipes

MOD6-BRG-4F1V-12.5.2-1 PCIe Gen 1 per Section 5.3 PCIe Gen 1 per Section 5.3

MOD6-BRG-4F1V-12.5.2-2 PCIe Gen 2 per Section 5.3 PCIe Gen 2 per Section 5.3

MOD6-BRG-4F1V-12.5.2-3 SRIO 2.0 at 5.0 Gbaud per Section 5.2 PCIe Gen 2 per Section 5.3

MOD6-BRG-4F1V-12.5.2-4 10GBASE- BX4 per Section 5.1.4

10GBASE- BX4 per Section 5.1.4

MOD6-BRG-4F1V-12.5.2-5 10GBASE- KX4 per Section 5.1.5

10GBASE- KX4 per Section 5.1.5


13 6U Standard Development Chassis Profiles Standard Development Chassis are chassis that are intended for development use in controlled environments, and are not intended for deployment in rugged environments.

Many applications will be able to utilize Standard Development Chassis Profiles in the development phase. This section defines 6U 16-slot, 10-slot, and 6-slot Standard Development Chassis Profiles that are believed to cover the majority of the of the development requirements.

Note that in some cases 6U development chassis will be tailored to the specific needs of a particular application, and this standard does not preclude that.

Note that this standard does not address 6U deployed chassis configurations, as those are specific to the application requirements.

13.1 6U Standard Development Chassis Profiles Common Section

For material common to both 6U and 3U Standard Development Chassis Profiles, see Section 9.

13.1.1 6U VITA 48.1 Air-Cooled Standard Development Chassis

Suggestion 13.1.1-1: It is suggested that 6U air-cooled Standard Development Chassis be designed to provide ≥150W per slot of DC power.

13.1.2 6U VITA 48.2 Conduction-Cooled Standard Development Chassis

Suggestion 13.1.2-1: It is suggested that 6U conduction-cooled Standard Development Chassis be designed to cool the chassis sidewalls to ≤55°C with all slots dissipating 150W at a 30°C ambient temperature and mean sea level (MSL).

Suggestion 13.1.2-2: It is suggested that 6U conduction-cooled Standard Development Chassis be designed to provide ≥150W per slot of DC power.

13.2 6U Standard Development Chassis Profile Definitions

This section details how to specify a 6U Standard Development Chassis configuration. Additional chassis mechanical characteristics are defined in Section 4. Due to the number of possible chassis/backplane configurations, a 6U Standard Development Chassis Profile is defined using a name constructed from the permitted options listed below.

Rule 13.2-1: OpenVPX 6U Standard Development Chassis Profiles shall be specified using the construct per Figure 13.2-1 and associated parameters. [VM = I]


Observation 13.2-1: The 6U Standard Development Chassis Profiles are 12V-centric and 5V-centric power profiles. This approach encourages module suppliers to standardize their power usage to draw the majority of power from 12V or 5V.

CHAS6-UUU-vv-WWW-x-YYY-z-bpn

Categorization Type

Form Factor

Chassis Type

PrimaryPower

Backplane Power

ChassisManager

Slot Count

Plug-in ModuleCooling

Backplane Profile Name

Figure 13.2-1 6U Standard Development Chassis Profile Name Construct

The parameters in Figure 13.2-1 are described below:

CHAS Standard Development Chassis Category

6 Form-factor = 6U

UUU Standard Development Chassis Type {RCK | TOW | OPN} Where RCK = 19” EIA Rack Mount TOW = Stand-alone Tower OPN = Open Frame

vv Slot Count {06 | 10 | 16}

Where 06 = 6 slots 10 = 10 slots 16 = 16 slots

WWW Primary Power {3PA | 3PB | 1PA | 1PB}

Where 3PA = 3 Phase, 208VAC, 50/60 Hz 3PB = 3 Phase, 400VAC 50 Hz (per CENELEC HD 472

S1:1988) 1PA = Single phase, 110/220VAC, 50/60 Hz 1PB = Single phase, 230VAC, 50 Hz (per CENELEC

HD 472 S1:1988)


X Plug-in Module Cooling Type {A | C} Where A = VITA 48.1 air cooled C = VITA 48.2 conduction cooled

YYY Backplane Power Option {12H | 5VH | VEN}

Where 12H = 12V centric power (see Table 13.2-1 for each chassis size)

5VH = 5V centric power (see Table 13.2-1 for each chassis size)

VEN = Supplier Defined (can be higher or lower)

z Chassis Manager {N | Y } Where N = None Y = There is a Chassis Manager.

bpn Backplane Profile Name {BKP6-XXXyy-z.z.z-n} from Section 11 (all profiles are not listed here; see Section 11) (e.g. BKP6-CEN16-11.2.2-n)

Table 13.2-1 6U Standard Development Chassis Backplane Power Options

Backplane Power Option

Chassis Size / Power Availability

6-Slot 10-Slot 16-Slot

12H

VS1/VS2 = 12V @ 75A, VS3 = 5V @ 18A, +3.3VAUX @ 12A, +12 VAUX @ 3A, -12 VAUX @ 3A

VS1/VS2 = 12V @ 125A, VS3=5V @ 30A, +3.3VAUX @ 16A, +12 VAUX @ 5A, -12 VAUX @ 5V

VS1/VS2 = 12V @ 200A, VS3=5V @ 80A, +3.3VAUX @ 22A, +12 VAUX @ 8A, -12 VAUX @ 8A

5VH

VS1/VS2 = 12V @ 15A, VS3 = 5V @ 132A +3.3VAUX @ 12A, +12 VAUX @ 3A, -12 VAUX @ 3A



VEN supplier specific (can be higher or lower)

supplier specific (can be higher or lower)



14 3U Slot Profiles The following sub-sections define different variants of 3U height Slot Profiles that are used in OpenVPX Backplane Profiles:

14.1 3U Slot Profiles Common Section

For material common to both 6U and 3U Slot Profiles, see Section 6.

14.2 3U Payload Slot Profiles Using VITA 46.0 Connectors



14.2.1 Payload Slot Profile SLT3-PAY-2F1F2U-14.2.1

The SLT3-PAY-2F1F2U-14.2.1 payload Slot Profile contains 2 Data Plane Fat Pipes and 8 pairs of Expansion Plane (frequently used as 1 Fat Pipe of Expansion Plane) and two Ultra-Thin Pipes for the Control Plane on P1/J1. Figure 14.2.1-1 provides an overview of the Slot Profile. Table 14.2.1-1 and Table 14.2.1-2 provide the pin assignments. For Module Profiles using this Slot Profile, see Section 16.2.1.

SE

DiffP2/J2

SE

SEP0/J0


User Defined

User Defined Expansion Plane — 8 Pairs

User Defined

User Defined


Utility Plane

Utility Plane

Key

Key

DiffP1/J1

Figure 14.2.1-1 Payload Slot Profile SLT3-PAY-2F1F2U-14.2.1





Rule 14.2.1.2-1: There shall be pins allocated for two Control Plane Ultra-Thin Pipes on P1/J1, CPutp01 and CPutp02, as given in Table 14.2.1-1, with usage complying with Section 6.2.2. [VM = I]


14.2.1.3 Data Plane

Rule 14.2.1.3-1: There shall be pins allocated for two Data Plane Fat Pipes on P1/J1, DP01 and DP02, as given in Table 14.2.1-1, with usage complying with Section 6.2.2. [VM = I]

Permission 14.2.1.3-1: The lanes of the two Data Plane Fat Pipes, may be repartitioned.

Rule 14.2.1.3-2: If the Data Plane Fat Pipes are repartitioned, they shall be repartitioned as one of the options shown in Table 6.2.4.1-2, with usage complying with Section 6.2.2. [VM = I]


Rule 14.2.1.4-1: There shall be pins allocated for four lanes of Expansion Plane on P1/J1, EP00 – EP03, as given in Table 14.2.1-1, with usage complying with Section 6.2.2. [VM = I]

Rule 14.2.1.4-2: If the Expansion Plane is broken into pipes, the Expansion Plane Lanes shall be assigned pipes following one of the options given in Table 6.2.4.2-1, with usage complying with Section 6.2.2. [VM = I]

Permission 14.2.1.4-1: Some pipes may be left un-used.







Permission 14.2.1.5-1: The User Defined pins on P1/J1-13 and P1/J1-14 of Table 14.2.1-1 may be utilized as a Control Plane Thin Pipe for external chassis I/O or RTM interfaces.


Table 14.2.1-1 Payload Slot Profile SLT3-PAY-2F1F2U-14.2.1 — P1 & J1 Plug-In Module P1



Dat

a Pl

ane

Port

1

X8 x4

/ 2x

2 / 4

x1 GDiscrete1 GND GND-J1 DP01-TD0- DP01-TD0+ GND GND-J1 DP01-RD0- DP01-RD0+

2 GND DP01-TD1- DP01-TD1+ GND-J1 GND DP01-RD1- DP01-RD1+ GND-J1 GND

3 P1-VBAT GND GND-J1 DP01-TD2- DP01-TD2+ GND GND-J1 DP01-RD2- DP01-RD2+


5

Dat

a Pl

ane

Port

2

x4 /

2x2

/ 4x1

SYS_CON* GND GND-J1 DP02-TD0- DP02-TD0+ GND GND-J1 DP02-RD0- DP02-RD0+


7 Reserved GND GND-J1 DP02-TD2- DP02-TD2+ GND GND-J1 DP02-RD2- DP02-RD2+


9

Expa

nsio

n Pl

ane

Port

1

x4 /

2x2

/ 4x1

UD GND GND-J1 EP00-TD- EP00-TD+ GND GND-J1 EP00-RD- EP00-RD+

10 GND EP01-TD- EP01-TD+ GND-J1 GND EP01-RD- EP01-RD+ GND-J1 GND

11 UD GND GND-J1 EP02-TD- EP02-TD+ GND GND-J1 EP02-RD- EP02-RD+


13

Use

r D

efin

ed


14 GND UD UD GND-J1 GND-J1 UD UD GND-J1 GND

15

Con

trol

Pl

ane

Maskable Reset* GND GND-J1 CPutp02-

TD- CPutp02-TD+ GND GND-J1 CPutp02-

RD- CPutp02-RD+

16 GND CPutp01-TD-

CPutp01-TD+ GND-J1 GND-J1 CPutp01-

RD- CPutp01-RD+ GND-J1 GND

Warning: Tables combine Plug-In Module & Backplane pin assignments, See Section 6.3.1.

Table 14.2.1-2 Payload Slot Profile SLT3-PAY-2F1F2U-14.2.1 — P2 & J2 Plug-In Mod P2






The SLT3-PAY-1F2F2U-14.2.2 payload Slot Profile contains 1 Data Plane Fat Pipe and 16 pairs of Expansion Plane (frequently used as 2 Fat Pipes of Expansion Plane) and two Ultra-Thin Pipes for the Control Plane on P1/J1. Figure 14.2.2-1 provides an overview of the Slot Profile. Table 14.2.1-1 and Table 14.2.1-2 provide the pin assignments. For Module Profiles using this Slot Profile, see Section 16.2.2.

SE

DiffP2/J2

SE

SEP0/J0


User Defined

User DefinedExpansion Plane — 16 Pairs

User Defined

User Defined

Data Plane — 1 Fat PipesUtility Plane

Utility Plane

Key

Key

DiffP1/J1








14.2.2.3 Data Plane

Rule 14.2.2.3-1: There shall be pins allocated for one Data Plane Fat Pipe on P1/J1, DP01, as given in Table 14.2.2-1, with usage complying with Section 6.2.2. [VM = I]

Permission 14.2.2.3-1: The lanes of the Data Plane Fat Pipe may be repartitioned.

Rule 14.2.2.3-2: If the Data Plane Fat Pipe is repartitioned, it shall be repartitioned as one of the options shown in Table 6.2.4.1-1, with usage complying with Section 6.2.2. [VM = I]


Rule 14.2.2.4-1: There shall be pins allocated for eight lanes of Expansion Plane on P1/J1, EP00 – EP07, as given in Table 14.2.2-1, with usage complying with Section 6.2.2. [VM = I]

Rule 14.2.2.4-2: If the Expansion Plane is broken into pipes, the Expansion Plane Lanes shall be assigned pipes following one of the options given in given in Table 6.2.4.2-2, with usage complying with Section 6.2.2. [VM = I]













Dat

a Pl

ane

Port

1

x4 /

2x2

/ 4x1

GDiscrete1 GND GND-J1 DP01-TD0- DP01-TD0+ GND GND-J1 DP01-RD0- DP01-RD0+




5

Expa

n. P

lane

Por

t 1

x8

x4 /

2x2

/ 4x1

SYS_CON* GND GND-J1 EP00-TD- EP00-TD+ GND GND-J1 EP00-RD- EP00-RD+


7 Reserved GND GND-J1 EP02-TD- EP02-TD+ GND GND-J1 EP02-RD- EP02-RD+


9

Expa

n. P

lane

Por

t 2

x4 /

2x2

/ 4x1

UD GND GND-J1 EP04-TD- EP04-TD+ GND GND-J1 EP04-RD- EP04-RD+




13

Use

r D

efin

ed



15

Con

trol

Pl

ane



RD- CPutp02-RD+

16 GND CPutp01-TD-

CPutp01-TD+ GND-J1 GND CPutp01-



Table 14.2.2-2 Payload Slot Profile SLT3-PAY-1F2F2U-14.2.2 — P2 & J2 Plug-In Mod P2






The SLT3-PAY-2F2U-14.2.3 payload Slot Profile contains two Fat Pipes (two Data Plane ports), user defined area, and two Ultra-Thin Pipes on the Control Plane on P1/J1. Figure 14.2.3-1 provides an overview of the Slot Profile. Table 14.2.2-1 and Table 14.2.2-2 provide the pin assignments. For Module Profiles using this Slot Profile, see Section 16.2.3.

SE

DiffP2/J2

SE

SEP0/J0


User Defined

User Defined

User Defined

User Defined


Utility Plane

Utility Plane

Key

Key

DiffP1/J1







14.2.3.3 Data Plane



Table 14.2.3-1 Payload Slot Profile SLT3-PAY-2F2U-14.2.3 — P1 & J1 Plug-in module P1



Dat

a Pl

ane

Port

1

X8 x4

/ 2x

2 / 4





5

Dat

a Pl

ane

Port

2

x4 /

2x2

/ 4x1





9

Use

r Def

ined







15

Con

trol

Pl

ane



RD- CPutp02-RD+

16 GND CPutp01-TD-




Table 14.2.3-2 Payload Slot Profile SLT3-PAY-2F2U-14.2.3 — P2 & J2 Plug-in mod P2






The SLT3-PAY-1F1F2U-14.2.4 payload Slot Profile contains two Fat Pipes (1 Data Plane port plus 1 Expansion Plane port), user defined area, and two Ultra-Thin Pipes on the Control Plane on P1/J1. Figure 14.2.4-1 provides an overview of the Slot Profile. Table 14.2.4-1 and Table 14.2.4-2 provide the pin assignments. For Module Profiles using this Slot Profile, see Section 16.2.4.

SE

DiffP2/J2

SE

SEP0/J0


User Defined

User Defined

Expansion Plane — 8 Pairs

User Defined

User Defined

Data Plane — 1 Fat PipesUtility Plane

Utility Plane

Key

Key

DiffP1/J1








14.2.4.3 Data Plane








Permission 14.2.4.4-2: The 4 lanes of Expansion Plane may be used as eight pairs.










Dat

a Pl

ane

x4 /

2x2

/ 4x1





5

Expa

nsio

n Pl

ane

x4 /

2x2

/ 4x1

SYS_CON* GND GND-J1 EP00-TD- EP00-TD+ GND GND-J1 EP00-RD- EP00-RD+




9

Use

r Def

ined







15

Con

trol

Pl

ane

Maskable Reset* GND GND-J1 CPutp02-TD- CPutp02-

TD+ GND GND-J1 CPutp02-RD-

CPutp02-RD+

16 GND CPutp01-TD- CPutp01-TD+ GND-J1 GND CPutp01-








14.2.5 Payload Slot Profile SLT3-PAY-2F2T-14.2.5

The SLT3-PAY-2F2T payload Slot Profile contains 2 Fat Pipes, user defined area, and two thin pipes for the Control Plane on P1. Figure 14.2.5-1 gives an overview of the Slot Profile. Table 14.2.5-1 and Table 14.2.5-2 give the detailed pin assignments. For Module Profiles using this Slot Profile, see Section 16.2.5.


User DefinedUser Defined SE

DiffP2/J2

SE Diff

P1/J1

SEP0/J0


Utility Plane

Key

Key

Control Plane — 2 Thin PipesUser Defined

Figure 14.2.5-1 Payload Slot Profile SLT3-PAY-2F2T-14.2.5





Rule 14.2.5.2-1: There shall be pins allocated for two Control Plane Thin Pipes, CPtp01 and CPtp02, as given in Table 14.2.5-1, with usage complying with Rule 6.2.2-2 and Rule 6.2.2-3. [VM = I]


14.2.5.3 Data Plane

Rule 14.2.5.3-1: There shall be pins allocated for two Data Plane Fat Pipes, DP01 and DP02, as given in Table 14.2.5-1, with usage complying with Section 6.2.2. [VM = I]










Dat

a Pl

ane

Port

1

X8 x4

/ 2x

2 / 4





5

Dat

a Pl

ane

Port

2

x4 /

2x2

/ 4x1





9

Use

r Def

ined





13

Con

trol

Pla

ne

UD GND GND-J4 CPtp02-DB- CPtp02-DB+ GND GND-J4 CPtp02-DA- CPtp02-

DA+

14 GND CPtp02-DD-

CPtp02-DD+ GND-J4 GND CPtp02-DC- CPtp02-

DC+ GND-J4 GND

15 Maskable Reset* GND GND-J4 CPtp01-DB- CPtp01-

DB+ GND GND-J4 CPtp01-DA- CPtp01-DA+

16 GND CPtp01-DD-

CPtp01-DD+ GND-J4 GND CPtp01-DC- CPtp01-

DC+ GND-J4 GND







14.2.6 Payload Slot Profile SLT3-PAY-1D-14.2.6

This profile is for a 3U Payload Module configured as 1 Double Fat Pipe. Figure 14.2.6-1 gives an overview of this profile. Table 14.2.6-1 and Table 14.2.6-2 give the detail pin assignments. For Module Profiles using this Slot Profile, see Section 16.2.6.

f

Data Plane — 1 Double Fat Pipe

User Defined SE

DiffP2/J2

SE Diff

P1/J1

SEP0/J0


Utility Plane

Key

Key

User Defined

Figure 14.2.6-1 Payload Slot Profile SLT3-PAY-1D-14.2.6

14.2.6.1 Utility Plane – Pins on P0 and SE of P1



14.2.6.2 P1 - Data Plane

Rule 14.2.6.2-1: There shall be pins allocated for one Data Plane Double Fat Pipes on P1/J1, DP01, as given in Table 14.2.6-1, with usage complying with Section 6.2.2. [VM = T,I]





Table 14.2.6-1 Payload Slot Profile SLT3-PAY-1D-14.2.6 — P1 & J1 Plug-In Module P1



Dat

a Pl

ane

Port

1





5 SYS_CON* GND GND-J1 DP01-T4- DP01-T4+ GND GND-J1 DP01-R4- DP01-R4+




9

Use

r Def

ined





13 UD GND GND-J1 UD DP04-T0+ GND GND-J1 UD UD










14.2.7 Payload Slot Profile SLT3-PAY-2F-14.2.7

This Slot Profile is for a Utility and Data Plane only Payload Module. Figure 14.2.7-1 gives an overview of this profile. Table 14.2.7-1 and Table 14.2.7-2 give the detail pin assignments. For Module Profiles using this Slot Profile see, Section 16.2.7.


User Defined SE

DiffP2/J2

SE Diff

P1/J1

SEP0/J0


Utility Plane

Key

Key

User Defined

Figure 14.2.7-1 Payload Slot Profile SLT3-PAY-2F-14.2.7




14.2.7.2 Data Plane

Rule 14.2.7.2-1: There shall be pins allocated for two Data Plane Fat Pipes on P1/J1, DP01 and DP02, as given in Table 14.2.7-1, with usage complying with Section 6.2.2. . [VM = I]








Dat

a Pl

ane

Port

1





5

Dat

a Pl

ane

Port

2





9

Use

r def

ined
















This Slot Profile can be used as either as a Payload or Switch Slot.

Figure 14.2.8-1 gives an overview of this profile. Table 14.2.8-1 and Table 14.2.8-2 give the detail pin assignments. For Module Profiles using this Slot Profile, see Section 16.2.8 and Section 16.4.4.

Data Plane — 1 Fat Pipe & 4 Ultra-Thin Pipes

User Defined SE

DiffP2/J2

SE Diff

P1/J1

SEP0/J0


Utility Plane

Key

Key

User Defined





14.2.8.2 Data Plane

Rule 14.2.8.2-2 There shall be pins allocated for one Data Plane Fat Pipe on P1/J1, DP01, as given in Table 14.2.8-1, with usage complying with Section 6.2.2. [VM = I]

Rule 14.2.8.2-3: There shall be pins allocated for 4 Data Plane Ultra-Thin Pipes on P1/J1, DP02 – DP05, as given in Table 14.2.8-1, with usage complying with Section 6.2.2. [VM = I]








Dat

a Pl

ane

Port

1





5

Dat

a Pl

ane

Port

S 2

-5 SYS_CON* GND GND-J1 DP02-T- DP02-T+ GND GND-J1 DP02-R- DP02-R+


7 Reserved GND GND-J1 DP04-T- DP04-T+ GND GND-J1 DP04-R- DP04-R+


9

Use

r def

ined















14.2.9 Payload Slot Profile SLT3-PAY-8U-14.2.9

This Slot Profile is for a Utility and Data Plane only Payload Module. Figure 14.2.9-1 gives an overview of this profile. Table 14.2.9-1 and Table 14.2.9-2 give the detail pin assignments. For Module Profiles using this Slot Profile, see Section 16.2.9.

Data Plane — 8 Ultra-Thin Pipes

User Defined SE

DiffP2/J2

SE Diff

P1/J1

SEP0/J0


Utility Plane

Key

Key

User Defined

Figure 14.2.9-1 Payload Slot Profile SLT3-PAY-8U-14.2.9




14.2.9.2 Data Plane

Rule 14.2.9.2-1: There shall be pins allocated for 8 Data Plane Ultra-Thin Pipes on P1/J1, DP01 – DP08, as given in Table 14.2.9-1, with usage complying with Section 6.2.2. [VM = I]





Table 14.2.9-1 Payload Slot Profile SLT3-PAY-8U-14.2.9 — P1 & J1 Plug-In Module P1



Dat

a Pl

ane

Port

1 –

4 GDiscrete1 GND GND-J1 DP01-T+ DP01-T+ GND GND-J1 DP01-T+ DP01-T+

2 GND DP02-T+ DP02-T+ GND-J1 GND DP02-T+ DP02-T+ GND-J1 GND

3 P1-VBAT GND GND-J1 DP03-T+ DP03-T+ GND GND-J1 DP03-T+ DP03-T+


5

Dat

a Pl

ane

Port

5 –

8 SYS_CON* GND GND-J1 DP05-T+ DP05-T+ GND GND-J1 DP05-T+ DP05-T+


7 Reserved GND GND-J1 DP07-T+ DP07-T+ GND GND-J1 DP07-T+ DP07-T+


9

Use

r def

ined










Table 14.2.9-2 Payload Slot Profile SLT3-PAY-8U-14.2.9 — P2 & J2 Plug-In Module P2






The SLT3-PAY-1F1U payload Slot Profile contains one Data Plane Fat Pipe and one Control Plane Ultra-Thin Pipe on P1/J1. Figure 14.2.10-1 provides an overview of the Slot Profile. Table 14.2.10-1 and Table 14.2.10-2 provide the pin assignments.

SE

DiffP2/J2

SE

SEP0/J0

Control Plane — 1 Ultra-Thin Pipe

User Defined

User Defined

User defined

User Defined

Data Plane — 1 Fat PipeUtility Plane

Utility Plane

Key

Key

DiffP1/J1

Reserved

Reserved






Rule 14.2.10.2-1: There shall be pins allocated for one Control Plane Ultra-Thin Pipe on P1/J1, CPutp01, as given in Table 14.2.10-1, with usage complying with Section 6.2.2 [VM = I]

Rule 14.2.10.2-2: The differential pair pins on P1/J1 wafer 15 shall be reserved. [VM = I]






Rule 14.2.10.3-3: The differential pair pins on P1/J1 wafers 5 - 8 shall be reserved. [VM = I]








Dat

a Pl

ane

Port

1

x4/ 2

x2/ 4





5

Res

erve

d

SYS_CON* GND GND-J1 Reserved Reserved GND GND-J1 Reserved Reserved

6 GND Reserved Reserved GND-J1 GND Reserved Reserved GND-J1 GND

7 Reserved GND GND-J1 Reserved Reserved GND GND-J1 Reserved Reserved

8 GND Reserved Reserved GND-J1 GND Reserved Reserved GND-J1 GND

9

Use

r Def

ined







15 Re-served

Maskable Reset* GND GND-J1 Reserved Reserved GND GND-J1 Reserved Reserved

16 Control Plane GND CPutp01-

TD- CPutp01-TD+ GND-J1 GND CPutp01-



Table 14.2.10-2 Payload Slot Profile SLT3-PAY-1F1U-14.2.10 — P2 & J2 Plug-In Mod P2






The SLT3-PAY-2F4F2U-14.2.11 Payload Slot Profile contains 2 Data Plane Fat Pipes and 32 pairs of Expansion Plane (frequently used as 4 Fat Pipes of Expansion Plane) and two Ultra-Thin Pipes for the Control Plane. Figure 14.2.11-1 provides an overview of the Slot Profile. Table 14.2.11-1 and Table 14.2.11-2 provide the pin assignments. For Module Profiles using this Slot Profile, see Section 16.2.10. This Slot Profile is the same as SLT3-PAY-2F1F2U-14.2.1, except that it adds 24 more pairs to the Expansion Plane. Notice that a Plug-In Module that complies with this Slot Profile will also comply with SLT3-PAY-2F1F2U-14.2.1 — the additional Expansion Plane lanes of this Slot Profile are User Defined with SLT3-PAY-2F1F2U-14.2.1.

User Defined


Expansion Plane — 24 pairs (EP15:EP04)SE

DiffP2/J2

SE

DiffP1/J1

SEP0/J0


Utility Plane

Key

Key

User Defined


Expansion Plane — 8 pairs (EP03:EP00)User Defined















Rule 14.2.11.4-3: If the Expansion Plane is broken into pipes, the Expansion Plane Lanes shall be assigned pipes following one of the options given in Table 6.2.4.2-3, with usage complying with Section 6.2.2. [VM = I]












Dat

a Pl

ane

Port

1

X8 x4

/ 2x

2 / 4


GND DP01-TD1- DP01-TD1+ GND-J1 GND DP01-RD1- DP01-RD1+ GND-J1 GND



5

Dat

a Pl

ane

Port

2

x4 /

2x2

/ 4x1





9

X16

usin

g [1

5:0]

x8 u

sing

[7:0

]

X4 u

sing

[3:0

] UD GND GND-J1 EP00-TD- EP00-TD+ GND GND-J1 EP00-RD- EP00-RD+




13

Use

r D

efin

ed


14 GND UD UD GND-J1 GND-J1 UD UD GND-J1 GND

15

Con

trol

Pl

ane



RD- CPutp02-RD+

16 GND CPutp01-TD-

CPutp01-TD+ GND-J1 GND-J1 CPutp01-







Expa

nsio

n Pl

ane

X16

usin

g [1

5:0]

x8 u

sing

[7:0

]

x4 u

sing

[7:3





5

x8 u

sing

[15:

8]

x4 u

sing

[11:





9

x4 u

sing

[15:





13

Use

r Def

ined







The SLT3-PAY-1F2U-14.2.12 Payload Slot Profile contains one Fat Pipe Data Plane port, user defined area, and two Ultra-Thin Pipes Control Plane ports on P1/J1. Figure 14.2.12-1 provides an overview of the Slot Profile. Table 14.2.12-1 and Table 14.2.12-2 provide the pin assignments. For Module Profiles using this Slot Profile, see Section 16.2.11.


Key

Key


User Defined

User Defined

DiffP1/J1

SE

DiffP2/J2

SE

SEP0/J0


Utility Plane

User Defined








Rule 14.2.12.3-1: There shall be pins allocated for one Data Plane Fat Pipes on P1/J1, DP01, as given in Table 14.2.12-1, with usage complying with Section 6.2.2. [VM = I]


Permission 14.2.12.3-1: The lanes of the Data Plane Fat Pipe, may be repartitioned.






Table 14.2.12-1 Payload Slot Profile SLT3-PAY-1F2U-14.2.12— P1 & J1 Plug-in module P1



Dat

a Pl

ane

Port

1

1x4

/ 2x2

/ 4x

1 GDiscrete1 GND GND-J1 DP01-TD0- DP01-TD0+ GND GND-J1 DP01-RD0- DP01-RD0+




5

Use

r Def

ined











15

Con

trol

Pl

ane



RD- CPutp02-RD+

16 GND CPutp01-TD-




Table 14.2.12-2 Payload Slot Profile SLT3-PAY-1F2U-14.2.12— P2 & J2 Plug-in mod P2






The SLT3-PAY-3F2U-14.2.13 Payload Slot Profile contains three Fat Pipes (three Data Plane ports), user defined area, and two Ultra-Thin Pipes on the Control Plane on P1/J1. Figure 14.2.13-1 provides an overview of the Slot Profile. Table 14.2.13-1 and Table 14.2.13-2 provide the pin assignments. For Module Profiles using this Slot Profile, see Section 16.2.12.


Key

Control Plane — 2 Ultra-Thin PipesUser Defined

User Defined

DiffP1/J1

SE

DiffP2/J2

SE

SEP0/J0


Utility Plane

Key

User Defined









Rule 14.2.13.3-1: There shall be pins allocated for three Data Plane Fat Pipes on P1/J1, DP01 thru DP03, as given in Table 14.2.13-1, with usage complying with Section 6.2.2. [VM = I]

Permission 14.2.13.3-1: The lanes of the three Data Plane Fat Pipes, may be repartitioned.

Rule 14.2.13.3-2: If the Data Plane Fat Pipes DP01 thru DP02 are repartitioned, they shall be repartitioned as one of the options shown in Table 6.2.4.1-2, with usage complying with Section 6.2.2. [VM = I]

Rule 14.2.13.3-3: If the Data Plane Fat Pipes DP03 is repartitioned, it shall be repartitioned as one of the options shown in Table 6.2.4.1-1, with usage complying with Section 6.2.2. [VM = I]





Table 14.2.13-1 Payload Slot Profile SLT3-PAY-3F2U-14.2.13 — P1 & J1 Plug-in module P1



Dat

a Pl

ane

Port

1

X8 1x

4 / 2

x2 /

4x1 GDiscrete1 GND GND-J1 DP01-TD0- DP01-TD0+ GND GND-J1 DP01-RD0- DP01-RD0+




5

Dat

a Pl

ane

Port

2

1x4

/ 2x2

/ 4x

1 SYS_CON* GND GND-J1 DP02-TD0- DP02-TD0+ GND GND-J1 DP02-RD0- DP02-RD0+




9

Dat

a Pl

ane

Port

3

1x4

/ 2x2

/ 4x

1 UD GND GND-J1 DP03-TD0- DP03-TD0+ GND GND-J1 DP03-RD0- DP03-RD0+




13

Use

r D

ef. UD GND GND-J1 UD UD GND GND-J1 UD UD


15

Con

trol

Pl

ane



RD- CPutp02-RD+

16 GND CPutp01-TD-




Table 14.2.13-2 Payload Slot Profile SLT3-PAY-3F2U-14.2.13 — P2 & J2 Plug-in mod P2





14.3 Peripheral Slot Profiles Using VITA 46.0 Connectors



The Peripheral Slot Profile SLT3-PER-2F contains 2 Fat Pipes and user defined areas. Figure 14.3.1-1 gives an overview of the Slot Profile. Table 14.3.1-1 and Table 14.3.1-2 give the detailed pin assignments. For Module Profiles using this Slot Profile, see Section 16.3.1.


User Defined

User Defined SE

DiffP2/J2

SE Diff

P1/J1

SEP0/J0


Utility Plane

Key

Key





14.3.1.2 Data Plane

Rule 14.3.1.2-1: There shall be pins allocated for two Data Plane Fat Pipes, DP01 and DP02, as given in Table 14.3.1-1, with usage complying with Section 6.2.2. [VM = I]








Dat

a Pl

ane

Port





5

Dat

a Pl

ane

Port

2





9

Use

r Def

ined
















Slot Profile is for a Utility and Data Plane only Peripheral Slot configured with one Fat Pipe as shown in Figure 14.3.2-1. Detailed pin assignments are shown in Table 14.3.2-1 and Table 14.3.2-2 . For Module Profiles using this Slot Profile, see Section 16.3.2.


User Defined SE

DiffP2/J2

SE Diff

P1/J1

SEP0/J0


Utility Plane

Key

Key

User Defined





14.3.2.2 Data Plane









Dat

a Pl

ane

Port

1





5

Use

r def

ined



















14.3.3 Peripheral Slot Profile SLT3-PER-1U-14.3.3

Slot Profile is for a Utility and Data Plane only Peripheral Slot configured with one Ultra-Thin Pipe as shown in Figure 14.3.3-1. Detailed pin assignments are shown in Table 14.3.3-1 and Table 14.3.3-2. For Module Profiles using this Slot Profile, see Section 16.3.3.

Data Plane — 1 Ultra-Thin Pipe

User Defined SE

DiffP2/J2

SE Diff

P1/J1

SEP0/J0


Utility Plane

Key

Key

User Defined

Figure 14.3.3-1 Peripheral Slot Profile SLT3-PER-1U-14.3.3



Rule 14.3.3.1-1: The Utility Plane shall be implemented as described in Table 3.7-1 and Table 3.7-2 for P0/J0, and Table 14.3.3-1 for single ended pins of P1/J1. [VM = I, T]

14.3.3.2 Data Plane

Rule 14.3.3.2-1: There shall be pins allocated for one Data Plane Ultra-Thin pipe on P1/J1, DP01, as given in Table 14.3.3-1, with usage complying with Section 6.2.2. [VM = T,I]








1 Port 1 GDiscrete1 GND GND-J1 DP01-T0- DP01-T0+ GND GND-J1 DP01-R0- DP01-R0+

2

Use

r def

ined

GND UD UD GND-J1 GND UD UD GND-J1 GND

3 P1-VBAT GND GND-J1 DU DU GND GND-J1 UD UD


5 SYS_CON* GND GND-J1 UD UD GND GND-J1 UD UD


















14.4 Switch Slot Profiles Using VITA 46.0 Connectors


14.4.1 Switch Slot Profile SLT3-SWH-6F6U-14.4.1

The SLT3-SWH-6F6U-14.4.1 is an integrated switch Slot Profile consisting of six Fat Pipes and six Ultra-Thin Pipes on the Data Plane and Control Plane respectively. There is also one Thin Pipe recommended on the user defined pins on the P2/J2 connector. Figure 14.4.1-1 provides an overview of the Slot Profile. Table 14.4.1-1 and Table 14.4.1-2 provide the pin assignments. For Module Profiles using this Slot Profile, see Section 16.4.1.

Data plane – 6 Fat Pipes

DiffP1

SE

DiffP2

SE

SEP0

User Defined

User defined

Utility Plane

Utility Plane

Key

Key

Control Plane — 6 Ultra-Thin PipesUser Defined

Figure 14.4.1-1 Switch Slot Profile SLT3-SWH-6F6U-14.4.1



Rule 14.4.1.1-1: The Utility Plane shall be implemented as described in Table 3.7-1 and Table 3.7-2 for P0/J0, and Table 14.4.1-1 for SE pins of P1/J1. [VM = I]



14.4.1.2.1 Ultra-Thin Pipes for Connection to 3U Payload Slots

Rule 14.4.1.2.1-1: There shall be pins allocated for five Control Plane Ultra-Thin Pipes on P2/J2, CPutp01 through CPutp05, as given in Table 14.4.1-2, with usage complying with Section 6.2.2. [VM = I]

Rule 14.4.1.2.1-2: There shall be pins allocated for one Control Plane Ultra-Thin Pipe, CSutp01, as given in Table 14.4.1-2, with usage complying with Section 6.2.2. [VM = I]

Rule 14.4.1.2.1-3: If there is a connection between Switch Slots, it shall use CSutp01. [VM = I]

Permission 14.4.1.2.1-1: Backplane Profiles that require more connections to Payload Slots than the number of Payload Ports available may use CSutp01, for a connection to a Payload Slot.

Observation 14.4.1.2.1-1: Port intended to be used as crossover connections between Switch Slots might have the option of running at a higher signaling rate than ports to Payload Slots and/or might have some protocol properties, which are different, such as Ethernet stacking ports.

14.4.1.3 Data Plane

Rule 14.4.1.3-1: There shall be pins allocated for four Data Plane Fat Pipes on P1/J1 and one on P2/J2, DP01 through DP05, as given in Table 14.4.1-1 and Table 14.4.1-2, with usage complying with Section 6.2.2 [VM = I]

Rule 14.4.1.3-2: There shall be pins allocated for one Data Plane Fat Pipe, DS01, as given in Table 14.4.1-2, with usage complying with Section 6.2.2. [VM = I]

Rule 14.4.1.3-3: If there is a connection between Switch Slots, it shall use DS01. [VM = I]

Permission 14.4.1.3-1: Backplane Profiles that require more connections to Payload Slots than the number of Payload Ports available may use DS01, for a connection to a Payload Slot.


Permission 14.4.1.3-2: The lanes of each Data Plane Fat Pipes, may be repartitioned.

Rule 14.4.1.3-4: If the Data Plane Fat Pipes are repartitioned, they shall each be repartitioned as one of the options shown in Table 6.2.4.1-1, with usage complying with Section 6.2.2. [VM = I]




14.4.1.4.1 Recommended Thin Pipe Intended for External Connection

Recommendation 14.4.1.4.1-1: If an external connection to the Switch is required, it should utilize the User Defined (Thin Pipe) differential pins on P2/J2 (Thin Pipes) as shown in Table 14.4.1-3. [VM = I]

Rule 14.4.1.4.1-1: If Recommendation 14.4.1.4.1-1 is followed, a Thin Pipe shall be mapped to P2/J2 as given in Table 14.4.1-3 . [VM = I]

Table 14.4.1-1 Switch Slot Profile SLT3-SWH-6F6U-14.4.1 — P1 & J1 Plug-In Module P1



Dat

a Pl

ane

Port

1





5

Dat

a Pl

ane

Port

2





9

Dat

a Pl

ane

Port

3

UD GND GND-J1 DP03-TD0- DP03-TD0+ GND GND-J1 DP03-RD0- DP03-RD0+




13

Dat

a Pl

ane

Port

4



15 Maskable Reset* GND GND-J1 DP04-TD2- DP04-TD2+ GND GND-J1 DP04-RD2- DP04-RD2+







Dat

a Pl

ane

Port

5





5

Dat

a Pl

ane

Por

t 6

UD GND GND-J2 DS01-TD0- DS01-TD0+ GND GND-J2 DS01-RD0- DS01-RD0+

6 GND DS01-TD1- DS01-TD1+ GND-J2 GND DS01-RD1- DS01-RD1+ GND-J2 GND

7 UD GND GND-J2 DS01-TD2- DS01-TD2+ GND GND-J2 DS01-RD2- DS01-RD2+


9

Con

trol

Pla

ne

Port

s 1

- 6

UD GND GND-J2 CSutp01-TD-

CSutp01-TD+ GND GND-J2 CSutp01-

RD- CSutp01-RD+

10 GND CPutp05-TD-



11 UD GND GND-J2 CPutp04-TD-

CPutp04-TD+ GND GND-J2 CPutp04-

RD- CPutp04-RD+

12 GND CPutp03-TD-





RD- CPutp02-RD+

14 GND CPutp01-TD-



15

UD




Table 14.4.1-3 User Defined Pins for Thin Pipe — P2 & J2 Plug-In Mod P2



For the rest of the pin assignments see Table 14.4.1-2. 15 UD GND GND-J2 CPtp01-DB- CPtp01-DB+ GND GND-J2 CPtp01-DA- CPtp01-DA+




The SLT3-SWH-8F-14.4.2 consists of all Data Plane ports, eight altogether. This Slot Profile does not have any Control Plane ports. Figure 14.4.2-1 provides an overview of the Slot Profile. Table 14.4.2-1 and Table 14.4.2-2 provide the pin assignments. For Module Profiles using this Slot Profile, see Section 16.4.2.

Data plane – 8 Fat Pipes

DiffP1/J1

SE

DiffP2/J2

SE

SEP0/J0

User Defined

User defined

Utility Plane

Utility Plane

Key

Key





14.4.2.2 Data Plane

Rule 14.4.2.2-1: There shall be pins allocated for seven Data Plane Fat Pipes, DP01 through DP07, as given in Table 14.4.2-1 and Table 14.4.2-2, with usage complying with Section 6.2.2. [VM = I]







Dat

a Pl

ane

Port

1





5

Dat

a Pl

ane

Port

2





9

Dat

a Pl

ane

Port

3





13

Dat

a Pl

ane

Port

4









Dat

a Pl

ane

Port

5

UD GND GND DP05-TD0- DP05-TD0+ GND GND DP05-RD0- DP05-RD0+

2 GND DP05-TD1- DP05-TD1+ GND GND DP05-RD1- DP05-RD1+ GND GND

3 UD GND GND DP05-TD2- DP05-TD2+ GND GND DP05-RD2- DP05-RD2+


5

Dat

a Pl

ane

Port

6





9

Dat

a Pl

ane

Port

7





13

Dat

a Pl

ane

Port

8

UD GND GND DS01-TD0- DS01-TD0+ GND GND DS01-RD0- DS01-RD0+

14 GND DS01-TD1- DS01-TD1+ GND GND DS01-RD1- DS01-RD1+ GND GND

15 UD GND GND DS01-TD2- DS01-TD2+ GND GND DS01-RD2- DS01-RD2+

16 GND DS01-TD3- DS01-TD3+ GND GND DS01-RD3- DS01-RD3+ GND GND



The SLT3-SWH-2F24U Slot Profiles consists of all Control Plane ports, with 2 Fat Pipes and 24 Ultra-Thin Pipes. This Slot Profile does not have any data plane ports. Figure 14.4.3-1, gives an overview of the Slot Profile. Table 14.4.3-1 and Table 14.4.3-2 give the detailed pin assignments. For Module Profiles using this Slot Profile, see Section 16.4.3.


SE

Control Plane — 2 Fat Pipes

SEP0/J0


Utility Plane

Key

Key

User Defined

SE Diff

P1/J1

DiffP2/J2






14.4.3.2.1 Fat Pipes for External Connections

Rule 14.4.3.2-1: There shall be pins allocated for 2 Control Plane Fat Pipes, CP01 and CP02, as given in Table 14.4.3-1, with usage complying with Section 6.2.2. [VM = I]


14.4.3.2.2 Ultra-Thin Pipes for Connection to Payload Slots

Rule 14.4.3.2.2-1: There shall be pins allocated for 24 Control Plane Ultra-Thin Pipes, CPutp01 thru CPutp24, as given in Table 14.4.3-1 and Table 14.4.3-2, with usage complying with Section 6.2.2. [VM = I]

Rule 14.4.3.2.2-2: If some number of Control Plane ports are more appropriate for being used as crossover connections to other Switch Slots, these crossover ports shall start with CPutp01 and work up. [VM = I]

Rule 14.4.3.2.2-3: Any ports that are intended for use as crossover connections shall also be capable of being connected to Payload Slots. [VM = I]

Observation 14.4.3.2.2-1: Ports intended to be used as crossover connections between Switch Slots might have the option of running at a higher signaling rate than ports to Payload Slots and/or might have some protocol properties, which are different, such as Ethernet stacking ports.







Con

trol

Pla

ne

Port

1

GDiscrete1 GND GND-J1 CP01-T0- CP01-T0+ GND GND-J1 CP01-R0- CP01-R0+


3 P1-VBAT GND GND-J1 CP01-T2- CP01-T2+ GND GND-J1 CP01-R2- CP01-R2+


5

Con

trol

Pla

ne

Port

2

SYS_CON* GND GND-J1 CP02-T0- CP02-T0+ GND GND-J1 CP02-R0- CP02-R0+


7 Reserved GND GND-J1 CP02-T2- CP02-T2+ GND GND-J1 CP02-R2- CP02-R2+


9

Con

trol

Pla

ne

Port

s 1

- 8

UD GND GND-J1 CPutp01-TD-


RD- CPutp01-RD+

10 GND CPutp02-TD-





TD- CPutp03-TD+

12 GND CPutp04-TD-





TD- CPutp05-TD+

14 GND CPutp06-TD-



15 Maskable Reset* GND GND-J1 CPutp07-


TD- CPutp07-TD+

16 GND CPutp08-TD-








1

Con

trol

Pla

ne P

ort 9

- 24

UD GND GND-J2 CPutp09-TD-


RD- CPutp09-RD+

2 GND CPutp10-TD-





RD- CPutp11-RD+

4 GND CPutp12-TD-





RD- CPutp13-RD+

6 GND CPutp14-TD-





RD- CPutp15-RD+

8 GND CPutp16-TD-





RD- CPutp17-RD+

10 GND CPutp18-TD-





RD- CPutp19-RD+

12 GND CPutp20-TD-





RD- CPutp21-RD+

14 GND CPutp22-TD-





RD- CPutp23-RD+

16 GND CPutp24-TD-





The primary purpose of this Switch Slot Profile is to support the expansion of master-slave fabrics such as PCI-express although in no way do we suggest that this is the only use.

This profile is for a 3U Switch Module configured with four Fat Pipes as shown in Figure 14.4.4-1. A detailed pin assignment is shown in Table 14.4.4-1 and Table 14.4.4-2. For Module Profiles using this Slot Profile, see Section 16.4.5.

DiffP1/J1

User Defined

SEP0/J0

SE

SE


Utility Plane

Key

Key

User Defined

Data Plane 4 Fat Pipes

DiffP2/J2





14.4.4.2 Data Plane









Dat

a Pl

ane

Port

1





5

Dat

a Pl

ane

Port

2





9

Dat

a Pl

ane

Port

3





13

Dat

a Pl

ane

Port

4












The primary purpose of this Switch Slot Profile is to support the expansion of master-slave fabrics such as PCI-express although in no way is it suggested that this is the only use.

This 3U Switch Profile is configured as two Fat and eight Ultra-Thin Pipes as shown in Figure 14.4.5-1. A detailed pin assignment is shown in Table 14.4.5-1 and Table 14.4.5-2. For Module Profiles using this Slot Profile, see Section 16.4.6.

User Defined

SEP0/J0

SE

SE


Utility Plane

Key

Key

User Defined

Data Plane 2 Fat Pipes and 8 Ultra Thin Pipes

DiffP1/J1

DiffP2/J2


Permission 14.4.5-1: This profile may also be used for a Control Plane switch. In this usage, the two Fat Pipes are intended for external connections and the eight Ultra-Thin Pipes are intended for connection to Payload Slots.



Rule 14.4.5.1-1: The Utility Plane shall be implemented as described in Table 3.7-1 and Table 3.7-2 for P0/J0, and Table 14.4.5-1 for single ended pins of P1/J1. [VM = I, T]


14.4.5.2 Data Plane

Rule 14.4.5.2-1: There shall be pins allocated for 2 Data Plane Fat Pipes on P1/J1, DP01 and DP02, as given in Table 14.4.5-1, with usage complying with Section 6.2.2. [VM = I]

Rule 14.4.5.2-4: There shall be pins allocated for 8 Data Plane Ultra-Thin Pipes on P1/J1, DPutp01 – DPutp08, as given in Table 14.4.5-1, with usage complying with Section 6.2.2. [VM = I]

Observation 14.4.5.2-1: When used for PCI-express switching DP01 is intended to connect to the root while DP02 can be connected to another switch or high speed Peripheral slot. See 15.2.12 for an example and Section 5.3 for more detail on Root Complex.








Dat

a P

lane

Po

rt 1





5

Dat

a Pl

ane

Port

2





9

Dat

e Pl

ane

Ultr

a-Th

in P

orts

1 -

8

UD GND GND-J1 DPutp01-TD-

DPutp01-TD+ GND GND-J1 DPutp01-

RD- DPutp01-RD+

10 GND DPutp02-TD-

DPutp02-TD+ GND-J1 GND DPutp02-

RD- DPutp02-RD+ GND-J1 GND

11 UD GND GND-J1 DPutp03-TD-


RD- DPutp03-RD+

12 GND DPutp04-TD-



13 UD GND GND-J1 DPutp05-TD-


RD- DPutp05-RD+

14 GND DPutp06-TD-



15 Maskable Reset* GND GND-J1 DPutp07-

TD- DPutp07-TD+ GND GND-J1 DPutp07-

RD- DPutp07-RD+

16 GND DPutp08-TD-









14.4.6 Switch Slot Profile SLT3-SWH-16T-14.4.6

This profile is for a 3U Switch Module configured with 16 Thin Pipes as shown in Figure 14.4.6-1. A detailed pin assignment is shown in Table 14.4.6-1 and Table 14.4.6-2. The intent of this profile is to provide a 1000BASE-T Switch and requires no routing of Data Plane signals within the backplane. For Module Profiles using this Slot Profile, see Section 16.4.7.

User Defined

SEP0/J0

SE

SE


Utility Plane

Key

Key

16 Thin Pipes

DiffP1/J1

DiffP2/J2

Figure 14.4.6-1 Switch Slot Profile SLT3-SWH-16T-14.4.6




14.4.6.2 Other Signals

Rule 14.4.6.2-1: There shall be pins allocated for 16 Thin Pipes on P1/J1 and P2/J2, TP01 – TP16, as given in Table 14.4.6-1 and Table 14.4.6-2, with usage complying with Rule 6.2.2-2 and Rule 6.2.2-3. [VM = I, T]


Table 14.4.6-1 Switch Slot Profile SLT3-SWH-16T-14.4.6 — P1& J1 Plug-In Module P1



8 Th

in P

ipes

GDiscrete1 GND GND-J1 TP01-DB- TP01-DB+ GND GND-J1 TP01-DA- TP01-DA+

2 GND TP01-DD- TP01-DD+ GND-J1 GND TP01-DC- TP01-DC+ GND-J1 GND

3 P1-VBAT GND GND-J1 TP02-DB- TP02-DB+ GND GND-J1 TP02-DA- TP02-DA+


5 SYS_CON* GND GND-J1 TP03-DB- TP03-DB+ GND GND-J1 TP03-DA- TP03-DA+


7 Reserved GND GND-J1 TP04-DB- TP04-DB+ GND GND-J1 TP04-DA- TP04-DA+


9 UD GND GND-J1 TP05-DB- TP05-DB+ GND GND-J1 TP05-DA- TP05-DA+






15 Maskable Reset* GND GND-J1 TP08-DB- TP08-DB+ GND GND-J1 TP08-DA- TP08-DA+


Warning: Tables combine Plug-In Module & Backplane pin assignments, see Section 6.3.1

Table 14.4.6-2 Switch Slot Profile SLT3-SWH-16T-14.4.6 — P2 & J2 Plug-In Module P2



8 Th

in P

ipes

UD GND GND-J2 TP09-DB- TP09-DB+ GND GND-J2 TP09-DA- TP09-DA+


















This profile is for a 3U Switch Module configured with 1 Fat Pipe and 14 Thin Pipes as shown in Figure 14.4.7-1. A detailed pin assignment is shown in Table 14.4.7-1 and Table 14.4.7-2. The intent of the Thin Pipes in this profile is to provide a 1000BASE-T Switch. For Module Profiles using this Slot Profile, see Section 16.4.8.

User Defined

SEP0/J0

SE

SE


Utility Plane

Key

Key

14 Thin Pipes

Data Plane 1 Fat PipeDiffP1/J1

DiffP2/J2





14.4.7.2 Data Plane

Rule 14.4.7.2-1: There shall be pins allocated for one Data Plane Fat Pipe on P1/J1, DP01, as given in Table 14.2.7-1. [VM = I]



Rule 14.4.7.3-1: There shall be pins allocated for 14 Thin Pipes on P1/J1 and P2/J2, TP01 – TP14, as given Table 14.4.7-1 and Table 14.4.7-2, with usage complying with Rule 6.2.2-2 and Rule 6.2.2-3. [VM = I]

Permission 14.4.7.3-1: Thin Pipes are not required to be routed within the backplane unless otherwise specified by the use case.




Table 14.4.7-1 Switch Slot Profile SLT3-SWH-1F14T-14.4.7 — P1& J1 Plug-In Module P1



Dat

a Pl

ane

Port

1





5

6 Th

in P

ipes

SYS_CON* GND GND-J1 TP01-DB- TP01-DB+ GND GND-J1 TP01-DA- TP01-DA+


7 Reserved GND GND-J1 TP02-DB- TP02-DB+ GND GND-J1 TP02-DA- TP02-DA+














8 Th

in P

ipes



















This profile is for a 3U Switch Module configured with 2 Fat Pipe and 12 Thin Pipes as shown in Figure 14.4.8-1. A detailed pin assignment is shown in Table 14.4.8-1 and Table 14.4.8-2. The intent of the Thin Pipes in this profile is to provide a 1000BASE-T Switch. For Module Profiles using this Slot Profile, see Section 16.4.9.

12 Thin Pipes


User Defined

SEP0/J0

SE

SE


Utility Plane

Key

Key

DiffP1/J1

DiffP2/J2





14.4.8.2 Data Plane

Rule 14.4.8.2-1: There shall be pins allocated for two Data Plane Fat Pipe on P1/J1, DP01 and DP02, as given in Table 14.4.8-1, with usage complying with Section 6.2.2. [VM = I]

Observation 14.4.8.2-1: Data Ports DP01 & DP02 can be used in a variety of ways. For example they can be used to round-robin or daisy chain switches together, or one port might


be used to connect to a controller using PCIe while the other port is used for inter-switch crossover. Use will be determined by Backplane and Module Profiles.


Rule 14.4.8.3-1: There shall be pins allocated for 12 Thin Pipes on P1/J1 and P2/J2, TP01 – TP12, as given in Table 14.4.8-1 and Table 14.4.8-2, with usage complying with Rule 6.2.2-2 and Rule 6.2.2-3. [VM = I]

Observation 14.4.8.3-1: Thin Pipes are frequently connected to cables instead of being routed in the backplane.




Table 14.4.8-1 Switch Slot Profile SLT3-SWH-2F12T-14.4.8 — J1 & P2 Plug-In Module P1



Dat

a Pl

ane

Port

1





5

Dat

a Pl

ane

Port

2





9

4 Th

in P

ipes










Table 14.4.8-2 Switch Slot Profile SLT3-SWH-2F12T-14.4.8 — P2& J2 Plug-In Module P2



8 Th

in P

ipes



















The SLT3-SWH-6F8U-14.4.9 is an integrated switch Slot Profile consisting of six Fat Pipes and eight Ultra-Thin Pipes on the Data Plane and Control Plane respectively. There is also one Thin Pipe recommended on the user defined pins on the P2/J2 connector. Figure 14.4.9-1 provides an overview of the Slot Profile. Table 14.4.9-1 and Table 14.4.9-2 provide the pin assignments. For Module Profiles using this Slot Profile, see Section 16.4.10.

DiffP1/J1


SE

DiffP2/J2

SE

SEP0/J0


Utility Plane

Key

Key

User DefinedControl Plane — 8 Ultra-Thin Pipes




Rule 14.4.9.1-1: The Utility Plane shall be implemented as described in Table 3.7-1 and Table 3.7-2 for P0/J0, and Table 14.4.1-1 for SE pins of P1/J1. [VM = I]

14.4.9.2 Control Plane Ultra-Thin Pipes for Connection to 3U Payload Slots

Rule 14.4.9.2-1: There shall be pins allocated for seven Control Plane Ultra-Thin Pipes on P2/J2, CPutp01 through CPutp07, as given in Table 14.4.9-2, with usage complying with Section 6.2.2. [VM = I]

Rule 14.4.9.2-2: There shall be pins allocated for one Control Plane Ultra-Thin Pipe, CSutp01, as given in Table 14.4.9-2, with usage complying with Section 6.2.2. [VM = I]


Rule 14.4.9.2-3: If there is a connection between Switch Slots, it shall use CSutp01. [VM = I]

Permission 14.4.9.2-1: Backplane Profiles that require more connections to Payload Slots than the number of Payload Ports available may use CSutp01, for a connection to a Payload Slot.

Observation 14.4.9.2-1: Port intended to be used as crossover connections between Switch Slots might have the option of running at a higher signaling rate than ports to Payload Slots and/or might have some protocol properties, which are different, such as Ethernet stacking ports.

14.4.9.3 Data Plane

Rule 14.4.9.3-1: There shall be pins allocated for four Data Plane Fat Pipes on P1/J1 and one on P2/J2, DP01 through DP05, as given in Table 14.4.9-1 and Table 14.4.9-2, with usage complying with Section 6.2.2 [VM = I]










14.4.9.4.1 Recommended Thin Pipe Intended for External Connection

Recommendation 14.4.9.4.1-1: If an external connection to the Switch is required, it should utilize the User Defined (Thin Pipe) single-ended pins on P2/J2 (Thin Pipes) as recommended in section 6.3.3.2 and shown in Table 6.3.3.2-1. [VM = I]

Rule 14.4.9.4.1-1: If Recommendation 14.4.9.4.1-1 is followed, a Thin Pipe shall be mapped to P2/J2 as given in Table 6.3.3.2-1. [VM = I]




Dat

a Pl

ane

Port

1





5

Dat

a Pl

ane

Port

2





9

Dat

a Pl

ane

Port

3





13

Dat

a Pl

ane

Port

4










Dat

a Pl

ane

Port

5





5

Dat

a Pl

ane

Por

t 6

UD GND GND-J2 DS01-TD0- DS01-TD0+ GND GND-J2 DS01-RD0- DS01-RD0+


7 UD GND GND-J2 DS01-TD2- DS01-TD2+ GND GND-J2 DS01-RD2- DS01-RD2+


9

Con

trol

Pla

ne

Port

s 1

- 8

UD GND GND-J2 CSutp01-TD-

CSutp01-TD+ GND GND-J2 CSutp01-

RD- CSutp01-RD+

10 GND CPutp05-TD-





RD- CPutp04-RD+

12 GND CPutp03-TD-





RD- CPutp02-RD+

14 GND CPutp01-TD-



15 UD GND GND-J2 Cputp07-TD-

Cputp07-TD+ GND GND-J2 Cputp07-

RD- Cputp07-RD+

16 GND CPutp06-TD-




14.5 3U Miscellaneous Slot Profiles Using VITA 46.0 Connectors



14.5.1 Storage Slot Profile SLT3-STO-2U-14.5.1

This profile is for a 3U Storage Module configured with 2 Ultra-Thin Pipes as shown in Figure 14.5.1-1. A detailed pin assignment is shown in Table 14.5.1-1. The profile supports serial storage protocols such as SATA and SAS.

This profile can also be combined with other Slot Profiles in order to support multi-function modules that have storage as one of their functions. For Module Profiles using this Slot Profile, see Section 16.5.1.

2 Ultra Thin Pipes (Storage Interface)

Utility Plane

Utility Plane

SEP0/J0

Key

DiffP1/J1

SE

SE

DiffP2/J2

Key

Reserved unless combined with another Profile

Reserved unless ...

Reserved ...

Reserved unless ...

Figure 14.5.1-1 Storage Slot Profile SLT3-STO-2U-14.5.1





14.5.1.2 P1 - Data Plane

Rule 14.5.1.2-1: If this profile is used on its own then the differential pairs on P1 wafers 1-8 shall be No Connect and reserved. [VM = I]

Permission 14.5.1.2-1: This profile may be combined with other Slot Profile(s) in order to support multi-function modules.

Rule 14.5.1.2-2: If this profile is combined with other Slot Profile(s) then the Data Plane connections of the other Slot Profile(s) shall apply. [VM = I]

Permission 14.5.1.2-2: This profile does not have a Data Plane connection but may be combined with other Slot Profile(s) that do have Data Plane connections.

14.5.1.3 Storage Interface(s)

Rule 14.5.1.3-1: There shall be pins allocated for 2 Ultra-Thin pipes on P1/J1, STRutp1 and STRutp2, as given in Table 14.5.1-1. [VM = I]

Permission 14.5.1.3-1: Either one or two Storage interfaces may be implemented.

Rule 14.5.1.3-2: If only one storage interface is implemented then it shall be on P1 wafer 9 (STRutp1) and P1 wafer 10 (STRutp2) shall be No Connect and reserved. [VM = I]

Observation 14.5.1.3-1: This profile supports serial storage protocols that can be implemented on an Ultra-Thin Pipe. Examples include SATA and SAS.

Permission 14.5.1.3-2: The storage interface signals may either be routed in the backplane or may be wired to the RTM.

Observation 14.5.1.3-2: The two Ultra-Thin Pipes are intended for use as storage interfaces.


Rule 14.5.1.4-1: If this profile is used on its own then the differential pairs on P1/J1 wafers 11-16, the single-ended signals on P1/J1 wafers 9, 11 and 13 and all of P2/J2 shall be No Connect. Note: For P1/J1 wafers 1-8, see Rule 14.5.1.2-1. [VM = I]

Permission 14.5.1.4-1: This profile may be combined with other Slot Profile(s) in order to support multi-function modules.


Rule 14.5.1.4-2: If this profile is combined with other Slot Profile(s) then the differential pair connections on P1/J1 wafers 11-16, the single-ended connections on P1/J1 wafers 9, 11 and 13 and all the connections on P2/J2 of the other Slot Profile(s) shall apply. [VM = I]



Table 14.5.1-1 Storage Slot Profile SLT3-STO-2U-14.5.1 — P1 & J1 Plug-In Module P1



Not

e 1

GDiscrete1 GND GND-J1 Note 1 Note 1 GND GND-J1 Note 1 Note 1

2 GND Note 1 Note 1 GND-J1 GND Note 1 Note 1 GND-J1 GND

3 P1-VBAT GND GND-J1 Note 1 Note 1 GND GND-J1 Note 1 Note 1


5 SYS_CON* GND GND-J1 Note 1 Note 1 GND GND-J1 Note 1 Note 1


7 Reserved GND GND-J1 Note 1 Note 1 GND GND-J1 Note 1 Note 1


9

Stor

age Note 1 GND GND-J1 STRutp 1-T- STRutp1-T+ GND GND-J1 STRutp1-R- STRutp1-R+

10 GND STRutp2-T- STRutp2-T+ GND-J1 GND STRutp2-R- STRutp2-R+ GND-J1 GND

11

Not

e 1

Note 1 GND GND-J1 Note 1 Note 1 GND GND-J1 Note 1 Note 1


13 Note 1 GND GND-J1 Note 1 Note 1 GND GND-J1 Note 1 Note 1


15 Maskable Reset* GND GND-J1 Note 1 Note 1 GND GND-J1 Note 1 Note 1


Note 1: These pins are reserved unless this Slot Profile is combined with another Slot Profile.


Table 14.5.1-2 Storage Slot Profile SLT3-STO-2U-14.5.1 — P2 & J2 Plug-In Module P2



This connector is all No Connect unless this Slot Profile is combined with another Slot Profile. See Section 14.5.1.4 for further details.


14.6 3U Payload Slot Profiles Using VITA 46.0 and 67 connectors

The Payload Slot Profiles in this section contain connectors in accordance to [VITA 67.0]. [VITA 67.0] and [VITA 67.1] have subsections for different configurations of 3U and 6U Slot Profiles utilizing VITA 67 defined connector modules. The Slot Profiles of this Section use VITA 46.0 connector types for the P0/J0 and P1/J1 positions. What happens with the P2/J2 positions can vary among the Slot Profiles of this section.


14.6.1 Payload Slot Profile SLT3-PAY-1F1F2U4R-14.6.1

The SLT3-PAY-1F1F2U4R-14.6.1 Payload Slot Profile contains two Fat Pipes (1 Data Plane port plus 1 Expansion Plane port), user defined area, and two Ultra-Thin Pipes on the Control Plane on P1/J1. Figure 14.6.1-1 provides an overview of the Slot Profile. Table 14.6.1-1 and Table 14.6.1-2 provide the pin assignments. For Module Profiles using this Slot Profile, see Section 16.6.1.

DiffP1/J1

Data Plane — 1 Fat PipeSE

SEP0/J0


Utility Plane

Key


Expansion Plane — 1 Fat Pipe

User Defined

User Defined SE

DiffP2/J2

Key

User Defined

VITA 67.1 — 4 RF Cavities

Figure 14.6.1-1 Payload Slot Profile SLT3-PAY-1F1F2U4R-14.6.1







14.6.1.3 Data Plane








Permission 14.6.1.4-2: The 4 lanes of Expansion Plane may be used as eight pairs.






14.6.1.6 VITA 67 RF Cavities

Rule 14.6.1.6-1: The connector block containing contacts Cx-A1, Cx-A2, Cx-B1, and Cx-B2 shall comply with [VITA 67.1]. [VM = I]

Table 14.6.1-1 Payload Slot Profile SLT3-PAY-1F1F2U4R-14.6.1— P1 & J1 Plug-In Module P1



Dat

a Pl

ane

1x4

/ 2x2

/ 4x





5

Expa

nsio

n Pl

ane

1x4

/ 2x2

/ 4x

1 SYS_CON* GND GND-J1 EP00-TD- EP00-TD+ GND GND-J1 EP00-RD- EP00-RD+




9

Use

r Def

ined







15

Con

trol

Pl

ane

Maskable Reset* GND GND-J1 CPutp02-TD- CPutp02-

TD+ GND GND-J1 CPutp02-RD-

CPutp02-RD+

16 GND CPutp01-TD- CPutp01-TD+ GND-J1 GND CPutp01-




Table 14.6.1-2 Payload Slot Profile SLT3-PAY-1F1F2U4R-14.6.1— P2 & J2 Plug-In Mod P2



1

Use

r Def

ined









9

RF

Cav

ity

Cx-A2 Cx-B2 10

11

12

13

Cx-A1 Cx-B1 14

15

16



14.6.2 Payload Slot Profile SLT3-PAY-4F4R-14.6.2

The SLT3-PAY-4F4R-14.6.2 Payload Slot Profile contains four Fat Pipes (4 Data Plane port), and user defined area on the Control Plane on P1/J1. Figure 14.6.2-1 provides an overview of the Slot Profile. Table 14.6.2-1 and Table 14.6.2-2 provide the pin assignments. For Module Profiles using this Slot Profile, see Section 16.6.2.

Utility Plane

User DefinedUtility Plane

User Defined


DiffP1/J1

SE

DiffP2/J2

SE

SEP0/J0

Key

Key

User Defined

VITA 67.1 — 4 RF Cavities

Figure 14.6.2-1 Payload Slot Profile SLT3-PAY-4F4R-14.6.2




14.6.2.2 Data Plane


Permission 14.6.2.2-1: The lanes of each Data Plane Fat Pipe may be repartitioned.

Rule 14.6.2.2-2: If one or more of the Data Plane Fat Pipes are repartitioned, they shall be repartitioned as one of the options shown in Table 6.2.4.1-1, with usage complying with Section 6.2.2. [VM = I]




14.6.2.4 VITA 67 RF Cavities

Rule 14.6.2.4-1: The connector block containing contacts Cx-A1, Cx-A2, Cx-B1, and Cx-B2 shall comply with [VITA 67.1]. [VM = I]

Table 14.6.2-1 Payload Slot Profile SLT3-PAY-4F4R-14.6.2— P1 & J1 Plug-In Module P1



Dat

a Pl

ane

Port

1

1x4

/ 2x2

/ 4x

1 GDiscrete1 GND GND-J1 DP01-T0- DP01-T0+ GND GND-J1 DP01-R0- DP01-R0+




5

Dat

a Pl

ane

Port

2

1x4

/ 2x2

/ 4x

1 SYS_CON* GND GND-J1 DP02-T0- DP02-T0+ GND GND-J1 DP02-R0- DP02-R0+




9

Dat

a Pl

ane

Port

3

1x4

/ 2x2

/ 4x





13

Dat

a Pl

ane

Port

4

1x4

/ 2x2

/ 4x







Table 14.6.2-2 Payload Slot Profile SLT3-PAY-4F4R-14.6.2— P2 & J2 Plug-In Mod P2



1

Use

r Def

ined









9

RF

Cav

ity

Cx-A2 Cx-B2 10

11

12

13

Cx-A1 Cx-B1 14

15

16



15 3U Backplane Profiles The following sub-sections define different variants of 3U height Backplane Profiles that are used in OpenVPX systems:

Table 15-1 and Table 15-3 summarize the key characteristics for each of the Backplane Profiles in the subsections that follow. These tables are informative and are provided to simplify the selection of a specific Backplane Profile. The section number, contained at the end of each profile name in the left hand column, is hyperlinked to the associated Backplane Profile for ease of reference. Within each Backplane Profile, the utilized Slot Profiles are also hyperlinked to their respective sections, and within each Slot Profile, a hyperlink is provided to a list of compatible Module Profiles.

For background on how topologies are characterized, see Section 1.3.4.

Table 15-2 and Table 15-4 give Module Profiles that can be used with each Backplane Profile. There are some important caveats to using this table:

• It is important to note that these are not the only Module Profiles that can be used with each Backplane. In many cases if some functionality is given up or some restriction is met, other Module Profiles can be used.

• The Backplane Profiles are protocol agnostic. When picking Modules for a particular Backplane Profile it is important to make sure that the Modules are compatible with each other. For example, if a Switch Module is chosen that uses Serial RapidIO for the Data Plane, then the Payload Modules need to use Serial RapidIO for the Data Plane also.

• Backplane Profiles include channel Gbaud rates, for the supported planes; a system integrator needs to make sure the rated Gbaud rates, for the supported planes, are high enough to support the Gbaud rates of the protocols of the modules being used.


Table 15-1 Summary of 3U Backplane Profiles Using VITA 46.0 Connectors


BKP3-CEN06-15.2.2-n

Payload 5 Control 1 x UTP — Star

Switch 1 Data 1 x FP — Star

Expansion 2 x FP — Daisy Chain

BKP3-CEN07-15.2.3-n



Expansion N/A

BKP3-CEN10-15.2.4-n



Expansion 1 x FP — Pairs


BKP3-CEN10-15.2.5-n Switch 2 Data 1 x FP — Star

Expansion 2 x FP — Daisy Chain

Payload 10 Control 1 x UTP — Cascaded Single-Stars

BKP3-CEN12-15.2.6-n Switch 2 Data 1 x FP — Cascaded Single-Stars

Expansion N/A

BKP3-DIS06-15.2.7-n


Switch 1 Data 2 x FP — 5-Slot Ring

Expansion N/A

BKP3-DIS02-15.2.8-n


Peripheral 1 Data 1 x DFP — Mesh

Expansion N/A


BKP3-CEN03-15.2.9-n Peripheral 2 Data 1 x FP — Star

Expansion N/A



BKP3-CEN06-15.2.10-n


Peripheral 5 Data 1 x FP or 1 x UTP — Star

Expansion N/A

BKP3-CEN09-15.2.11-n


Peripheral 8 Data 1 x UTP — Star

Expansion N/A


BKP3-CEN06-15.2.12-n Peripheral 4 Data 1 or 2 x FP — Cascaded Single-Stars

Switch 1 Expansion N/A


BKP3-DIS05-15.2.13-n Peripheral 2 Data 2 x FP — Daisy Chain

Expansion N/A

Payload 5 Control 2 x UTP — Dual-Star

BKP3-DIS06-15.2.14-n Switch 1 Data 2 x FP — 5-Slot Ring

Expansion N/A

Payload 6 Control 2 x UTP — Dual-Star

BKP3-CEN08-15.2.15-n Switch 2 Data 2 x FP — Dual-Star

Expansion N/A


BKP3-CEN08-15.2.16-n Switch 2 Data 1 x FP — Star

Expansion N/A

Payload 8 Control 1 x UTP - Single Star 1 x UTP - Available to RTM

BKP3-CEN09-15.2.17-n Switch 1 Data 1 or 3 x FP — Cascaded Single-Stars

Expansion 2 x FP - Ring, last four slots only


Table 15-2 Matching Module Profiles to Backplane Profiles Using VITA 46.0 Connectors






CEN06-15.2.2-n 1F2F2U-16.2.2-n 6F6U-16.4.1-n

CEN07-15.2.3-n 2F2U-16.2.3-n 6F6U-16.4.1-n

CEN10-15.2.4-n 1F1F2U-16.2.4-n 2F8U-16.4.6-n 8F-16.4.2-n

CEN10-15.2.5-n 1F2F2U-16.2.2-n 2F24U-16.4.3-n 8F-16.4.2-n

CEN12-15.2.6-n 2F2U-16.2.3-n 6F6U-16.4.1-n

DIS06-15.2.7-n 2F2T-16.2.5-n 16T-16.4.7-n

DIS02-15.2.8-n 1D-16.2.6-n

CEN03-15.2.9-n 2F-16.2.7-n 1F-16.3.2-n

CEN06-15.2.10-n 1F4U-16.2.8-n 1F-16.3.2-n 1U-16.3.3-n

CEN09-15.2.11-n 8U-16.2.9-n 1U-16.3.3-n

CEN06-15.2.12-n 2F-16.2.7-n 4F-16.4.5-n 1F-16.3.2-n

DIS05-15.2.13-n 2F-16.2.7-n 1F-16.3.2-n

DIS06-15.2.14-n 2F2T-16.2.5-n 16T-16.4.7-n

CEN08-15.2.15-n 2F2U-16.2.3-n 6F6U-16.4.1-n

CEN08-15.2.16-n 2F2U-16.2.3-n 6F6U-16.4.1-n 2F24U-16.4.3-n

CEN09-15.2.17-n 3F2U-16.2.12-n 1F2U-16.2.11-n 1F2F2U-16.2.2-n

6F8U-16.4.10-n


Table 15-3 Summary of 3U Backplane Profile Using VITA 46.0 and VITA 67 Connectors



BKP3-DIS05-15.3.2-n VITA 67 I/O 3 Data 4 x FP — 5-Slot Mesh

Expansion N/A

Payload 2 Control 1 x UTP — Star 1 x UTP — Available to RTM

BKP3-CEN05-15.3.3-n VITA 67 I/O 2 Data 1 x FP — Star

Switch 1 Expansion 1 x FP — Two segments

Table 15-4 Matching Module Profiles to Backplane Profiles Using VITA 46.0 and VITA 67 Connectors






DIS05-15.3.2-n 4F4R-16.6.2-n 4F-16.4.5-n

CEN05-15.3.3-n 1F1F2U-16.2.4-n 1F1F2U4R-16.6.1-n 6F6U-16.4.1-n


15.1 3U Backplane Profiles Common Section

For material common to both 6U and 3U Backplane Profiles, see Section 7.

15.2 3U Backplane Profiles Using VITA 46.0 Connectors

15.2.1 Common Section for 3U Backplanes Using VITA 46.0 Connectors

This section is for items that are common to all 3U Backplane Profiles that use VITA 46.0 connectors.




Recommendation 15.2.1.1-1: Any signal not routed in the backplane should be made available on the backplane RTM connectors (RJx), unless a requirement in a Backplane Profile specifically states otherwise. [VM = I]



15.2.1.2.1 Power Distribution

There are general requirements concerning Power Distribution in Section 3.1.

The following Rules are for Power Distribution signals that are bussed on the backplane:


Recommendation 15.2.1.2.1-1: Vs1 should be sized to be able to distribute at least 14 A per slot. Refer to connector current load limits in [VITA 46.0]. [VM = A]



Recommendation 15.2.1.2.1-2: Vs2 should be sized to be able to distribute at least 14 A per slot. Refer to connector current load limits in [VITA 46.0]. [VM = A]


Recommendation 15.2.1.2.1-3: Vs3 should be sized to be able to distribute at least 15 A per slot. Refer to current load limits in [VITA 46.0]. [VM = A]

Rule 15.2.1.2.1-4: -12V_AUX shall be bussed among all slots in the backplane and be brought out on suitable connectors or connection points. Refer to current load limits in [VITA 46.0]. [VM = I]

Rule 15.2.1.2.1-5: 3.3V_AUX shall be bussed among all slots in the backplane and be brought out on suitable connectors or connection points. Refer to current load limits in [VITA 46.0]. [VM = A]

Rule 15.2.1.2.1-6: +12V_AUX shall be bussed among all slots in the backplane and be brought out on suitable connectors or connection points. Refer to connector current load limits in [VITA 46.0]. [VM = A]

Rule 15.2.1.2.1-7: P1-VBAT shall be bussed among all slots in the backplane and be brought out on suitable connectors or connection points. [VM = I]

15.2.1.2.2 SYS_CON*

There are general requirements concerning SYS_CON* in Section 3.4.1.

Rule 15.2.1.2.2-1: There shall be a method for optionally pulling the SYS_CON* signal low for all slots, including any Switch Slots. [VM = I]

Rule 15.2.1.2.2-2: SYS_CON* shall be pulled low for one and only one slot. [VM = I]

15.2.1.2.3 NVMRO

Rule 15.2.1.2.3-1: NVMRO shall be bussed among all slots in the backplane and be brought out on suitable connectors or connection points. [VM = I]

Recommendation 15.2.1.2.3-1: The backplane should have a jumper that can be used to ground NVMRO. [VM = I]

Observation 15.2.1.2.3-1: The jumper of Recommendation 15.2.1.2.3-1 can be used to drive NVMRO for cases where there is no other chassis level control, rather than requiring a module to drive it.

15.2.1.2.4 Other Utility Plane Signals

There are general requirements concerning system control signals in Section 3.4 and system clocks in Section 3.5.


The following Rules are for Utility Plane signals that are bussed on the backplane:

Rule 15.2.1.2.4-1: SYSRESET* shall be bussed among all slots in the backplane and be brought out on suitable connectors or connection points. [VM = I]

Rule 15.2.1.2.4-2: SM[3:0] shall each be bussed among all slots in the backplane and be brought out on suitable connectors or connection points. [VM = I]

Rule 15.2.1.2.4-3: REF_CLK-/+ shall be bussed among all slots in the backplane. [VM = I]

Rule 15.2.1.2.4-4: AUX_CLK-/+ shall be bussed among all slots in the backplane. [VM = I]

Rule 15.2.1.2.4-5: GDiscrete1 shall be bussed among all slots in the backplane. [VM = I]

The following Rules are for Utility Plane signals that are not bussed:

Rule 15.2.1.2.4-6: GAP* and GA[4:0] shall be wired to indicate physical slot numbers, with the numbers going from 1 thru N, where N is the number of slots (including both Payload and Switch Slots). Note: The physical slot numbers can be different from the logical Slot numbers in this document. [VM = I]

Rule 15.2.1.2.4-7: P1-G7 / J1-i7 is a reserved signal. It shall not be routed to anything by the backplane. [VM = I]

Rule 15.2.1.2.4-8: The User Defined pins J1-i9, J1-i11, and J1-i13 shall not be bussed unless the particular Backplane Profile specifically calls it out. [VM = I]


15.2.2 6-Slot — BKP3-CEN06-15.2.2-n (5 Payloads + 1 Switch)

These Backplane Profiles are intended for a development environment. Some systems might be able to deploy with these backplanes. It is expected that many deployed systems will not use RTMs; instead the I/O signals that these Backplane Profiles route to RTMs would be routed, via the backplane, to connectors. For more on RTMs, see Section 4.4. Note: It is up to the RTM implementation (the rear Plug-In Module) whether it connects to these signals and what is done with them.

Figure 15.2.2-1 and Figure 15.2.2-2 give an overview of the topology. The dotted lines, from the Switch Slot, are signals that are available to RTMs.

VPX1

VPX2

VPX3

VPX4

PayloadSlots

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

DataPlane

DataPlane

DataPlane

DataPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

IPMC IPMC IPMC IPMC

VPX6

ChMC

ContrlSwitch

Switch/ Management

Utility Plane Includes Power


Control Plane(UTP)

Data Plane(FP)

ExpansionPlane(FP)

VPX5

ExpanPlane

DataPlane

ContrlPlane

IPMC

DataSwitch

Slot numbers are logical, physical slot number may be different

FP

TPUTP



Type B Slot 1

EP[3:0]

EP[7:4]

Type A Slot 2

EP[3:0]

EP[7:4]

Type BSlot 3

EP[3:0]

EP[7:4]

Type ASlot 4

EP[3:0]

EP[7:4]

Type BSlot 5

EP[3:0]

EP[7:4]


The remainder of this Section gives detailed Rules for these Backplane Profiles. Table 15.2.2-1 provides requirements that can vary among the Backplane Profiles of this section, such as channel baud rate and slot pitch. The Slot Profiles include the definition of what connectors are used. The RTM connectors are explicitly specified by this table because they are part of the Backplane Profile that is not specified by the Slot Profiles.


Profile name


Pitch (in)


Control Plane

Data Plane

Expan- sion

Plane

BKP3-CEN06-15.2.2-1 1.0 VITA 46.10

SLT3-PAY-1F2F2U-

14.2.2

SLT3-SWH- 6F6U- 14.4.1

1.25 3.125 5.0

BKP3-CEN06-15.2.2-2 1.0 VITA 46.10

SLT3-PAY-1F2F2U-

14.2.2

SLT3-SWH- 6F6U- 14.4.1

1.25 5.0 5.0

BKP3-CEN06-15.2.2-3 1.0 VITA 46.10

SLT3-PAY-1F2F2U-

14.2.2

SLT3-SWH- 6F6U- 14.4.1

1.25 6.25 5.0



Permission 15.2.2.1-2: The physical slot number may be in the same order as the logical slot number for this profile.


Rule 15.2.2.1-1: Logical slots 1 through 5 shall be Payload Slots using the Slot Profile specified in Table 15.2.2-1, for the particular Backplane Profile. [VM = I]

Rule 15.2.2.1-2: Logical slot 6 shall be Switch Slot using the Slot Profile specified in Table 15.2.2-1, for the particular Backplane Profile. [VM = I]



15.2.2.2.1 SYS_CON*



Rule 15.2.2.3-1: Each Payload Slot shall have its Control Plane port CPutp02 not routed in the backplane. [VM = I]

Permission 15.2.2.3-1: Each Payload Slot may have its CPutp02 port available on RTM connectors on the rear of the backplane.

Rule 15.2.2.3-2: The logical Payload Slot’s Control Plane ports shall connect to the Switch Slot Control Plane as shown in Table 15.2.2-2, complying with the Rules of Section 7.2.1. For example, logical payload slot 1 Control Plane port CPutp01 connects to the switch slot Control Plane port CPutp01. [VM = I]


Table 15.2.2-2 BKP3-CEN06-15.2.2-n Control Plane Port connections

Logical Payload Slot

Payload Control Plane Port

Switch Control Plane Port

1 CPutp01 CPutp01

1 Cputp02 No Connect, can go to RTM

2 CPutp01 CPutp02


3 CPutp01 CPutp03


4 CPutp01 CPutp04


5 CPutp01 CPutp05


Rule 15.2.2.3-3: The CSutp01 port of the Switch Slot Control Plane shall be available on RTM connectors on the rear of the backplane. [VM = I]

Rule 15.2.2.3-4: Each Control Plane channel for the Backplane Profile name listed in Table 15.2.2-1, shall comply with the baud rate specified in the Channel Gbaud Rate column. [VM = T,A]

15.2.2.4 Data Plane

Rule 15.2.2.4-1: The logical Payload Slot’s Data Plane ports shall connect to the switch slot Data Plane as shown in Table 15.2.2-3, complying with the Rules of Section 7.2.1. For example, logical Payload Slot 5 Data Plane port DP01 connects to the switch slot Data Plane port DP05. [VM = T]


Table 15.2.2-3 BKP3-CEN06-15.2.2-n Data Plane Port connections


Payload Data Plane Port

Switch Data Plane Port

1 DP01 DP01

2 DP01 DP02

3 DP01 DP03

4 DP01 DP04

5 DP01 DP05

Rule 15.2.2.4-2: Switch Slot Data Plane inter-switch port DS01 shall be available on RTM connectors on the rear of the backplane. [VM = I]

Rule 15.2.2.4-3: Each Data Plane channel for the Backplane Profile name listed in Table 15.2.2-1 shall comply with the baud rate specified in the Channel Gbaud Rate column. [VM = T,A]


Figure 15.2.2-2 shows how the Expansion Plane interconnects Payload Slots. The slot types are as follows:





Rule 15.2.2.5-1: Slot 1 Expansion Plane lanes EP[3:0] shall connect to slot 2 Expansion Plane lanes EP[7:4], complying with the Rules of Section 7.2.1. [VM = I]

Rule 15.2.2.5-2: Slots 2 and 3 Expansion Plane shall connect to each other using Lanes EP[3:0], complying with the Rules of Section 7.2.1. [VM = I]






Rule 15.2.2.5-5: Each Expansion Plane channel for the Backplane Profile name listed in Table 15.2.2-1 shall comply with the baud rate specified in the Channel Gbaud Rate column. [VM = T,A]



Observation 15.2.2.6-1: User Defined pins that are following a suggested or recommended use, such as a Control Plane Thin Pipe on P2/J2, as given by Recommendation 14.4.1.4.1-1, are still User Defined pins and are therefore made available on the rear of the backplane for RTM connections.

15.2.2.7 Slot Pitch




The BKP3-CEN07-15.2.3-n Backplane Profiles are closely related to the BKP3-CEN06-15.2.2-n Backplane Profiles. These two profiles are both based on a centralized topology; both utilize the same integrated switch but different Slot Profiles. There are three areas where the two topologies differ: 1) These profiles do not have an Expansion Plane while the BKP3-CEN06-15.2.2-n Profiles do, 2) these profiles provide 6 Payload Slots while the BKP3-CEN06-15.2.2-n Backplane Profiles provide only 5 Payload Slots; and 3) these profiles utilizes all of the switch’s Data Plane and Control Plane ports leaving none for chassis-to-chassis expansion, while the BKP3-CEN06-15.2.2-n Backplane Profiles provide expansion capability for both Control and Data Planes.

It is expected that many deployed systems will not use RTMs; instead the I/O signals that this Backplane Profile routes to RTMs would be routed, via the backplane, to connectors. For more on RTMs, see Section 4.4. Note: It is up to the RTM implementation (the rear Plug-In Module) whether it connects to these signals and what is done with them.

Figure 15.2.3-1 provides an overview of the topology of the BKP3-CEN0-15.2.3-n Backplane Profiles. The dotted line, from the Switch Slot, is a signal that is available to RTMs.

VPX3

VPX4

VPX5

PayloadSlots

DataPlane

DataPlane

DataPlane

ContrlPlane

ContrlPlane

ContrlPlane

IPMC IPMC IPMC

VPX7

ChMC

ContrlSwitch

Switch/ Management

TP

VPX6

DataPlane

ContrlPlane

IPMC

DataSwitch



Control Plane(UTP)

Data Plane(FP)

VPX2

DataPlane

ContrlPlane

IPMC

VPX1

DataPlane

ContrlPlane

IPMC




The remainder of this Section gives detailed Rules for these Backplane Profiles. Table 15.2.3-1 provides requirements that might vary among the Backplane Profiles of this section, such as channel baud rate and slot pitch. The Slot Profiles include the definition of what connectors are used. The RTM connectors are explicitly specified by this table because they are part of the Backplane Profile that is not specified by the Slot Profiles.


Profile name

Mechanical Slot Profiles and Section Channel Gbaud

Rate

Pitch (in)


Control Plane

Data Plane

BKP3-CEN07-15.2.3-1 1.0 VITA 46.10

SLT3-PAY-2F2U-14.2.3

SLT3-SWH- 6F6U- 14.4.1

1.25 3.125

BKP3-CEN07-15.2.3-2 1.0 VITA 46.10


SLT3-SWH- 6F6U- 14.4.1

1.25 5.0

BKP3-CEN07-15.2.3-3 1.0 VITA 46.10


SLT3-SWH- 6F6U- 14.4.1

1.25 6.25









15.2.3.2.1 SYS_CON*





Rule 15.2.3.3-2: The logical Payload Slots Control Plane ports shall connect to the switch slot Control Plane as shown in Table 15.2.3-2, complying with the Rules of Section 7.2.1. For example, logical payload slot 1 Control Plane port CPutp01 connects to the switch slot Control Plane port CPutp01. [VM = I]

Rule 15.2.3.3-3: Each Control Plane channel for the Backplane Profile name listed in Table 15.2.3-1 shall comply with baud rate specified in the Channel Gbaud Rate column. [VM = T,A]





1 CPutp01 CPutp01

2 CPutp01 CPutp02

3 CPutp01 CPutp03

4 CPutp01 CPutp04

5 CPutp01 CPutp05

6 CPutp01 CSutp01

15.2.3.4 Data Plane

Rule 15.2.3.4-1: The logical Payload Slots Data Plane ports shall connect to the switch slot Data Plane as shown in Table 15.2.3-3, complying with the Rules of Section 7.2.1. For example, logical payload slot 5 Data Plane port DP01 connects to the switch slot Data Plane port DP05. [VM = I]

Rule 15.2.3.4-2: Each Payload Slot shall have its Data Plane port DP02 not routed in the backplane. [VM = I]


Permission 15.2.3.4-1: Each Payload Slot may have its Data Plane port DP02 available on RTM connectors on the rear of the backplane.






1 DP01 DP01

2 DP01 DP02

3 DP01 DP03

4 DP01 DP04

5 DP01 DP05

6 DP01 DS01




15.2.3.6 Slot Pitch




The BKP3-CEN10-15.2.4-n Backplane Profiles provide a higher number of Payload Slots (total of eight) than the BKP3-CEN06-15.2.2-n or BKP3-CEN07-15.2.3-n Backplane Profiles. Unlike the BKP3-CEN12-15.2.6-n Backplane Profiles, which cascade two integrated switches, these Backplane Profiles use dedicated Control and Data Plane switches. In addition, unlike the BKP3-CEN06-15.2.2-n Backplane Profiles, where the Expansion Planes are daisy-chained, the BKP3-CEN10-15.2.4-n Backplane Profiles wire the Expansion Planes between pairs of odd and even Payload Slots.

These Backplane Profiles are intended for a development environment. Some systems might be able to deploy with these backplanes. It is expected that many deployed systems will not use RTMs; instead the I/O signals that this Backplane Profile routes to RTMs would be routed, via the backplane, to connectors. For more on RTMs, see Section 4.4. Note: It is up to the RTM implementation (the rear Plug-In Module) whether it connects to these signals and what is done with them.




Control Plane(UTP)

Data Plane(FP)

ExpansionPlane(FP)

VPX7

VPX8

VPX9

VPX10

PayloadSlots

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

DataPlane

DataPlane

DataPlane

DataPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

IPMC IPMC IPMC IPMC

VPX5

Switch/Management

ChMC

ContrlSwitch

DataSwitch

IPMC

VPX1

VPX2

VPX3

VPX4

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

DataPlane

DataPlane

DataPlane

DataPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

IPMC IPMC IPMC IPMC

VPX6

FP

PayloadSlots




Slot 1

EP[3:0]

Slot 2

EP[3:0]

Slot 3

EP[3:0]

Slot 4

EP[3:0]

Expansion Plane Lane Interfaces Slot 7

EP[3:0]

Slot 8

EP[3:0]

Slot 9

EP[3:0]

Slot 10

EP[3:0]




Profile name


Pitch (in)

RTM Conn Payload

Switches

Control Plane

Data Plane

Expan- sion

Plane Control Plane Data Plane

BKP3-CEN10-15.2.4-1 1.0 VITA

46.10

SLT3-PAY-1F1F2U-

14.2.4

SLT3-SWH-2F8U-14.4.5

SLT3-SWH-8F-14.4.2 1.25 3.125 5.0

BKP3-CEN10-15.2.4-2 1.0 VITA

46.10

SLT3-PAY-1F1F2U-

14.2.4


SLT3-SWH-8F-14.4.2 1.25 5.0 5.0

BKP3-CEN10-15.2.4-3 1.0 VITA

46.10

SLT3-PAY-1F1F2U-

14.2.4


SLT3-SWH-8F-14.4.2 1.25 6.25 5.0





Rule 15.2.4.1-1: Logical slots 1 through 4 and slots 7 through 10 shall be Payload Slots using the Slot Profile specified in Table 15.2.4-1, for the particular Backplane Profile. [VM = I]

Rule 15.2.4.1-2: Logical slot 5 shall be Control Plane Switch Slot using the Slot Profile specified in Table 15.2.4-1, for the particular Backplane Profile. [VM = I]

Observation 15.2.4.1-1: In addition to the Slot Profile given in Table 15.2.4-1, Modules with a Slot Profile of SLT3-SWH-2F24U-14.4.3 can also be used in the Control Plane Switch Slot, as long as, there is not an RTM in place that has electrically incompatible signals, where the additional Control Plane Ultra-Thin Pipes of the SLT3-SWH-2F24U-14.4.3 Slot Profile are located.

Rule 15.2.4.1-3: Logical slot 6 shall be the Data Plane switch slot utilizing the all Data Plane Slot Profile specified in Table 15.2.4-1, for the particular Backplane Profile. [VM = I]



15.2.4.2.1 SYS_CON*



Note: Although, the Switch Slot Profile being used for the Control Plane follows naming conventions of a Data Plane Switch, it is being used as a Control Plane Switch in this Backplane Profile.



Rule 15.2.4.3-2: Each Payload Slot shall have its Control Plane Port CPutp01 connected to the Control Plane switch slot, one of ports DPutp01 thru DPutp08, complying with the Rules of Section 7.2.1. [VM = I]


Permission 15.2.4.3-2: With the Switch Slot, which Payload Slot Control Plane Port connects to which Switch Slot Control Plane Port may be jumbled.


Rule 15.2.4.3-3: The two Control Plane Switch Slot, Fat Pipes DP01 and DP02 shall be available on RTM connectors on the rear of the backplane. [VM = I]

Rule 15.2.4.3-4: Each Control Plane channel for the Backplane Profile name listed in Table 15.2.4-1 shall comply with the baud rate specified in the Channel Gbaud Rate column. [VM = T,A]

15.2.4.4 Data Plane







1 DP01 DP01

2 DP01 DP02

3 DP01 DP03

4 DP01 DP04

7 DP01 DP05

8 DP01 DP06

9 DP01 DP07

10 DP01 DS01










15.2.4.7 Slot Pitch



15.2.5 10-Slot - BKP3-CEN10-15.2.5-n (8 Payload + 2 Switch)

The BKP3-CEN10-15.2.5-n Backplane Profiles provide an alternative 10-slot option to the BKP3-CEN10-15.2.4-n Backplane Profiles for a 3U centralized topology. The BKP3-CEN10-15.2.5-n Backplane Profiles connect both Control Plane interfaces from all Payload Slots to the Control Plane switch slot. In this topology the Expansion Plane, like the BKP3-CEN06-15.2.2-n Backplane Profiles, is daisy chained.

These Backplane Profiles are intended for a development environment. Some systems might be able to deploy with these backplanes. It is expected that many deployed systems will not use RTMs; instead the I/O signals that this Backplane Profile routes to RTMs would be routed, via the backplane, to connectors. For more on RTMs, see Section 4.4. Note: It is up to the RTM implementation (the rear Plug-In Module) whether it connects to these signals and what is done with them.




Control Plane(UTP)

Data Plane(FP)

ExpansionPlane(FP)

VPX7

VPX8

VPX9

VPX10

PayloadSlots

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

DataPlane

DataPlane

DataPlane

DataPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

IPMC IPMC IPMC IPMC

VPX5

Switch/Management

ChMC

ContrlSwitch

DataSwitch

IPMC

VPX1

VPX2

VPX3

VPX4

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

DataPlane

DataPlane

DataPlane

DataPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

IPMC IPMC IPMC IPMC

VPX6

FP

PayloadSlots


UTP



Type B Slot 1

EP[3:0]

Type A Slot 2

EP[3:0]

Type B Slot 3

EP[3:0]

Type B Slot 4

EP[3:0]

Expansion Plane Lane Interfaces

Type A Slot 7

EP[3:0]

Type B Slot 8

EP[3:0]

Type A Slot 9

EP[3:0]

Type B Slot 10

EP[3:0]

EP[7:4] EP[7:4] EP[7:4] EP[7:4] EP[7:4] EP[7:4] EP[7:4] EP[7:4]




Profile name


Pitch (in)

RTM Conn Payload

Switches

Control Plane

Data Plane

Expan- sion

Plane Control Plane Data Plane

BKP3-CEN10-15.2.5-1 1.0 VITA

46.10

SLT3-PAY-1F2F2U-

14.2.2

SLT3-SWH-2F24U-14.4.3

SLT3-SWH-8F-14.4.2 1.25 3.125 5.0

BKP3-CEN10-15.2.5-2 1.0 VITA

46.10

SLT3-PAY-1F2F2U-

14.2.2

SLT3-SWH-2F24U-14.4.3

SLT3-SWH-8F-14.4.2 1.25 5.0 5.0

BKP3-CEN10-15.2.5-3 1.0 VITA

46.10

SLT3-PAY-1F2F2U-

14.2.2

SLT3-SWH-2F24U-14.4.3

SLT3-SWH-8F-14.4.2 1.25 6.25 5.0





Rule 15.2.5.1-1: Logical slots 1 through 4 and slots 7 through 10 shall be Payload Slots using the Slot Profile specified in Table 11.2.5-1, for the particular Backplane Profile. [VM = I]

Rule 15.2.5.1-2: Logical slot 5 shall be Control Plane Switch Slot using the Slot Profile specified in Table 11.2.5-1, for the particular Backplane Profile. [VM = I]

Rule 15.2.5.1-3: Logical slot 6 shall be the Data Plane switch slot utilizing the Slot Profile specified in Table 11.2.5-1, for the particular Backplane Profile. [VM = I]



15.2.5.2.1 SYS_CON*



Rule 15.2.5.3-1: Each Payload Slot shall have each of its Control Plane Ports CPutp01 and CPutp02 connected to the Control Plane switch slot, one of the ports CPutp01 thru CPutp16, complying with the Rules of Section 7.2.1. [VM = I]

Permission 15.2.5.3-1: With the Control Plane Switch Slot, which Payload Slot Control Plane Port connects to which Switch Slot Control Plane Port may be jumbled.


Rule 15.2.5.3-2: The two Control Plane Switch Slot Fat Pipes CP01 and CP02 shall be available on RTM connectors on the rear of the backplane. [VM = I]

Rule 15.2.5.3-3: Two Control Plane Switch Slot Ultra-thin Pipes CPutp23 and CPutp24 shall be available on RTM connectors on the rear of the backplane. [VM = I]

Permission 15.2.5.3-2: The Control Plane Switch Slot ports CPutp17 thru CPutp22 may be available on RTM connectors on the rear of the backplane.



15.2.5.4 Data Plane







1 DP01 DP01

2 DP01 DP02

3 DP01 DP03

4 DP01 DP04

7 DP01 DP05

8 DP01 DP06

9 DP01 DP07

10 DP01 DS01


Figure 15.2.5-2 shows how the Expansion Plane interconnects Payload Slots. The slot types are as follows:


• Type B — If some Plug-In Modules have only one port as opposed to two, it is intended that the Type B slots be used by Modules with a single port. The topology is such that if a Type B slot has a single port Module, the single port connects to a Type A slot. Type B slots can also be used by modules with 2 ports. It is intended that if there is a mix of 2-port


and 1-port modules that the 2-port modules go into type A slots first then if there are any leftover 2-port modules they go into Type B or C slots.








Rule 15.2.5.5-6: Slots 8 and 9 Expansion Plane shall connect to each other using Lanes EP[3:0] , complying with the Rules of Section 7.2.1. [VM = I]








15.2.5.7 Slot Pitch




The BKP3-CEN12-15.2.6-n Backplane Profiles are a cascading the BKP3-CEN07-15.2.3-n Backplane Profiles with one less Payload Slot in each section of the cascade. Unlike the BKP3-CEN10-15.2.4-n Backplane Profiles, these cascaded backplanes utilize two integrated switches to provide ten Payload Slots.


Figure 15.2.6-1 provides an overview of the topology. The dotted lines, from the Switch Slots, are signals that are available to RTMs.



Control Plane(UTP)

Data Plane(FP)

VPX2

VPX3

VPX4

PayloadSlots

DataPlane

DataPlane

DataPlane

ContrlPlane

ContrlPlane

ContrlPlane

IPMC IPMC IPMC

VPX6

ChMC

ContrlSwitch

Switch/ Management

VPX5

DataPlane

ContrlPlane

IPMC

DataSwitch

VPX1

DataPlane

ContrlPlane

IPMC

VPX8

VPX9

VPX10

PayloadSlots

DataPlane

DataPlane

DataPlane

ContrlPlane

ContrlPlane

ContrlPlane

IPMC IPMC IPMC

VPX12

IPMC

ContrlSwitch

Switch

VPX11

DataPlane

ContrlPlane

IPMC

DataSwitch

VPX7

DataPlane

ContrlPlane

IPMC


TP

TP



The remainder of this Section gives detailed Rules for these Backplane Profiles. Table 15.2.6-1 gives requirements that can vary among the Backplane Profiles of this section, such as channel baud rate and slot pitch. The Slot Profiles include the definition of what connectors are used. The RTM connectors are explicitly specified by this table because they are part of the Backplane Profile that is not specified by the Slot Profiles.


Profile name


Rate

Pitch (in)


Control Plane

Data Plane

BKP3-CEN12-15.2.6-1 1.0 VITA 46.10


SLT3-SWH- 6F6U- 14.4.1

1.25 3.125

BKP3-CEN12-15.2.6-2 1.0 VITA 46.10


SLT3-SWH- 6F6U- 14.4.1

1.25 5.0

BKP3-CEN12-15.2.6-3 1.0 VITA 46.10


SLT3-SWH- 6F6U- 14.4.1

1.25 6.25




Rule 15.2.6.1-1: Logical slots 1 through 5 and 7 through 11 shall be Payload Slots using the Slot Profile specified in Table 15.2.6-1, for the particular Backplane Profile. [VM = I]

Rule 15.2.6.1-2: Logical slots 6 and 12 shall be Switch Slot using the Slot Profile specified in Table 15.2.6-1, for the particular Backplane Profile. [VM = I]




15.2.6.2.1 SYS_CON*





Rule 15.2.6.3-2: The logical Payload Slots Control Plane ports shall connect to the switch slot Control Plane as shown in Table 15.2.6-2, complying with the Rules of Section 7.2.1. [VM = I]

Rule 15.2.6.3-3: Logical Switch Slots 6 and 12 Control Plane shall connect to each other via CSutp01, complying with the Rules of Section 7.2.1. [VM = I]







1 CPutp01 Switch Slot 6 - CPutp01





7 CPutp01 Switch Slot 12 – CPutp01





15.2.6.4 Data Plane

Rule 15.2.6.4-1: The logical Payload Slots Data Plane ports shall connect to the switch slot Data Plane as shown in Table 15.2.6-3, complying with the Rules of Section 7.2.1. [VM = I]



Rule 15.2.6.4-3: Switch Slots 6 and 12 Data Plane shall connect to each other via DS01, complying with the Rules of Section 7.2.1. [VM = I]







1 DP01 Switch Slot 6 - DP01













15.2.6.6 Slot Pitch






VPX1

VPX2

VPX3

VPX4

VPX6



Control Plane(TP)

Data Plane(FP)

IPMC

Switch/Management

Payloadslots

VPX5

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

TPTP

TPTP

CntrlSwitch

ContrlPlane



DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

Five Slot Ring

5 TPs

5 TPs

TP

TP





Profile name


Rate

Pitch (in)


BKP3-DIS06-15.2.7-1 1.0 VITA 46.10

SLT3-PAY-2F2T- 14.2.5

SLT3-SWH-16T-14.4.6 3.125

BKP3-DIS06-15.2.7-2 1.0 VITA 46.10

SLT3-PAY-2F2T- 14.2.5

SLT3-SWH-16T-14.4.6 5.0

BKP3-DIS06-15.2.7-3 1.0 VITA 46.10

SLT3-PAY-2F2T- 14.2.5

SLT3-SWH-16T-14.4.6 6.25


Rule 15.2.7.1-1: Slots 1 through 5 shall be Payload Slots using the Slot Profile specified in Table 15.2.7-1, for the particular Backplane Profile. [VM = I]

Rule 15.2.7.1-2: Slots 6 shall be a Switch Slot using the Slot Profile specified in Table 15.2.7-1, for the particular Backplane Profile. [VM = I]



15.2.7.2.1 SYS_CON*







Observation 15.2.7.3-2: The Thin Pipes from Payload Slots can be connected to the Switch Slot ports TP05 thru TP14, using RTMs and external cables to implement a dual star topology for the Control Plane.


Observation 15.2.7.3-3: The lowest number ports of the Control Switch are to be used as stacking ports. Given that there are no inter-switch connections, these ports are run to RTM connectors in case stacking ports are to be used for inter-chassis connections.

Rule 15.2.7.3-3: ***Deleted***This Rule was assigned in error, it does not apply. Each Control Plane channel for the Backplane Profile name listed in Table 15.2.7-1 shall comply with the baud rate specified in the Channel Gbaud Rate column. [VM = T,A]


15.2.7.4 Data Plane



Channel DP01 DP02 1

5-Sl

ot M

esh

Clu

ster

1

VPX03-DP01 VPX02-DP02

2 VPX04-DP01 VPX01-DP02





Channel DP01 DP02 1

5-Sl

ot M

esh

Clu

ster

1






Rule 15.2.7.4-1: Each Payload Slot shall have its Data Plane Ports DP01 and DP02 connected as described by Table 15.2.7-2 or Table 15.2.7-3, complying with the Rules of Section 7.2.1. [VM = I]


Recommendation 15.2.7.4-1: Documentation for backplanes should specify which of Table 15.2.7-2 or Table 15.2.7-3, they comply with.




15.2.7.6 Slot Pitch



15.2.8 2-Slot — BKP3-DIS02-15.2.8-n (1 Payload + 1 Peripheral)

These Backplane Profiles are intended for a development environment. Some systems might be able to deploy with this backplane. It is expected that many deployed systems will not use RTMs; instead the I/O signals that this Backplane Profile routes to RTMs would be routed, via the backplane, to connectors. For more on RTMs, see Section 4.4. Note: It is up to the RTM implementation whether it connects to these signals and what is done with them.


VPX1

VPX2

Periphera

l

Slots

DataPlane

DataPlane

Utility Plane including Power


Data Plane(DFP)

Payload


ChMC IPMC

Figure 15.2.8-1 Topology of 2 Slot - BKP3-DIS02-15.2.8-n


Table 15.2.8-1 gives requirements that can vary among the Backplane Profiles of this section, such as channel baud rate and slot pitch.


Profile name


Gbaud Rate VPX 1 VPX 2

Pitch (in)


BKP3-DIS02-15.2.8-1 1.0 VITA

46.10 SLT3-PAY-1D-14.2.6 SLT3-PAY-1D-14.2.6 2.5

BKP3-DIS02-15.2.8-2 1.0 VITA

46.10 SLT3-PAY-1D-14.2.6 SLT3-PAY-1D-14.2.6 5.0

BKP3-DIS02-15.2.8-3 1.0 VITA

46.10 SLT3-PAY-1D-14.2.6 SLT3-PAY-1D-14.2.6 6.25



Rule 15.2.8.1-1: Slot VPX1 shall be Payload Slot using the Slot Profiles specified in Table 15.2.8-1 for the particular Backplane Profile. [VM = I]

Rule 15.2.8.1-2: Slot VPX2 shall be Peripheral Slot using the Slot Profiles specified in Table 15.2.8-1 for the particular Backplane Profile. [VM = I]

Observation 15.2.8.1-1: See Sections 6.2.2, 6.2.3 and Section 8.5 to understand how Plug-In Modules with Slot Profiles SLT3-PER-2F-14.3.1 and SLT3-PAY-2F-14.2.7 can also be compatible with these Backplane Profiles, in place of SLT3-PAY-1D-14.2.6.



15.2.8.2.1 SYS_CON*



15.2.8.3 Data Plane

Rule 15.2.8.3-1: Payload Slot VPX 1 port DP01 shall be routed as a single Double Fat Pipe to Peripheral Slot VPX 2 port DP01, complying with the Rules of Section 7.2.1. [VM = I]

Observation 15.2.8.3-1: Routing the Backplane as a Double Fat Pipe, as indicated above, will insure proper wiring for use both by Modules with two Fat Pipes and Modules with a single Dual Fat Pipe.




15.2.8.5 Slot Pitch




These Backplane Profiles are intended for a development environment. Some systems might be able to deploy with this backplane. It is expected that many deployed systems will not use RTMs; instead the I/O signals that these Backplane Profile route to RTMs would be routed, via the backplane, to connectors. For more on RTMs, see Section 4.4. Note: It is up to the RTM implementation whether it connects to these signals and what is done with them.


VPX1

VPX2

VPX3

Peripheral Slots

DataPlane

DataPlane

DataPlane


Data Plane(FP)

Payload


ManagementPlane (IPMB) IPMC IPMCChMC





Profile name


Gbaud Rate VPX 1 VPX 2 and VPX 3

Pitch (in)


BKP3-CEN03-15.2.9-1 1.0 VITA

46.10 SLT3-PAY-2F-14.2.7 SLT3-PER-1F-14.3.2 2.5

BKP3-CEN03-15.2.9-2 1.0 VITA

46.10 SLT3-PAY-2F-14.2.7 SLT3-PER-1F-14.3.2 5.0

BKP3-CEN03-15.2.9-3 1.0 VITA

46.10 SLT3-PAY-2F-14.2.7 SLT3-PER-1F-14.3.2 6.25



Rule 15.2.9.1-1: Slot VPX 1 shall be a Payload Slot using the Slot Profiles specified in Table 15.2.9-1, for the particular Backplane Profile. [VM = I]

Rule 15.2.9.1-2: Slots VPX 2 and VPX 3 shall be Peripheral Slots using the Slot Profiles specified in Table 15.2.9-1, for the particular Backplane Profile. [VM = I]

Observation 15.2.9.1-1: See Section 6.2.3 and Section 8.5 to understand how Plug-In Modules with Slot Profiles SLT3-PER-2F-14.3.1 and SLT3-PAY-2F-14.2.7 can also be compatible with these Backplane Profiles, in place of a Plug-In Module with the Slot Profile SLT3-PER-1F-14.3.2. If done care must be made to insure unused pins of DP02 do not have an adverse effect on the RTM since DP02 will be routed to the RTM.




15.2.9.2.1 SYS_CON*


15.2.9.3 Data Plane

Rule 15.2.9.3-1: VPX 1 DP01 shall be routed as a single Fat Pipe to VPX 2 DP01, complying with the Rules of Section 7.2.1. [VM = I]





15.2.9.5 Slot Pitch




These Backplane Profiles are intended for a development environment. Some systems might be able to deploy with these backplanes. It is expected that many deployed systems will not use RTMs; instead the I/O signals that these Backplane Profiles route to RTMs would be routed, via the backplane, to connectors. For more on RTMs, see Section 4.4. Note: It is up to the RTM implementation whether it connects to these signals and what is done with them.


v

VPX1

VPX2

VPX3

VPX4

Peripheral Slots

DataPlane

DataPlane

DataPlane

DataPlane

VPX6


Data Plane(FP, UTP)

VPX5

DataPlane

DataPlane

Payload Slot


ManagementPlane (IPMB) IPMC IPMC IPMC IPMC IPMCChMC





Profile name

Mechanical Slot Profiles and Section

Channel Gbaud Rate

VPX 1 VPX 2 VPX 3 - 6

Pitch (in)

RTM Conn Payload Peripheral Peripheral

Data Plane

BKP3-CEN06-15.2.10-1 1.0 VITA

46.10 SLT3-PAY-1F4U-14.2.8

SLT3-PER-1F-14.3.2

SLT3-PER-1U-14.3.3 2.5

BKP3-CEN06-15.2.10-2 1.0 VITA

46.10 SLT3-PAY-1F4U-14.2.8

SLT3-PER-1F-14.3.2

SLT3-PER-1U-14.3.3 5.0

BKP3-CEN06-15.2.10-3 1.0 VITA

46.10 SLT3-PAY-1F4U-14.2.8

SLT3-PER-1F-14.3.2

SLT3-PER-1U-14.3.3 6.25


This section was here in error. Use Section 15.2.10.2.



Rule 15.2.10.2-1: Slot VPX 1 shall be a Payload Slot using the Slot Profiles specified in Table 15.2.10-1, for the particular Backplane Profile. [VM = I]


Rule 15.2.10.2-2: Slots VPX 2 thru 6 shall be Peripheral Slots using the Slot Profiles specified in Table 15.2.10-1, for the particular Backplane Profile. [VM = I]




15.2.10.3.1 SYS_CON*




Rule 15.2.10.4-2: VPX 1 DP02 shall be routed as an Ultra-Thin Pipe to VPX 3 DP01, complying with the Rules of Section 7.2.1. [VM = I]











These Backplane Profiles are intended for a development environment. Some systems might be able to deploy with these backplanes. It is expected that many deployed systems will not use RTMs; instead the I/O signals that this Backplane Profile routes to RTMs would be routed, via the backplane, to connectors. For more on RTMs, see Section 4.4. Note: It is up to the RTM implementation whether it connects to these signals and what is done with them.


VPX1

VPX2

VPX3

VPX4

Peripheral Slots

DataPlane

DataPlane

DataPlane

DataPlane

VPX6



Data Plane(UTP)

VPX5

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

VPX7

VPX8

VPX9

Payload Slot


IPMC IPMC IPMC IPMC IPMC IPMC IPMCChMC IPMC

v





Profile name



Pitch (in)


BKP3-CEN09-15.2.11-1 1.0 VITA

46.10 SLT3-PAY-8U-14.2.9 SLT3-PER-1U-14.3.3 2.5

BKP3-CEN09-15.2.11-2 1.0 VITA

46.10 SLT3-PAY-8U-14.2.9 SLT3-PER-1U-14.3.3 5.0

BKP3-CEN09-15.2.11-3 1.0 VITA

46.10 SLT3-PAY-8U-14.2.9 SLT3-PER-1U-14.3.3 6.25



Rule 15.2.11.1-1: Slot VPX 1 shall be a Payload Slot using the Slot Profile specified in Table 15.2.11-1, for the particular Backplane Profile. [VM = I]


Rule 15.2.11.1-2: Slots VPX 2 thru 9 shall be Peripheral Slots using the Slot Profile specified in Table 15.2.11-1, for the particular Backplane Profile. [VM = I]



15.2.11.2.1 SYS_CON*



15.2.12 6-Slot — BKP3-CEN06-15.2.12-n (1 Payload + 4 Peripheral + 1 Switch)


Figure 15.2.12-1 gives an overview of the topology. The remainder of this Section gives detailed Rules for these Backplanes Profile.

VPX1

VPX2

VPX3

VPX4

Peripheral Slots

DataPlane

DataPlane

DataPlane

DataPlane

VPX6



Data Plane(FP)

VPX5

DataPlane

DataPlane

Payl

oad

Slot

Switc

h Sl

ot

Perip

hera

l Sl

otSlot numbers are logical, physical slot numbers may be different

IPMC IPMC IPMC IPMC IPMCChMC





Profile name

Mechanical Slot Profiles and Section

Channel Gbaud Rate

VPX 1 VPX 3 VPX 2, 4 - 6

Pitch (in)

RTM Conn Payload Switch Peripheral

Data Plane

BKP3-CEN06-15.2.12-1 1.0 VITA

46.10 SLT3-PAY-

2F-14.2.7 SLT3-SWH-

4F-14.4.4 SLT3-PER-1F-14.3.2 2.5

BKP3-CEN06-15.2.12-2 1.0 VITA

46.10 SLT3-PAY-

2F-14.2.7 SLT3-SWH-

4F-14.4.4 SLT3-PER-1F-14.3.2 5.0

BKP3-CEN06-15.2.12-3 1.0 VITA

46.10 SLT3-PAY-

2F-14.2.7 SLT3-SWH-

4F-14.4.4 SLT3-PER-1F-14.3.2 6.25


Rule 15.2.12.1-1: Slot VPX 1 shall be a Payload Slot using the Slot Profile specified in Table 15.2.12-1, for the particular Backplane Profile. [VM = I]

Rule 15.2.12.1-2: Slot VPX 2 and Slots VPX 4 thru VPX 6 shall be Peripheral Slots using the Slot Profile specified in Table 15.2.12-1, for the particular Backplane Profile. [VM = I]

Rule 15.2.12.1-3: Slot VPX 3 shall be a Switch Slot using the Slot Profile specified in Table 15.2.12-1, for the particular Backplane Profile. [VM = I]




15.2.12.2.1 SYS_CON*




Rule 15.2.12.3-1: Data Pipe Port DP01 from payload Slot 1 shall be routed as a Fat Pipe to the first Data Plane Port DP01 of Slot 2, complying with the Rules of Section 7.2.1. [VM = I]

Rule 15.2.12.3-2: Data Pipe Port DP02 Payload Slot 1 shall be routed as a Fat Pipe to the first Data Plane Port DP01 of Slot 3, complying with the Rules of Section 7.2.1. [VM = I]

Rule 15.2.12.3-3: Data Pipe Ports DP02 through DP04 of Slot 3 shall be routed to DP01 of Slots 4 thru 6, complying with the Rules of Section 7.2.1. [VM = I]

Permission 15.2.12.3-1: The implementer may decide which data Plane Port DP02 through DP04 of Slot 3 goes to each of the DP01 Ports of Slots 4 through 6.







15.2.13 5-Slot — BKP3-DIS05-15.2.13-n (3 Payload + 2 Peripheral)



VPX1

VPX2

VPX3

VPX4

DataPlane

DataPlane

DataPlane

DataPlane



Data Plane(FP)

VPX5

DataPlane

Payl

oad

Slot

Payl

oad

Slot

Payl

oad

Slot

Perip

hera

l Sl

ot

Perip

hera

l Sl

otSlot numbers are logical, physical slot numbers may be different

IPMC IPMC IPMC IPMCChMC

Figure 15.2.13-1 Topology of 5 Slot - BKP3-DIS05-15.2.13-n




Profile name


Gbaud Rate

VPX 1, 2, and 4 VPX 3 and 5

Pitch (in)


BKP3-DIS05-15.2.13-1 1.0 VITA

46.10 SLT3-PAY-2F-14.2.7 SLT3-PER-1F-14.3.2 2.5

BKP3-DIS05-15.2.13-2 1.0 VITA

46.10 SLT3-PAY-2F-14.2.7 SLT3-PER-1F-14.3.2 5.0

BKP3-DIS05-15.2.13-3 1.0 VITA

46.10 SLT3-PAY-2F-14.2.7 SLT3-PER-1F-14.3.2 6.25

Note: The Utility Plane Section is at the end, see Section 15.2.13.5.


Rule 15.2.13.1-1: Slots VPX 3 and VPX 5 shall be Peripheral Slots using the Slot Profile specified in Table 15.2.13-1, for the particular Backplane Profile. [VM = I]

Rule 15.2.13.1-2: Slots VPX 1, VPX 2, and VPX 4 shall be Payload Slots using the Slot Profile specified in Table 15.2.13-1, for the particular Backplane Profile. [VM = I]



Rule 15.2.13.2-1: Data Pipe Port DP01 from payload Slot 1 shall be routed as a Fat Pipe to the first Data Plane Port DP01 of Slot 2, complying with the Rules of Section 7.2.1. [VM = I]

Rule 15.2.13.2-2: Data Pipe Port DP02 Payload Slot 2 shall be routed as a Fat Pipe to the first Data Plane Port DP01 of Slot 3, complying with the Rules of Section 7.2.1. [VM = I]


Rule 15.2.13.2-3: Data Pipe Ports DP02 of Slot 1 shall be routed as a Fat Pipe to DP01 of Slot 4 complying with the Rules of Section 7.2.1. [VM = I]

Rule 15.2.13.2-4: Data Pipe Ports DP02 of Slot 4 shall be routed as a Fat Pipe to DP01 of Slot 5 complying with the Rules of Section 7.2.1. [VM = I]








15.2.13.5.1 SYS_CON*




These Backplane Profiles are intended for a development environment. Some systems might be able to deploy with these backplanes. It is expected that many deployed systems not use RTMs; instead the I/O signals that these Backplane Profiles route to RTMs would be routed, via the backplane, to connectors. For more on RTMs, see Section 4.4. Note: It is up to the RTM implementation (the rear Plug-In Module) whether it connects to these signals and what is done with them.

Figure 15.2.14-1 gives an overview of the topology. The dotted lines, from the Switch Slot, are signals that are available to RTMs.

VPX1

VPX2

VPX3

VPX4

VPX6



Control Plane(TP)


IPMC

Switch/Management

Payloadslots

VPX5

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

TPTP

TPTP

CntrlSwitch

ContrlPlane



DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

Five Slot Ring

TP

TP





Profile name


Rate

Pitch (in)


BKP3-DIS06-15.2.14-1 1.0 VITA

46.10 SLT3-PAY-2F2T-14.2.5

SLT3-SWH-16T-14.4.6 3.125

BKP3-DIS06-15.2.14-2 1.0 VITA

46.10 SLT3-PAY-2F2T-14.2.5

SLT3-SWH-16T-14.4.6 5.0

BKP3-DIS06-15.2.14-3 1.0 VITA

46.10 SLT3-PAY-2F2T-14.2.5

SLT3-SWH-16T-14.4.6 6.25


Rule 15.2.14.1-1: Slots VPX 1 through VPX 5 shall be Payload Slots using the Slot Profile specified in Table 15.2.14-1, for the particular Backplane Profile. [VM = I]

Rule 15.2.14.1-2: Slots VPX 6 shall be a Switch Slot using the Slot Profile specified in Table 15.2.14-1, for the particular Backplane Profile. [VM = I]



15.2.14.2.1 SYS_CON*




Rule 15.2.14.3-1: Each Payload Slot shall have its Control Plane Ports CPtp01 and CPtp02 connected to the Switch Slot, one of ports TP05 thru TP14, complying with Section 7.2.2. [VM = I]


Rule 15.2.14.3-2: The Switch Slot shall have its Control Plane ports, TP01 thru TP04 available on RTM connectors on the rear of the backplane. [VM = I]

Observation 15.2.14.3-1: The lowest number ports of the Control Switch are to be used as stacking ports. Given that there are no inter-switch connections, these ports are run to RTM connectors in case stacking ports are to be used for inter-chassis connections.

Rule 15.2.14.3-3: The Switch Slot shall have its Control Plane ports, TP15 thru TP16 available on RTM connectors on the rear of the backplane. [VM = I]

Rule 15.2.14.3-4: ***Deleted***This Rule was assigned in error, it does not apply. Each Control Plane channel for the Backplane Profile name listed in Table 15.2.14-1 shall comply with the baud rate specified in the Channel Gbaud Rate column. [VM = T,A]




Channel DP01 DP02 1

5-Sl

ot M

esh

Clu

ster

1







Channel DP01 DP02 1

5-Sl

ot M

esh

Clu

ster

1






Rule 15.2.14.4-1: Each Payload Slot shall have its Data Plane Ports DP01 and DP02 connected as described by Table 15.2.14-2 or Table 15.2.14-3, complying with the Rules of Section 7.2.1. [VM = I]



Recommendation 15.2.14.4-1: Documentation for backplanes should specify which of Table 15.2.14-2 or Table 15.2.14-3, they comply with.






15.2.15 8-Slot — BKP3-CEN08-15.2.15-n (6 Payloads + 2 integrated Switches)

The BKP3-CEN08-15.2.15-n Backplane Profiles are centralized backplanes hosting 6 payloads and 2 integrated switches.

Figure 15.2.15-1 provides an overview of the topology of the BKP3-CEN08-15.2.15-n Backplane Profiles. The dotted lines, from the Switch Slot, are signals that are available to RTMs.

VPX1

VPX2

VPX3

VPX4

VPX5

VPX6

VPX7



Control Plane(UTP = 2 pair)


Payload slots Switch slots

ContrlPlane

DataPlane

DataSwitch

IPMC IPMC IPMC IPMC IPMC IPMC

VPX8

ContrlSwitch

DataSwitch

TP

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlSwitch

ChMC ChMC






Profile name


Rate

Pitch (in)


Control Plane

Data Plane

BKP3-CEN08-15.2.15-1 1.0 VITA

46.10 SLT3-PAY-2F2U-14.2.3

SLT3-SWH- 6F6U- 14.4.1

1.25 3.125

BKP3-CEN08-15.2.15-2 1.0 VITA

46.10 SLT3-PAY-2F2U-14.2.3

SLT3-SWH- 6F6U- 14.4.1

1.25 5.0

BKP3-CEN08-15.2.15-3 1.0 VITA

46.10 SLT3-PAY-2F2U-14.2.3

SLT3-SWH- 6F6U- 14.4.1

1.25 6.25




Rule 15.2.15.1-2: Logical slots 7 and 8 shall be Switch Slots using the Slot Profile specified in Table 15.2.15-1, for the particular Backplane Profile. [VM = I]



15.2.15.2.1 SYS_CON*




Refer to Figure 15.2.15-1 and Table 15.2.15-2.

Rule 15.2.15.3-1: Each Payload Slot shall have its Control Plane ports CPutp01 and CPutp02 routed in the backplane. [VM = I]

Rule 15.2.15.3-2: The logical Payload Slots Control Plane ports shall connect to the Switch Slots 7 and 8 Control Plane, complying with the Rules of Section 7.2.1. [VM = I]

Rule 15.2.15.3-3: The logical Payload Slot 6 Control Plane ports shall connect to the Switch Slots Control Plane as shown in Table 15.2.15-2. For example, logical Payload Slot 6 Control Plane port CPutp01 connects to the Switch Slot 7 Control Plane port CSutp01. [VM = I]

Permission 15.2.15.3-1: Table 15.2.15-2 shows an example of a possible port connection ordering at Switch Slots 7 and 8. Which Payload Slot Port connects to which Switch Slot Port may be jumbled except for logical Payload Slot 6 Control Plane ports.




Payload Control Plane Ports

Slot 7 Switch Control Plane Port


1 CPutp01 CPutp01

CPutp02 CPutp01

2 CPutp01 CPutp02

CPutp02 CPutp02

3 CPutp01 CPutp03

CPutp02 CPutp03

4 CPutp01 CPutp04

CPutp02 CPutp04

5 CPutp01 CPutp05

CPutp02 CPutp05

6 CPutp01 CSutp01

CPutp02 CSutp01




Rule 15.2.15.4-1: The logical Payload Slots Data Plane ports shall connect to the Switch Slots Data Plane as shown in Table 15.2.15-3, complying with the Rules of Section 7.2.1. For example, logical Payload Slot 5 Data Plane port DP01 connects to the Switch Slot 7 Data Plane port DP05. [VM = I]





Slot 7 Switch Data Plane Port


1 DP01 DP01

DP02 DP01

2 DP01 DP02

DP02 DP02

3 DP01 DP03

DP02 DP03

4 DP01 DP04

DP02 DP04

5 DP01 DP05

DP02 DP05

6 DP01 DS01

DP02 DS01





15.2.16 8-Slot — BKP3-CEN08-15.2.16-n (6 Payloads + 2 segregated Switches)

The BKP3-CEN08-15.2.16-n Backplane Profiles are centralized backplanes hosting 6 payloads and 2 segregated switches.

Figure 15.2.16-1 provides an overview of the topology of the BKP3-CEN08-15.2.16-n Backplane Profiles. The dotted line, from the Switch Slot, is a group of signals that is available to RTMs.

VPX1

VPX2

VPX3

VPX4

VPX5

VPX6

VPX7



Control Plane(UTP = 2 pair)


Payload slots Switch slots

ContrlPlane

DataPlane

IPMC IPMC IPMC IPMC IPMC IPMC

VPX8

DataSwitch

UTP

DataPlane

DataPlane

DataPlane

DataPlane

DataPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlPlane

ContrlSwitch

ChMC ChMC


12





Profile name


Rate

Pitch (in)

RTM Conn Payload

Slot 7 Data Plane Switch

Slot 8 Control Plane Switch

Control Plane

Data Plane

BKP3-CEN08-15.2.16-1 1.0 VITA

46.10 SLT3-PAY-2F2U-14.2.3

SLT3-SWH- 6F6U- 14.4.1

SLT3-SWH-2F24U-14.4.3 1.25 3.125

BKP3-CEN08-15.2.16-2 1.0 VITA

46.10 SLT3-PAY-2F2U-14.2.3

SLT3-SWH- 6F6U- 14.4.1

SLT3-SWH-2F24U-14.4.3 1.25 5.0

BKP3-CEN08-15.2.16-3 1.0 VITA

46.10 SLT3-PAY-2F2U-14.2.3

SLT3-SWH- 6F6U- 14.4.1

SLT3-SWH-2F24U-14.4.3 1.25 6.25




Rule 15.2.16.1-2: Logical slots 7 and 8 shall be Switch Slots using the Slot Profile specified in Table 15.2.16-1, for the particular Backplane Profile. [VM = I]



15.2.16.2.1 SYS_CON*





Rule 15.2.16.3-1: Each Payload Slot shall have its Control Plane Ports CPutp01 connected to Switch Slot 8, one of ports CPutp17 thru CPutp22, complying with the Rules of Section 7.2.1. [VM = I]

Rule 15.2.16.3-2: Each Payload Slot shall have its Control Plane Ports CPutp02 connected to Switch Slot 8, one of ports CPutp11 thru CPutp16, complying with the Rules of Section 7.2.1. [VM = I]

Permission 15.2.16.3-1: Table 15.2.16-2 shows an example of a possible port connection ordering at Switch Slot 8. Which Payload Slot Port connects to which Switch Slot Port may be jumbled as long as Control Plane ports number remains comprised between 11 and 22 and the 6 port numbers 17 to 22 are distributed to 6 different Payload Slots.

Rule 15.2.16.3-3: Switch Slot Control Plane ports CP01 and CP02 shall be available on RTM connectors on the rear of the backplane. [VM = I]

Rule 15.2.16.3-4: Switch Slot Control Plane ports CPutp01 thru CPutp10 shall be available on RTM connectors on the rear of the backplane. [VM = I]





Payload Control Plane Ports


1 CPutp01 CPutp22

CPutp02 CPutp16

2 CPutp01 CPutp21

CPutp02 CPutp15

3 CPutp01 CPutp20

CPutp02 CPutp14

4 CPutp01 CPutp19

CPutp02 CPutp13

5 CPutp01 CPutp18

CPutp02 CPutp12

6 CPutp01 CPutp17

CPutp02 CSutp11



Rule 15.2.16.4-1: The logical Payload Slots Data Plane ports shall connect to the Switch Slot Data Plane as shown in Table 15.2.16-3, complying with the Rules of Section 7.2.1. For example, logical Payload Slot 5 Data Plane port DP01 connects to the Switch Slot 7 Data Plane port DP05. [VM = I]









1 DP01 DP01

2 DP01 DP02

3 DP01 DP03

4 DP01 DP04

5 DP01 DP05

6 DP01 DS01









Figure 15.2.17-1 and Figure 15.2.17-2 give an overview of the topology.

VPX4

ChMC

DataSwitch



Control Plane(UTP)

Data Plane(FP)

VPX3

ControlPlane

IPMC

VPX2

DataPlane

ControlPlane

IPMC

VPX1

ControlPlane

IPMC

Expansion Plane(FP)

Payload Slots

Switch/ Management

VPX6

VPX7

VPX8

DataPlane

DataPlane

DataPlane

ControlPlane

ControlPlane

ControlPlane

IPMC IPMC IPMC

VPX9

DataPlane

ControlPlane

VPX5

DataPlane

ControlPlane

IPMC IPMC

DataPlane

DataPlane

Payload Slots

ControlSwitch

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane



Expansion Plane lanes Payloadslots 6-9 of 9-slot backplane(FP = 4 lanes)

Slot 7

EP(3:0)

EP(7:4)

Slot 6

EP(3:0)

EP(7:4)

Slot 9

EP(3:0)

EP(7:4)

Slot 8

EP(3:0)

EP(7:4)




Profile name


Pitch (in)

RTM Conn

Slot 1 Payload

Slots 2, 3, 5

Payload Slots 6-9 Payload

Slot 4 Switch

Con-trol

Plane Data Plane

Expan- sion

Plane

BKP3-CEN09-15.2.17-1

1.0 VITA 46.10

SLT3-PAY-3F2U-14.2.13

SLT3-PAY-1F2U-14.2.12

SLT3-PAY-1F2F2U-14.2.2


1.25 3.125 5.0

BKP3-CEN09-15.2.17-2

1.0 VITA 46.10

SLT3-PAY-3F2U-14.2.13

SLT3-PAY-1F2U-14.2.12



1.25 5.0 5.0

BKP3-CEN09-15.2.17-3

1.0 VITA 46.10

SLT3-PAY-3F2U-14.2.13

SLT3-PAY-1F2U-14.2.12



1.25 6.25 5.0




Rule 15.2.17.1-1: Logical slots 1 through 3 and 5 through 9 shall be Payload Slots using the Slot Profile specified in Table 15.2.17-1, for the particular Backplane Profile. [VM = I]

Rule 15.2.17.1-2: Logical slot 4 shall be a Switch Slot using the Slot Profile specified in Table 15.2.17-1, for the particular Backplane Profile. [VM = I]



15.2.17.2.1 SYS_CON*




Rule 15.2.17.3-1: The logical Payload Slot’s Control Plane ports shall connect to the Switch Slot Control Plane as shown in Table 15.2.17-2, complying with the Rules of Section 7.2.1. For example, logical Payload Slot 1 Control Plane port CPutp01 connects to the Switch Slot Control Plane port CPutp01. [VM = I]









1 CPutp01 CPutp01

1 CPutp02 No Connect, can go to RTM

2 CPutp01 CPutp02


3 CPutp01 CPutp03


5 CPutp01 CPutp04


6 CPutp01 CPutp05


7 CPutp01 CPutp06


8 CPutp01 CPutp07


9 CPutp01 CSutp01



Refer to Figure 15.2.17-1, Table 15.2.17-3 and Table 15.2.17-4.

Rule 15.2.17.4-1: The logical Payload Slot’s Data Plane ports shall connect to the switch slot Data Plane ports as shown in Table 15.2.17-3, complying with the Rules of Section 7.2.1. For example, logical Payload Slot 5 Data Plane port DP01 connects to the switch slot Data Plane port DP02. [VM = T]

Rule 15.2.17.4-2: The logical Payload Slot 1 Data Plane ports DP02 through DP03 shall connect to the Logical slots 2 and 3 Data Plane DP01 as shown in Table 15.2.17-4, complying with the Rules of Section 7.2.1. For example, logical Payload Slot 1 Data Plane port DP02 connects to the logical slot 3 Data Plane port DP01. [VM = I]







1 DP01 DP01

5 DP01 DP02

6 DP01 DP03

7 DP01 DP04

8 DP01 DP05

9 DP01 DS01




Logical Payload Slot 1

2 DP01 DP03

3 DP01 DP02


Figure 15.2.17-2 shows how the Expansion Plane interconnects Payload Slots.


Rule 15.2.17.5-2: Slots 7 Expansion Plane lanes EP[3:0] shall connect to slot 9 Expansion Plane lanes EP[3:0], complying with the Rules of Section 7.2.1. [VM = I]





15.3 3U Backplane Profiles Using VITA 46.0 and 67 connectors

The backplanes in this section incorporate one or more slot profiles that contain connectors in accordance to [VITA 67.0] and [VITA 67.1] in addition to [VITA 46.0] — Slot Profiles from Section 14.6 in addition to ones from earlier sections.

15.3.1 Common Section for 3U Backplanes Using VITA 46.0 and VITA 67 Connectors




Recommendation 15.3.1.1-1: Any signal not routed in the backplane, that utilizes VITA 46.0 connectors, should be made available on the backplane RTM connectors (RJx), unless a requirement in a Backplane Profile specifically states otherwise. [VM = I]



The Backplane Profiles of this Section (15.3) only use VITA 46.0 connector types for the J0 (See Section 6.4) and J1 positions. Depending on the Slot Profile, none, some or all of the J2 may be RF cavities.

Rule 15.3.1.2-1: The requirements of Section 15.2.1.2 shall be met. [VM = I]


15.3.2 5-Slot — BKP3-DIS05-15.3.2-n (2 Payload + 3 Payload with RF Cavities)

These Backplane Profiles are intended for a development environment. Some systems might be able to deploy with these backplanes. It is expected that many deployed systems will not use RTMs; instead the I/O signals that these Backplane Profiles route to RTMs would be routed, via the backplane, to connectors. For more on RTMs, see Section 4.4. Note: It is up to the RTM implementation (the rear Plug-In Module) whether it connects to these signals and what is done with them. The signals carried by the VITA 67 RF connectors are not connected within the backplane. Instead, coaxial cable is used to convey these signals via a special housing on the backplane enabling the coaxial signals to be routed to the back side of the backplane [VITA 67.1]. The dotted lines on the VITA 67 I/O modules depicted in Figure 15.3.2-1, represent this coaxial cable arrangement.

Figure 15.3.2-1 gives an overview of the topology.

Payload Slots



Data Plane(FP)


DataPlane

VITA 67 I/O(RF)

VPX1

VPX2

VPX3

VPX4

VPX5

VITA 67 RF

VITA 67 RF

VITA 67 RF

DataPlane

DataPlane

DataPlane

DataPlane

IPMC ChMCIPMC IPMC IPMC





Profile name Mechanical Slot Profiles and Section

Channel Gbaud Rate

Pitch (in)

RTM Conn

Payload Slots 1-2

Payload Slots 3-5

Data Plane

BKP3-DIS05-15.3.2-1 1.0 VITA 46.10

SLT3-SWH-4F-14.4.4

SLT3-PAY-4F4R-14.6.2 3.125

BKP3-DIS05-15.3.2-2 1.0 VITA 46.10

SLT3-SWH-4F-14.4.4

SLT3-PAY-4F4R-14.6.2 5.0

BKP3-DIS05-15.3.2-3 1.0 VITA 46.10

SLT3-SWH-4F-14.4.4

SLT3-PAY-4F4R-14.6.2 6.25



Rule 15.3.2.1-1: Slots VPX 1 through VPX 5 shall be Payload Slots using the Slot Profile specified in Table 15.3.2-1, for the particular Backplane Profile. [VM = I]

Observation 15.3.2.1-1: Although the Slot Profile SLT3-SWH-4F-14.4.4 is a Switch Slot Profile, the general expected usage is, for the module plugging into the slots indicated by Table 15.2.14-1, is to be used as a Payload Module as opposed to a Switch Module, so the slots using SLT3-SWH-4F-14.4.4 are referred to as Payload Slots in Figure 15.3.2-1.



15.3.2.2.1 SYS_CON*





Observation 15.3.2.3-1: This Profile does not implement a Control Plane.

15.3.2.4 Data Plane




5-Sl

ot M

esh

Clu

ster

1










15.3.2.6 Slot Pitch



15.3.3 5-Slot — BKP3-CEN05-15.3.3-n (2 Payload + 2 Payload with RF Cavities and 1 Switch)

These Backplane Profiles are intended for a development environment. Some systems might be able to deploy with these backplanes. It is expected that many deployed systems will not use RTMs; instead the I/O signals that these Backplane Profiles route to RTMs would be routed, via the backplane, to connectors. For more on RTMs, see Section 4.4. Note: It is up to the RTM implementation (the rear Plug-In Module) whether it connects to these signals and what is done with them. The signals carried by the VITA 67 RF connectors are not connected within the backplane. Instead, coaxial cable is used to convey these signals via a special housing on the backplane enabling the coaxial signals to be routed to the back side of the backplane [VITA 67.1]. The dotted lines on the VITA 67 I/O modules depicted in Figure 15.3.3-1, represent this coaxial cable arrangement.

Figure 15.3.3-1 and Figure 15.3.3-2 give an overview of the topology.

FPFP



Control Plane(UTP)

Data Plane(FP)

Expansion Plane(FP)

Switch/ Management

VPX1

VPX2

VPX3

DataPlane

DataPlane

DataPlane

ControlPlane

ControlPlane

IPMC IPMC IPMC

VPX5

ChMC

Control Switch

VPX4

DataPlane

ControlPlane

IPMC

DataSwitch

ExpanPlane

ExpanPlane

ExpanPlane

ExpanPlane

Payload Slots

ControlPlane

VITA 67 RF

VITA 67 RF

VITA 67 I/O(4 RF)

UTPUTP




Expansion Plane lanes Payloadslots of 5-slot backplane(4DFP = 4 lanes)EP(3:0) on P1

Slot 2

EP(3:0)

Slot 1

EP(3:0)

Slot 4

EP(3:0)

Slot 3

EP(3:0)




Profile Name Mechanical Slot Profiles and Section Channel Gbaud Rate

Pitch (in)

RTM Conn

Payload Slots 1,3

Payload Slots 2, 4

Switch Slot 5

Control Plane

Data Plane

Expan Plane

BKP3-CEN05-15.3.3-1

1.0 VITA 46.10

SLT3-PAY-1F1F2U-

14.2.4

SLT3-PAY-

1F1F2U4R-14.6.1


1.25 3.125 5.0

BKP3-CEN05-15.3.3-2

1.0 VITA 46.10

SLT3-PAY-1F1F2U-

14.2.4

SLT3-PAY-

1F1F2U4R-14.6.1


1.25 5.0 5.0

BKP3-CEN05-15.3.3-3

1.0 VITA 46.10

SLT3-PAY-1F1F2U-

14.2.4

SLT3-PAY-

1F1F2U4R-14.6.1


1.25 6.25 5.0








15.3.3.2.1 SYS_CON*




Rule 15.3.3.3-1: The logical Payload Slot’s Control Plane ports shall connect to the Switch Slot Control Plane as shown in Table 15.3.3-2, complying with the Rules of Section 7.2.1. For example, logical payload slot 1 Control Plane port CPutp01 connects to the switch slot Control Plane port CPutp01. [VM = I]

Rule 15.3.3.3-2: Each Payload Slot shall not have its Control Plane port CPutp02 routed in the backplane. [VM = I]


Rule 15.3.3.3-3: Ports CSutp01 and CPutp05 of the Switch Slot Control Plane shall be available on RTM connectors on the rear of the backplane. [VM = I]







1 CPutp01 CPutp01


2 CPutp01 CPutp02


3 CPutp01 CPutp03


4 CPutp01 CPutp04


15.3.3.4 Data Plane


Rule 15.3.3.4-1: The logical Payload Slot’s Data Plane ports shall connect to the switch slot Data Plane as shown in Table 15.3.3-3, complying with the Rules of Section 7.2.1. For example, logical Payload Slot 4 Data Plane port DP01 connects to the switch slot Data Plane port DP01. [VM = T]

Rule 15.3.3.4-2: Switch Slot Data Plane inter-switch port DS01 shall be available on RTM connectors on the rear of the backplane. [VM = I]

Permission 15.3.3.4-1: Switch Slot Data Plane inter-switch port DP05 may be available on RTM connectors on the rear of the backplane. [VM = I]







1 DP01 DP01

2 DP01 DP02

3 DP01 DP03

4 DP01 DP04


Figure 15.3.3-2 shows how the Expansion Plane interconnects Payload Slots.







15.3.3.7 Slot Pitch



16 3U Module Profiles The following sub-sections define different variants of 3U height Module Profiles that are used in OpenVPX systems:

16.1 3U Module Profiles Common Section

For material common to both 6U and 3U Module Profiles, see Section 8.

16.1.1 Module Cooling Types





16.1.1.1 3U VITA 48.1 Air-Cooled Modules

Recommendation 16.1.1.1-1: In order to allow their use in a Standard Development Chassis, 3U air-cooled modules should be designed to require ≤75W per slot. [VM = T,D,A]

Permission 16.1.1.1-1: 3U air-cooled modules may be designed to require >75W per slot, but these modules might not be properly powered in a Standard Development Chassis.

16.1.1.2 3U VITA 48.2 Conduction-Cooled Modules

Recommendation 16.1.1.2-1: In order to allow their use in Standard Development Chassis, 3U conduction-cooled modules should be designed to require ≤ 75W per slot. [VM = T,D,A]

Permission 16.1.1.2-1: 3U conduction-cooled modules may be designed to require >75W per slot, but these modules might not be properly powered or cooled in a Standard Development Chassis.

16.1.2 Power voltages and System Management

These Rules apply to all 3U Module Profiles, unless specified otherwise in the specific Module Profile Section:







16.2 3U Payload Module Profiles Using VITA 46.0 Connectors

16.2.1 Payload Module Profiles MOD3-PAY-2F1F2U-16.2.1-n


Rule 16.2.1-1: Plug-In Modules conforming to these profiles shall comply with Slot Profile SLT3-PAY-2F1F2U-14.2.1. [VM = I]




Table 16.2.1-1 Module Profiles MOD3-PAY-2F1F2U-16.2.1-n

Profile Name

Data Plane 2 Fat Pipes Expansion

Plane


DP01 DP02 CPutp01 CPutp02

MOD3-PAY-2F1F2U-16.2.1-1




MOD3-PAY-2F1F2U-16.2.1-2




MOD3-PAY-2F1F2U-16.2.1-3 PCIe Gen 1 per Section 5.3 PCIe Gen 1 per

Section 5.3 1000BASE-BX per

Section 5.1.1

MOD3-PAY-2F1F2U-16.2.1-4 PCIe Gen 2 per Section 5.3 PCIe Gen 2 per

Section 5.3 1000BASE-BX per

Section 5.1.1

MOD3-PAY-2F1F2U-16.2.1-5




MOD3-PAY-2F1F2U-16.2.1-6




MOD3-PAY-2F1F2U-16.2.1-7




MOD3-PAY-2F1F2U-16.2.1-8




MOD3-PAY-2F1F2U-16.2.1-9




MOD3-PAY-2F1F2U-16.2.1-10




MOD3-PAY-2F1F2U-16.2.1-11




MOD3-PAY-2F1F2U-16.2.1-12








Rule 16.2.2-2: The Plug-In Modules conforming to these profiles shall use connectors complying with [VITA 46.0]. [VM = I]




Profile Name

Data Plane 1 Fat Pipe Expansion

Plane


DP01 CPutp01 CPutp02

MOD3-PAY-1F2F2U-16.2.2-1




MOD3-PAY-1F2F2U-16.2.2-2




MOD3-PAY-1F2F2U-16.2.2-3




MOD3-PAY-1F2F2U-16.2.2-4




MOD3-PAY-1F2F2U-16.2.2-5




MOD3-PAY-1F2F2U-16.2.2-6




MOD3-PAY-1F2F2U-16.2.2-7




MOD3-PAY-1F2F2U-16.2.2-8




MOD3-PAY-1F2F2U-16.2.2-9




MOD3-PAY-1F2F2U-16.2.2-10




MOD3-PAY-1F2F2U-16.2.2-11




MOD3-PAY-1F2F2U-16.2.2-12









Rule 16.2.3-3: For the applicable Module Profile row Table 16.2.3-1, the Plug-In Module shall comply with the Plane protocol listed in each corresponding column. [VM = T]



Profile Name

Data Plane 2 Fat Pipes Control Plane 2 UTPs

DP01 DP02 CPutp01 CPutp02

MOD3-PAY-2F2U-16.2.3-1

SRIO 1.3 at 3.125 Gbaud per Section 5.2 1000BASE-BX per Section 5.1.1

MOD3-PAY-2F2U-16.2.3-2 PCIe Gen 1 per Section 5.3 1000BASE-BX per Section 5.1.1

MOD3-PAY-2F2U-16.2.3-3 PCIe Gen 2 per Section 5.3 1000BASE-BX per Section 5.1.1

MOD3-PAY-2F2U-16.2.3-4

10GBASE-BX4 per Section 5.1.4 1000BASE-BX per Section 5.1.1

MOD3-PAY-2F2U-16.2.3-5

10GBASE-KX4 per Section 5.1.5 1000BASE-BX per Section 5.1.1

MOD3-PAY-2F2U-16.2.3-6


MOD3-PAY-2F2U-16.2.3-7


MOD3-PAY-2F2U-16.2.3-8


MOD3-PAY-2F2U-16.2.3-9




Profile Name

Data Plane 1 Fat Pipe Expansion

Plane

Control Plane


MOD3-PAY-1F1F2U-16.2.4-1




MOD3-PAY-1F1F2U-16.2.4-2




MOD3-PAY-1F1F2U-16.2.4-3




MOD3-PAY-1F1F2U-16.2.4-4




MOD3-PAY-1F1F2U-16.2.4-5




MOD3-PAY-1F1F2U-16.2.4-6




MOD3-PAY-1F1F2U-16.2.4-7




MOD3-PAY-1F1F2U-16.2.4-8




MOD3-PAY-1F1F2U-16.2.4-9




MOD3-PAY-1F1F2U-16.2.4-10




MOD3-PAY-1F1F2U-16.2.4-11




MOD3-PAY-1F1F2U-16.2.4-12





16.2.5 Payload Module Profiles MOD3-PAY-2F2T-16.2.5-n


Rule 16.2.5-1: Plug-In Modules conforming to these profiles shall comply with Slot Profile SLT3-PAY-2F2T-14.2.5. [VM = I]



Table 16.2.5-1 Module Profiles MOD3-PAY-2F2T-16.2.5-n

Profile Name

Data Plane Control Plane

Fat Pipe DP01

Fat Pipe DP02

Thin Pipe CPtp01

Thin Pipe CPtp02

MOD3-PAY-2F2T-16.2.5-1 Serial RapidIO 1.3 at 3.125 Gbaud 1000BASE-T per Section 5.1.3

MOD3-PAY-2F2T-16.2.5-2 PCIe Gen 1 per Section 5.3 1000BASE-T per Section 5.1.3

MOD3-PAY-2F2T-16.2.5-3 PCIe Gen 2 per Section 5.3 1000BASE-T per Section 5.1.3

MOD3-PAY-2F2T-16.2.5-4 10GBASE-BX4 per Section 5.1.4 1000BASE-T per Section 5.1.3

MOD3-PAY-2F2T-16.2.5-5 10GBASE-KX4 per Section 5.1.5 1000BASE-T per Section 5.1.3

MOD3-PAY-2F2T-16.2.5-6 Serial RapidIO 2.0 at 5.0 Gbaud per Section 5.2 1000BASE-T per Section 5.1.3





16.2.6 Payload Module Profiles MOD3-PAY-1D-16.2.6-n


Rule 16.2.6-1: Plug-In Modules conforming to these profiles shall comply with Slot Profile SLT3-PAY-1D-14.2.6. [VM = I]



Table 16.2.6-1 Module Profiles MOD3-PAY-1D-16.2.6-n

Profile Name

Data Plane

Double Fat Pipe

MOD3-PAY-1D-16.2.6-1 PCIe Gen 1 – 2.5 Gbaud per Section 5.3

MOD3-PAY-1D-16.2.6-2 PCIe Gen 2 – 5.0 Gbaud per Section 5.3


16.2.7 Payload Module Profiles MOD3-PAY-2F-16.2.7-n


Rule 16.2.7-1: Plug-In Modules conforming to these profiles shall comply with Slot Profile SLT3-PAY-2F-14.2.7. [VM = I]





Recommendation 16.2.7-2: The following precedence should be followed; starting with the Pipe nearest to P0 following in order to the last Pipe; signaling using Peer to Peer protocols on DP01 followed by signaling using Master / Slave protocols on DP02. [VM = I]

Table 16.2.7-1 Module Profiles MOD3-PAY-2F-16.2.7-n

Profile Name

Data Plane


MOD3-PAY-2F-16.2.7-1 PCIe Gen 1 – 2.5 Gbaud per Section 5.3

PCIe Gen 1 – 2.5 Gbaud per Section 5.3

MOD3-PAY-2F-16.2.7-2 PCIe Gen 2 – 5.0 Gbaud per Section 5.3


MOD3-PAY-2F-16.2.7-3 SRIO 1.3 - 3.125 Gbaud per Section 5.2


MOD3-PAY-2F-16.2.7-4 SRIO 1.3 - 3.125 Gbaud per Section 5.2

SRIO 1.3 - 3.125 Gbaud per Section 5.2








Profile Name

Data Plane

DP01 Fat Pipe DP02 – DP05 Ultra-Thin Pipes

MOD3-PAY-1F4U-16.2.8-1 PCIe Gen 1 – 2.5 Gbaud per Section 5.3


MOD3-PAY-1F4U-16.2.8-2 SRIO 1.3 - 3.125 Gbaud per Section 5.25.2


MOD3-PAY-1F4U-16.2.8-3 PCIe Gen 2 – 5.0 Gbaud per Section 5.3


MOD3-PAY-1F4U-16.2.8-4 SRIO 1.3 - 3.125 Gbaud per Section 5.2



16.2.9 Payload Module Profiles MOD3-PAY-8U-16.2.9-n


Rule 16.2.9-1: Plug-In Modules conforming to these profiles shall comply with Slot Profile SLT3-PAY-8U-14.2.9. [VM = I]



Table 16.2.9-1 Module Profiles MOD3-PAY-8U-16.2.9-n

Profile Name

Data Plane

DP01 – DP08 Ultra-Thin Pipes

MOD3-PAY-8U-16.2.9-1 PCIe Gen 1 – 2.5 Gbaud per Section 5.3

MOD3-PAY-8U-16.2.9-2 PCIe Gen 2 – 5.0 Gbaud per Section 5.3



Profile Name

Data Plane 2 Fat Pipes Expansion

Plane


DP01 DP02 DP01 DP02

MOD3-PAY-2F4F2U-16.2.10-1




MOD3-PAY-2F4F2U-16.2.10-2




MOD3-PAY-2F4F2U-16.2.10-3




MOD3-PAY-2F4F2U-16.2.10-4




MOD3-PAY-2F4F2U-16.2.10-5




MOD3-PAY-2F4F2U-16.2.10-6




MOD3-PAY-2F4F2U-16.2.10-7




MOD3-PAY-2F4F2U-16.2.10-8




MOD3-PAY-2F4F2U-16.2.10-9




MOD3-PAY-2F4F2U-16.2.10-10




MOD3-PAY-2F4F2U-16.2.10-11




MOD3-PAY-2F4F2U-16.2.10-12











Profile Name

Data Plane 1 Fat Pipe Control Plane 2 Ultra-Thin Pipes


MOD3-PAY-1F2U-16.2.11-1

PCIe Gen 1 at 2.5 Gbaud per Section 5.3 1000BASE-BX per Section 5.1.1

MOD3-PAY-1F2U-16.2.11-2


MOD3-PAY-1F2U-16.2.11-3


MOD3-PAY-1F2U-16.2.11-4

10GBASE-KX4 Per Section 5.1.5 1000BASE-BX per Section 5.1.1

MOD3-PAY-1F2U-16.2.11-5


MOD3-PAY-1F2U-16.2.11-6


MOD3-PAY-1F2U-16.2.11-7


MOD3-PAY-1F2U-16.2.11-8





Rule 16.2.12-1: Plug-In Modules conforming to these profiles shall comply with Slot Profile SLT3-PAY-3F2U-14.2.13-n. [VM = I]




Profile Name

Data Plane 3 Fat Pipes Control Plane 2 Ultra-Thin Pipes

DP01 to DP03 CPutp01 to CPutp02

MOD3-PAY-3F2U-16.2.12-1


MOD3-PAY-3F2U-16.2.12-2


MOD3-PAY-3F2U-16.2.12-3


MOD3-PAY-3F2U-16.2.12-4


MOD3-PAY-3F2U-16.2.12-5



MOD3-PAY-3F2U-16.2.12-6



MOD3-PAY-3F2U-16.2.12-7


MOD3-PAY-3F2U-16.2.12-8



16.3 3U Peripheral Module Profiles Using VITA 46.0 Connectors





Rule 16.3.1-3: For the applicable Module Profile row in Table 16.3.1-1 the Plug-In Module shall comply with the Plane protocol listed in each corresponding column. [VM = T]


Profile Name

Data Plane


MOD3-PER-2F-16.3.1-1 Serial RapidIO 1.3 at 3.125 Gbaud per Section 5.2
















Profile Name

Data Plane

Fat Pipe DP01

MOD3-PER-1F-16.3.2-1 PCIe Gen 1 – 2.5 Gbaud per Section 5.3

MOD3-PER-1F-16.3.2-2 PCIe Gen 2 – 5.0 Gbaud per Section 5.3


16.3.3 Peripheral Module Profiles MOD3-PER-1U-16.3.3-n


Rule 16.3.3-1: Plug-In Modules conforming to these profiles shall comply with Slot Profile SLT3-PER-1U-14.3.3. [VM = I]



Table 16.3.3-1 Module Profiles MOD3-PER-1U-16.3.3-n

Profile Name

Data Plane

Ultra-Thin Pipe DP01

MOD3-PER-1U-16.3.3-1 PCIe Gen 1 – 2.5 Gbaud per Section 5.3

MOD3-PER-1U-16.3.3-2 PCIe Gen 2 – 5.0 Gbaud per Section 5.3


16.4 3U Switch Module Profiles Using VITA 46.0 Connectors

16.4.1 Switch Module Profiles MOD3-SWH-6F6U-16.4.1-n


Rule 16.4.1-1: Plug-In Modules conforming to these profiles shall comply with Slot Profile SLT3-SWH-6F6U-14.4.1. [VM = I]



Recommendation 16.4.1-1: If Recommendation 14.4.1.4.1-1 is followed, the 2 Thin Pipes (CPtp01 and CPtp02) should be used for either 1000BASE-T or 10GBASE-T. [VM = T]



Profile Name


Payload Slots DP01 – DP05

Inter-Switch DS01

Payload Slots CPutp01 to

CPutp05

Inter-Switch CSutp01

MOD3-SWH-6F6U-16.4.1-1


MOD3-SWH-6F6U-16.4.1-2

PCIe Gen 1- 2.5 Gbaud per Section 5.3 1000BASE-BX per Section 5.1.1

MOD3-SWH-6F6U-16.4.1-3

PCIe Gen 2 – 5.0 Gbaud |per Section 5.3 1000BASE-BX per Section 5.1.1

MOD3-SWH-6F6U-16.4.1-4


MOD3-SWH-6F6U-16.4.1-5


MOD3-SWH-6F6U-16.4.1-6


MOD3-SWH-6F6U-16.4.1-7


MOD3-SWH-6F6U-16.4.1-8


MOD3-SWH-6F6U-16.4.1-9





Rule 16.4.2-1: Plug-In Modules conforming to these profiles shall comply with Slot Profile SLT3-SWH-8F-14.4.2. [VM = I]




Profile Name



Inter-Switch DS01

MOD3-SWH-8F-16.4.2-1 SRIO 1.3 at 3.125 Gbaud per Section 5.2

MOD3-SWH-8F-16.4.2-2 PCIe Gen 1 – 2.5 Gbaud per Section 5.3

MOD3-SWH-8F-16.4.2-3 PCIe Gen 2 – 5.0 Gbaud per Section 5.3

MOD3-SWH-8F-16.4.2-4 10GBASE-BX4 per Section 5.1.4

MOD3-SWH-8F-16.4.2-5 10GBASE-KX4 per Section 5.1.5












Profile Name

Control Plane 24 UTPs Control Plane 2 FPs

UTP Pipes CPutp01 – CPutp24

External CP01 to CP02

MOD3-SWH-2F24U-16.4.3-1 1000BASE-BX

per Section 5.1.1 10GBASE-BX4 per Section 5.1.4

MOD3-SWH-2F24U-16.4.3-2 1000BASE-BX

per Section 5.1.1 10GBASE-KX4 per Section 5.1.5



This Module Profile uses the SLT3-PAY-1F4U-14.2.8 Slot Profile and can be used in many different ways.



Observation 16.4.4-1: Although the name of the Slot Profile for this Module reflects that it is Payload Slot Profile, this same Slot Profile can be used as a Switch Slot Profile.



Rule 16.4.4-4: The single Fat Pipe shall always be configured as a FAT Pipe. [VM = T]


Profile Name

Data Plane

DP01 FAT Pipe DP02 – DP05 Ultra-Thin Pipes

MOD3-SWH-1F4U-16.4.4-1 PCIe Gen 1 – 2.5 Gbaud

per Section 5.3 PCIe Gen 1 – 2.5 Gbaud

per Section 5.3



per Section 5.3



This set of Module Profiles uses the SLT3-SWH-4F-14.4.4. Slot Profile and can be used in many different ways. That is, a Switch Carrier combination, or Switch SATA peripheral, or Switch I/O, etc.


Rule 16.4.5-1: Plug-In Modules conforming to these profiles shall comply with Slot Profile SLT3-SWH-4F-14.4.4. [VM = I]




Profile Name

Data Plane

DP01 – DP02 Fat Pipes DP03 – DP04 Fat Pipes

MOD3-SWH-4F-16.4.5-1 PCIe Gen 1 – 2.5 Gbaud


per Section 5.3

MOD3-SWH-4F-16.4.5-2 PCIe Gen 2 – 5.0 Gbaud


per Section 5.3

MOD3-SWH-4F-16.4.5-3 SRIO 1.3 - 3.125 Gbaud


per Section 5.3

MOD3-SWH-4F-16.4.5-4 SRIO 1.3 - 3.125 Gbaud

per Section 5.2 SRIO 1.3 - 3.125 Gbaud

per Section 5.2



This set of Module Profiles uses the SLT3-SWH-2F8U-14.4.5 Slot Profile and can be used in many different ways. That is, a Switch Carrier combination, or Switch SATA peripheral, or Switch I/O, etc.




Rule 16.4.6-3: For the applicable Module Profile row in Table 16.4.6-1, the Plug-In Module shall comply with the Plane protocol listed in each corresponding column. [VM = I]

Rule 16.4.6-4: If using the PCIe protocol the Module DP01 shall always be configured as a Fat Pipe using all 4 lanes. [VM = I]



Profile Name

Data Plane

DP01 – DP02 Fat Pipes

DPutp01 – DPutp08 Ultra-Thin Pipes



per Section 5.3



per Section 5.3

MOD3-SWH-2F8U-16.4.6-3 Serial RapidIO 1.3 at 3.125 Gbaud per Section 5.2 1000BASE-BX per Section 5.1.1




per Section 5.3 1000BASE-BX per Section 5.1.1


per Section 5.3 1000BASE-BX per Section 5.1.1

MOD3-SWH-2F8U-16.4.6-8 10GBASE-BX4 per Section 5.1.4 1000BASE-BX per Section 5.1.1

MOD3-SWH-2F8U-16.4.6-9 10GBASE-KX4 per Section 5.1.5 1000BASE-BX per Section 5.1.1


16.4.7 Switch Module Profiles MOD3-SWH-16T-16.4.7-n

This set of Module Profiles uses the SLT3-SWH-16T-14.4.6 Slot Profile.


Rule 16.4.7-1: Plug-In Modules conforming to these profiles shall comply with Slot Profile SLT3-SWH-16T-14.4.6. [VM = I]


Rule 16.4.7-3: For the applicable Module Profile row in Table 16.4.7-1, the Plug-In Module shall comply with the Plane protocol listed in each corresponding column. [VM = I]

Table 16.4.7-1 Module Profiles MOD3-SWH-16T-16.4.7-n

Profile Name

Thin Pipes Routed

TP01 thru TP16

MOD3-SWH-16T-16.4.7-1 1000BASE-T per Section 5.1.3



This set of Module Profiles uses the SLT3-SWH-1F14T-14.4.7 Slot Profile and can be used in many different ways. That is, a Switch Carrier combination, or Switch SATA peripheral, or Switch I/O, etc.


Rule 16.4.8-1: Plug-In Modules conforming to these profiles shall comply with Slot Profile SLT3-SWH-1F14T-14.4.7. [VM = I]


Rule 16.4.8-3: For the applicable Module Profile row in Table 16.4.8-1, the Plug-In Module shall comply with the Plane protocol listed in each corresponding column. [VM = T,I]

Observation 16.4.8-1: The single Fat Pipe is intended for Switch-to-Switch inter-communications. Many different protocols exist and they will vary between switch chip manufacturers. Consult the board vendor for details.

Observation 16.4.8-2: Although intended for Switch-to-Switch inter-communications this is not the only purpose of the Data Plane Pipe. Other examples of use would be Network Analyzer attachment or Deep Packet Inspection engine tie-in. Therefore, use of this pipe is left to the discretion of the implementer.


Profile Name

Data Plane TP01 thru TP14 Thin Pipes DP01 Fat Pipe

MOD3-SWH-1F14T-16.4.8-1 10GBASE-BX4 per Section 5.1.4 1000BASE-T per Section 5.1.3

MOD3-SWH-1F14T-16.4.8-2 10GBASE-KX4 per Section 5.1.5 1000BASE-T per Section 5.1.3



This set of Module Profiles uses the SLT3-SWH-2F12T-14.4.8 Slot Profile and can be used in many different ways. That is, a Switch Carrier combination, or Switch SATA peripheral, or Switch I/O, etc.


Rule 16.4.9-1: Plug-In Modules conforming to these profiles shall comply with Slot Profile SLT3-SWH-2F12T-14.4.8 [VM = I]



Observation 16.4.9-1: The two Fat Pipes are intended for Switch-to-Switch inter-communications. Many different protocols exist and they will vary between switch chip manufacturers. Consult the board vendor for details.

Observation 16.4.9-2: Although intended for Switch-to-Switch expansion communications this is not the only purpose of the Data Plane Pipes. Other examples of use would be Network Analyzer attachment or Deep Packet Inspection engine tie-in. Therefore, use of these pipes is left to the discretion of the implementer.


Profile Name

Data Plane TP01 thru TP1

Thin Pipes DP01 DP02

MOD3-SWH-2F12T-16.4.9-1 10GBASE-BX4 per Section 5.1.4

10GBASE-BX4 per Section 5.1.4 1000BASE-T per Section 5.1.3

MOD3-SWH-2F12T-16.4.9-2 10GBASE-KX4 per Section 5.1.5

10GBase-KX4 per Section 5.1.5 1000BASE-T per Section 5.1.3



Profile Name



Inter-Switch DS01

Payload Slots CSutp01-CPutp07

Inter-Switch CSutp01

MOD3-SWH-6F8U-16.4.10-1


MOD3-SWH-6F8U-16.4.10-2

PCIe Gen 2 at 5.0 Gbaud |per Section 5.3 1000BASE-BX per Section 5.1.1

MOD3-SWH-6F8U-16.4.10-3


MOD3-SWH-6F8U-16.4.10-4


MOD3-SWH-6F8U-16.4.10-5


MOD3-SWH-6F8U-16.4.10-6


MOD3-SWH-6F8U-16.4.10-7


MOD3-SWH-6F8U-16.4.10-8


MOD3-SWH-6F8U-16.4.10-9



16.5 3U Miscellaneous Module Profiles Using VITA 46.0 Connectors

16.5.1 Storage Module Profiles MOD3-STO-2U-16.5.1-n


Rule 16.5.1-1: Plug-In Modules conforming to these profiles shall comply with Slot Profile SLT3-STO-2U-14.5.1. [VM = I]



Table 16.5.1-1 Module Profiles MOD3-STO-2U-16.5.1-n

Profile Name

Storage Interfaces

STRutp01 STRutp02

MOD3-STO-2U-16.5.1-1 SATA 1.5 Gbaud SATA 1.5 Gbaud



MOD3-STO-2U-16.5.1-4 SAS 3.0 Gbaud SAS 3.0 Gbaud

MOD3-STO-2U-16.5.1-5 SAS 6.0 Gbaud SAS 6.0 Gbaud


16.6 3U Payload Module Profiles Using VITA 46.0 and 67 connectors

Each of the modules in this section conform to 3-U Slot Profiles described in Section 14.6. The distinguishing feature of these Payload Module Profiles is that they define Module Profiles that in addition to utilizing connectors defined by [VITA 46.0] they also utilize connectors defined by [VITA 67.0] and [VITA 67.1].

16.6.1 Payload Module Profiles MOD3-PAY-1F1F2U4R-16.6.1-n


Rule 16.6.1-1: Plug-In Modules conforming to these profiles shall comply with Slot Profile SLT3-PAY-1F1F2U4R-14.6.1. [VM = I]

Rule 16.6.1-2: Plug-In Modules conforming to these profiles shall use connectors complying with [VITA 46.0], except where the Slot Profile calls out [VITA 67.1]. [VM = I]



Table 16.6.1-1 Module Profiles MOD3-PAY-1F1F2U4R-16.6.1-n

Profile Name

Data Plane 1 FP

Expansion Plane

Ctrl Plane 2 UTPs RF Cavities

DP01 CPutp01, CPutp02 RFpCx-A1 to

RFpCx-B2

MOD3-PAY-1F1F2U4R-16.6.1-1

PCIe Gen 1 at 2.5 Gbaud

per Section 5.3

PCIe Gen 2 at 5.0 Gbaud per Section

5.3

1000BASE-BX per Section 5.1.1 N/A

MOD3-PAY-1F1F2U4R-16.6.1-2


5.3


5.3


MOD3-PAY-1F1F2U4R-16.6.1-3



5.3


MOD3-PAY-1F1F2U4R-16.6.1-4



5.3


MOD3-PAY-1F1F2U4R-16.6.1-5

SRIO 1.3 at 3.125 Gbaud per Section

5.2


5.3


MOD3-PAY-1F1F2U4R-16.6.1-6



5.3


MOD3-PAY-1F1F2U4R-16.6.1-7



5.3


MOD3-PAY-1F1F2U4R-16.6.1-8



5.3


MOD3-PAY-1F1F2U4R-16.6.1-9



5.3



16.6.2 Payload Module Profiles MOD3-PAY-4F4R-16.6.2-n


Rule 16.6.2-1: Plug-In Modules conforming to these profiles shall comply with Slot Profile SLT3-PAY-4F4R-14.6.2. [VM = I]

Rule 16.6.2-2: Plug-In Modules conforming to these profiles shall use connectors complying with [VITA 46.0], except where the Slot Profile calls out [VITA 67.1]. [VM = I]


Table 16.6.2-1 Module Profiles MOD3-PAY-4F4R-16.6.2-n

Profile Name

Data Plane 4 FP RF Cavities

DP01 – DP04 RFpCx-A1 to

RFpCx-B2

MOD3-PAY-4F4R-16.6.2-1 PCIe Gen 1 at 2.5 Gbaud per Section 5.3 N/A

MOD3-PAY-4F4R-16.6.2-2 PCIe Gen 2 at 5.0 Gbaud per Section 5.3 N/A

MOD3-PAY-4F4R-16.6.2-3 10GBASE-KX4 per Section 5.1.5 N/A

MOD3-PAY-4F4R-16.6.2-4 10GBASE-BX4 per Section 5.1.4 N/A

MOD3-PAY-4F4R-16.6.2-5 SRIO 1.3 at 3.125 Gbaud per Section 5.2 N/A






17 3U Standard Development Chassis Profiles Standard Development Chassis are chassis that are intended for development use in controlled environments, and are not intended for deployment in rugged environments.

Many applications will be able to utilize standard development Chassis Profiles in the development phase. This Section defines 3U 10-slot, 6-slot, and 2-slot standard development Chassis Profiles that are believed to cover the majority of the of the development requirements.

Note that in some cases 3U development chassis will be tailored to the specific needs of a particular application, and this standard does not preclude that.

Note that this standard does not address deployed 3U chassis configurations, as those are specific to the application requirements.

17.1 3U Standard Development Chassis Profiles Common Section

For material common to both 6U and 3U Standard Development Chassis Profiles, see Section 9.

17.1.1 3U VITA 48.1 Air-Cooled Standard Development Chassis

Suggestion 17.1.1-1: It is suggested that 3U air-cooled Standard Development Chassis be designed to provide ≥75W per slot of DC power.

17.1.2 3U VITA 48.2 Conduction-Cooled Standard Development Chassis

Suggestion 17.1.2-1: It is suggested that 3U conduction-cooled Standard Development chassis be designed to cool the chassis sidewalls to ≤55°C with all slots dissipating 75W at a 30°C ambient temperature and mean sea level (MSL).

Suggestion 17.1.2-2: It is suggested that 3U conduction-cooled Standard Development Chassis be designed to provide ≥75W per slot of DC power.

17.2 3U Standard Development Chassis Profile Definitions

This section details how to specify a 3U Standard Development Chassis configuration. Additional chassis mechanical characteristics are defined in Section 4. Due to the number of possible chassis/backplane configurations, a 3U Standard Development Chassis Profile is defined using a name constructed from the permitted options listed below.

Rule 17.2-1: OpenVPX 3U Standard Development Chassis profiles shall be specified using the construct per Figure 17.2-1 and associated parameters. [VM = I]


Observation 17.2-1: The 3U Standard Development Chassis Profiles are 12V-centric and 5V-centric power profiles. This approach encourages module suppliers to standardize their power usage to draw the majority of power from 12V or 5V.

C H AS3-U U U-vv-W W W -x-YYY-z-bpn

C ategorization Type

Form Factor

C hassis Type

Prim aryPow er

Backp lane Pow er

C hassisM anager

S lot C ount

P lug-in M oduleC ooling

Backplane P rofile N am e

Figure 17.2-1 3U Standard Development Chassis Profile Name Construct

The parameters in Figure 17.2-1 are described below:

CHAS Standard Development Chassis Category

3 Form-factor = 3U

UUU Standard Development Chassis Type {RCK | TOW | OPN} Where RCK = 19” EIA Rack Mount TOW = Stand-alone Tower OPN = Open Frame

vv Slot Count {02 | 06 | 10}

Where 02 = 2 slots 06 = 6 slots 10 = 10 slots

WWW Primary Power {3PA | 3PB | 1PA | 1PB}

Where 3PA = 3 Phase, 208VAC, 50/60 Hz 3PB = 3 Phase, 400VAC 50/60 Hz (per CENELEC HD

472 S1:1988) 1PA = Single phase, 110/220VAC, 50/60 Hz 1PB = Single phase, 230VAC, 50/60 Hz (per CENELEC

HD 472 S1:1988)


x Plug-in Module Cooling Type {A | C} Where A = VITA 48.1 air cooled C = VITA 48.2 conduction cooled

YYY Backplane Power Option {12H | 5VH | VEN}

Where 12H = 12V centric power (see Table 17.2-1 for each chassis size)

5VH = 5V centric power (see Table 17.2-1 for each chassis size)

VEN = Supplier Defined (can be higher or lower)

z Chassis Manager {N | Y } Where N = None Y = There is a Chassis Manager.

bpn Backplane Profile Name {BKP6-XXXyy-z.z.z-n} from Section 15 (all profiles are not listed here; see Section 15) (e.g. BKP6-CEN16-15.2.2-n)

Table 17.2-1 3U Standard Development Chassis Backplane Power Options

Backplane Power Option

Chassis Size / Power Availability

2-Slot 6-Slot 10-Slot

12H

VS1 = 12V @ 12.5A, VS2 = 3.3V @ 4.5A, VS3 = 5V @ 15A, +3.3VAUX @ 8A, +12 VAUX @ 1A, -12 VAUX @ 1A

VS1= 12V @ 37.5A, VS2 = 3.3V @ 13.5A, VS3 = 5V @ 18A, +3.3VAUX @ 9A, +12 VAUX @ 3A, -12 VAUX @ 3A

VS1 = 12V @ 62.5 A, VS2 = 3.3 V @ 22.5A, VS3 = 5V @ 30A, +3.3VAUX @ 16A, +12 VAUX @ 5A, -12 VAUX @ 5A

5VH

VS1 = 12V @ 6.5A, VS2 = 3.3V @ 4.5A, VS3 = 5V @ 30A, +3.3VAUX @ 8A, +12 VAUX @ 1A, -12 VAUX @ 1A

VS1 = 12V @ 7.5A, VS2 = 3.3 V @ 13.5A, VS3 = 5V @ 90A, +3.3VAUX @ 9A, +12 VAUX @ 3A, -12 VAUX @ 3A

VS1 = 12V @ 12.5A, VS2 = 3.3 V @ 22.5A, VS3 = 5V @ 150A, +3.3VAUX @ 16A, +12 VAUX @ 5A, -12 VAUX @ 5A

VEN supplier specific (can be higher or lower)




18 6U/3U Hybrid Backplane Profiles This Section currently does not have any content. It is a placeholder in case we want to add future content here.


19 6U/3U Hybrid Standard Development Chassis Profiles This Section currently does not have any content. It is a placeholder in case we want to add future content here.

approved american national standard · 2016-10-26 · ansi/vita 65-2010 (r2012) page 2 of 555...

Documents