apps with hardware - usenix · apps with hardware enabling run-time ... user (operating system)...
TRANSCRIPT
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AppswithHardwareEnablingRun-timeArchitecturalCustomizationinSmartPhones
MichaelCoughlin,AliIsmail,EricKellerUniversityofColoradoBoulder
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MobileDevices
2
Devicesaredesignedaroundcertainrestrictions
Thisleadsvendorstomaketradeoffs
Whatifusersanddeveloperscouldchoose?
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Vision:SmartPhonewithanFPGA
3
HW SW
Android
FPGA ARM
App
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Software-definedRadio
4
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High-performanceComputing
5
Cryptography
http://www.nallatech.com/40gbit-aes-encryption-using-opencl-and-fpgas/
Analytics
http://www.datanami.com/2015/03/10/fpga-system-smokes-spark-on-streaming-analytics/
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ArchitecturalEnhancements
6
Somniloquy (NSDI09)(SEC04)
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Whyisnowtherighttime?
7
SoCs withProgrammableLogiccoupledwithARMCortexA9 (sameasiPhone4andmanyothersmartphones)
High-levelSynthesisWriteC/C++/SystemC /OpenCL code
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8
FundamentalProblem:
SharingtheFPGAbetweenapplications
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Whatwecanalreadydo
9
Processor
Apploads:softwarerunsonprocessor,FPGAconfiguredwithhardware
FPGA
AppX
AppXHardware
AppXSoftware
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Whatwecanalreadydo
10
Thisiscurrentlypossible– run-timereconfiguration
Processor FPGAAppXHardware
AppXSoftware
Apploads:softwarerunsonprocessor,FPGAconfiguredwithhardware
Sortof
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Whatwecan’tdo
11
Whatifwehavetwoapps?
Processor FPGAAppXHardware
AppXSoftware
AppY
AppYHardware
AppYSoftware
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Whatwecan’tdo
12
Whatifit’sasinglechip(andsomeI/OgoesthroughtheFPGA)
I/O
Processor FPGAAppXHardware
AppXSoftware
I/O
AppY
AppYHardware
AppYSoftware
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• Overadecadeofresearchhasproposedtwomainsolutions:– Run-timeplace-and-route– Slot-basedreconfiguration
Whyhasn’tthisbeensolvedbefore?
13
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• ThereisfreespaceintheFPGA• Placeanewmodulethere
14
Approach1:Run-timePlace/Route
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• Routingcanfail• Routingisalsoverytimeconsuming
• Therefore,isnotpractical
15
Approach1:Run-timePlace/Route
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• IdenticalemptyregionsarereservedinFPGA
• Constraintoolsto:– Notusewires/logicinsideofslots– Useexactsamewiresforinterface
16
Approach2:Slot-BasedReconfiguration
Slot1
Slot2
Slot3
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• Hardwareisloadedintoslots• Problem:ifotherlogicexists,wireroutingbecomesveryconstrained
• Therefore,isalsonotpractical
17
Approach2:Slot-BasedReconfiguration
Slot1
Slot2
Slot3
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• Run-timePlaceandRoute– Isverycomputationallyexpensive– Canpossiblyfail
• Slot-baseReconfiguration– Constrainedroutingisveryrestrictiveandnotapplicablegenerally
• Therefore,previousresearchisnotpractical
PreviousResearch
18
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• AllowsforsharingoftheFPGAbetweengeneralapps
• Usesexistingvendortechnologies
• Adoptstheideaofslotsfrompreviousresearch
• CloudRTRmakesexistingvendortechnologyworkforgeneralapps
IntroducingCloudRTR
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TheAppDeploymentModel
20
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CloudRTR
21
Manufacturers
Developer
CloudRTR
Android
FPGA ARM
Consumer
StaticDesign
1 2 3
StaticDesign
1 2 3
StaticDesign
1 2 3
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• Createsastaticdesign– Alllogicthatdoesnotchange
• Designincludesareasreservedforslots
• Sendsthistothecloudcompiler
Manufacturer
22
StaticDesign
1 2 3
GPU AXI
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• Createanappusingexistingtools
• CreateahardwaredefinitioninC
Developer
23
boolexample(ap_uint<32>*inap_uint<32>*out,bool*enabled,
)
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• Compileshardwareforeachapp– Foreachdevicevariant– Foreachslotineachvariant
AppStore(CloudCompiler)
24
X
App
[device1:[slot1:a.bit,slot2:b.bit,slot3:c.bit]]
[device2:[slot1:d.bit,slot2:e.bit]]
CloudCompiler
StaticDesign
1 2 3
StaticDesign
1 2 3
StaticDesign
1 2 3
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• Asystemservicemanagesslots
• Downloadedappsincludeslothardware
• Thesystemserviceloadsapphardwareforapps
User(OperatingSystem)
25
.apk:[device1:[slot1:a.bit,slot2:b.bit,slot3:c.bit]]
FPGAGPU AXI
1 2 3X
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• Theslotmanagerenforcesaccesstohardware
• However,FPGAscantheoreticallydirectlyaccesssensitiveresources(whilebypassingtheOS)
• Asecureloadingsystemensuresthatappscannotaccesssensitiveresources
SecurityConsiderations
26
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Secureloadingsystem
27
Processor
FPGA
Howdoesthesecureloaderwork?
Slot1 Slot2
MemoryController
OperatingSystem SignatureVerification
ReconfigurationModule
ICAP
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Secureloadingsystem
28
Processor
FPGA
Slot2
MemoryController
OperatingSystem SignatureVerification
ReconfigurationModule
ICAP
Signedmodule
Slot1
TheOSwantstoreconfigureSlot1
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Secureloadingsystem
29
Processor
FPGA
Slot1 Slot2
MemoryController
OperatingSystem SignatureVerification
ReconfigurationModule
ICAP
Signedmodule
Thesignatureofthemoduleisverified
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Secureloadingsystem
30
Processor
FPGA
Slot1 Slot2
MemoryController
OperatingSystem SignatureVerification
ReconfigurationModule
ICAP
Signedmodule
ThemoduleiswrittentotheICAP
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Secureloadingsystem
31
Processor
FPGA
Slot1 Slot2
MemoryController
OperatingSystem SignatureVerification
ReconfigurationModule
ICAPSignedmodule
TheICAPperformsthereconfiguration
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• Istherevalueinappswithhardware?
• Isthecloud-basedcompilationofCloudRTRpractical?
Evaluation
32
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Microbenchmark1:QAMdemodulator
33
4ordersofmagnitude
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Microbenchmark2:AES
34
FPGAis3xvs.
OpenSSL
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• Wealsoimplementedahardwarememoryscanner
• ItcanscantheentireaddressspacetransparentlytotheOS– 2.7%memoryreadperformancehit– 5.5%memorywriteperformancehit
• WetestedthisusingtheLMbench testbench
Microbenchmark3:MemoryScanner
35
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Brute-forcecompilation
36
GooglePlayStore Figures
#ofAppsas of Dec 14 1.43Million
AverageMonthlyAppGrowth 6.10%
#ofAppsforJanuary16 117,521
provided by AppFigures.
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Brute-forcecompilation
37
Max#ofApps Compiledperday
#ofSlots
Apps
2 121
3 96
4 76
5 59
6 51
2SlotsRequirements %ofAprilApps thatuseHardware(#ofAppsUploadedperDay)
0.1(3)
1(34)
10(347)
#ofDeviceVariants
#ofMachines RequiredtoCompileApps
1 1 1 310 1 3 29100 3 29 2881000 29 288 2875
Reasonableformostscenarios
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Brute-forcecompilation
38
6SlotsRequirements %ofAprilApps thatuseHardware(#ofAppsUploadedperDay)
0.1(3)
1(34)
10(347)
#ofDeviceVariants
#ofMachines RequiredtoCompileApps
1 1 1 710 1 7 69100 7 69 6811000 69 681 6809
Max#ofApps Compiledperday
#ofSlots
Apps
2 121
3 96
4 76
5 59
6 51
Stillreasonableformostscenarios
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• Compilationcanbeoffloadedtomanufacturers
• Manufacturerswilllikelyreusedesigns (Qualcomm,ARMchipsareoftenreused)
• Developerswilllikelyuselibraries
Reducingthenumbersevenmore
39
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• ToronAndroid
• AESisonthecriticalpath
• ExamineAESasanintegrationstudy
ImplementationCaseStudy:Orbot
40
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Whatwefound:• Memoryoperationsarethebottleneck– Datamustbeplacedcorrectlyinmemory– Userspace I/Ohashighoverhead– ManysystemcallsareincompatiblewithUIO
• Itiseasiertobuildanapplicationfromground-up
ImplementationCaseStudy:Orbot
41
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• Wehavepresentedourvisionofappswithhardware
• CloudRTRimplementsourvisionbyleveragingthemobileappdeploymentmodel
• Wehavedemonstratedthevalueandpracticalityofourvision
Conclusion
42
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VendorSupportedPartialReconfiguration
44
TargetFPGA
StaticDesign
DynamicModule (s)
Vendor tools
• base.bit• partial_1.bit• partial_2.bit
(Partialbitstreams workin1location,andarejustforbase.bit)
Goal:Spacesavingforcustomer
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• Crypto– Asymmetric(RSA,ECDSA,etc…)– Symmetric(3DES,Twofish,Blowfish)
• Softprocessors• Encoding– Networkencoding(Reed-Solmon,etc…)– Mediaencoding(JPEG,MPEG,etc…)
• DSP– FFTs,Filters,etc…
ExamplesofLibraries
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boolexample(ap_uint<32>*inap_uint<32>*out,bool*enabled,
)
Examplehardwaredefinition
46
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typedef ap_uint<32>uint32_t_hw;typedef hls::stream<uint32_t_hw>mem_stream32;
boolaes(volatileunsignedintm_mm2s_ctl[500],volatileunsignedintm_s2mm_ctl[500],volatileunsignedsourceAddress,ap_uint<128>*key_in,ap_uint<128>*iv,volatileunsigneddestinationAddress,unsignedint numBytes,intmode,mem_stream32&s_in,mem_stream32&s_out
)
Morecomplicatedhardwaredefinition
47
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Theproblem
48
Let’sexaminetheproblem
Processor FPGA
AppXhardware
AppXsoftware
I/O
I/O
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Theproblem
49
Processor FPGA
AppXhardware
AppXsoftware
I/O
I/O
First,therearevariousinterconnectsneeded
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Theproblem
50
Processor FPGA
AppXhardware
AppXsoftware
I/O
I/O
Controlsignalsandlogicmustalsobeplaced
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Theproblem
51
Processor FPGA
AppXhardware
AppXsoftware
I/O
I/O
Theappmayhavecomplexinputs,orneedtointeractwithotherlogic
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• AtrustedsystemisbootedwithSecureBoot
• Includedisastaticmodulethatreconfiguresslots
• Thismoduleonlyallowssignedmodulesintoslotsthataccesssensitiveresources
Secureloadingsystem
52
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• Buildsoffofpriorresearch…
• …butinawaythatiscompatiblewithvendortools
• Todothis,weleveragethedeploymentmodelformobileapps
Oursolution
53