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  • Architecting for VLSI Implementation

    Presenter : Chandra Shekhar

    DirectorCEERIPilani 333 031(Rajasthan)

    Phone : FAX :

    Email :

  • Architecting for VLSI Implementation

    Logic Specification vs. Implementation

    Logic Specification and Logic Implementation are two different things.

    Logic Specification precedes Logic Implementation.

    For a particular Logic Specification, there are many different possible LogicImplementations.

    These different Logic Implementations may widely differ in their cost, speedof operation and power consumption.

    Logic Specification is also called Behavioural Description of logic.

    Logic Implementation is also called Structural Description of logic.c CEERI, Pilani 1

  • Architecting for VLSI Implementation

    Specifying Logic

    How do we specify logic ?

    1. Through Boolean Expressions.

    2. Through Truth Tables.

    3. Through Natural Language Statements.

    c CEERI, Pilani 2

  • Architecting for VLSI Implementation

    !"Specifying Logic

    4. Through Programming Language Statements.

    ( , , # $% $& , $% , ' () * ) + , . . . )

    5. Through Behavioural Description Constructs of Hardware Description Lan-guages ( ,- . , , & / ) e.g. Process statement in ,- . .

    c CEERI, Pilani 3

  • Architecting for VLSI Implementation

    Implementing Logic

    How do you efficiently implement logic given the constraints on

    Speed of Operation.

    Power Consumption.

    Design Time.

    Design Cost.

    c CEERI, Pilani 4

  • Architecting for VLSI Implementation

    !"Implementing Logic

    Product Cost.

    Upgradability.

    The strategic planning and selection of an optimal approach for implementationof logic is typically called architecting or architecture design.

    c CEERI, Pilani 5

  • Architecting for VLSI Implementation

    Specifying and Implementing Logic

    Example Logic Specification

    0 1Architecture #1 (Combinational) for Logic Implementation

    ++

    ++

    ABCD

    E

    Z

    c CEERI, Pilani 6

  • Architecting for VLSI Implementation

    !"Implementing Logic

    Architecture #2 (Combinational) for Logic Implementation

    +AB

    DC

    +E

    ++

    Z

    c CEERI, Pilani 7

  • Architecting for VLSI Implementation

    !"Implementing Logic

    Architecture #3 (Sequential) for Logic Implementation

    B C D E RA

    2:1

    +

    Control

    Mux

    Select

    c CEERI, Pilani 8

  • Architecting for VLSI Implementation

    Sequential Architectures

    Characteristics of Sequential Architectures:

    They need storage elements besides combinational logic.

    They need a sequence of steps to implement the full logic specification.

    Next step should be taken only when the logic function of the previousstep has been completed and its result saved.

    c CEERI, Pilani 9

  • Architecting for VLSI Implementation

    !"Sequential Architectures

    The stepping can be asynchronous/self-timed/synchronous (with a timingsignal called clock).

    Depending upon the selection of method of stepping, sequential architec-tures can be asynchronous/self-timed/synchronous.

    c CEERI, Pilani 10

  • Architecting for VLSI Implementation

    !"Implementing Logic

    Architecture #4 (Pipelined; Synchronous) for Logic Implementation

    +AB

    DC

    +

    ++

    Z

    E

    c CEERI, Pilani 11

  • Architecting for VLSI Implementation

    !"Implementing Logic

    Architecture #5 (Pipelined; Synchronous) for Logic Implementation

    +AB

    DC

    +

    + +Z

    E

    c CEERI, Pilani 12

  • Architecting for VLSI Implementation

    Pipelined Architectures

    Characteristics of Pipelined Architectures:

    They increase the sustained throughput of logic function computation (roughlyby a factor of 2 for a 2 -stage pipelined architecture)

    They do not reduce the delay of computation of the logic function.

    Their cost is higher due to the need of pipeline registers.

    c CEERI, Pilani 13

  • Architecting for VLSI Implementation

    !"Pipelined Architectures

    They can be coarse-grained or fine-grained.

    The pipeline can be balanced (all pipeline stages have identical delays) orunbalanced (different pipeline stages have different delays).

    c CEERI, Pilani 14

  • Architecting for VLSI Implementation

    Other Architectural Choices

    Parallel Combinational Architectures.

    Parallel Sequential Architectures.

    Parallel Pipelined Architectures.

    Mixed Architectures.

    c CEERI, Pilani 15

  • Architecting for VLSI Implementation

    !"Implementing Logic

    Architecture #6 (Control-Programmable; Sequential) for Logic Implemen-tation

    B C D E RA

    Mux2:1

    ALU

    Op_Select

    Select

    Control

    c CEERI, Pilani 16

  • Architecting for VLSI Implementation

    Control-Programmable Sequential Architectures

    Characteristics of Control-Programmable Sequential Architectures:

    They have a fixed execution unit, but a programmable controller.

    By appropriately programming the controller, any logic function can beimplemented.

    A popular choice for control programming is through micro-programmingvia a Writable Control Store (WCS).

    c CEERI, Pilani 17

  • Architecting for VLSI Implementation

    !"Implementing Logic

    Architecture #7 (Instruction-set Based; Programmable; Sequential) forLogic Implementation

    The von Neumann architecture of a general-purpose stored-program digitalcomputer (CISC).

    Memory CPU

    3 3 0

    0 3 3 0

    0 3 3 0

    0 3 1 3 0

    c CEERI, Pilani 18

  • Architecting for VLSI Implementation

    CPU Block Diagram

    Control

    Sequencer

    DecoderInstruction

    Bus ControllerGenerator

    Clock

    State

    InstructionRegister

    Register Bank MAR PC ALU MDR

    Execution Unit

    Generator

    c CEERI, Pilani 19

  • Architecting for VLSI Implementation

    Instruction-Set Based Architectures

    Characteristics of Instruction-Set Based Architectures:

    They completely decouple the implementing of hardware from the logicspecification (the user logic specification).

    Each instruction in the instruction set specifies a soft gate (or virtual gate)with an appropriate logic function and its connectivity to other soft gates(through operand address specification).

    A sequence of instructions (program), therefore, can be translated into anequivalent logic network of soft gates (or a netlist of soft gates).

    c CEERI, Pilani 20

  • Architecting for VLSI Implementation

    !"Instruction-Set Based Architectures

    The equivalent logic network of virtual gates (soft gates) can be easilymodified by changing the order of instructions in the program (instructionsequence) or by changing the operand address or both.

    The implementation of each soft logic gate (instruction) using hardwarelogic is done by the CPU.

    A user implements his logic specification using only soft gates.

    A Random Access Memory (RAM) is used to store the logic specificationsimplementation in terms of soft gates including logical values of the allthe circuit nodes in the equivalent logic network of soft gates.

    c CEERI, Pilani 21

  • Architecting for VLSI Implementation

    !"Instruction-Set Based Architectures

    The instruction set (which defines the soft gates) acts as a hardware-software interface for the implementation of user specified logic function.

    The hardware implementation of logic functions of each instruction (softgate) is decided by the CPU architect/designer (and, therefore, is beyondthe control of the programmer).

    The soft gates implementation of the users logic specification is com-pletely under the control of the programmer.

    c CEERI, Pilani 22

  • Architecting for VLSI Implementation

    CISC Architectures (Register-Memory Architectures)

    Characteristics of CISC Architectures:

    Feature a large variety of addressing modes to address the memory operand(for implementing data structures in the memory4 convenient specifica-tion of interconnections amongst soft gates).

    Typically 2 operands per instruction up to one of which can be in the mem-ory (the other is in a general purpose register).

    Most instructions can use most of the addressing modes.

    c CEERI, Pilani 23

  • Architecting for VLSI Implementation

    !"Benefits of CISC Architectures

    Excellent support for data structuring and program structuring at assemblylanguage level.

    Compact object codes.

    c CEERI, Pilani 24

  • Architecting for VLSI Implementation

    !"Disadvantages of CISC Architectures

    Variable instruction lengths and many different instruction formats greatlyincrease the complexity of CPU implementation (instruction decoding andcontrol generation part of the CPU).

    Widely varying clock cycle counts for completion of different instructions makes the use of pipelining difficult.

    Increased complexity of the control part which occupies a large part of thechip area (crowding out the execution unit).

    Increased complexity of the control part also becomes a speed bottle-neck.

    c CEERI, Pilani 25

  • Architecting for VLSI Implementation

    !"Implementing Logic

    Architecture #8 (Instruction-set Based; Programmable; Sequential) forLogic Implementation

    The Harvard architecture of a gener

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