architecture and automated design flow for digital network

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ArchitectureandAutomatedDesignFlowforDigitalNetwork‐on‐chipforAnalog/RFBuildingBlockControl

WolfgangEberle,PhDIMEC|BioelectronicSystems

Wolfgang Eberle, tubs.CITY symposium July 2009 imec 2009

Bridgingsoftwareandanalog/RF

Onewayofdoingit…

Isthisstraightforward?‘Keepdigitaloutthere’,‘avoidlongwires’,‘match’,‘becompatiblewithourfloorplan’,‘don’tdisturbanalog/RF’,‘allowlatemodifications’,‘noerrors’,…

Software‐definedradio…SWcontrollinganalog/RFthroughdigitalmeans

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Outline

•  Motivation•  Digitalcommunicationnetworkforanalog/RF

–  Concept

–  Architecture

–  Designflow

–  Designflowautomation

•  Examples–  Scaldio‐1aSDR

–  Scaldio‐1bSDR

–  Neuralrecording&stimulationfront‐end(Preview)


Increaseincontrolcomplexity

FMtransmitter

1tuningknob(C9)

{WLAN,GSM,UMTS,WiMAX,…}

SDRtransceiver

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Compatibilitywithanalog/RF

Analog‐friendlyoperation,architecture,layout

Compatibilitywithanalog/RFfloorplan&designflow


State‐of‐the‐artdoesn’tmatchSDRneeds

Source:NXPAN10216‐01,I2CManual&DesignCon2003

Origin:Backplane,PCB,andIC‐level

I2C=2‐wire

SPI=(3+n)‐wire P2PandP2MP(common!)

NoCasfoundinSoCs–  Busses

–  Meshes

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Avoidingrat’snestsintelecom

Origin:Telecomnetworkinfrastructure


Scalablering‐basedarchitecture

•  Scalabilityintopology–  Ringtopology

–  Multi‐master

•  Scalabilityinthroughput&delay:–  Serialcommunication

–  Shortandlongpackets

•  Analog‐friendly–  Inactiveduringsensitiveanalogoperations

–  3‐wireinterfaceacrossthewholechip

–  Lowvoltagepossible

•  Predictabilityinarea,floorplanning:–  Nodetemplates

–  Routingchannels

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•  Singlelongpacket:Fastcontrolloops(withinastandard):controlalldistributedrelevantbitsatonce

•  Multipleshortpackets:Start‐up,standardchange:settingallparametersmaytakemoretime

Scaldio‐1a:40‐MHzclock,Scaldio‐1b:100‐MHzclock

Packetformatadaptedtooperationalrequirements


Template‐basedimplementation

•  VHDLtemplatefor–  masternode

–  slavenode

•  Modulardesign:–  Modrx,modtx:physical

–  Modmac:MAC

–  Modbitdec:logical

–  Modbufstg:phy‐analog

•  Basisforfurtherautomation–  Fromspecification

–  Towardslayout

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Whyautomation?

•  Fastdesigncycle:–  reuse

•  Latedesignchanges(quickiterations)–  Adding&droppingparameters

–  Changeinfloorplan(e.g.interference)

•  Avoidingspec2designerrorsandbettertestability–  Specasinput

–  Floorplanasinput

–  Synthesizedblocksasoutput


•  Excelsheetwith–  programmingparameters

–  format&properties(grouping,fast/slow,defaultvalue)

Toolextractspins,groups,properties

Programming:Software‐controllableparametersasstartingpoint

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(setq*noc‐layout*'((RXRF(11.84.6)("RXLNA_Pup":top"ME7"0.62.1)("RXMIX_Pup":top"ME7"0.64.5)("RXLNA_HG<0>":left"ME5"0.23.8)("RXLNA_HG<1>":left"ME5"0.22.8)("RXLNA_HG<2>":left"ME5"0.21.7))))

Analogdesignerdesignatestargetarea

Toolextractspinsandtheircoordinates

Analog/RF:floorplanasstartingpoint


Easytouseinterface

•  EmbedsentireflowintoasingleGUI

•  Hidesdifferent‘non‐classical’toolsunderneath

•  Usablebyanydesigner(system,analog,software,…)

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Examplecases:SDRfront‐end


Examplecase:SDR

Digitalcontrolnetworkfortwomulti‐standardSDRtransceiversdesigns

0.13‐mm1.2VCMOSICdirectconv.Rx,Tx,2synth.forFDDStandardscovered:UMTS,3GPP‐LTE,HSDPA,802.16e,802.11a/b/g/j/n,802.15.1/4,DAB/

DMB/DVB‐HRF:100MHz‐6GHz,BW:1‐40MHz,Power:60‐120mW

[Craninckx,ISSCC2007][Ingels,ESSCIRC2007]

Scaldio‐1bvs1a:19%moreflexibility

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Overalltopology&synthesizednode


Reducedsiliconarea

Logicsynthesis:0.25mm2vs9mm2overall

areaAreaincreaseduetologicarea:2.7%

Reductioninroutingareacompared

toP2P:>95%

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Previewneuralstimulation&recordingfront‐end


Neuro‐electronicsforbrainimplants

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Architecturalrefinementrevealsparametercontrolcomplexity


Acloserlook

•  Challenges–  Technologychange?0.13‐um

0.35‐um

–  Expected#programmingbitsforcurrentfeatureset

•  Minimum:~170bit•  Maximum:~820bit

–  SimilartoSDRfront‐end:calibrationneeds,AGC,DCO

–  Significantincreasein#blockstocontrolandspatialspreadoverthelayout

–  Considerdataread‐outusingsameroute

•  Approach–  Reusesamemethodology&tool

–  Optimizeprotocolparametersfortheapplication

Wiseetal.,Proc.IEEE,Jan2004

Recording Stimulation

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Cnclusin

•  Conceptfordigitalcontrolofanalog/RFfront‐ends–  Novelring‐basedtopology

–  Analog‐friendlyarchitecture

–  Fullpathfromspecificationtofloorplanning

–  Completeimplementationfromspecificationtologicsynthesis&layout

•  Fulldesignautomationsupport–  User‐guidedspec‐to‐layouttoolautomation

–  Compatiblewithstandardtools(Cadence)

•  Examplecases–  Fullyfunctional@(40MHz,420bits)and(100MHz,499bits)intwostate‐of‐the‐art

multi‐standardSDRtransceiverdesigns

–  Successfuldesignreusecase,latedesignchange

–  Previewreusecase:neuralstimulation&recordingfront‐end

architecture and automated design flow for digital network

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