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ARM

Memory Interface

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OverviewARM7TDMIs memory interface consists of the following

basic elements:

32-bit address bus: This specifies to memory the location

to be used for the transfer. 32-bit data bus: Instructions and data are transferred

across this bus. Data may be word, half word or byte widein size. ARM7TDMI includes a bidirectional data bus,D[31:0], plus separate unidirectional data busses,DIN[31:0] and DOUT[31:0].

Control signals: These specify, for example, the size ofthe data to be transferred, and the direction of thetransfer together with providing privileged information.

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Cycle Types All memory transfer cycles can be placed in one of four

categories:

Non-sequential cycle ARM7TDMI requests a transfer to

or from an address which is unrelated to the addressused in the preceding cycle.

Sequential cycle ARM7TDMI requests a transfer to orfrom an address which is either the same as the addressin the preceding cycle, or is one word or half word afterthe preceding address.

Internal cycle ARM7TDMI does not require a transfer,as it is performing an internal function and no usefulprefetching can be performed at the same time.

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Coprocessor register transfer ARM7TDMI wishes touse the data bus to communicate with a coprocessor, butdoes not require any action by the memory system.

These four classes are distinguishable to the memorysystem by inspection of the nMREQ and SEQ controllines

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Data Transfer Size In an ARM7TDMI system, words, half words or bytes may

be transferred between the processor and the memory

The size of the transaction taking place is determined by

the MAS[1:0] memory access size pins. These areencoded as follows:

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The processor always produces a byte address, butinstructions are either words (4 bytes) or half words (2bytes), and data can be any size.

Note that when word instructions are fetched frommemory, A[1:0] are undefined and when half wordinstructions are fetched, A[0] is undefined.

When a data read of byte or half word size is performed(eg LDRB), the memory system may safely ignore thefact that the request is for a sub-word sized quantity andpresent the whole word.

ARM7TDMI will always correctly extract the addressedbyte or half word from the data.

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When a byte or half word write occurs (eg STRH),ARM7TDMI will broadcast the byte or half word acrossthe whole of the bus. The memory system must then

decode A[1:0] to enable writing only to the addressedbyte or half word.

One way of implementing the byte decode in a DRAMsystem is to separate the 32-bit wide block of DRAM intofour byte wide banks, and generate the column address

strobes independently

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Instruction Fetch

ARM7TDMI will perform 32- or 16-bit instruction fetchesdepending on whether the processor is in ARM orTHUMB state.

The processor state may be determined externally by thevalue of the TBIT signal.

When this is LOW, the processor is in ARM state and 32-bit instructions are fetched. When TBIT is HIGH, theprocessor is in THUMB state and 16-bit instructions arefetched.

The size of the data being fetched is also indicated on theMAS[1:0] bits, as described above.

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When the processor is in ARM state, 32-bit instructionsare fetched on D[31:0].

When the processor is in THUMB state, 16-bitinstructions are fetched from either the upper, D[31:16],or the lower D[15:0] half of the bus.

This is determined by the endianism of the memorysystem, as configured by the BIGEND input, and thestate of A[1].

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When a 16-bit instruction is fetched, ARM7TDMI ignoresthe unused half of the data bus.

Endianism effect on instruction position describes

instructions fetched from the bidirectional data bus (i.e.BUSEN is LOW). When the unidirectional data bussesare in use (i.e. BUSEN is HIGH), data will be fetched fromthe corresponding half of the DIN[31:0] bus.

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Memory Management

The ARM7TDMI address bus may be processed by anaddress translation unit before being presented to thememory.

The ABORT input to the processor may be used by thememory manager to inform ARM7TDMI of page faults.

Various other signals enable different page protection levelsto be supported:

nRW can be used by the memory manager to protectpages from being written to. When 1 then processor writecycle, and when 0 then processor read cycle.

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nTRANS indicates (i.e. when 0 indicates user mode)whether the processor is in user or a privileged mode,and may be used to protect system pages from the user,

or to support completely separate mappings for thesystem and the user.

Address translation will normally only be necessary on anN-cycle.

The times when translation is necessary can be deduced

by keeping track of the cycle types that the processoruses.

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Locked Operations The ARM instruction set of ARM7TDMI includes a data

swap (SWP) instruction that allows the contents of amemory location to be swapped with the contents of a

processor register. This instruction is implemented as an uninterruptible pair

of accesses; the first access reads the contents of thememory, and the second writes the register data to thememory.

These accesses must be treated as a contiguousoperation by the memory controller to prevent anotherdevice from changing the affected memory locationbefore the swap is completed.

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ARM7TDMI drives the LOCK signal HIGH for the durationof the swap operation to warn the memory controller notto give the memory to another device.

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Stretching Access Times All memory timing is defined by MCLK, and long access

times can be accommodated by stretching this clock.

It is usual to stretch the LOW period of MCLK, as this

allows the memory manager to abort the operation if theaccess is eventually unsuccessful.

Either MCLK can be stretched before it is applied toARM7TDMI, or the nWAIT input can be used togetherwith a free-running MCLK. If nWAIT is not used it must

be tied HIGH.

Taking nWAIT LOW has the same effect as stretching theLOW period of MCLK.

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ARM7TDMI does not contain any dynamic logic whichrelies upon regular clocking to maintain its internal state.Therefore there is no limit upon the maximum period forwhich MCLK may be stretched, or nWAIT held LOW.

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The ARM Data Bus To ease the connection of ARM7TDMI to sub-word sized

memory systems, input data and instructions may belatched on a byte by byte basis.

This is achieved by use of the BL[3:0] input signalswhere BL[3] controls the latching of the data present onD[31:24] of the data bus and so on.

In a memory system containing word wide memory only,BL[3:0] may be tied HIGH.

For sub word wide memory systems, BL[3:0] are used tolatch the data as it is read out of memory.

For example, a word access to half word wide memorymust take place in two memory cycles.

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In the first cycle, the data for D[15:0] is obtained from thememory and latched into the processor on the fallingedge of MCLK when BL[1:0] are both HIGH.

In the second cycle, the data for D[31:16] is latched intothe processor on the falling edge of MCLK when BL[3:2]are both HIGH.

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The External Data Bus ARM7TDMI has a bidirectional data bus, D[31:0].

However, since some ASIC design methodologiesprohibit the use of bidirectional buses, unidirectional data

in, DIN[31:0], and data out, DOUT[31:0], busses are alsoprovided.

When the bidirectional data bus is being used, theunidirectional busses must be disabled by driving BUSENLOW.

The timing of the bus for three cycles, load-store-load.

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The unidirectional data bus When the unidirectional data busses are being used, (i.e.

when BUSEN is HIGH), the bidirectional bus, D[31:0],must be left unconnected.

When BUSEN is HIGH, all instructions and input data arepresented on the input data bus, DIN[31:0].

The timing of this data is similar to that of the bidirectionalbus when in input mode. Data must be set up and held tothe falling edge of MCLK.

In this configuration, all output data is presented onDOUT[31:0].

The value on this bus only changes when the processorperforms a store cycle.

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When BUSEN is LOW, the buffer between DIN[31:0] andD[31:0] is disabled. Any data presented on DIN[31:0] isignored.

Also, when BUSEN is low, the value on DOUT[31:0] isforced to 0x00000000.

Typically, the unidirectional busses would be usedinternally in ASIC embedded applications.

Externally, most systems still require a bidirectional databus to interface to external memory.

Unidirectional busses may be joined up at the pads of anASIC to connect to an external bidirectional bus.

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The bidirectional data bus ARM7TDMI has a bidirectional data bus, D[31:0].

Most of the time, the ARM reads from memory and so thisbus is configured to input. During write cycles however,

the ARM7TDMI must output data. During phase 2 of the previous cycle, the signal nRW is

driven HIGH to indicate a write cycle.

During the actual cycle, nENOUT is driven LOW toindicate that the ARM7TDMI is driving D[31:0] as anoutput.