arm a9 mpcore

7/25/2019 Arm A9 Mpcore

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ARM Cortex-A9

MPCore

Processor

Presented by-M. Jawwad RafqFA15-R01-017Ce no! "9#-$$$%$$55&'


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Cortex-A (er)es

Efcient application processors orevery level o perormance.

Application processors or OS anduser applications.

Processors in smartphones, tablets,notebooks, eBook readers etc.


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Cortex-A (er)es

Hih perormance, in a amily o lo!

po!er.

"orte#$A% sinle core processor or a

scalable multicore processor& t*e

Cortex-A9 MPCore +rocessor.


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'here is it used(

E#amples&$ Apple A) *iPhone +S, iPad , iPad mini-


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'here is it used( *-

E#amples&$ /010A 2era *3otorola 4oom, 1roid 4-


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'here is it used( *5-

E#amples&$ PlayStation /ita


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'hat are its specs(

"orte#$A% processors One to our

67 cache si8e per A% processor 79,5,9

6 cache 7; :B3H8>core *1hrystone

=enerally clocked bet!een ;??3H8 and=H8

Out$o$Order Superscalar Pipeline stae77

EO @ P


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'hat are its specs(

Branch Predicator

2echnoloy node +? nm to 9)nm

Supply /oltae 7.?)/

2ransistor "ount 9,??,???

Po!er "onsumption ?.) ' to 7.% '

Ca8elle Support 5D A3 traditional reisters, ;? eon

reisters

2humb$ instruction set


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eisters

A3 has 5D reisters in total, all o!hich are 5$bits lon.

7 dedicated proram counter

7 dedicated current proram statusreister

) dedicated saved proram status

reisters 5? eneral purpose reisters

79 reisters only visible in A3.

A particular SPS *saved proram


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eisters


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Pipeline Staes in A%


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Presentation Overvie!

3icro$architecture

3emory System


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3icroarchitecture Overvie!

/ariable lenth, out o order, superscalarpipeline

2!o instructions are etched in one cycle

0ssue up to + instructions per cycle into&

Primary data processin pipeline

Secondary data processin pipeline

6oad$store pipeline

"ompute enine *P>EO- pipeline


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"orte#A% 3icroarchitecture

0nstructio

n etch

1ecode

0ssueenam

e

E#ecut

e

'rite

back

3emor

y


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0nstruction etch

0nstruction cache si8e& 79:B, 5:B, or 9+:B

Superscalar pipeline& etchin t!o instructions at once

Branch Prediction&

=lobal History BuFer& 7: G 79: entries

Branch$2aret Address "ache& )7 G +: entries

eturn stack o + # 5 bits

ast$loop mode& instruction loop that are smaller than 9+bytes oten complete !ithout additional instruction cache

accesses


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0nstruction 1ecode

Super Scalar 1ecoder$ "apable o decodin t!o ull instructions per

cycle


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ename

eister enamin$ esolvin data dependencies andunroll small loops by hard!are

$ /irtual renamin o reisters


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0ssue

0ssue can dispatch up to + instructions percycle

Out o order selection o instructions rom


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E#ecute

/ariable lenth E#ecutin Stae *7 G 5 cycles-

$ 3ost 0nstructions Inish !ithin 7 cycle$ 0nstruction !hich olds shits and rotates can take 5

cycles$ A11 r?, r7, r 6S6 r5 *5 cycle- 6oical shit let

immediate *6S6-


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3emory Hierarchy

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0nstruction

"ache

1ata

"ache

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0nstruction

"ache

1ata

"ache

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0nstruction

"ache

1ata

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0nstruction

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1ata

"ache

Snoop "ontrol nit *S"-Accelerator"oherence

Port

6 "ache

3ain 3emory

"orte# A% 3Pcore


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67 caches

79, 5 or 9+:B Support or Security E#tensions

0 cache& 1 cache&

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3ain 3emory

"orte# A%3Pcore

A, R%'-b)tb/s

A, R%'-b)tb/s


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6 cache

Shared 7;:B to ;3B

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6 "ache

3ain 3emory

"orte# A%3Pcore

A, R%'-b)tb/s

A, R%'-b)tb/s


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Snoop "ontrol nit

0nteral part o cachememory systems

"onnects processors tomemory system throuhA40*Advanced E#tensible0nterace- interaces

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6 "ache

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"orte# A%3Pcore

A, R%'-b)tb/s

A, R%'-b)tb/s


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arm a9 mpcore

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