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  • ARM® Cortex®-A17 MPCore Processor Revision: r1p1

    Technical Reference Manual

    Copyright © 2014 ARM. All rights reserved. ARM DDI 0535C (ID091814)

  • ARM Cortex-A17 MPCore Processor Technical Reference Manual

    Copyright © 2014 ARM. All rights reserved.

    Release Information

    The following changes have been made to this book.

    Proprietary Notice

    Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

    Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

    The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

    This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

    Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.

    Confidentiality Status

    This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

    Product Status

    The information in this document is final, that is for a developed product.

    Web Address

    http://www.arm.com

    Change history

    Date Issue Confidentiality Change

    11 March 2014 A Confidential First release for r0p0

    28 June 2014 B Non-Confidential First release for r1p0

    18 September 2014 C Non-Confidential First release for r1p1

    ARM DDI 0535C Copyright © 2014 ARM. All rights reserved. ii ID091814 Non-Confidential

  • Contents ARM Cortex-A17 MPCore Processor Technical Reference Manual

    Preface About this book .......................................................................................................... vii Feedback .................................................................................................................... xi

    Chapter 1 Introduction 1.1 About the Cortex-A17 MPCore processor ............................................................... 1-2 1.2 Compliance .............................................................................................................. 1-3 1.3 Features ................................................................................................................... 1-5 1.4 Interfaces ................................................................................................................. 1-6 1.5 Implementation options ............................................................................................ 1-7 1.6 Product documentation and design flow .................................................................. 1-8 1.7 Product revisions ................................................................................................... 1-10

    Chapter 2 Functional Description 2.1 About the Cortex-A17 MPCore processor functions ................................................ 2-2 2.2 Interfaces ................................................................................................................. 2-6 2.3 Clocking and resets ................................................................................................. 2-8 2.4 Power management ............................................................................................... 2-17

    Chapter 3 Programmers Model 3.1 About the programmers model ................................................................................ 3-2 3.2 ThumbEE instruction set .......................................................................................... 3-3 3.3 Jazelle Architecture Extension ................................................................................. 3-4 3.4 Advanced SIMD and VFP Extensions ..................................................................... 3-6 3.5 Security Extensions architecture ............................................................................. 3-7 3.6 Virtualization Extensions architecture ...................................................................... 3-8

    ARM DDI 0535C Copyright © 2014 ARM. All rights reserved. iii ID091814 Non-Confidential

  • Contents

    3.7 Large Physical Address Extension architecture ...................................................... 3-9 3.8 Multiprocessing Extensions ................................................................................... 3-10 3.9 Operating states .................................................................................................... 3-11 3.10 Memory model ....................................................................................................... 3-12

    Chapter 4 System Control 4.1 About system control ............................................................................................... 4-2 4.2 Register summary .................................................................................................... 4-3 4.3 Register descriptions ............................................................................................. 4-27

    Chapter 5 Memory Management Unit 5.1 About the MMU ........................................................................................................ 5-2 5.2 TLB organization ...................................................................................................... 5-3 5.3 TLB match process .................................................................................................. 5-4 5.4 Memory access sequence ....................................................................................... 5-5 5.5 MMU enabling and disabling ................................................................................... 5-7 5.6 Intermediate table walk cache ................................................................................. 5-8 5.7 Memory types ........................................................................................................ 5-10 5.8 Memory region attributes ....................................................................................... 5-11

    Chapter 6 L1 Memory System 6.1 About the L1 memory system .................................................................................. 6-2 6.2 Cache features ........................................................................................................ 6-3 6.3 L1 instruction memory system ................................................................................. 6-4 6.4 L1 data memory system .......................................................................................... 6-6 6.5 Data prefetching ...................................................................................................... 6-9 6.6 Direct access to internal memory .......................................................................... 6-10

    Chapter 7 L2 Memory System 7.1 About the L2 Memory system .................................................................................. 7-2 7.2 L2 cache .................................................................................................................. 7-3 7.3 Cache coherency ..................................................................................................... 7-6 7.4 ACE master interface ............................................................................................... 7-7 7.5 ACP ....................................................................................................................... 7-12 7.6 Peripheral port ....................................................................................................... 7-14 7.7 External aborts and asynchronous errors .............................................................. 7-15

    Chapter 8 Generic Timer 8.1 About the Generic Timer .......................................................................................... 8-2 8.2 Generic Timer functional description ....................................................................... 8-3 8.3 Timer programmers model ...................................................................................... 8-4

    Chapter 9 Debug 9.1 About debug ............................................................................................................ 9-2 9.2 Debug register interfaces ......................................................................................... 9-4 9.3 Debug register summary ......................................................................................... 9-6 9.4 Debug register descriptions ................................................................................... 9-10 9.5 Debug events ......................................................................................................... 9-30 9.6 External debug interface ........................................................................................ 9-31

    Chapter 10 Performance Monitoring Unit 10.1 Abo

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