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Cortex -A8

Revision: r3p1

Technical Reference Manual

Copyright 2006-2009 ARM Limited. All rights reserved. ARM DDI 0344I

Cortex-A8Technical Reference Manual Copyright 2006-2009 ARM Limited. All rights reserved.Release Information The following changes have been made to this book.Change history Date 18 July 2006 13 December 2006 13 July 2007 16 November 2007 14 March 2008 06 October 2008 24 October 2008 03 December 2008 30 January 2009 Issue A B C D E F G H I Confidentiality Confidential Non-Confidential Non-Confidential Non-Confidential Non-Confidential Non-Confidential Non-Confidential Restricted Access Non-Confidential Unrestricted Access Non-Confidential Unrestricted Access Change First release for r1p0 First release for r1p1 First release for r2p0 First release for r2p1 First release for r2p2 First release for r2p3 First release for r3p0 Second release for r3p0 First release for r3p1

Proprietary Notice Words and logos marked with or are registered trademarks or trademarks owned by ARM Limited, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners. Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder. The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded. This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product. Some material in this document is based on ANSI/IEEE Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic and on IEEE Std. 1500-2005, IEEE Standard Testability Method for Embedded Core-based Integrated Circuits. The IEEE disclaims any responsibility or liability resulting from the placement and use in the described manner.

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Copyright 2006-2009 ARM Limited. All rights reserved. Non-Confidential

ARM DDI 0344IUnrestricted Access

Where the term ARM is used it means ARM or any of its subsidiaries as appropriate. Confidentiality Status This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to. Unrestricted Access is an ARM internal classification. Product Status The information in this document is final, that is for a developed product. Web Addresshttp://www.arm.com

ARM DDI 0344IUnrestricted Access

Copyright 2006-2009 ARM Limited. All rights reserved. Non-Confidential

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Copyright 2006-2009 ARM Limited. All rights reserved. Non-Confidential

ARM DDI 0344IUnrestricted Access

Contents Cortex-A8 Technical Reference Manual

PrefaceAbout this manual .................................................................................... xxviii Feedback ................................................................................................. xxxiv

Chapter 1

Introduction1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 About the processor .................................................................................... 1-2 ARMv7-A architecture ................................................................................. 1-3 Components of the processor ..................................................................... 1-4 External interfaces of the processor ............................................................ 1-8 Debug ......................................................................................................... 1-9 Power management .................................................................................. 1-10 Configurable options ................................................................................. 1-11 Product documentation and architecture .................................................. 1-12 Product revisions ...................................................................................... 1-14

Chapter 2

Programmers Model2.1 2.2 2.3 2.4 2.5 2.6 About the programmers model .................................................................... 2-3 Thumb-2 instruction set .............................................................................. 2-4 ThumbEE instruction set ............................................................................. 2-6 Jazelle Extension ...................................................................................... 2-10 Security Extensions architecture ............................................................... 2-13 Advanced SIMD architecture .................................................................... 2-15

ARM DDI 0344IUnrestricted Access

Copyright 2006-2009 ARM Limited. All rights reserved. Non-Confidential

v

Contents

2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 2.16 2.17 2.18

VFPv3 architecture ................................................................................... Processor operating states ....................................................................... Data types ................................................................................................ Memory formats ........................................................................................ Addresses in a processor system ............................................................. Operating modes ...................................................................................... Registers .................................................................................................. The program status registers .................................................................... Exceptions ................................................................................................ Software consideration for Security Extensions ....................................... Hardware consideration for Security Extensions ...................................... Control coprocessor .................................................................................

2-16 2-17 2-18 2-19 2-21 2-22 2-23 2-27 2-35 2-44 2-45 2-48

Chapter 3

System Control Coprocessor3.1 3.2 About the system control coprocessor ....................................................... 3-2 System control coprocessor registers ........................................................ 3-9

Chapter 4

Unaligned Data and Mixed-endian Data Support4.1 4.2 4.3 About unaligned and mixed-endian data .................................................... 4-2 Unaligned data access support .................................................................. 4-3 Mixed-endian access support ..................................................................... 4-5

Chapter 5

Program Flow Prediction5.1 5.2 5.3 5.4 5.5 5.6 About program flow prediction .................................................................... Predicted instructions ................................................................................. Nonpredicted instructions ........................................................................... Guidelines for optimal performance ............................................................ Enabling program flow prediction ............................................................... Operating system and predictor context ..................................................... 5-2 5-3 5-6 5-7 5-8 5-9

Chapter 6

Memory Management Unit6.1 6.2 6.3 6.4 6.5 6.6 6.7 About the MMU ........................................................................................... Memory access sequence .......................................................................... 16MB supersection support ........................................................................ MMU interaction with memory system ........................................................ External aborts ........................................................................................... TLB lockdown ............................................................................................. MMU software-accessible registers ............................................................ 6-2 6-3 6-4 6-5 6-6 6-7 6-8

Chapter 7

Level 1 Memory System7.1 7.2 7.3 7.4 7.5 7.6 About the L1 memory system ..................................................................... 7-2 Cache organization ..................................................................................... 7-3 Memory attributes ....................................................................................... 7-6 Cache debug .............................................................................................. 7-9 Data cache features ................................................................................. 7-10 Instruction cache features ........................................................................ 7-11

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Copyright 2006-2009 ARM Limited. All rights reserved. Non-Confidential

ARM DDI 0344IUnrestricted Access

Contents

7.7 7.8

Hardware support for virtual aliasing conditions ....................................... 7-13 Parity detection ..........................................

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