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• TECHNISCHE UNIVERSITÄT • KAISERSLAUTERN

Armin Wellig

Design Space Exploration of Memory­dominated 3G Baseband Receivers

Design-Exploration von speicherdominanten 3G Basisband Empfängern

Forschungsberichte Mikroelektronik • Band 9

Herausgegeben von Prof. Dr.-Ing. N. Wehn

Contents

Chapter 1 Introduction 1

1.1 Evolution of radio access technologies 1

1.2Battery technology trends 3

1.3 Objectives and outline 4

Chapter 2 Design Space Exploration 6

2.1 Thedesign space exploration tree 7

2.1.1 Application domain 7

2.1.2 Architecture domain 8

2.1.3 Design space modeling 9

2.1.4 Design objectives 10

2.1.5 Design metrics 11

2.1.6 Exploration methodology 12

2.1.7 Languages and tools 13

2.2 A customized exploration framework for dataflow Systems 14

2.2.1 Application domain: 3GPP-compliant baseband receiver 14

2.2.2 System-on-Chip component portfolio 16

2.2.3 Design and exploration flow 18

2.3 Conclusion 24

Chapter 3 Design techniques for energy-efficient and low power Systems 25

3.1 The quest for energy-efficiency and low power 26

3.1.1 Power versus Energy 26

3.1.2 Power consumption in CMOS circuits 27

3.1.3 Low power CMOS design 31

3.2 Energy-efficient memory Systems 35

3.2.1 Dynamic energy reductions 36

3.2.2 Static power reductions 37

3.3 Conclusion 43

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Chapter 4 Hybrid-ARQ design 44

4.1 High Speed Downlink Packet Access 45

4.1.1 HSDPA concepts 45

4.1.2 Sector throughput 46

4.2 Memory-subsystem exploration 49

4.2.1 H-ARQ architecture template 49

4.2.2 Architecture exploration 53

4.3 H-ARQ IP Core Architecture 57

4.3.1 Leap-frog de-puncturing 58

4.4 Conclusion 61

Chapter 5 Interleaving 62

5.1 Interleaving basics 63

5.1.1 Interleaving, Channel Coding and Power Control 63

5.1.2 Block interleaver 64

5.1.3 State-of-the-art deinterleaver implementations 66

5.2 Interleaving and Multiplexing Subsystems 68

5.2.1 The 2-stage MCIL Subsystem 68

5.2.2 The C-fold decimation property 70

5.3 Two-level memory hierarchy design 77

5.3.1 Correlation properties 77

5.3.2 Embedded Reordering 79

5.3.3 Architecture Performance 81

5.4 Application-specific high-throughput design 92

5.4.1 HSDPA-specific architecture exploration 92

5.4.2 Channel-interleaveddeinterleaving 93

5.4.3 Architecture template 94

5.4.4 Synthesis results 95

5.5 Conclusion 96

Chapter 6 Short sequence decoding 98

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6.1 Introduction 98

6.1.1 TFCIencoding 99

6.2 Reduced-Search MLSE 102

6.2.1 MLSE algorithm 102

6.2.2 Reduced-Search MLSE algorithm 104

6.3 TFCI decoding 105

6.3.1 State-of-the-art TFCI decoding 106

6.3.2 Reduced Search TFCI decoding 108

6.3.3 Implementation Performance 109

6.4 Conclusion 113

Chapter 7 Conclusion 115

Chapter 8 Zusammenfassung 118

Appendix A 125

Appendix B 134

Appendix C 135

Bibliography 143

ListofFigures 155

ListofTables 158

Lebenslauf 159

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