ARM's NEW ARCHITECTURE FOR AUTOMOTIVE AND

INDUSTRIAL CONTROL MARKETS

1

CONTENTS

Sl.No. Topic Page.No.

I LIST OF FIGURES i

II LIST OF TABELS ii

III NOMENCLATURE iii

1 ABSTRACT 01

2. INTRODUCTION 02

2.1 Advanced Driver Assistance Systems (ADAS) 02

2.2 Hybrid Electric vehicle (HEV) power train control 02

3. WHAT’S SPECIAL IN THIS VERSION? 03

4. KEY FEATURES OF ARMv8-R ARCHITECTURE 05

4.1 Virtual memory system architecture (VMSA) 05

4.2 About the VMSA 05

5. VIRTUALIZATION 08

5.1 Hardware vitualization/ platform virtualization 08

5.1.1 Different Types of Hardware Virtualization 08

5.2 Hardware-assisted virtualization 09

6. VFP v3/4 09

7. GIC Registers 09

8. WHY HYPERVISOR FOR AUTOMOTIVE? 11

9. TODAY’S CORTEX-R ARCHITECTURE 14

10. CONCLUSION 18

11. BIBILIOGRAPHY 19

2

LIST OF THE FIGURES

FIG. No NAME OF FIGURE PAGE No

1. ARM v8-R Privilege Levels 04

2. The ARMV8-R Architecture 07

3. ARMv8-R in a car 12

4. Instruction Set of ARMv8-R and ARMv8-A 15

3

LIST OF TABLES

TABLE. No TABLE NAME PAGE. No

1 CORTEX-A15 GIC memory-map 09

2 A-profile, R-profile and M-profile 16

3 Cortex-R4, Cortex-R5, and Cortex-R7 17

4

NOMENCLATURE

ABBREVIATION EXPANSION

ARM Advanced RISC Machine

RISC Reduced Instruction Set computer

ADAS Advanced Driver Assistance Systems

HEV Hybrid Electric vehicle

ACC Adaptive Cruise Control

ISA Intelligent Speed Advice

ICE Internal Combustion Engine

TMC Toyota Motor Company

SIMD Single Instruction to

Multiple Data

SEI System Error Interrupt

VMSA Virtual Memory System Architecture

CRC Cyclic Redundancy Check

MMU Memory Management Unit

TLB Translation Lookaside Buffer

ASID Application Space Identifier

OEM Original Equipment Manufacturer

PMSA Protected Memory System Architecture

MPU Memory Protection Unit

5

1. ABSTRACT:

ARM Holdings reveals latest evolution of the ARM real time architecture profile, targeted

specifically for the automotive and industrial segments. ARM is a RISC-based architecture

designed specifically for low-power computing, mainly because processors based on these

architectures use fewer transistors than those found in a traditional processor. As a result, ARM-

based processors are extremely popular in portable and battery powered devices, and almost all

smartphones and tablets are powered by them. ARM has now launched a new generation of

Cortex-R series of real time processors for automotive and industrial safety and control

applications. Featuring some real time capabilities of application (A) profile ARMv8-A and real

time (R) profile ARMv7-R architectures, ARMv8-R is built with key architectural developments

to focus on requirements of future integrated control and safety applications. ARMv8-R

architecture specification will have high end memory protection capabilities with real time and

industrial safety characteristics. The deployment of ARMv8-R architecture will result in cost

reduction and improvement in efficiency and performance of the embedded systems to match the

needs of the automotive applications such as Advanced Driver Assistance Systems (ADAS),

Hybrid Electric vehicle (HEV) power train control and factory automation.

Index Terms—VMSA (virtual memory system architecture), PMSA (protected memory

system architecture), microcontroller unit (MCU)

6

2. INTRODUCTION:

2.1 Advanced Driver Assistance Systems (ADAS):

They are the systems to help the driver in the driving process. When designed with a safe

Human-Machine Interface it should increase car safety and more generally road safety.

Examples of such system are:

In-vehicle navigation system with typically GPS and TMC for providing up-to-date

traffic information

Adaptive cruise control(ACC)

Lane departure warning system

Collision avoidance system (precrash system)

Intelligent speed adaptation or intelligent speed advice(ISA)

Night vision

Adaptive light control

Pedestrian protection system

Automatic parking

Traffic sign recognition

Blind spot detection

Driver drowsiness detection

Vehicular communication systems

Hill descent control

Electric vehicle warning sounds used in hybrids and plug-in-electric vehicle.

2.2 Hybrid Electric vehicle (HEV) power train control:

The Toyota Prius is the world’s best selling hybrid car, with cumulative global sales of over 3

million units through June 2013. A hybrid electric vehicle is a type of hybrid vehicle and electric

7

vehicle which combines a conventional internal combustion engine (ICE) propulsion system

with an electric propulsion system.

The presence of the electric powertrain is intended to achieve either better fuel economy than a

conventional vehicle or better performance. There are a variety of HEV types, and the degree to

which they function as EVs varies as well. The most common form of HEV is the hybrid electric

car, although hybrid electric trucks (pickups and tractors) and buses also exist.

Modern HEVs make use of efficiency-improving technologies such as regenerative braking,

which converts the vehicle’s kinetic energy into electric energy to charge the battery, rather than

wasting it as heat energy as conventional brakes do. Some varieties of HEVs use their internal

combustion engine to generate electricity by spinning an electrical generator ( this combination

is known as a motor-generator), to either recharge their batteries or to directly power the electric

drive motors. Many HEVs reduce idle emissions by shutting down the ICE at idle and restarting

it when needed; this is known as a start-stop system.

A hybrid electric produces less emission from its ICE than a comparably sized gasoline car, since

an HEV’s gasoline engine is usually smaller than a comparably sized pure gasoline-burning

vehicle (natural gas and propane fuels produce lower emissions) and if not used to directly drive

the car, can be geared to run at maximum efficiency, further improving fuel economy. About 6.8

million hybrid electric vehicles have been sold worldwide by august 2013, led by Toyota Motor

Company(TMC) with more than 5.5 million Lexus and Toyota hybrids sold as of August 2013.

3. What's special in this version?

One of the key developments in 32-bit ARMv8-R architecture is use of a hypervisor mode in

processor hardware and support for hardware virtualization. Combing the two will result in a

virtual machine monitor, enabling programmers to combine different operating systems,

applications and real-time tasks on a single processor and at the same time ensuring isolation of

memory and processing time between those operating systems, applications and real-time tasks.

This will facilitate software consolidation and re-use, which will accelerate time-to-market and

reduce development costs

8

Fig 1: ARM v8-R Privilege Levels

9

4. Key Features of ARMv8-R architecture:

•Support for ARM's advanced SIMD extensions (ARM NEON Technology) for accelerating

multimedia and signal processing algorithms.

•System register mapping of the interrupt control registers and the addition of a System Error

Interrupt (SEI) for improvement of interrupt response time and handling of critical errors.

•Support for full Virtual Memory System Architecture (VMSA) for the use of wide range of

software assets present in application processor and rich operating system world.

•

Instruction sets from ARMv8-A architecture with new instructions for managing memory

protection, Cyclic Redundancy Check (CRC) instructions and enhanced floating point

instructions according to the latest IEEE standard.

4.1 Virtual memory system architecture (VMSA):

It is based on a memory management unit (MMU). It contains the following sections:

4.2 About the VMSA:

Complex operating systems typically use a virtual memory system to provide separate, protected

address spaces for different processes. Processes are dynamically allocated memory and other

memory mapped system resources under the control of a memory management unit(MMU). The

MMU allows fine-grained control of a memory system through a set of virtual to physical

address mappings and associated memory properties held within one or more structures known

as Translation Look aside Buffers (TLBs) within the MMU. The contents of the TLBs managed

through hardware translation lookups from a set of translation tables maintained in memory.

The process of doing a full translation table lookup is called a translation table walk. It is

performed automatically by hardware, and has a significant cost in execution time, atleast one

main memory access, and often two. TLBs reduce the average cost of a memory access by

caching the results of translation table walks. Implementations can have a unified TLB( von

Neumann architecture) or separate instruction and Data TLBs( Harvard architecture).

The VMSA has been significantly enhanced in ARMv6. This is referred to as VMSAv6. To

prevent the need for TLB invalidation on a context switch, each virtual to physical address

10

mapping can be marked as being associated with a particular application space, or as global for

all application spaces. Only global mappings and those for the current application space are

enabled at any time. By changing the application space identifier (ASID), the enabled set of

virtual to physical address mappings can be altered. VMSAv6 has added definitions for different

memory types

Memory access sequence

Memory access control:

This controls whether a program has no-access, read-only access, or read/write access to

the memory area. When an access is not permitted, a memory abort is signaled to the

processor. The level of access allowed can be affected by whether the program is running

in user mode, or a privileged mode, and by the use of domains.

Memory region attributes:

These describe properties of a memory region, examples include device (VMSAv6), non-

cacheable, write-through, and write-back.

Thumb instructions:

The Thumb instruction set is a subset of the most commonly used 32-bit ARM instructions.

Thumb instructions are each 16 bits long, and have a corresponding 32-bit ARM instruction that

has the same effect on the processor model. Thumb instructions operate with the standard ARM

register configuration, allowing excellent interoperability between ARM and Thumb states. On

execution, 16-bit Thumb instructions are transparently decompressed to full 32-bit ARM

instructions in real time, without performance loss.

Thumb has all the advantages of a 32-bit core:

32-bit address space

32-bit registers

32-bit shifter, and Arithmetic Logic Unit (ALU)

11

Fig 2. The ARMV8-R Architecture

12

5. Virtualization:

It refers to the act of creating virtual (rather than actual) version of something including but not

limited to a virtual computer hardware platform, operating system, and storage device or

computer network resources.

The term “virtualization” traces its roots to 1960s mainframes, during which it was a method of

logically dividing the mainframes resources for different applications since then, the meaning of

the term has evolved to the afore mentioned.

5.1 Hardware virtualization/ platform virtualization:

It refers to the creation of a virtual machine that acts like a real computer with an OS software

executed on these virtual machines is separated from the underlaying hardware resources. For

example, a computer that is running Microsoft windows may host a virtual machine that looks

like a computer with Ubuntu Linux OS, Ubuntu-based software can be run on the virtual

machine. In hardware virtualization, the host machine is the actual machine on which the

virtualization takes place, and the guest machine is the virtual machine. The words host and

guest are used to distinguish the software that runs on the physical machine from the software

that runs on the virtual machine.

The software or firmware that creates a virtual machine on the host hardware is called a

hypervisor or virtual machine manager.

5.1.1 Different Types of Hardware Virtualization:

i. Full virtualization:

Almost complete simulation of the actual hardware to allow software, which typically

consists of a guest OS, to run unmodified.

ii. Partial virtualization:

Some but not all of the target environment is simulated. Some guest programs, therefore,

may need modifications to run in this virtual environment.

iii. Para virtualization:

A hardware environment is not simulated, however, the guest programs are executed in

their own isolated domains, as if they are running on a separate system modified to run in

this environment.

13

5.2 Hardware-assisted virtualization:

It is a way of improving the efficiency of hardware virtualization and involves employing

specially designed CPUs, hardware components that help improve the performance of a guest

environment.

6. VFP v3/4:

VFP can be used for “normal” (non-vector) floating point calculations. Also, NEON doesn’t

support double-precision FP so only VFP instructions can be used for that. Instructions starting

with V (eg.vldl.32, vmla.f32) are NEON instructions, and those starting with F(eg.fldd, fmacd)

are VFP.( Although ARM docs now prefer using the vprefix even for VFP instructions.

VFPv3 is an optional extension to the ARM, ThumbEE instruction sets in the ARMv7-A and

ARMv7-R profiles. Some of the VFP extension register banks are VFPv2, VFPv3-D16-FP16 and

VFPv3-D16.

7. GIC Registers:

The GIC registers are grouped into four contiguous 4 kb or 8 kb pages. The distributor block

reside in the 4kb page, while the cpu interface, virtual interface control, and virtual cpu interface

blocks reside in the 8kb pages. The GIC provides two ways to access the GIC virtual interface

control registers. A single common base address for the GIC virtual interface control registers.

Each processor can access to its own GIC virtual interface control registers through this base

address.

CORTEX-A15 GIC memory-map:

Base offset Offset range GIC block

0x0000 0x0000-0x0FFF Reserved

0x1000 0x1000-0x1FFF Distributor

0x2000 0x2000-0x3FFF CPU interface

0x4000 0x5000-0x4FFF Virtual interface control

( common base address)

0x5000 0x6000-0x7FFF Virtual CPU interface

Table 1: CORTEX-A15 GIC memory-map

14

A number of operating system products will support ARMv8-R architecture ecosystem including

INTEGRITY from Green Hills Software, Nucleus from Mentor Graphics, and T-Kernel from

eSOL.

According to David Kleidermacher, chief technology officer at Green Hills Software, "The

evolution to support concurrent general-purpose and real-time operating systems is a significant

development for ARM architecture and the ARM ecosystem."

Mentioning about automotive and industrial interoperability and safety standards, he said, “We

expect our eT-Kernel real-time OS and its dedicated IDE to be certified for ISO 26262

automotive functional safety standard in the second quarter in 2014."

Glenn Perry, general manager of Mentor Graphics Embedded Software Division said, "Mentor’s

support of the ARMv8-R architecture will enable both ARM licensees and embedded developers

to create innovative solutions for automotive, industrial, and safety-critical applications."

“Our mutual customers can make use of this innovative architecture ahead of silicon availability

through virtual prototypes and also when ARMv8-R based devices are available with the small

footprint, power-efficient Nucleus RTOS, Mentor Embedded Linux, virtualization technologies,

AUTOSAR solutions and Sourcery Code Bench tools," he added.

MADISON, Wis.-

ARM has unveiled its new microprocessor architecture specifically designed to run

deterministic, real-time embedded applications in automotive electronics and other

industrial control systems.

One of the highlights of the new architecture--dubbed ARMv8-R—is a hardware-assisted

virtualization mode designed in its real-time embedded processor. EE Times has learned

that Nvidia is likely to be among the first companies to license the ARMv8-R

architecture.

Described by ARM as a “bare-metal” hypervisor mode, the new architecture’s

virtualization feature is in big demand among real-time embedded system designers

saddled with the “increasingly sticky problem of combining different software with

safety-critical applications,” says Richard York, director of product marketing at ARM.

The need to run different operating systems, applications, and real-time tasks on a single

15

processor is paramount. Yet system designers are asked to do so by ensuring they are

strictly isolated from one another.

Automotive customers—carmakers and Tier 1s included—are particularly eager for the

virtualization feature, according to York.

The ARMv8-R architecture is designed to run rich Oss( such as Android for a graphical

user interface) and real-time operating systems on the same processor. It is also designed

to allow both virtual memory and protected memory systems to coexist on one processor.

ARMv8-R architecture enables a “rich” OS with memory management.

Kevin Krewell, senior analyst at the Linley Group, summed it up:

“A system designer can consolidate multiple real-time microcontroller functions into one

ARM8-R based processor without posing real-time responsiveness and process

isolation.”

Those looking to play a bigger role in the automotive market are paying close attention to

ARM’s new microprocessor architecture. Asked about ARMv8-R, Nvidia told EE Times

in a separate interview in which Nvidia is investing heavily in the development of

hypervisor solutions for a number of markets, including automotive. Based on the ARM

architecture, Nvidia automobile solutions will be able to run multiple operating systems

on a single processor to enable simultaneous use of both infotainment applications and

more safety-critical functions.

8. Why hypervisor for automotive?

A big change in the automotive landscape in recent years is that more and more features in new

cars are defined in software and electronics, rather than mechanical systems. As a result, “more

and more car OEMs have begun writing their own software codes.” Explained York. Carmakers,

seeking a little bit more control over their own cars, are coming up with clever new features

through their own software.

The need to handle the growing load of disparate software including contributed codes by OEMs

is, in turn, pressuring Tier 1 modular vendors such as Bosch or continental, said York. Their

modules are now expected to run, on the same ECU, new contributed codes from OEMs

16

(original equipment manufacturers) alongside existing software—some of which are safety-

critical applications—“without mucking everything up,” said York.

Fig 3. ARMv8-R in a car

Contributed codes are all over the map. Their spectrum ranges from safety-related features such

as braking to less critical functions like window wipers, seat positioning, and new graphics on

the human-machine interface. The key for the successful integration of such diverse software is

the microprocessor’s ability to make a clear partition separating one app from another.

Leading software vendors such as Green Hills Software already offer secure virtualization

through a well proven hypervisor layer, York told us. To date, however, none had developed

hardware support for virtualization. With hardware support, “you no longer need to rely on

writing complex software, which is often a very expensive solution.”

The fundamentals of the ARMv8-R architecture are consistent with the ARMv8-A, according to

York. While the previously announced ARMv8-A architecture is focused more on high

performance, the ARMv8-R zeroes in on real-time processing. The new architecture, for the time

being, only supports 32-bit register, as the company does not see, for now, the need for 64-bit

17

among real-time embedded applications, said York. The new ARMv8-R will maintain backward

compatibility with ARMv7-R ARM and Thumb instruction sets.

Ecosystem support for the ARMv8-R architecture is anticipated in a number of operating system

products including Green Hills Software’s Integrity, Nucleus from Mentor Graphics, and T-

kernel from eSOL, according to ARM. These integrated hardware and software solutions will be

capable of supporting stringent automotive and industrial interoperability and safety standards,

including AUTOSAR, ISO 26262, and IEC61508. ARM will be disclosing details of the new

architecture at the upcoming event.

The ARM architecture continuosly evolves to support deployment of energy-efficient

computation devices in a growing spectrum of applications that can take advantage of progress in

semiconductor technology.

Recent advances included the large physical address extensions (LPAE) for the ARMv7-A

applications architecture and the new 32-/64 bit ARMv8-A applications architecture. These

developments will lead to a new generation of cortex-R processors that will meet the needs of

integrated control and safety systems in applications such as ADAS, HEV power train control

and factory automation.

ARM is known primarily for its range of cortex-A processors used in significant numbers of

consumer devices such as smart phones and tablets. Each of these processors is based on

evolutions of ARM’s application profile (A profile) architecture, with each generation adding

new features for increased performance and capabilities, while ensuring compatibility with a

broad software ecosystem. Some features—for example , the addition of 64-bit processing in

ARMv8-A-- benefit significantly from being presented to the ARM ecosystem ahead of products

containing this feature becoming available; this provides an opportunity for discussion and

development of associated software, including operating systems, and system IP collateral, as

well as providing guidance on ARM’s intended direction.

In addition to the A profile, the ARM architecture also contains profiles targeting the specific

needs of embedded, real-time processors and microcontrollers, respectively called the Real-time

(R profile) and microcontroller profiles (M profile). Found in systems ranging from anti-lock-

braking to white goods to cell phone radios, the Cortex-R and Cortex-M series processors, based

18

on these profiles, form the relatively unknown masses of CPUs that make the everyday world

work in a safe and reliable way.

9. Today’s Cortex-R Architecture:

ARM’s current lineup of embedded, real-time processors is based on the ARMv7-R architecture,

and is formed of three complementary processors: the cortex-R4, cortex-R5 and cortex-R7

processors. In common with processors based on the ARMv7-A architecture, these processors

execute both the ARM(A32) and Thumb(T32) instruction sets, but differ by offering a range of

features for safety and real-time applications. From an architectural point of view, the key

difference between the A and R profiles are the memory system capabilities. The ARMv8-A

profile provides full virtual memory support via the virtual system memory architecture (VMSA)

commonly found on desktop and mobile-phone platforms. The ARMv8-R profile implements

memory protection without translation via the protected memory system architecture (PMSA).

The PMSA uses registers tightly coupled to the processor in a memory protection unit( MPU) to

provide protection of memory without the non-deterministic behavior introduced by potential

TLB misses. PMSA provides support for running Real-Time Operating Systems (RTOS) with

the ability to prevent erroneous execution of tasks corrupting either other tasks or the kernel.

Cortex- R4 processor in 2005, the features and capabilities of ARM’s embedded

processors have been driven to provide a portfolio capable of supporting high-

performance computing solutions for embedded systems, where high availability, fault

tolerance, maintainability and real-time responses are required, such as:

Automotive:

Airbag, braking, stability, dashboard, engine management

Storage:

Hard disk drive controllers, solid state drive controllers

Mobile Handsets:

3G, 4G, LTE, WiMax, smartphones and baseband modems

Embedded:

Medical, industrial, high-end microcontroller units (MCU)

19

Enterprise:

Networking and printers; inkjet and multi-function printer

Home:

Digital TV, BluRay players and portable media players

Cameras:

Digital still camera (DSC) and digital video camera (DVC)

Fig 4. Instruction Set of ARMv8-R and ARMv8-A

In addition to the requirements of today’s systems ARM sees four new challenges for real-time

application developers such as Desire for consolidation( Aim of providing more capable

systems), Increased safety and integrity, Demand for future rich software.

20

A profile, R profile, and M profile:

Application profile Real-time profile Microcontroller profile

32-bit and 64-bit

registers

32-bit register width 32-bit register width

A32(ARM),

T32(Thumb) and A64

instruction sets

ARM and Thumb

instructions

Thumb instruction set

only

Runs rich operating

systems

Protected-memory

support

Protected memory

support

Virtualization

extension

Runs real-time OS Virtualization

extension

Table 2. A-profile, R-profile and M-profile

Thus it provides a wide range of applications such as in automotives, storage devices, mobile

handsets, embedded, and enterprise and has a scope of providing better features as the

technology is advanced depending upon the requirement whether it is 32-bit or 62-bit and it may

be either thumb instructions or extensions of versions of virtual floating point variables. The

above tabular form represents the different profiles that are used such as application profile, real-

time profile and microcontroller profile in which we are focusing on real-time profile based

applications

21

Cortex-R4 , Cortex-R5 and Cortex-R7:

Introduced 2005 Introduced 2010 Introduced 2012

ARMv7-R architecture ARMv7-R architecture ARMv7-R architecture

High- performance,

real-time, deeply

embedded processor

Low-latency peripheral

port and Accelerator

coherency port

Large-performance

increase and Advanced

micro-architecture

Deterministic event

response

Smaller floating- point

unit, Enhanced memory

protection

Symmetric

multiprocessing

Soft and hard error

handling

Dual core in split or lock

step

Quality of service features

Configurable feature

set

Bus error management Integrated-interrupt

controller

Table 3. Cortex-R4, Cortex-R5, and Cortex-R7

22

Latest ARMv8-R and its future scope:

The ARMv8-R architecture represents the latest evolution of the ARM real-time architecture

profile. While adopting some features from the ARMv8-A architecture announced in 2011,

ARMv8-R remains a 32-bit architecture using the AArch32 exception model( compatible with

that used in ARMv7-R ) and executing the A32(ARM) and T32(Thumb) instruction sets. In

addition to the real-time features already present in ARMv7-R, the ARMv8-R architecture adds a

number of key architectural capabilities aimed at addressing the requirements of future integrated

control and safety applications.

Consolidation via virtualization is to address the requirement to be able to consolidate multiple

systems onto a single processor, ARMv8-R architecture brings support for hardware

virtualization. In common with ARMv8-A, this results in the addition of a new exception level of

higher priority than any that already exists on current Cortex-R processors.

10. CONCLUSION:

Thus the ARMv8-R architecture adds a number of key architectural capabilities aimed at

addressing the requirements of future integrated control and safety applications and results in the

addition of a new exception level of higher priority than any that already exists on current

Cortex-R processors.

23

11. BIBILIOGRAPHY:

REFERENCES:

[1] ARM Limited, Introducing NEONTM - Development Article,

2009.

[2] ARM Limited, ARM v8-A Instruction Set Overview, July

[3] ARM Limited, ARM Architecture Reference Manual - ARM

v7-A and ARM v7-R edition Errata markup, 2011.

[4] S. Bentmar Holgersson, “Optimising IIR Filters Using ARM NEON,” 2012

[5]R. Kutil, “Parallelization of IIR filters using SIMD extensions,”2008 15th International

Conference on Systems,Signals and Image Processing, vol. 1, no. June, pp. 65–68,Jun. 2008

[6] www.elctronicsforu.com

[7]www.EFYtimes.com

[8]www.efymagonline.com

[9]www.linuxforu.com

[10]www.efytechcenter.com

24