array multiplier - devi ahilya · pdf filem bit array multiplier • delay due to ands in...

Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009

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Lesson 06:Array Multiplier

Chapter 03: Computer ArithmeticComputer Arithmetic


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Objective

• Learn Array Multiplier method


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Multiplication Process By Array Multiplier


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Multiplication of decimal 11 (0b1011), multiplicand (Y) by the decimal 5 (0b0l01)

• Multiplication of decimal 11 (0b1011)• Multiplicand (Y) by the decimal 5 (0b0l01)• Multiplier (X) • An n-bit × n bit multiplication done in steps


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• Step A: First, 0b1011 is copied by each bit of 0b0l01 to get the product by lsb (=1)

• Step B: then 0b1011 is taken as 0b0000 to get the product by next to lsb (= 0) shown in the second line

• Step C: then 0b1011 is copied by each bit of 0b0l01 to get the product by next to next of lsb=(1) shown in the third line


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• Step D: then 0b1011 is taken as 0b0000 to get the product by msb (=0) shown in the fourth line.

• The four results are added to get the final result. Note that each successive line is shifted to the left one position to the left to account for the differing place values of the bits in the second input


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Array multiplier method 0b1011 ×××× multiplicand (Y) by 0b0l01

• Step A: n × n Partial product generation using array of AND gates by multiplying x0.y0, x0.y1, …, up to xn−1. yn−1 in parallel at the same time

• n = 4 in the example of multiplying 0b1011 with 0b0l01


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• Step B: Use adders to add the partial products at the n-levels. Note that each level m partial product x xm.y0, xm.y1, …, up to x1. yn–1 is shifted to the left one position to the left to account for the differing place values of the bits in the second input


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• Step C: Generating final result using two-bit operand adders


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Step A: Partial product generation using array of AND gate

• x0.y0, x0.y1, …, up to x0. y4−1in array of ANDs at the same time

• Then x1.y0, in array x1.y1, …, up to x1. y4−1 of ANDs in parallel at the same time

• and so on

0b1011

× 0b0101

1011 level 0

0000 level 1

1011 level 2

0000 level 3

+0b110111


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Step A

• Partial product generation using array of 2-bit ADDERs at (n − 1) levels

• Logic circuit of generating partial products at each level using 4 ANDs in 4 × 4 array of ANDs when n = 4


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Array Multiplier

• Refer Figure 3.21


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Step B



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Step C



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Designing Array Multiplier

• Total Number of logic units in n-bit × m bit Array Multiplier

• n × m two-input ANDs and (m – 1) units of n-bit adders


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Total Delay in n-bit ×××× m bit Array Multiplier

• Delay due to ANDs in partial products at all level is just one unit AND gate delay. But delay at levels 1 to (m – 1) units of n-bit adders = (m –1) × delay of one-unit 16-bit adder

• The delay in adders is very large if ripple carry adders are used

• The delay in adders reduced by using carry-look-ahead adders


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Advantage of Array Multiplier

1. An array multiplier─ a multiplication method in which an array of identical cells generates new partial product and accumulation of it at the same time


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2. We can use pipelines at each level• Result from the adder can be latched at each

level and used as input for next level adder circuit


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3. The delay is logarithmically proportional to the bit size of multiplicand and multiplier if we use the high speed array multiplier circuit


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Disadvantage of Array Multiplier

• Large number of logic gates required to design an array multiplier


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Summary


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• Multiplication circuit becomes fast by array multiplier

• A multiplication method in which an array of identical cells generates new partial product and accumulation of it at the same time

We learntWe learnt


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End of Lesson 06 on Array Multiplier Circuit

array multiplier - devi ahilya · pdf filem bit array multiplier • delay due to ands in...

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