as the crow flies model to implementation via automatic ... · as the crow flies – model to...
TRANSCRIPT
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1 © 2014 The MathWorks, Inc.
As the crow flies – Model to Implementation via
Automatic Production Code Generation
aka SLX2C – State-of-the-Art from Model to Embedded Code
http://www.mathworks.de/embedded-code-generation/
Michael Fröstl
Pilot Engineering, Production Code Generation
MathWorks
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switch(braindump)
{
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case ‘Applications’:
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Sonova’s hearing aid and cochlear
implant solutions.
Van Helvoort (left) and van Bakel with
a Philips Healthcare MRI scanner.
The USS Makin Island.
A Toyota engine.
The IRIS observatory. Alstom Grid’s HVDC demonstrator
system with power converter
modules.
http://www.mathworks.com/company/user_stories
The HB-SIA aircraft on a test
flight over San Francisco Bay.
Photo © Solar Impulse | Revillard | Rezo.ch
The AirSonea device, which
connects to an asthma patient’s
smartphone …
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case ‘Programming’:
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ASCII MATLAB
C
C++
ASM
IEC 61131-3
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case ‘Hardware’:
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MCU /
DSP
ARM®
Analog Devices®
Atmel®
Freescale™
Infineon®
Intel®
Microchip®
NXP™ Renesas®
STMicroelectronics®
Texas Instruments™
Xilinx®
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case ‘Operating Systems’:
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OS
Green Hills® Integrity RTOS
Embedded Linux®
Texas Instruments™ DSP/BIOS™
Wind River® VxWorks®
OSEK-OS
Microsoft® Windows Embedded
QNX® Neutrino® RTOS
Android™
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case ‘Standards’:
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NORM
AUTOSAR MISRA AC AGC
ISO 26262
IEC 61508
EN 50128
DO-178B/C
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default :
printf(“Wrong session?”);
}
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MBD_Overview();
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TE
ST
& V
ER
IFIC
AT
ION
INTEGRATION
IMPLEMENTATION
ANALYSIS • SPECIFICATION • DESIGN
REQUIREMENT
DOCUMENTS
RESEARCH
ACTIVITIES
Model
Environment
Physical
Components
Algorithms
Architecture
Constraints
FPGA ASIC
Structured
Text VHDL, Verilog C, C++
PLC PAC MCU DSP
Test Cases
Test Cases
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16
TE
ST
& V
ER
IFIC
AT
ION
INTEGRATION
IMPLEMENTATION
ANALYSIS • SPECIFICATION • DESIGN
REQUIREMENT
DOCUMENTS
RESEARCH
ACTIVITIES
Model
Environment
Physical
Components
Algorithms
Architecture
Constraints
FPGA ASIC
Structured
Text VHDL, Verilog C, C++
PLC PAC MCU DSP
Test Cases
Test Cases
Standardkonforme Absicherung mit
Model-Based Design
MATLAB für FPGA Design und ASIC
Prototyping
Rapid Prototyping und HiL-Simulation mit
Simulink Real-Time
Physical Modelling mit Simscape
Mit Polyspace die Qualität des generierten
und handgeschriebenen Codes effektiv
verbessern
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switch(topics)
{
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case ‘Code Generation – Top 5’:
V with slope and bias encoding scheme: V = 1*Q + 1
V
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IP Protection
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Password Protected Models
Support options
– Simulation: Allow
Accelerator mode simulation
– Code generation: Include
obfuscated code to support
code generation
– (New in R2013b) Read-only
view: Web view of model
– (New in R2013b) Password
protection: Access protected
by password
Protect design IP for models and
generated code
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AUTOSAR Roundtrip
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AUTOSAR Roundtrip with Simulink Merge
updateModel method automates
ARXML import and merge
– Simulink model
– Workspace variables
– AUTOSAR configuration
Generates report of changes with
hyperlinks to model
Identifies changes left for user
Update and merge AUTOSAR authoring
tool changes into Simulink models for iterative round-trip workflows
Modellbasierte Entwicklung Eingebetteter
Systeme für AUTOSAR mit der MathWorks-
Toolkette
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RAM Optimization
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Average Global RAM & Unnecessary Data Copy Reduction
Since R2008b (Using 70+ Industry Models)
Rela
tive to
R2008b
Global RAM Usage
86%
88%
90%
92%
94%
96%
98%
100%
102%
8b 9a 9b 10a 10b 11a 11b 12a 12b 13a 13b
Data Copy Measurement
70.00%
75.00%
80.00%
85.00%
90.00%
95.00%
100.00%
105.00%
8b 9a 9b 10a 10b 11a 11b 12a 12b 13a 13b
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Simulink Data Dictionary
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Code Generation for Simulink Data
Dictionary
Componentization
Scalability and
performance
Change tracking
and differencing
Integration with
Simulink Projects
Code generation
Manage data outside
of base workspace
Simulink
SLX
File SLX
File
Model 1
Model 2
Model 3
SLX
File
SLDD
File SLDD
File SLDD
File Global Data
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case ‘Targets’:
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31 http://www.mathworks.de/hardware-support/home.html
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32 http://www.mathworks.de/services/consulting/areas/developing-embedded-targets.html
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case ‘Getting FREEd’:
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Embedded Coder Support Package
for Freescale FRDM-KL25Z Board
Integration of the GNU-ARM Toolchain
Automatically:
1. Generates C code
2. Compiles code
3. Loads binary to hardware
Now available via Support Package Installer
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“Go Green” – Getting Started
Blink a LED
Create a new Model
Set it up for the Freescale Target
Add Blocks (incl. I/O)
Generate code
Deploy to the hardware
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default :
printf(“Brain up-to-date!”);
}
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37
TE
ST
& V
ER
IFIC
AT
ION
INTEGRATION
IMPLEMENTATION
ANALYSIS • SPECIFICATION • DESIGN
REQUIREMENT
DOCUMENTS
RESEARCH
ACTIVITIES
Model
Environment
Physical
Components
Algorithms
Architecture
Constraints
FPGA ASIC
Structured
Text VHDL, Verilog C, C++
PLC PAC MCU DSP
Test Cases
Test Cases