asic 121: practical vhdl digital design for fpgas

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ASIC 121: Practical VHDL Digital Design for FPGAs Tutorial 2 October 4, 2006

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ASIC 121: Practical VHDL Digital Design for FPGAs. Tutorial 2 October 4, 2006. Contributions. I have taken some of the slides in this tutorial from Jeff Wentworth’s ASIC 120. Combination vs Sequential. Combinational Logic Output only depends on input Examples: AND, OR, MUX - PowerPoint PPT Presentation

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Page 1: ASIC 121: Practical VHDL Digital Design for FPGAs

ASIC 121: Practical VHDL Digital Design for FPGAs

Tutorial 2October 4, 2006

Page 2: ASIC 121: Practical VHDL Digital Design for FPGAs

Contributions

• I have taken some of the slides in this tutorial from Jeff Wentworth’s ASIC 120

Page 3: ASIC 121: Practical VHDL Digital Design for FPGAs

Combination vs Sequential

• Combinational Logic– Output only depends on input– Examples: AND, OR, MUX

• Sequential Logic– Output depends on inputs and memory– Examples: State Machine, Counter

Page 4: ASIC 121: Practical VHDL Digital Design for FPGAs

Memory

• Two popular ways of implementing memory:– Synchronous memory (most popular)

• Uses Flip Flops with a Clock signal– Asynchronous memory

• Uses Latches• Much more difficult to design with

Page 5: ASIC 121: Practical VHDL Digital Design for FPGAs

Basic Feedback Element: SR latch

S R Q Qnext

0 0 0 00 0 1 10 1 0 0

0 1 1 01 0 0 11 0 1 11 1 0 N/A1 1 1 N/A

Page 6: ASIC 121: Practical VHDL Digital Design for FPGAs

D Flip-Flop or RegisterD Clk Q Qnext

0 0 0 00 0 1 11 0 0 0

1 0 1 10 01 0 00 01 1 01 01 0 11 01 1 1

Page 7: ASIC 121: Practical VHDL Digital Design for FPGAs

ASIC 120

• Read through the ASIC 120 Tutorial 2• Gives a good explanation of state

machines and basic VHDL

Page 8: ASIC 121: Practical VHDL Digital Design for FPGAs

Independent Tasks

• All students should have evaluation copies of Modelsim and Quartus II, if not see Tutorial 1

Page 9: ASIC 121: Practical VHDL Digital Design for FPGAs

Quartus II Exercise

• This exercise builds on the one performed in Tutorial 1

• Open Quartus II, Select File->New Project Wizard, Select a valid working directory (should be an empty folder)

• Name the project and entity “full_adder”• Click next for all other menus• Select File->New. Select VHDL File

Page 10: ASIC 121: Practical VHDL Digital Design for FPGAs

Quartus II Exercise Cont• Save the file as full_adder.vhd, with the contents:

library ieee;use ieee.std_logic_1164.all;

entity full_adder is Port ( i_X, i_Y, i_Cin : in STD_LOGIC; o_FA_Sum, o_FA_Cout : out STD_LOGIC );end full_adder;

architecture main of full_adder is Component half_adder

Port ( i_A, i_B : in STD_LOGIC;o_Sum, o_Carry : out STD_LOGIC

);end Component;

signal carry_1, carry_2, sum_1: STD_LOGIC;

Page 11: ASIC 121: Practical VHDL Digital Design for FPGAs

Quartus II Exercise Contbegin

adder1 : half_adder Port map(i_A => i_X,i_B => i_Y,o_Sum => sum_1,o_Carry => carry_1);

adder2 : half_adder Port map(i_A => i_Cin,i_B => sum_1,o_Sum => o_FA_Sum,o_Carry => carry_2);

o_FA_Cout <= carry_1 or carry_2;

end main;

Page 12: ASIC 121: Practical VHDL Digital Design for FPGAs

Quartus II Exercise Cont

• Go to Project->Add Files and add the half_adder.vhd file from Tutorial 1

• You have now seen a hierarchical VHDL design with multiple files

Page 13: ASIC 121: Practical VHDL Digital Design for FPGAs

Quartus II Exercise Cont

• Select Processing->Start->Analysis and Synthesis

• Make sure it completes successfully• Next Step

– Read through the help file under “simulation”– Try Simulating the design

Page 14: ASIC 121: Practical VHDL Digital Design for FPGAs

Exercise 2

• Full adders can be chained together into something called a “ripple adder”

• 3 bit adder (A + B = S):

Full AdderFull AdderFull Adder

A0A1A2 B0B1B2

Carry InCarry Out

S0S1S2

Page 15: ASIC 121: Practical VHDL Digital Design for FPGAs

Exercise 2 Cont’d• Create the architecture description for a 4 bit

ripple adder to implement the entity:

library ieee;use ieee.std_logic_1164.all;

entity ripple_adder is port (

A : in std_logic_vector(3 downto 0);B : in std_logic_vector(3 downto 0);c_in : in std_logic;sum : out std_logic_vector(3 downto 0);c_out : out std_logic

);end ripple_adder;

Page 16: ASIC 121: Practical VHDL Digital Design for FPGAs

VHDL DFF (Flip Flop)library ieee;use ieee.std_logic_1164.all;

entity DFF is port ( d, clk : in STD_LOGIC; q : out STD_LOGIC

);end DFF;

architecture main of DFF is begin

process (clk)begin

if (clk'event and clk = '1') thenq <= d;

end if;end process;

end main;