assembly+language+ +lecture+6,+7

7/27/2019 Assembly+Language+ +Lecture+6,+7

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Assembly language programming

Lecture 6, 7


2/87

Structure of an assembly language

program

The architecture of a processor is the

assembly language programmers view of it

Architecture is made up of the processors

register, its instruction set, and its addressing

modes

Structure of an assembly language program is

composed of both instructions and commands

assembler directives


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programORG $400

MOVE P,D0

ADD Q,D0

MOVE D0,R

STOP #$2700

*

ORG $500

P DC.W 2

Q DC.W 4R DS.W 1

END $400


4/87


program assembler directives

Assembler statements can be divided into two types:executable statements and assembler directives

An executable statements is an instruction inmnemonic form that the assembler translates into themachine code of the target microprocessor

MOVE P,D0

ADD Q,D0

MOVE D0,RSTOP #$2700


5/87



An assembler directive tells the assemblersomething it needs to know about the program itis assembling:

E.g., the assembler directive ORG means origin andtells the assembler where the instructions or data areto be loaded in memory

The expression ORG $400 tells the assebler to loadinstruction in memory starting at address 40016

The value of 40016 is used because the 68K reservesthe first 1024 bytes of memory in locations 0 to 3FF16for a special purpose


6/87


program assembler directives1 00000400 ORG $400

2 00000400 303900000500 MOVE P,D0

3 00000406 D07900000502 ADD Q,D0

4 0000040C 33C000000504 MOVE D0,R

5 00000412 4E722700 STOP #$2700

6 *

7 00000500 ORG $500

8 00000500 0002 P: DC.W 2

9 00000502 0004 Q: DC.W 410 00000504 00000002 R: DS.W 1

11 00000400 END $400

Line

number

Address or

memory

location

Operand or

contents of

memory

The label

field

Mnemonic

or assembler

Directive

field

Operand

field


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As you can see the instruction MOVE D0,R is

located on line 4 and is stored in memory

location 40C16

This instruction is translated into the machine

code 33C00000050416, where the operation

code is 33C016 and the address of operand R is

0000050416


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The assembler maintains a variable, called the

location counter, that keeps track of where

the next instruction or data element is to be

located in memory

When one writes ORG directive, the location

counters value is preset to that specified by

the ORG.


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The define constantassembler directive, DC,

allows you to load a constant in memory (i.e.

it provides means of presetting memory

locations with data before a program isexecuted)

This directive is written DC.B to store a byte,

DC.W to store a word, and DC.L to store alongword


10/87



In the exampleORG $500

P: DC.W 2

a programmer places the value 2 in memory, and labelsthe location P

Since the directive is located immediately after theORG $500 assembler directive, the integer 2 islocated at memory location 50016

This memory location (i.e. 50016) can be referred to asP (MOVE P,D0)

Because the size of the operand is a word, the value

0000 0000 0000 00102 is stored in location 50016


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The next assembler directive

Q: DC.W 4

loads the constant 4 in the next available

location 50216

The define storage directive, DS, tells theassembler to reserve memory locations and

also takes a .B, .W, or a .L qualifier For example DS.W 1 tells the assembler to

reserve a word in memory and to equate theaddress of the first word with R


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The difference between DC.B N and DS.B N is

that the former stores the 8-bit value N in

memory, whereas the latter reserves N bytes

of memory by advancing the location counterby N

The final assembler directive, END $400,

tells the assembler that the end of theprogram has been reached and that there is

nothing else left to assemble


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Another important assembler directive is EQU,

which equates a symbolic name to a numeric

value.

For example, in case ofTuesday EQU 2

one can use the symbolic name Tuesday

instead of its value, 2.

Statements ADD #Tuesday,D0 and ADD

#2,D0 are identical


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Example of drawing a memory map

ORG $1000

Size DC.B 25

Width DC.B 14

Perim DS.B 1

ORG $1200

MOVE.B Size,D0

ADD.B Width,D0

ADD.B D0,D0

MOVE.B D0,Perim

STOP #$2700

END $1200


15/87

Example of drawing a memory map

$1000 25 Size

$1001 14 Width Data area

$1002 Perim

$1200 MOVE.B Size,D0

$1204 ADD.B Width,D0

$1208 ADD.B D0,D0 Program area$120A MOVE.B D0,Perim

$120E STOP #$2700

$1212


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Example of drawing a memory map:

relationship between a source program, assembled

program, and memory map

1 00001000 ORG $1000

2 00001000 19 Size DC.B 25

3 00001001 0E Width DC.B 144 00001002 00000001 Perim DS.B 1

5 00001200 ORG $1200

6 00001200 10381000 MOVE.B Size,D0

7 00001204 D0381001 ADD.B Width,D0

8 00001208 D000 ADD.B D0,D09 0000120A 11C01002 MOVE.B D0,Perim

10 0000120E 4E722700 STOP #$2700

11 00001200 END $1200


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This program uses two define-constant directivesto set up constants called Size and Width inmemory

These two constants are 25 and 14, which arerepresented in hexadecimal as $19 and $0E,respectively

These two define-constants are 1-byte directiveseach and hence are loaded at addresses $1000

and $1001, respectively The define-storage assembler directive, PerimDS.B 1, reserves a one-byte location calledPerim at $1002


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The second ORGdirective resets the assemblerslocation counter to $1200

The first instruction, MOVE.B Size,D0, copies

the contents of memory location Size to dataregister D0

The next instruction adds the contents ofmemory location Width to the contents ofD0

The result is then doubled

The operation MOVE.B D0,Perim copies theresult into the memory location Perim


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Operand size and the 68K

The 68K has a 32-bit architecture and a 16-bitorganization

The sizes of operands assembler programmer operateswith is important

The 68K has a byte-addressable architecture.Successive bytes in memory are stored at consecutivebyte addresses (0,1,2,3) and any byte in memory canbe individually read from or written to

In case if 16-bit word is sent down to memory, thensuccessive words are stored at consecutive evenaddresses: 0,2,4,6

32-bit longwords are stored at addresses 0,4,8,...


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8 bits (1byte) 16 bits (1 word) 32 bits (1 longword)1000 1000 1000

1001 1002 1004

1002 1004 1008

1003 1006 100C

1004 1008 1010

1005 100A 1014

1006 100C 1018

1007 100E 101C

1008 1010 1020

1009 1012 1024

100A 1014 1028

100B 1016 102C


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If one stores a 32-bit longword at memory

location $1000, the most-significant byte of an

operand goes to the lowest address

E.g., when longword $12345678 is stored,

byte $12 goes to the address $1000

This storage order is called Big-Endian

Intel processors are Little-Endian and store

bytes in the reverse order to the 68K family


22/87


All addresses processed and stored by the 68Kare 32-bit values. However, not all 32 addresslines are connected to pins. Addresses from 24 to31 are not connected to the pins and hence

cannot be used to access memory The 68Ks address bus is effectively 24 bits wide

and can access only 2^24 bytes (16 Mbyte) ofaddressable memory

Later members of the 68K family support a full32-bit wide address bus and a 2^32 byte (4GByte)address space


23/87

The 68Ks registers

The 68K has a register-to-memory architecture andtherefore it needs registers to be able to accessmemory

The 68K has eight 32-bit general-purpose dataregisters, eight 32-bit address registers, an 8-bitcondition code register, an 8-bit status byte, and a 32-bit program counter

The status byte is only accessed by the operating

system and is invisible to the user programmer becauseit simply defines the 68Ks operating mode and controlsthe way in which interrupts are dealt with

Th 68K i t


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The 68Ks registersd31 d16 d15 d08 d07 d00

D0

D1

D2

D3

D4

D5

D6

D7

a31 a16 a15 a08 a07 a00

A0

A1

A2

A3

A4

A5

A6

A7

PCX N Z V C CCR


25/87

Data registers

The 68K has eight general-purpose data registers,numbered D0 to D7

Any operation that can be applied to data register Dican also be applied Dj

There are no special purpose data registers reservedfor certain types of instruction

When a byte operation is applied to the contents of adata register, only bits D00 to D07 of the register areaffected, similarly, a word operation affects bits D00 toD15. Only the lower-order byte (word) of a register isaffected by a byte (word) operation


26/87

Data registers

For example, applying a byte operation to data

register D1 affects only bits 0 to 7 and leaves

bits 8 to 31 unchanged.

CLR.B D1 forces the contents of D1 to XXXX

XXXX XXXX XXXX XXXX XXXX 0000 0000


27/87

Address registers

The 68K has eight 32-bit address registers,called A0 to A7, which act aspointer registers

Registers A0-A6 are identical in that whatever

we can do to Ai, we can also do to Aj. Addressregister A7 has an additional function of beingused as a stack pointerfor the storage ofsubroutine addresses

Operations on address registers do not affectthe 68Ks condition code register


28/87

Address registers

The contents of an address register is consideredto be a single entry, byte and word divisions ofaddress registers are meaningless

All operations on an address register arelongword operations

.W operations are automatically extended to .L

Addresses are treated as signed twos

complement values. If we perform operation onthe lower-order word of an address register, thesign bit is extended from A15 to bits A16 to A31.


29/87

Address registers

For instance the operation

MOVEA.W #$8022,A3

has the effect [A3]


30/87

Address registers

Positive and negative addresses can seem strangebut in fact positive address can be thought ofmeaning forward and negative addressmeaning backward

E.g., A1 contains the value 1280 and A2 containsthe value 40(stored as the appropriate twoscomplement value). Adding the contents ofA1 tothe contents ofA2 by ADDA.L A1,A2 to create

a composite address results in the value 1240,which is 40 locations back from the addresspointed at by A1


31/87

The 68Ks instruction set:

data movement instructions Typical 68K data and address movement instructions are:

MOVE Di,Dj

[Dj]


32/87


data movement instructions

The EXG instruction exchanges the contents oftwo registers (its intrinsically a lognwordoperation). EXG may be used to transfer thecontents of an address register into a dataregister and vice versa.

SWAP exchanges the upper- and lower- orderwords of a given data register.

The LEA (load effective address) instructiongenerates an address and puts it in an addressregister


33/87


arithmetic and logical operations

Arithmetic operations are those that act onnumeric data (i.e. signed and unsigned integers)

Simple example is ADD M,Di

Other arithmetic operations implemented by the68Kare SUB (subtract), DIVU, DIVS (unsignedand signed divide), MULU and MULS (unsignedand signed multiply), and NEG (negate)

The 68Ks logic (i.e. Boolean) operations AND, OR,EOR, NOT act on the individual bits of a word,whereas arithmetic operations act on the wholenumber


34/87


shift operations

Shift operation moves a group of bits one ormore places left or right. Shift operations in the68K can be applied by bytes, words andlongwords

Example: logical shift by one place right, LSR, of the 8-bit value1100 1010 will give: 0110 0101

arithmetic shift treats the data shifted as a signed

twos complement value and the value of11001010 (-54) after arithmetic shift right, ASR, willbecome 1110 0101 (-27)


35/87


shift operations

Operand 0

C

X

LSL

Operand 0

C

X

LSR

Logical shift left

(a 0 enters theleast-significant bit

and the most-

significant bit is

copied to the C and

X flags in the CCR

Logical shift right

(a 0 enters the

most-significant bit

and the least-

significant bit iscopied to the C and

X flags in the CCR


36/87


shift operations

Operand 0

C

X

ASL

Arithmetic shift left

(a 0 enters theleast-significant bit

and the most-

significant bit is

copied to the C and

X flags in the CCR

Arithmetic shift

right

(the old most-

significant bit is

copied into the newmost-significant bit

and the least-

significant bit is

copied to the C and

X flags in the CCR

Operand C

X

ASR

MSB


37/87


circular shifts and rotates

A circular shift or rotate treats the data beingshifter as a ring with the most-significant bitadjacent to the least-significant bit

Circular shifts result in the most-significant bitbeing shifted into the least-significant bit position(left shift), or vice versa for a right shift

No data is lost during a circular shift

The 68K supports two types of circular shift of thebits of a register: rotate left (ROL) and rotateright (ROR)


38/87



The bit that is shifted out at one end is shifted

into the other end and also copied into the

carry bit

Example:

Initial D0 Shift D0 after the shift

11001110 ROL.B #1,D0 10011101

11001110 ROR.B #1,D0 01100111

11110000 ROL.B #2,D0 11000011


39/87



Operand C

ROL Rotate leftthe most-significant bit is

copied into the least-

significant bit and the

carry flag

Operand C

ROR

Rotate rightthe least-significant bit is

copied into the most-

significant bit and the

carry flag


40/87


circular shifts and rotatesRotate left throughextend

the most-significant

bit is copied into the

X and C flags in the

CCR and the old X bit

into the least-significant bit

Rotate right through

extend

the least-significantbit is copied into the

X and C flags in the

CCR and the old X bit

into the most-

significant bit

Operand C

ROXL

X

Operand C

ROXR

X


41/87



In figure, one can see the 68Ks two circular shift

operations that include the extend bit (X-bit) in the

condition code register

The mnemonics for these instructions are ROXL andROXR (rotate left through extend and rotate right

through extend)


42/87


logical operations and branching

Like shift operations, logical operations allow

you to directly manipulate the individual bits

of a word.

The 68K implements four logical operations:

NOT, AND, OR, and EOR.

NOT inverts the bits of an operand:

[D0]=11001010, the operation NOT.B D0 results in

[D0]=00110101


43/87



The AND operation is dyadic and is applied to asource and destination operand.

Bit i of the source is AND-ed with bit i of thedestination and the result is stored in bit i of the

destination If [D0]=1100 1010, operation AND.B #%1111 0000, D0

results in [D0]=1100 0000

The AND operation is used to mask the bits of a

word If one AND bit x with bit y, the result is 0 if y=0 and x if

y = 1.


44/87



The OR operation is used to set one or more bitsof a word to 1. ORing a bit with 0 has no effect,and ORing the bit with 1 sets it.

if [D0]=1100 1010, the operation OR.B #%1111 0000,D0 results in [D0]=1111 1010

The EOR operation is used to toggle one or moreits of a word. EORing a bit with 0 has no effect,

and EORing it with 1 inverts it. if [D0]=1100 1010, the operation EOR.B #%1111 0000,

D0 results in [D0]=0011 1010


45/87



By using the NOT, AND, OR, and EORinstructions, you can perform any logicaloperations on a word.

Suppose you wish to clear bits 0, 1, and 2, setbits 3, 4, and 5, and toggle bits 6 and 7 of thebyte in D0:

AND.B #%1111 1000, D0 clear bits 0, 1, and 2

OR.B #%0011 1000, D0 set bits 3, 4, and 5

EOR.B #%1100 0000, D0 toggle bits 6 and 7

h


46/87



A branch instruction modifies the flow of

control and causes the program to continue

execution at the targetaddress specified by

the branch.

The simplest branch instruction is the

unconditionalbranch instruction, BRA target

that always forces a jump to the instruction atthe target address.

h i i


47/87



In the following example, the BRA Hereinstruction forces the 68K to execute next theinstruction on the line which is labeled by Here

BRA Here

.

.

.

Here MOVE D0, D4 The 68K provides 14 conditional branch

instructions of the form Bcc, where cc is one of14 possible combinations

Th 68K i i


48/87


logical operations and branchingMnemonic Instruction Branch on condition

BCC branch on carry clear C

BCS branch on carry set C

BEQ branch on equal Z

BNE branch on not equal Z

BGE branch on greater than or equal to N V + N V

BGT branch on greater than N V Z + N V Z

BHI branch on higher than C Z

BLE branch on less than or equal to Z + N V + N V

BLS branch on lower than or same C + Z

BLT branch on less than N V + N V

BMI branch on minus N

BPL branch on plus N

BVC branch on overflow clear V

BVS branch on overflow set V

Th 68K i i


49/87



Conditional branch instructions test one ormore bits of the CCR. If the result of the test istrue, a branch is made to the target address.

Otherwise the instruction following thebranch is executed.

Without branch instructions we would not beable to implement high-level language

constructs such as IFTHENELSE orDOWHILE

Th 68K i i


50/87



When the CPU executes most instructions, CCRs flagbits are automatically updated. Each flag bit in the CCRmay be set by an instruction, cleared by it, or remainunaffected.

The Z-bit is set if the result of an operation yields a zeroresult. The N-bit is set if the most-significant bit of theresult is one. The carry bit is set if the carry out of themost-significant bit of the result is one. The V-bit is set

if the operation yields an out of range result when theoperand(s) and result are all regarded as twoscomplement values

Th 68K i t ti t


51/87



Remember that for the purpose of setting orclearing bits of the CCR, the term most-significant bit refers to bit 7, 15, or 31,

depending on whether the current operationis a byte, word, or longword operation,respectively.

You can also directly modify the contents of

the CCR by special instructions like MOVE#N,CCR

Th 68K i t ti t


52/87



As shown, some branch instructions test a singlebit in the CCR, whereas others test two or threebits.

Some test are applied to unsigned numbers and

some to signed numbers. Consider the numbers P=1111 0000 and Q=0011

0000. If these numbers are unsigned, P=240 andQ=48, and P>Q. If these numbers are regarded as

signed, P=-16 and Q=48, and P we would use BGT

with signed numbers and BHI with unsignednumbers.

Th 68K i t ti t


53/87



The target address used by a branch instruction isautomatically calculated by the assembler. All thatneeds to be written is Bcc and then labelthe appropriate target instruction with .

Consider the following example:ADD D1, D2 add D1 to D2 and

branch IF the result isminus

BMI ERROR ELSE part

ERROR ... THEN part

Th 68K i t ti t


54/87



ADD D1, D2 add D1 to D2 andbranch IF the result isminus

BMI ERROR

ELSE part

BRA EXIT Skip past the THEN part

ERROR ... THEN partEXIT

The unconditional branch instruction BRA EXIT forces thecomputer to execute the next instruction at EXIT and skips

past the ERROR clause.

Th 68K i t ti t


55/87



Lets now look at more detailed example on

conditional behavior. Example is a subroutine to

convert a 4-bit hexadecimal value into its ASCII

equivalent.

Th 68K i t ti t


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logical operations and branchingASCII character Hexadecimal value Binary value

0 30 0000

1 31 0001

2 32 0010

3 33 0011

4 34 0100

5 35 0101

6 36 0110

7 37 0111

8 38 1000

9 39 1001

A 41 1010

B 42 1011

C 43 1100

D 44 1101

E 45 1110

F 46 1111

Th 68K i t ti t


57/87



For example, if the internal binary value in aregister is 0000 1010, its hexadecimal equivalentis A16.

In order to print the letter A on a terminal, onehas to transmit the ASCII code for the letter A(i.e. $41) to it.

Note the difference between the internal binaryrepresentation of a number within a computerand the code used to represent the symbol forthat number.

The 68Ks instruction set


58/87



Number six is expressed in eight bits by the binarypattern 0000 0110 and is stored in the computersmemory in this form.

On the other hand, the symbol for a six (i.e. 6) is

represented by the binary pattern 0011 0110 in theASCII code.

If we want a printer to make a mark on papercorresponding to 6, we must send the binary

number 0011 0110 to it. All numbers held in the computer must be

converted to their ASCII forms before they can beprinted.



59/87



We can now derive an algorithm to convert a 4-

bit internal value into its ASCII form. A

hexadecimal value in the range 0 to 9 is

converted into ASCII form by adding hexadecimal30 to the number.

A hexadecimal value in the range $A to $F is

converted to ASCII by adding hexadecimal $37.



60/87

The 68K s instruction set:


If we represent the number to be converted by

HEX and the number to be converted by ASCII,

we can write down a suitable algorithm in the

formIF HEX$39 THEN ASCII:=ASCII+7



61/87



The alternative algorithm can be translated into low levellanguage as

ADD.B #$30,D0 ASCII:=HEX+$10

CMP.B #$39,D0 IF ASCII


62/87



Using instruction CMP source,

destination leads to the effect of

subtracting the source operand from the

destination operand and then set the flag bits ofthe CCR accordingly.

CMP is the same as SUB except that the result is

not recorded.



63/87


logical operations and branching Example:

* IF x=y THEN y=6

* IF x>y THEN y=y+1

CMP.B D0,D1 Assume that x is in D0 and y in D1

BNE NotEqu IF x=y THEN

MOVE.B #6,D1 y=6

BRA exit and leave the algorithm

NotEqu BGE exit IF x


64/87



Note that we perform two tests after thecomparison CMP.B D0,D1. One is a BNE and theother is BGE.

We can carry out the two tests in successionbecause no intervening instruction modifies thestate of the CCR.

Although the conditional test performed by a high-

level language can be quite complex (e.g. IF X+Y-Z>3t), the conditional test at the assembly languagelevel is rather more basic, as this exampledemonstrates



65/87


templates for control structures

We can readily represent some of the control structures ofhigh-level languages as templates in assembly language. Atemplate is a pattern or example that can be modified tosuit the actual circumstances.

In each of the following examples, the high-level constructis provided as a comment.

This condition tested is [D0]=[D1] and the actions to becarried out are Action1 or Action2.

The aim of templates is to provide the appropriate testinstead of CMP D0,D1 and provide the appropriatesequence of assembly language statements instead ofAction1 or Action2.



66/87



* IF [D0]=[D1] THEN Action1

*

CMP D0,D1 perform test

BNE EXIT IF [D0][D1] THEN exit

Action1 ...

...EXIT Exit point for construct



67/87



* IF [D0]=[D1] THEN Action1

* ELSE Action2

CMP D0,D1 Compare D0 with D1

BNE Action2 IF [D0][D1] perform Action2

Action1 ...

...

BRA EXITSkip round Action2

Action2 ... Action2

...

EXIT Exit point for construct



68/87



* FOR K=1 TO J

* ...

* ENDFOR

*MOVE #1,D2 Load loop counter, D2, with 1

Action1 ... Perform Action1

...

ADD #1,D2 Increment loop counterCMP #J+1,D2 Test for end of loop

BNE Action1 IF not end THEN go round again

EXIT ELSE exit



69/87



* WHILE [D0]=[D1] Perform Action1

*

Repeat CMP D0,D1 Perform test

BNE Exit If [D0][D1] THEN Exit

Action1 ... Else carry out Action1

...

BRA Repeat REPEAT loop

EXIT Exit from construct



70/87



* REPEAT Action1 UNTIL [D0]=[D1]

*

Action1 ... Perform Action1

...

CMP D0,D1 Carry out test

BNE Action1 REPEAT as long as [D0][D1]

EXIT Exit from loop



71/87

templates for control structures* CASE OF I

* I=0 Action0* I=1 Action1

* I=2 Action2

* I=3 Action3

* ...

* I=N ActionN

* I>N Exception

*

CMP.B #N,I Test for I out of rangeBGT EXCEPTION IF I>N THEN exception

MOVE.W I,D0 Pick up value of I in D0

MULU #4,D0 Each address is a longword

LEA Table,A0 A0 points to table of addresses

LEA (A0,D0),A0 A0 now points to case 1 in table

MOVEA.L (A0),A0 A0 contains address of case 1 handler

JMP (A0) Execute case 1 handler

*

Table ORG Here is the table of exceptionsAction0 DC.L Address of case 0 handler

Action1 DC.L Address of case 1 handler

Action2 DC.L Address of case 2 handler

...

ActionN NDC.L Address of case N handler

*

EXCEPTION ... Exception handler here


72/87

Addressing modes

Addressing modes are concerned with how anoperand is located by the CPU. A computersaddressing modes are almost entirely analogousto human addressing modes, as the following

example demonstrate: Heres 100 USD (literal value)

Get the cash from 12 North Street (absolute address)

Go to 10 East Street and they will tell you where to get

the cash (indirect address) Go to 2 North Street and get the cash from the fifth

house to the right (relative address)


73/87

Addressing modes

These four addressing modes show that we can

provide data itself (i.e. the $100 cash), say exactly

where it is, or explain how you go about finding

where it is Up to now we have dealt largely with the

absolute addressing mode, in which the actual

address in memory of an operand is specified by

the instruction, or with register direct addressing

in which the address of an operand is a register


74/87

Addressing modes

We now introduce other ways of specifyingthe location of an operand.

Because the address of an operand can be

calculated in several ways, we use the termeffective address as a general expression for

the address of an operand

Addressing modes: absolute


75/87


addressing

In absolute or directaddressing the operand field ofthe instruction provides the address of the operand inmemory

E.g., the instruction MOVE 1234,D0 copies the contents

of memory location 1234 into data register D0: MOVE D0,1234 [D0] -> [1234]

MOVE 1234,1234 [1234]->[1234]

ADD 1234,D0 [D0]


76/87


addressing

High LevelLanguage

Low LevelLanguage

Machine Code Memory Map

x:=y MOVE y,x

...

...

ORG $1000

y DS.B 1

x DS.B 1

11FB10001001 400 11FB Opcode

402 1000 Operand

404 1001 Operand

1000 x Data

1001 y Data

Addressing modes: immediate


77/87


addressing

Immediate addressing is also referred to as literal

addressing. Immediate addressing is provided by

all microprocessors and allow the programmer to

specify a constant as an operand The value following the op-code in an instruction

is not a reference to the address of an operand

but is the actual operand itself. In 68K assembly

language, the symbol # precedes the operand to

indicate immediate addressing



78/87


addressing

1.MOVE 1234,D0

2.MOVE #1234,D0

3.ADD 1234,D0

4.ADD #1234,D0



79/87


addressing

Dont confuse the symbol # with the symbols

$ (hexadecimal) or % (binary).

Expressions

MOVE #25,D0

MOVE #$19,D0

MOVE #%00011001,D0

have identical effects

Addressing modes: application of


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Addressing modes: application of

immediate addressing

Immediate addressing is used whenever the value ofthe operand required by an instruction is known atthe time the program is written

That is, it is used to handle constants as opposed tovariables. Immediate addressing is faster thanabsolute addressing, because only one memoryreference is required to read the instruction duringthe fetch phase

E.g., when the instruction MOVE #5,D0 is read from

memory in a fetch cycle, the operand, 5, is availableimmediately without a further memory access tolocation 5 to read the actual operand

Addressing modes: application of immediate


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addressing as an arithmetic constant

MOVE NUM,D0 [D0]


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addressing as an arithmetic constant

The 68K can, in fact, add an immediateoperand to a memory location directly

without using a data register by means of the

special add immediate instruction ADDI. For example, ADDI #22,NUM adds the

constant value 22 to the contents of the

location called NUM.



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addressing in a comparison with a constant

Consider the test on a variable NUM to determinewhether it lies in the range 7


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Addressing modes: application of immediate addressing as a

method of terminating loop structures

A typical loop structure is illustrated in BASIC,Pascal and C:

The higher level language FOR... construct

can readily by translated into 68K assembly

language.

10 IF FOR I=1 TO N

...

50 NEXT I

FOR I:=1 TO N DO

BEGIN

...

END

for (int i:=0; i


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N EQU 10 Define the loop sizeweve used N=10 here...

MOVE #1,D0 Load D0 with initial value of the loop counter

NEXT ... Start of the loop

...

... Body of loop

...

ADD #1,D0 Increment the loop counter CMP#N+1,D0 Test for the end of the loop

BNE NEXT IF not end THEN repeat loop



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At the end of the loop, the counter isincremented by means of the instruction

ADD #1,D0. The counter D0 is then compared

with its terminal value by CMP #N+1,D0 On the last time round the loop, the variable

I becomes N+1 after incrementing and the

branch to NEXT is not taken, allowing theloop to be exited

Add i t i di t dd i


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Address register indirect addressing

At the end of the loop, the counter isincremented by means of the instruction

ADD #1,D0. The counter D0 is then compared

with its terminal value by CMP #N+1,D0 On the last time round the loop, the variable

I becomes N+1 after incrementing and the

branch to NEXT is not taken, allowing theloop to be exited

assembly+language+ +lecture+6,+7

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