asyncronous logic

8/13/2019 Asyncronous Logic

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Asynchronous Sequential Logic

For most figures:


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We know dont we?

We have learned how to analyzeand design circuits with memory,dont we?

We have designed reallycomplicated circuits and can do sofor any problem, right?

How about taking a look at ourlovely latch circuit?


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Asynchronous sequential circuits

No clock pulses Change of an internal state occurs

when there is a change in theinputs.

More difficult to design/analyzethan synchronous sequentialcircuits.

Useful in cases where speed is

important. More economical to use.

Combinational circuits withfeedback loops (connectedthrough delayed lines).

Secondary variables: input end ofthe feedback loops., e.g. Y1, y2,yk.


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Example

One input: x Two feedback loops Two excitation variables:

Y1 and Y2

Two secondary variables: y1 and y2


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Transition table

Y1 = xy1 + xy2 Y2 = xy1 + xy2

The input (x) is also part of the state Stable states are the circled ones

where

Y1 = y1 and Y2 = y2


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Understanding the transition table

Four stable states: y1y2x = {000,011,110,101}

If y1y2x = 000 and x: 0 1 Then Y1Y2x = 011


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Procedure for analysis

Determine all feedback loops Assign Yi's (excitation variables), yi's (the secondary variables)

Derive the Boolean functions of all Yi's Plot each Y function in a map Construct the state table Circle the stable states


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Flow table

A flow table is a state transition table with its internal state beingsymbolized with letters

(a) is called a primitive flow table since it has only one stable state ineach row

output


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Race conditions

Race conditions occurwhen two or more

state variables aresupposed to changesimultaneously due toa change in the input.

For instance:

From y1y2=00 toy1y2 = 11 Three possible

transitions:

00 11 0010 11 00 01 11

Critical vs non-criticalrace conditions


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Non-critical races

Three possibletransitions: 00 11 0010 11 00 01 11

If all possibletransitions lead us tothe same final state,then it is a non-critical race.


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Critical races


If differenttransitions lead todifferent final states,then it is a criticalrace.


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Cycles

Cycle: a unique sequence of unstable states that the circuit goes.


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Unstability

Y = (x1 y)x2 = x1x2 + x2 y

If x1x2y = 111 Y = 0 If x1x2Y = 110 Y = 1

Oscillation between 1 and 0.Y will be a square wave.


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SR latch - revisited

Forbidden input: 11


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Asynchronous sequential circuits

No clock pulses Change of an internal state occurs

when there is a change in theinputs.

More difficult to design/analyzethan synchronous sequentialcircuits.

Useful in cases where speed isimportant.

More economical to use.

Combinational circuits withfeedback loops (connectedthrough delayed lines).

Secondary variables: input end ofthe feedback loops., e.g. Y1, y2,yk.


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Transition table

Y1 = xy1 + xy2 Y2 = xy1 + xy2

The input (x) is also part of the state Stable states are the circled ones

where

Y1 = y1 and Y2 = y2


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Procedure for analysis

Determine all feedback loops Assign Yi's (excitation variables), yi's (the secondary variables)

Derive the Boolean functions of all Y

i's

Plot each Y function in a map Construct the state table Circle the stable states


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Flow table

A flow table is a state transition table with itsinternal state being symbolized with letters

(a) is called a primitive flow table since it has only one stable state ineach row

output


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Designing an asynch. seq. ckt.

Assign a = 0 b = 1


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Race conditions

Race conditions occurwhen two or more

state variables aresupposed to changesimultaneously due toa change in the input.

For instance:

From y1y2=00 toy1y2 = 11 Three possible

transitions:

00 11 0010 11 00 01 11

Critical vs non-criticalrace conditions


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Critical races


If differenttransitions lead todifferent final states,then it is a criticalrace.


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Cycles

Cycle: a unique sequence of unstable states that the circuit goes.


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Analysis example


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Design with a latch WRONG!

How were we designing inSequential Logic?


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Design Procedure

Gated latch with two inputs G and D. If G=1, then Q (latch output)

should follow D. When G becomes 0, then the value of D at the time ofthe transition from G=1 to G=0 is retained at Q; i.e., once G becomes 0,the value of D does not change Q.

Inputs Output

State D G Q Commentsa 0 1 0 D=Q because G=1

b 1 1 1 D=Q because G=1

c 0 0 0 After state a or d

d 1 0 0 After state ce 1 0 1 After state b or f

f 0 0 1 After state e

Let us start by giving

a state to each row.


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Inputs Output

State D G Q Comments

a 0 1 0 D=Q because G=1



d 1 0 0 After state c

e 1 0 1 After state b or f


Primitive flow table formation

Step 1: Stable states, and outputs are inserted. Since we allow only oneof DG to change, put - to where they both change.


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Primitive flow table formation-2

Step 1: Stable states, and outputs are inserted. Step 2: Unstable states are determined. Outputs at these unstable

states dont matter. Use - to indicate this.


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Reduction of the flow table


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Set a=0 and b=1

Transition table


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Gated latch logic


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Gated latch with SR latch


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Assigning output to unstable states

Set the output of thetransient state to 0 if thestart and finish states havethe output 0.

Set the output of thetransient state to 1 if the

start and finish states havethe output 1.

Set the output of thetransient state to - if thestart and finish states havedifferent outputs.


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Design Procedure

Gated latch with two inputs G and D. If G=1, then Q (latch output)

should follow D. When G becomes 0, then the value of D at the time ofthe transition from G=1 to G=0 is retained at Q; i.e., once G becomes 0,the value of D does not change Q.

Inputs Output

State D G Q Commentsa 0 1 0 D=Q because G=1



d 1 0 0 After state ce 1 0 1 After state b or f


Let us start by giving

a state to each row.


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Inputs Output

State D G Q Comments

a 0 1 0 D=Q because G=1



d 1 0 0 After state c

e 1 0 1 After state b or f


Primitive flow table formation

Step 1: Stable states, and outputs are inserted. Since we allow only oneof DG to change, put - to where they both change.


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Primitive flow table formation-2

Step 1: Stable states, and outputs are inserted. Step 2: Unstable states are determined. Outputs at these unstable

states dont matter. Use - to indicate this.


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Reduction of the flow table


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Set a=0 and b=1

Transition table


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Gated latch logic

G d l h h l h


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Gated latch with SR latch

bl


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Assigning output to unstable states

Set the output of thetransient state to 0 if thestart and finish states havethe output 0.

Set the output of thetransient state to 1 if the

start and finish states havethe output 1.

Set the output of thetransient state to - if thestart and finish states havedifferent outputs.

A f l d f d i fl bl


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A formal procedure for reducing flow table

In (a,b), x=0 -> next states: (c,d) x=1 -> next states: (a,b)

In (c,d), x=0 -> next states: (a,b) x=1 -> next state: d

Any Equivalent

States?

If c=d, then we can say a=b. In other words, (a,b) implies (c,d).

A f l d f d i fl t bl


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A formal procedure for reducing flow table

Place a X for all pairs of states

whose outputs differ. Fill in the remaining cells withvalues of implied states. For each confirmed implication,put a tick.

I li ti t bl f th fl t bl


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Implication table from the flow table

What happens if the circuit is not completely specified? Compatible states: two incompletely specified states that can be combined

(i.e., there is no conflict! )

M Di f Fi di M i l C tibl


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Merger Diagram for Finding Maximal Compatibles

Links are drawn between compatible states. An n-state compatible is represented by an n-sided polygon with all its

diagonals connected.

H t M i th M Di ?


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How to Merge using the Merger Diagram?

The resulting set ofcompatibles need to be:

Covering: Contains all initialstates.

Closed: Contains all theimplied states.

The closed & covering setof compatibles determine

the reduced flow table. So, what is the subset of (a,b), (a,c,d), (b,e,f) thatsatisfy coverage and closedness?

For coverage, (a,c,d) and (b,e,f) are sufficient.

Do (a,c,d) and (b,e,f) satisfy closedness? Are the implied states of (a,c), (a,d), (c,d),

(b,e), (b,e), (b,f) included in the selected set?

A th E l f M Di


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Another Example for Merger Diagram

Q i


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Quizzzz

1. Derive the implication table for the following transition table.2. Draw the merger diagram and determine the set of maximal

compatibles.3. Determine the minimum set of maximal compatibles and draw thereduced transition table.

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Hazards


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Hazards

A hazard is a condition in which a change in a single variable produces a momentarychange in output when no change should occur.

All inputs are 1 at the beginning. When x2 becomes 0, due to delay caused

by the NOT gate, Y may temporarily become 0.

Types of Hazards


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Types of Hazards

Removing Hazards


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Removing Hazards

Hazars are produced when changingfrom one term to another!

This causes a problem becauseduring the transition, neither ofthe terms might be 1.

So, make redundant terms/groupsso that the new terms make surethat the transition is covered.

The Circuit After Removing the Hazard


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The Circuit After Removing the Hazard

Another way to avoid hazards


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Another way to avoid hazards

Implement the circuit with SR latches!!!Why would this remove hazards?

Implementation with SR latches to avoid hazards


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Implementation with SR latches to avoid hazards

Essential Hazards


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Essential Hazards

Due to delays, feedback loops mightproduce hazards. These hazards cannot be corrected byadding gates/terms. They can be avoided only by adjusting thedelays in the feedback loops according to

the delays in the input signals.

Quiz


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the last of the Asyncronous Logic part

Check whether the following circuit has a hazard. If it does, remove the hazard by both

a) adding redundant terms to the Y function,b) implementing the circuit with SR-latches.

asyncronous logic

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