atel4223 lab 2011_12

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ATEL 4223 VHDL laboratory manual

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TUNKU ABDUL RAHMAN COLLEGE

SCHOOL OF TECHNOLOGY

DIVISION OF ELECTRONIC ENGINEERING

ELECTRONIC ENGINEERING LABORATORY MANUAL

ATEL4223 Digital Systems Design

ADVANCED DIPLOMA IN TECHNOLOGY

(ELECTRONIC ENGINEERING & TELECOMMUNICATIONS)

SEMESTER 2

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Table of Contents

Introduction

Instructions and Guide to Quartus II IDE

Week 1 : Familiarization to Quartus II IDE

Experiment 1a: familiarization of graphical method

Experiment 1b: familiarization of lpm_add_sub component.

Experiment 2: familiarization of VHDL code and syntax.

Week 2:

Experiment 3a: Simulation on VHDL code.Experiment 3b: Simulation on graphical symbol.

Experiment 4: Assemble all components and configure the DE 1 board

Week 3:Demonstration of laboratory work & Report writing

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5. From Family & Device Setting [page 3 of 5]. Decide on Device family : Cyclone II Available Devices : EP2C35F672C6 NEXT

6. From EDA Tool Setting [page 4 of 5]. Decide on Simulation : ModelSim-Altera NEXT

7. Summary [page 5 of 5].Finish

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Step 3 Start a new file

1. From Quartus II main menu , file new Design files Block Diagram/Schematic File

2. Click OK.3. Save the file as lab1a.bdf by (file Save as)

Step 4 Drawing Schematic

You will now entry your design with graphical method.

In this lab, we will design a 4-bit adder.

You task is to draw the schematic as shown in FIGURE 1A

There are 3 type of components in this design, that is 74283, input pin and output pin.

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Double click on any blank spot on the schematic workspace.

A dialog box SYMBOL is pop-up.Key in component name 74283

Symbol component , 74283 4 Bit Adder appear on the work space. Press OK

Double click on any blank spot on the schematic workspace again.

A dialog box SYMBOL is pop-up.

Key in component name input.

Press OK

Note: You can duplicate the symbol by clicking on Repeat-insert mode. Press OK. Press Esc to exit

Repeat-insert mode.

Key in component name output using similar ways.

Click on input and output pin to rename the pin name.Then file Save.

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After you have enter all the components, connect them together as shown in FIGURE 1A.

To connect, move your cursor to the joining point.

Click and drag it to the other joining point.

FIGURE 1A

When you have done, check the design entry error by clicking

Quartus II main menu, processing Analyze current file

If you have entered all the symbols correctly, the compiler message will show 0 error. Otherwise,

correct the error and Analyze current file again.

Close the compiler window when you have done it.

(Remember to save it into you own thumb drive)

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Lab 1B

Objective: To familiarize with lpm_add_sub component in Quartus II IDE.

Create C:\lab 1b directory in your hard disk.

To start a new graphic design project,

under Quartus main menu select FileNew Project Wizard Save the file as lab1b.bdf in c:\ lab 1b directory that you have just created. Add the file oflab1b.bdfinto the project. (in Add Files [page 2 of 5]) Same settings as in Lab 1A for page 3 to 5. To start a new graphic design project,

To start a new file

From Quartus II main menu , file new Design files Block Diagram/Schematic File double clicking on any blank spot on the schematic workspace. Key in component name

lpm_add_sub in dialog box SYMBOL pop-up window.

OKThe MegaWizard Plug-In Manager[page 2c] dialog box will pop-up.

Click the type of output file to be created as VHDL

Leave the output file name as default lpm_add_sub0

Click next

Edit parameter value as follows in MegaWizard Plug-In Manager[page 3 of 8]:

How wide shshould the dataa and datab input buses be? 4

Which operating mode do you want for the adder/subtractor? Addition only

Click next

Click No, both values vary

Click Unsigned

Click next

Click create a carry input

Click create a carry output

Click finish

Click finish

A lpm_add_sub component can now be drag to theschematic workspace. Double click on any blankspace to obtain input and output pins .

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Complete the schematic diagram as shown in Figure 1B.

FIGURE 1B

When you have done, check the design entry error by clicking

Quartus II main menu, processingAnalyze current file

If you have entered all the symbols correctly, the compiler message will show 0 error. Otherwise,

correct the error and Analyze current file again.

Close the compiler window when you have done it.


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LAB 2

Objective: To create a binary to BCD converter using VHDL.

Create C:\ lab 2 directory in your hard disk.

Start a new project wizard. Directory C:\ lab 2. Name of project lab2.

Add the file ofbinbcd.vhd into the project. (in Add Files [page 2 of 5]) Same settings as in Lab 1A for page 3 to 5.

Start a new file, from file new VHDL file.

Save the file as binbcd.vhd (File Save as) in the directory that you have just created.

You will now entry your design with VHDL method.

Enter the VHDL code as shown below:

Library IEEE;Use IEEE.std_logic_1164.all;

Use IEEE.std_logic_unsigned.all;

Use IEEE.std_logic_arith.all;

Entity binbcd is

Port ( bin: in integer range 0 to 31;

bcd_1 : out integer range 0 to 15;

bcd_2 : out integer range 0 to 15;

clkc : in std_logic);

end binbcd;

architecture bhv of binbcd isbegin

P1 :process(clkc)

Begin

If rising_edge(clkc) then

If bin < 10 then

bcd_1

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Quartus II main menu, processing Start compilation

If you have entered all the syntax correctly, the compiler message will show 0 error.

Otherwise, correct the error and do the compilation again.

Close the compiler window when you have done.


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LAB 3A

Objective: To simulate the function of the binary to BCD created in lab2.

Open the design file c:\lab 2 \ binbcd.vhd

Objective: To simulate the function of the binary to BCD created in lab2.

Open the design file c:\lab 2 \ binbcd.vhd

(Quartus II main menu, File open)

Set the project to \ binbcd.vhd by

(Quartus II main menu, project Add/Remove files in project)

Ensure that the file contains only binbcd.vhd

From menu select compiler

(Quartus II main menu, processing Start compilation)

You should see

Info: Quartus II Full Compilation was successful. 0 errors, 8 warnings.

You may Ignore the warnings, but correct the error and compile the file again.

To perform waveform simulation

1. From Quartus II main menu, Tools options Select EDA Tool Options. LinkModelSim-Altera to the correct paths. ClickOK

2. From Quartus II main menu, Tools Run Simulation Tool Gate Level Simulation orselect icon as shown.

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The binbcd is then link to ModelSim-Altera and simulate in this environment.

Modelsim is a simulation tool. it just compiles the code, checks syntax and provides the waveform

of the design behaviour according to the inputs values defined at the Test Bench file. Therefore,

Modelsim is a tool for the functional checking of the design.

In ModelSim ALTERA STARTER Edition 10.0c Environment, Clicksimulate Start simulation

In Design Unit(s)enter binbcd ok

Drag the input and output pins from objects window to wave window

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In Wave window, right click on the input pin, example: the clkc pin (clock input), the Define Clock

will appear. You can change the length of the mark (high) and space (low), by changing the period and

the first edge show on the wave window.

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Then right click on the bin input, you can change the radix to binary, decimal. In this example, we will

change it to decimal. Hence, the waveform shown on the wave window later will be in decimal value.

Then right click on the bin input again to enter the waveform pattern of it. Select Force, enter for value

01100 (12), delay for 200, then clickOK.

Repeat to right click on the bin input, select Force, enter for value 10101 (21), delay for 400, then

clickOK.

Repeat to right click on the bin input, select Force, enter for value 01111 (16), delay for 600, cancel

After 800, then clickOK.

Now, we will run the stimulus by Simulate Run Run-All.

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The simulation result will be shown on the wave window. To stop simulation, clickSimulate Break.

The simulation command can also be written in the transcript as point by the arrow. Refer to HELP file

in ModelSim for more information. Some useful command is attached in the appendix A.

Exercise: Try to obtain the waveform pattern as shown in the following figure.

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Enter different values of bin to confirm the functionality of the binbcd entity on your own.

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LAB 3B

Objective: To simulate the function of the adder created in lab 1b.

Open the project file c:\lab 1b \ lab1b.bdf

Open the design file c:\lab 1b \ lab1b.bdf

(Quartus II main menu, File open)

From menu select compiler

(Quartus II main menu, processing Start compilation)

You should see

Info: Quartus II Full Compilation was successful. 0 errors, 13 warnings.

You may Ignore the warnings, but correct the error and compile the file again.

To perform waveform simulation

1. From Quartus II main menu, Tools options Select EDA Tool Options. LinkModelSim-Altera to the correct paths. ClickOK

2. From Quartus II main menu, Tools Run Simulation Tool Gate Level Simulation.

ClickRun

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3. The lab1b is then link to ModelSim-Altera and simulate in ModelSim environment.4. In ModelSim ALTERA STARTER Edition 10.0c Environment, Clicksimulate Start

simulation

5. In Design Unit(s)enter lab1b ok.6. Drag the input and output pins (cin, a, b , sum and cout) from objects window to wave window.7. In Wave window, right click on the input pin to enter the waveform patterns as shown. Then

run the stimulus by Simulate Run Run-All.

8. Verify that the result is the correct one.9. Enter different values of cin, a and b to confirm the functionality of the lab1b entity on your

own.

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LAB 4

Section A

Create C:\ lab 4A directory in your hard disk.

To start a New Project Wizard

Select Create a New Project. Name the project as segment Next add segment.vhd file into it

To start a new file

From Quartus II main menu , file new Design files VHDL file OK Enter the VHDL code of segment.vhd as shown below:

Library IEEE;

Use IEEE.std_logic_1164.all;

Entity segment is

Port ( segment_out : out std_logic_vector ( 6 downto 0 );

Bcd_in :in std_logic_vector ( 3 downto 0 );

Clk_in :in std_logic);

End segment;

Architecture behavioural of segment is

Begin

P1:process (bcd_in, clk_in )

Begin

If rising_edge(clk_in) then

CASE bcd_in IS

WHEN "0000" => segment_out segment_out segment_out segment_out segment_out segment_out segment_out segment_out segment_out segment_out segment_out

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Then check the design entry error by(Quartus II main menu, processing Start compilation).

If you have enter all the syntax correctly, the compiler massage will shows 0 error.

Otherwise, correct the error and do compilation again.

Section B

Create C:\ lab 4B directory in your hard disk.

To start a New Project Wizard

Select Create a New Project. Name the project as Top_level Next Add the file c:\ lab 4A \ segment.vhd to this directory Add the file c:\ lab 1b \ lpm_add_sub0.vhd to this directory Add the file c:\lab 2 \ binbcd.vhd to this directory

To start a new file

3. From Quartus II main menu , file new Design files Block Diagram/Schematic FileOK

4. From project navigator, click on Files, all files added into this project will be shown.5. Right click on the segment.vhd file, to create symbol of it.

6. Wait for symbol to be created, pop_up meassage of Create Symbol File was successful.7. Repeat for binbcd.vhd file.8. Right click on the top_level.bdf to set it as top level files.

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9. Open the top_level.bdf file, double click on any blank space in the schematic workspace.10.Popup window Symbol appear, enter Name as binbcd OK.

11.Binbcd symbol can now be drag to the top_level.bdf workspace.12.Repeat the steps 8 to 11 for lpm_add_sub0.vhd and segment.vhd. Repeat twice as 2 segment

symbols are needed.

13.Now, the symbols can be connected as shown.

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14.Add in input and output pins.15.Label the by right click properties.16.Enter the name as shown in the diagram. Example: bin[3..0], digit1[6..0], bcd_1[3..0], bin[4].

17.Save the file as top_level.bdf. then from Quartus II main menu, processing Startcompilation.

18.Ensure 0 error, otherwise correct the error then recompile.19.Start simulation by Tool Run Simulation Tool Gate Level Simulation.20.Under ModelSim Altera Starter environment, Simulate Start Simulation. Design unit is

top_level.bdf.

21.Drag the input and output pins to the wave window, then force the stimulus at the input pins.Confirm the functionality of this design unit.

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When you have done all the above, the program will be downloaded into DE 2 board.

To programme into the programmer

ClickTools programmer

Important: Before download into programmer, make sure that the input and output of the entity

are properly assign to respective pin in the DE II board.

Optional: To create a Chain Description File (.cdf), first click file menu save as, key in and enter save.

To set up configuration hardware

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From Quartus main menu, clickTools EP2C35F672C6Programmer.2. Check that the Hardware setup is ByteBlaster and Mode is JTAG.3. Check file is top_level.sof, click add file if the required file is not available.4. Check device is , EP2C35F672, add Device, if the target Device is different . Cyclone II

EP2C35F672

5. Then clickStart to download the design unit into the target FPGA. Progress of downloadingwill be shown.

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Altera DE 2 Board

6. In Quartus main menu, ClickAssignments Pin Planner to assign the connection ofinput/output devices of DE 2 to design unit (top_level). Fill in the location the correct pin

assignment. To check the design unit on the DE 2 board, switches (sw) can be used as input (a,

b and cin) and key as the clock. The output will be displayed on the LEDs. Refer to Appendix

B for pin location.

The active-low Seven segment display

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Appendix A

Useful commands

cd {full_path} - change directory pwd -print name of current/working directory vlib {folder name}create folder

vmap {physical_folder work } mapping to vitrual folder work

vcom -93quietwork work {full_path/ file name.vhd}compile the chosen fileto work

vsim t {units} work.test_bench_entity_name- load simulation

add waver * - add all wave (recursive search) to simulation window

run t units run simulation for t time units restart f - reload simulation quit simend of current simulation quit f - kill process (modelsim) .main clear clear the transcript window

notepad open the Modelsim build-in editor alias new_mame original_name allows to rename existing command alias new_mame original_name allows to rename existing commandFor example : alias cls .main clear

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Appendix B ----- DE 2 Pin Assignments

SW[0] PIN_N25

SW[1] PIN_N26

SW[2] PIN_P25SW[3] PIN_AE14

SW[4] PIN_AF14

SW[5] PIN_AD13

SW[6] PIN_AC13

SW[7] PIN_C13

SW[8] PIN_B13

SW[9] PIN_A13

SW[10] PIN_N1

SW[11] PIN_P1

SW[12] PIN_P2SW[13] PIN_T7

SW[14] PIN_U3

SW[15] PIN_U4

SW[16] PIN_V1

SW[17] PIN_V2

HEX0[0] PIN_AF10

HEX0[1] PIN_AB12

HEX0[2] PIN_AC12

HEX0[3] PIN_AD11HEX0[4] PIN_AE11

HEX0[5] PIN_V14

HEX0[6] PIN_V13

HEX1[0] PIN_V20

HEX1[1] PIN_V21

HEX1[2] PIN_W21

HEX1[3] PIN_Y22

HEX1[4] PIN_AA24

HEX1[5] PIN_AA23

HEX1[6] PIN_AB24

KEY[0] PIN_G26

KEY[1] PIN_N23

KEY[2] PIN_P23

KEY[3] PIN_W26

atel4223 lab 2011_12

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